CSD25501F3T

CSD25501F3 SLPS692B – OCTOBER 2017 – REVISED OCTOBER 2021 CSD25501F3 –20-V P-Channel FemtoFET™ MOSFET Product Summary 1 Features • • • • • • • TA = 25°C Low on-resistance Ultra-low Qg and Qgd Ultra-small footprint – 0.7 mm × 0.6 mm Low profile – 0.22-mm max height Integrated ESD protection diode Lead and halogen free RoHS compliant UNIT VDS Drain-to-Source Voltage –20 V Qg Gate Charge Total (–4.5 V) 1.02 nC Qgd Gate Charge Gate-to-Drain RDS(on) Drain-to-Source On-Resistance VGS(th) Threshold Voltage 0.09 nC VGS = –1.8 V 120 VGS = –2.5 V 86 VGS = –4.5 V 64 –0.75 mΩ V Device Information 2 Applications • • • TYPICAL VALUE Optimized for load switch applications Battery applications Handheld and mobile applications DEVICE(1) QTY CSD25501F3 3000 CSD25501F3T 250 (1) 3 Description This –20-V, 64-mΩ, P-Channel FemtoFET™ MOSFET is designed and optimized to minimize the footprint in many handheld and mobile applications. This technology is capable of replacing standard small signal MOSFETs while providing a substantial reduction in footprint size. The integrated 10-kΩ clamp resistor (RC) allows the gate voltage (VGS) to be operated above the maximum internal gate oxide value of –6 V, depending on duty cycle. The gate leakage (IGSS) through the diode increases as VGS is increased above –6 V. MEDIA PACKAGE SHIP 7-Inch Reel Femto 0.73-mm × 0.64-mm Land Grid Array (LGA) Tape and Reel For all available packages, see the orderable addendum at the end of the data sheet. Absolute Maximum Ratings TA = 25°C (unless otherwise stated) VALUE UNIT VDS Drain-to-Source Voltage –20 V VGS Gate-to-Source Voltage –20 V ID Continuous Drain Current(1) –3.6 A IDM Pulsed Drain Current(1) (2) –13.6 A PD Dissipation(1) 500 mW Human Body Model (HBM) 4000 Charged Device Model (CDM) 2000 V(ESD) TJ, Tstg (1) (2) Power Operating Junction, Storage Temperature –55 to 150 V °C Typical RθJA = 255°C/W mounted on FR4 material with minimum Cu mounting area. Pulse duration ≤ 100 μs, duty cycle ≤ 1%. G RC RG 0.2 mm D S 0.6 mm 0.7 mm Top View......... Typical Part Dimensions............... An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CSD25501F3 www.ti.com SLPS692B – OCTOBER 2017 – REVISED OCTOBER 2021 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Specifications.................................................................. 3 5.1 Electrical Characteristics.............................................3 5.2 Thermal Information....................................................3 5.3 Typical MOSFET Characteristics................................ 4 6 Device and Documentation Support..............................6 6.1 Receiving Notification of Documentation Updates......6 6.2 Support Resources..................................................... 6 6.3 Trademarks................................................................. 6 6.4 Electrostatic Discharge Caution..................................6 6.5 Glossary......................................................................6 7 Mechanical, Packaging, and Orderable Information.... 7 7.1 Mechanical Dimensions.............................................. 7 7.2 Recommended Minimum PCB Layout........................8 7.3 Recommended Stencil Pattern................................... 8 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (January 2018) to Revision B (October 2021) Page • Added footnote with link to support document....................................................................................................8 Changes from Revision * (October 2017) to Revision A (January 2018) Page • Added mechanical dimension information and Table 7-1 .................................................................................. 7 2 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CSD25501F3 CSD25501F3 www.ti.com SLPS692B – OCTOBER 2017 – REVISED OCTOBER 2021 5 Specifications 5.1 Electrical Characteristics TA = 25°C (unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT nA STATIC CHARACTERISTICS BVDSS Drain-to-source voltage VGS = 0 V, IDS = –250 μA IDSS Drain-to-source leakage current VGS = 0 V, VDS = –16 V –50 IGSS Gate-to-source leakage current VDS = 0 V, VGS = –6 V –50 nA VDS = 0 V, VGS = –16 V –1 mA VGS(th) Gate-to-source threshold voltage RDS(on) gfs Drain-to-source on-resistance Transconductance VDS = VGS, IDS = –250 μA –20 –0.45 V –0.75 –1.05 VGS = –1.8 V, IDS = –0.1 A 120 260 VGS = –2.5 V, IDS = –0.4 A 86 125 VGS = –4.5 V, IDS = –0.4 A 64 76 VDS = –2 V, IDS = –0.4 A 3.4 V mΩ S DYNAMIC CHARACTERISTICS Ciss Input capacitance 295 Coss Output capacitance Crss Reverse transfer capacitance RG Series gate resistance RC Series clamp resistance Qg Gate charge total (–4.5 V) 1.02 Qgd Gate charge gate-to-drain 0.09 nC Qgs Gate charge gate-to-source 0.45 nC Qg(th) Gate charge at Vth 0.36 nC Qoss Output charge td(on) Turnon delay time tr Rise time td(off) Turnoff delay time tf Fall time VGS = 0 V, VDS = –10 V, ƒ = 100 kHz VDS = –10 V, IDS = –0.4 A VDS = –10 V, VGS = 0 V VDS = –10 V, VGS = –4.5 V, IDS = –0.4 A, RG = 0 Ω 385 pF 70 91 pF 4.1 5.3 pF 33 Ω 10,000 Ω 1.33 nC 1.8 nC 474 ns 428 ns 1154 ns 945 ns DIODE CHARACTERISTICS VSD Diode forward voltage Qrr Reverse recovery charge trr Reverse recovery time ISD = –0.4 A, VGS = 0 V VDS = –10 V, IF = –0.4 A, di/dt = 200 A/μs –0.73 –0.95 V 3.0 nC 7.4 ns 5.2 Thermal Information TA = 25°C (unless otherwise stated) THERMAL METRIC RθJA (1) (2) TYPICAL VALUES UNIT Junction-to-ambient thermal resistance(1) 90 °C/W Junction-to-ambient thermal resistance(2) 255 °C/W Device mounted on FR4 material with 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu. Device mounted on FR4 material with minimum Cu mounting area. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CSD25501F3 3 CSD25501F3 www.ti.com SLPS692B – OCTOBER 2017 – REVISED OCTOBER 2021 5.3 Typical MOSFET Characteristics TA = 25°C (unless otherwise stated) -IDS - Drain-to-Source Current (A) 12 Figure 5-1. Transient Thermal Impedance VGS = -1.8 V VGS = -2.5 V VGS = -4.5 V 10 8 6 4 2 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 -VDS - Drain-to-Source Voltage (V) 1.8 2 D002 Figure 5-2. Saturation Characteristics -IDS - Drain-To-Source Current (A) 12 TC = 125° C TC = 25° C TC = -55° C 10 8 6 4 2 0 0 0.5 1 1.5 2 2.5 -VGS - Gate-To-Source Voltage (V) 3 D003 VDS = –5 V Figure 5-3. Transfer Characteristics 1000 Measured At External Gate Pin Charge At Internal Gate Node 8 7 C - Capacitance (pF) -VGS - Gate-to-Source Voltage (V) 9 6 5 4 3 100 10 2 Ciss = Cgd + Cgs Coss = Cds + Cgd Crss = Cgd 1 1 0 0 0.25 0.5 0.75 1 Qg - Gate Charge (nC) ID = –0.4 A 1.25 1.5 0 2 D004 VDS = –10 V 4 6 8 10 12 14 16 -VDS - Drain-to-Source Voltage (V) 18 20 D005 Figure 5-5. Capacitance Figure 5-4. Gate Charge 4 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CSD25501F3 CSD25501F3 www.ti.com SLPS692B – OCTOBER 2017 – REVISED OCTOBER 2021 5.3 Typical MOSFET Characteristics (continued) TA = 25°C (unless otherwise stated) 180 RDS(on) - On-State Resistance (m:) -VGS(th) - Threshold Voltage (V) 1.05 0.95 0.85 0.75 0.65 0.55 0.45 0.35 -75 -50 -25 0 25 50 75 100 TC - Case Temperature (qC) 125 150 TC = 25° C, ID = -0.4 A TC = 125° C, ID = -0.4 A 150 120 90 60 30 0 175 1 1.5 D006 ID = –250 µA 2 2.5 3 3.5 4 4.5 5 -VGS - Gate-To-Source Voltage (V) 5.5 6 D007 Figure 5-7. On-State Resistance vs Gate-to-Source Voltage Figure 5-6. Threshold Voltage vs Temperature 10 VGS = -1.8 V VGS = -2.5 V VGS = -4.5 V 1.4 -ISD - Source-To-Drain Current (A) Normalized On-State Resistance 1.5 1.3 1.2 1.1 1 0.9 TC = 25qC TC = 125qC 1 0.1 0.01 0.001 0.8 0.0001 0.7 -75 0 -50 -25 0 25 50 75 100 TC - Case Temperature (qC) 125 150 0.2 0.4 0.6 0.8 -VSD - Source-To-Drain Voltage (V) 175 1 D009 Figure 5-9. Typical Diode Forward Voltage D008 ID = –0.4 A Figure 5-8. Normalized On-State Resistance vs Temperature 5.0 -IDS - Drain-to-Source Current (A) -IDS - Drain-To-Source Current (A) 100 10 1 100 ms 10 ms 0.1 0.1 1 ms 100 µs 1 10 -VDS - Drain-To-Source Voltage (V) 100 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -50 -25 D010 Single pulse, typical RθJA = 255°C/W Figure 5-10. Maximum Safe Operating Area 0 25 50 75 100 125 TA - Ambient Temperature (qC) 150 175 D011 Typical RθJA = 90°C/W Figure 5-11. Maximum Drain Current vs Temperature Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CSD25501F3 5 CSD25501F3 www.ti.com SLPS692B – OCTOBER 2017 – REVISED OCTOBER 2021 6 Device and Documentation Support 6.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 6.2 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 6.3 Trademarks FemtoFET™ and TI E2E™ are trademarks of Texas Instruments. All trademarks are the property of their respective owners. 6.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 6.5 Glossary TI Glossary 6 This glossary lists and explains terms, acronyms, and definitions. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CSD25501F3 CSD25501F3 www.ti.com SLPS692B – OCTOBER 2017 – REVISED OCTOBER 2021 7 Mechanical, Packaging, and Orderable InformationPACKAGE OUTLINE PicoStar 0.22 mm max height TheYJN0003A following pages include mechanical, packaging, and orderable- information. This information is the most TM current data available for the designated devices. This data is subject to change without PicoStarnotice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. TM 7.1 Mechanical Dimensions 0.73 0.65 A B PIN 1 INDEX AREA 0.64 0.56 C 0.22 MAX SEATING PLANE 0.4 0.225 2 3 0.175 0.51 0.49 0.35 1 0.16 0.14 C B A 2X 0.015 2X 0.16 0.14 0.015 0.26 0.24 C A B 4223685/A 05/2017 PicoStar is a trademark of Texas Instruments. for reference only. Dimensioning and A. NOTES: All linear dimensions are in millimeters. Any dimensions in parenthesis are 1. Y14.5M. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing tolerancing per ASME per ASME Y14.5M B. This drawing is subject to change without notice. 2. This drawing is subject to change without notice. This package is a bumpbump design. Bump finish mayfinish vary. may To determine exact finish,the refer to thefinish, devicerefer datasheet C. 3. This package isPb-free a Pb-free design. Bump vary. Tothedetermine exact to the device data sheet or contact a or contact a local TI representative. local TI representative. Table 7-1. Pin Configuration POSITION DESIGNATION Pin 1 Gate Pin 2 Source Pin 3 Drain www.ti.com Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CSD25501F3 7 CSD25501F3 www.ti.com SLPS692B – OCTOBER 2017 – REVISED OCTOBER 2021 7.2 Recommended Minimum PCB Layout (0.15) 2X (0.25) 2X (0.15) 0.05 MIN ALL AROUND TYP 1 3 SYMM (0.35) (0.5) EXAMPLE STENCIL DESIGN 2 YJM0003A (R0.05) TYP SOLDER MASK TM PicoStar OPENING TYP PKG METAL UNDER SOLDER MASK TYP (0.175) - 0.35 mm max height PicoStar TM (0.4) A. B. All dimensions are in millimeters. LAND PATTERN EXAMPLE SOLDER MASK DEFINED For more information, see FemtoFET Surface Mount Guide (SLRA003D). SCALE:50X 7.3 Recommended Stencil Pattern 2X (0.25) 2X (0.2) (0.15) 1 3 SYMM (0.4) 2X (0.15) (0.5) 2 PKG (R0.05) TYP 2X SOLDER MASK EDGE (0.175) (0.4) A. 4222304/A 09/2015 All dimensions are in millimeters. NOTES: (continued) SOLDER PASTE EXAMPLE ON 0.075 - 0.1 mm THICK STENCIL 4. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). SCALE:50X www.ti.com 8 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CSD25501F3 PACKAGE OPTION ADDENDUM www.ti.com 8-Sep-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) CSD25501F3 ACTIVE PICOSTAR YJN 3 3000 RoHS & Green Call TI Level-1-260C-UNLIM -55 to 150 V CSD25501F3T ACTIVE PICOSTAR YJN 3 250 RoHS & Green Call TI Level-1-260C-UNLIM -55 to 150 V (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of