CSD75207W15

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents CSD75207W15 SLPS418A – JUNE 2013 – REVISED JUNE 2014 CSD75207W15 Dual P-Channel NexFET™ Power MOSFET 1 Features • • • • • 1 • • Dual P-Channel MOSFETs Common Source Configuration Small Footprint 1.5-mm × 1.5-mm Gate-Source Voltage Clamp Gate ESD Protection >4 kV – HBM JEDEC standard JESD22-A114 Pb and Halogen Free RoHS Compliant Product Summary TA = 25°C UNIT Drain-to-Drain Voltage –20 V Qg Gate Charge Total (–4.5 V) 2.9 nC Qgd Gate Charge Gate to Drain RD1D2(on) Drain-to-Drain On Resistance VGS(th) 0.4 nC VGS = –1.8 V 119 mΩ VGS = –2.5 V 64 mΩ VGS = –4.5 V 45 mΩ Threshold Voltage –0.8 V Ordering Information(1) 2 Applications • • • TYPICAL VALUE VD1D2 Battery Management Battery Protection Load and Input Switching Device Package Media CSD75207W15 1.5-mm × 1.5-mm Wafer Level Package 7-Inch Reel Qty Ship 3000 Tape and Reel (1) For all available packages, see the orderable addendum at the end of the data sheet. 3 Description Absolute Maximum Ratings The CSD75207W15 device is designed to deliver the lowest on-resistance and gate charge in the smallest outline possible with excellent thermal characteristics in an ultra-low profile. Low on-resistance coupled with the small footprint and low profile make the device ideal for battery-operated space-constrained applications. The device has also been awarded with U.S. patents 7952145, 7420247, 7235845, and 6600182. TA = 25°C VALUE UNIT VD1D2 Drain-to-Drain Voltage –20 V VGS Gate-to-Source Voltage –6.0 V Continuous Drain to Drain Current(1) (2) –3.9 A Pulsed Drain to Drain Current, TC = 25°C(3) –24 A Continuous Source Pin Current –1.2 A Pulsed Source Pin Current(3) –15 A Continuous Gate Clamp Current –0.5 A ID1D2 IS IG Text added for space (3) Pulsed Gate Clamp Current –7 A PD Power Dissipation(1) 0.7 W TJ, Tstg Operating Junction and Storage Temperature Range –55 to 150 °C (1) Per device, both sides in conduction (2) Device operating at a temperature of 105ºC (3) Pulse duration 10 μs, duty cycle ≤2% Text added for space Top View RD1D2(on) vs VGS G1 SS G2 D1 D2 D2 RD1D2(on) - On-State Resistance (mΩ) 140 D1 D1 120 110 100 90 80 70 60 50 40 30 D2 TC = 25°C Id = −1A TC = 125ºC Id = −1A 130 0 1 2 3 4 5 − VGS - Gate-to- Source Voltage (V) 6 G001 P0109-01 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CSD75207W15 SLPS418A – JUNE 2013 – REVISED JUNE 2014 www.ti.com Table of Contents 1 2 3 4 5 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Specifications......................................................... 1 1 1 2 3 5.1 Electrical Characteristics.......................................... 3 5.2 Thermal Information .................................................. 3 5.3 Typical MOSFET Characteristics.............................. 4 6 Device and Documentation Support.................... 7 6.1 Trademarks ............................................................... 7 6.2 Electrostatic Discharge Caution ................................ 7 6.3 Glossary .................................................................... 7 7 Mechanical, Packaging, and Orderable Information ............................................................. 8 7.1 CSD75207W15 Package Dimensions ...................... 8 7.2 Recommended PCB Land Pattern............................ 9 7.3 Tape and Reel Information ....................................... 9 4 Revision History Changes from Original (June 2013) to Revision A Page • Increased continuous drain to drain current to 3.9 A ............................................................................................................ 1 • Updated the continuous drain to drain current conditions to specify a temperature of 105ºC .............................................. 1 2 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: CSD75207W15 CSD75207W15 www.ti.com SLPS418A – JUNE 2013 – REVISED JUNE 2014 5 Specifications 5.1 Electrical Characteristics (TA = 25°C unless otherwise stated). Specifications and graphs are Per MOSFET unless otherwise stated. Drain to Drain measurements are done with both MOSFETs in series (common source configuration. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT STATIC CHARACTERISTICS BVD1D2 Drain-to-Drain Voltage VGS = 0 V, ID1D2 = –250 μA BVGSS Gate-to-Source Voltage VD1D2 = 0 V, IG = -250 μA IDDS Drain-to-Drain Leakage Current VGS = 0 V, VD1D2 = –16 V IGSS Gate-to-Source Leakage Current VD1D2 = 0 V, VGS = –6 V VGS(th) Gate-to-Source Threshold Voltage VD1D2 = VGS, IDS = –250 μA RD1D2(on) Drain-to-Drain On-Resistance gfs Transconductance –20 V –6 –0.6 V –1 μA –100 nA –0.8 –1.1 V VGS = –1.8 V, ID1D2 = –1 A 119 162 mΩ VGS = –2.5 V, ID1D2 = –1 A 64 77 mΩ VGS = –4.5 V, ID1D2 = –1 A 45 54 mΩ VD1D2 = –10 V, ID1D2 = –1 A 6.2 S DYNAMIC CHARACTERISTICS CISS Input Capacitance COSS Output Capacitance CRSS Reverse Transfer Capacitance Rg Series Gate Resistance 27 Qg Gate Charge Total (–4.5 V) 2.9 Qgd Gate Charge – Gate to Drain 0.4 nC Qgs Gate Charge – Gate to Source 0.7 nC Qg(th) Gate Charge at Vth 0.4 nC QOSS Output Charge 3.1 nC td(on) Turn On Delay Time 12.8 ns tr Rise Time td(off) Turn Off Delay Time tf Fall Time VGS = 0 V, VD1D2 = –10 V, ƒ = 1 MHz VD1D2 = –10 V, ID1D2 = –1 A VD1D2 = –9.5 V, VGS = 0 V VD1D2 = –10 V, VGS = –4.5 V, ID1D2 = –1 A, RG = 30 Ω 458 595 pF 225 293 pF 10.4 13.5 pF Ω 3.7 nC 8.6 ns 32.1 ns 16.0 ns DIODE CHARACTERISTICS VSD Diode Forward Voltage ID1D2 = –1 A, VGS = 0 V –0.8 Qrr Reverse Recovery Charge Vdd = –10 V, IF = –1 A, di/dt = 200 A/μs 10.5 –1 nC V trr Reverse Recovery Time Vdd = –10 V, IF = –1 A, di/dt = 200 A/μs 23 ns 5.2 Thermal Information (TA = 25°C unless otherwise stated) THERMAL METRIC R θJA (1) (2) (3) Junction-to-Ambient Thermal Resistance (1) Junction-to-Ambient Thermal Resistance (2) (3) (2) TYPICAL VALUE UNIT 70 °C/W 165 Device mounted on FR4 material with Minimum Cu mounting area. Measured with both devices biased in a parallel condition. Device mounted on FR4 material with 1-inch2 of Cu (2 oz). Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: CSD75207W15 3 CSD75207W15 SLPS418A – JUNE 2013 – REVISED JUNE 2014 www.ti.com Typ RθJA = 165°C/W when mounted on minimum pad area of 2-oz. Cu. Typ RθJA = 70°C/W when mounted on 1-inch2 of 2 oz. Cu. G1 S G2 D2 D1 G1 S G2 D2 D1 M0169-01 M0170-01 5.3 Typical MOSFET Characteristics (TA = 25°C unless otherwise stated) Figure 1. Transient Thermal Impedance 4 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: CSD75207W15 CSD75207W15 www.ti.com SLPS418A – JUNE 2013 – REVISED JUNE 2014 Typical MOSFET Characteristics (continued) (TA = 25°C unless otherwise stated) 15 − ID1D2 - Drain 1 to Drain 2 Current (A) − ID1D2 - Drain 1 to Drain 2 Current (A) 10 VGS = −4.5V VGS = −2.5V VGS = −1.8V 9 8 7 6 5 4 3 2 1 0 0 0.2 0.4 0.6 0.8 1 1.2 − VD1D2 - Drain 1 to Drain 2 Voltage (V) VD1D2 = −5V 12 9 6 0 1.4 TC = 125°C TC = 25°C TC = −55°C 3 0 0.5 G001 Figure 2. Saturation Characteristics G001 700 ID = −1A VD1D2 =−10V Ciss = Cgd + Cgs Coss = Cds + Cgd Crss = Cgd f = 1MHz VGS = 0V 600 4 C − Capacitance (nF) − VGS - Gate-to-Source Voltage (V) 3 Figure 3. Transfer Characteristics 5 3 2 500 400 300 200 1 100 0 0 0.5 1 1.5 2 2.5 Qg - Gate Charge (nC) 3 0 3.5 0 1 2 3 4 5 6 − VD1D2 - Drain 1 to Drain 2 Voltage (V) G001 Figure 4. Gate Charge 7 8 G001 Figure 5. Capacitance 140 RD1D2(on) - On-State Resistance (mΩ) 1.1 ID = −250uA − VGS(th) - Threshold Voltage (V) 1 1.5 2 2.5 − VGS - Gate-to-Source Voltage (V) 1 0.9 0.8 0.7 0.6 0.5 0.4 −75 −25 25 75 125 TC - Case Temperature (ºC) Figure 6. Threshold Voltage vs Temperature 175 TC = 25°C Id = −1A TC = 125ºC Id = −1A 130 120 110 100 90 80 70 60 50 40 30 0 G001 1 2 3 4 5 − VGS - Gate-to- Source Voltage (V) 6 G001 Figure 7. On-State Resistance vs Gate-to-Source Voltage Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: CSD75207W15 5 CSD75207W15 SLPS418A – JUNE 2013 – REVISED JUNE 2014 www.ti.com Typical MOSFET Characteristics (continued) (TA = 25°C unless otherwise stated) 1.4 10 VGS = −2.5V VGS = −4.5V ID = −1A − ISD − Source-to-Drain Current (A) Normalized On-State Resistance 1.5 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 −75 −25 25 75 125 TC - Case Temperature (ºC) 175 TC = 25°C TC = 125°C 1 0.1 0.01 0.001 0.0001 0 Figure 8. Normalized On-State Resistance vs Temperature G001 Figure 9. Typical Diode Forward Voltage 1ms 10ms 100ms 1s DC − IAV - Peak Avalanche Current (A) − ID1D2 - Drain 1 to Drain 2 Current (A) 1 100 1000 100 10 1 0.1 Single Pulse Typical RthetaJA =165ºC/W(min Cu) 0.01 0.1 0.2 0.4 0.6 0.8 − VSD − Source-to-Drain Voltage (V) G001 1 10 − VD1D2 - Drain 1 to Drain 2 Voltage (V) 10 TC = 25ºC TC = 125ºC 1 0.01 100 0.1 TAV - Time in Avalanche (ms) G001 Figure 10. Maximum Safe Operating Area 1 G001 Figure 11. Single Pulse Unclamped Inductive Switching − ID1D2 - Drain 1 to Drain 2 Current (A) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 Typical RthetaJA =70ºC/W(max Cu) 0.0 −50 −25 0 25 50 75 100 125 TA - Ambient Temperature (ºC) 150 175 G001 Figure 12. Maximum Drain Current vs Temperature 6 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: CSD75207W15 CSD75207W15 www.ti.com SLPS418A – JUNE 2013 – REVISED JUNE 2014 6 Device and Documentation Support 6.1 Trademarks NexFET is a trademark of Texas Instruments. 6.2 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 6.3 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: CSD75207W15 7 CSD75207W15 SLPS418A – JUNE 2013 – REVISED JUNE 2014 www.ti.com 7 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 7.1 CSD75207W15 Package Dimensions Solder Ball Ø 0.31 ±0.075 Pin 1 Mark 1 2 3 2 3 1 A B 1.50 B 1.00 +0.00 –0.08 0.50 A C C 1.50 +0.00 –0.08 0.62 Max Top View 0.50 Bottom View 0.04 0.62 Max 0.35 ±0.10 Side View Seating Plate Front View M0171-01 NOTE: All dimensions are in mm (unless otherwise specified) Pinout 8 POSITION DESIGNATION A1 Gate1 A2, A3, B3 Drain1 C1 Gate2 C2, C3, B2 Drain2 B1 Source Sense Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: CSD75207W15 CSD75207W15 www.ti.com SLPS418A – JUNE 2013 – REVISED JUNE 2014 7.2 Recommended PCB Land Pattern Ø 0.25 1 2 3 1.00 0.50 A B C 0.50 M0172-01 NOTE: All dimensions are in mm (unless otherwise specified). 7.3 Tape and Reel Information 4.00 ±0.10 Ø 1.50 ±0.10 4.00 ±0.10 Ø 0.50 ±0.05 0.86 ±0.05 1.60 ±0.05 5° Max 3.50 ±0.05 8.00 +0.30 –0.10 1.75 ±0.10 2.00 ±0.05 0.254 ±0.02 1.60 ±0.05 5° Max M0173-01 NOTE: All dimensions are in mm (unless otherwise specified). Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: CSD75207W15 9 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) CSD75207W15 ACTIVE DSBGA YZF 9 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -55 to 150 75207 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of