CSD86311W1723

CSD86311W1723 www.ti.com SLPS251 – MAY 2010 Dual N-Channel NexFET™ Power MOSFET Check for Samples: CSD86311W1723 PRODUCT SUMMARY FEATURES 1 • • • • • • • Dual N-Ch MOSFETs Common Source Configuration Small Footprint 1.7 mm × 2.3 mm Ultra Low Qg and Qgd Pb Free RoHS Compliant Halogen Free VDS Drain to Source Voltage 25 V Qg Gate Charge Total (4.5V) 3.1 nC Qgd Gate Charge Gate to Drain RDS(on) Drain to Source On Resistance VGS(th) nC 37 mΩ VGS = 4.5V 31 mΩ VGS = 8V 29 mΩ Threshold Voltage 1 V Text Added for Spacing ORDERING INFORMATION APPLICATIONS • • • 0.33 VGS = 2.5V Battery Management Battery Protection DC-DC Converters Device Package Media Qty Ship CSD86311W1723 1.7-mm × 2.3-mm Wafer Level Package 7-inch reel 3000 Tape and Reel Text Added for Spacing ABSOLUTE MAXIMUM RATINGS DESCRIPTION The device has been designed to deliver the lowest on resistance and gate charge in the smallest outline possible with thermal characteristics in an ultra low profile. Low on resistance and gate charge coupled with the small footprint and low profile make the device ideal for battery operated space constrained application in load management as well as DC-DC converter applications Top View G1 D1 D1 TA = 25°C unless otherwise stated VALUE UNIT VDS Drain to Source Voltage 25 V VGS Gate to Source Voltage +10 / -8 V 4.5 A 6 A 1.5 W –55 to 150 °C Continuous Drain Current (1) (2)(3) ID Pulsed Drain Current (1) (2)(3) Continuous Gate Clamp Current (4) IG Pulsed Gate Clamp Current (4) PD Power Dissipation (1) TJ, TSTG Operating Junction and Storage Temperature Range D1 S S S S G2 D2 D2 D2 (1) (2) (3) (4) May be limited by Max source current Based on Min Cu footprint Per MOSFET Total for device P0115-01 RD1D2(on) vs VGS 50 ID = 2A 45 T C = 125°C 40 35 30 T C = 25°C 25 20 0 1 2 3 4 5 6 7 8 VGS - Gate-to-Source Voltage - V 9 10 G006 RD1D2(on) - Drain-Drain On-State Resistance - mΩ RDS(on) - Drain-Source On-State Resistance - mΩ RDS(on) vs VGS 100 ID = 2A 90 80 70 T C = 125°C 60 50 40 30 T C = 25°C 20 0 1 2 3 4 5 6 7 8 VGS - Gate-to-Source Voltage - V 9 10 G013 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated CSD86311W1723 SLPS251 – MAY 2010 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Static Characteristics BVDSS Drain to Source Voltage VGS = 0V, ID = 250mA IDSS Drain to Source Leakage Current VGS = 0V, VDS = 20V IGSS Gate to Source Leakage Current VDS = 0V, VGS = +10 / -8V VGS(th) Gate to Source Threshold Voltage VDS = VGS, ID = 250mA RDS(on) RDD(on) gfs Drain to Source On Resistance Drain to Drain On Resistance Transconductance 25 0.85 V 1 mA ±100 nA 1 1.4 V VGS = 2.5V, IDS = 2A 37 51 mΩ VGS = 4.5V, IDS = 2A 31 42 mΩ VGS = 8V, IDS = 2A 29 39 mΩ VGS = 2.5V, ID = 2A 52 75 mΩ VGS = 4.5V, IDS = 2A 41 55 mΩ VGS = 8V, IDS = 2A 38 50 mΩ VDS = 10V, ID = 2A 6.4 S Dynamic Characteristics CISS Input Capacitance COSS Output Capacitance CRSS Reverse Transfer Capacitance RG Seried Gate Resistance Qg Gate Charge Total (4.5V) Qgd Gate Charge Gate to Drain Qgs Gate Charge Gate to Source Qg(th) Gate Charge at Vth QOSS Output Charge td(on) Turn On Delay Time tr Rise Time td(off) Turn Off Delay Time tf Fall Time VGS = 0V, VDS = 12.5V, f = 1MHz VDS = 12.5V, ID = 2A VDS = 12.2V, VGS = 0V VDS = 12.5V, VGS = 4.5V, ID = 2A, RG = 2Ω 450 585 pF 250 325 pF 10 13 pF 1.4 2.8 Ω 3.1 4 nC 0.33 nC 0.85 nC 0.48 nC 4.5 nC 5.4 ns 4.3 ns 13.2 ns 2.9 ns Diode Characteristics VSD Diode Forward Voltage IS = 2A, VGS = 0V Qrr Reverse Recovery Charge trr Reverse Recovery Time Vdd= 12.2V, IF = 2A, di/dt = 300A/ms 0.78 1 V 4.2 nC 13.4 ns THERMAL CHARACTERISTICS (TA = 25°C unless otherwise stated) PARAMETER MIN R qJA Thermal Resistance Junction to Ambient (Minimum Cu area) R qJA Thermal Resistance Junction to Ambient (1 in2 Cu area) (1) (2) (3) 2 (1) (2) (2) (3) TYP MAX UNIT 165 °C/W 68 °C/W Device mounted on FR4 material with minimum Cu mounting area. Measured with both devices biased in a parallel condition. Device mounted on FR4 material with 1 in2 of 2oz. Cu. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CSD86311W1723 CSD86311W1723 www.ti.com SLPS251 – MAY 2010 CSD75211W1723 TTA MIN Rev 0 CSD86311W1723 CSD75211W1723 TTA MIN Rev 0 CSD86311W1723 Max RqJA = 165°C/W when mounted on minimum pad area of 2 oz. Cu. Max RqJA = 68°C/W when mounted on 1inch2 of 2 oz. Cu. G1 S G2 D2 D1 G1 S G2 D2 D1 M0183-01 M0182-01 TYPICAL MOSFET CHARACTERISTICS (TA = 25°C unless otherwise stated) ZqJA - Normalized Thermal Impedance 10 1 0.5 0.3 0.1 0.01 0.1 0.05 Duty Cycle = t1/t2 0.02 0.01 P t1 Single Pulse t2 0.001 0.0001 0.0001 Typical RqJA = 132°C/W (min Cu) TJ = P ´ ZqJA ´ RqJA 0.001 0.01 0.1 1 tp - Pulse Duration - s 10 100 1k G012 Figure 1. Transient Thermal Impedance Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CSD86311W1723 3 CSD86311W1723 SLPS251 – MAY 2010 www.ti.com TYPICAL MOSFET CHARACTERISTICS (continued) 20 20 18 18 IDS - Drain-to-Source Current - A IDS - Drain-to-Source Current - A (TA = 25°C unless otherwise stated) 16 14 VGS = 2.5V 12 VGS = 3V 10 VGS = 3.5V 8 6 VGS = 4.5V 4 VGS = 8V 2 VDS = 5V 16 T C = 25°C 14 12 T C = 125°C 10 8 6 T C = -55°C 4 2 0 0 0 0.5 1 1.5 2 VDS - Drain-to-Source Voltage - V 2.5 1 3 1.5 2 2.5 VGS - Gate-to-Source Voltage - V G001 Figure 2. Saturation Characteristics 4 3 2 C - Capacitance - nF 5 C - Capacitance - nF VGS - Gate-to-Source Voltage - V 1k ID = 2A VDS = 12.5V Ciss = Cgd + Cgs 100 Coss = Cds + Cgd 10 1 Crss = CGgd f = 1MHz VGS = 0V 0 1 0 0.5 1 1.5 2 2.5 Qg - Gate Charge - nC 3 3.5 4 0 5 G003 1.4 ID = 250µA 1.2 1 0.8 0.6 0.4 0.2 0 -75 -25 25 75 T C - Case Temperature - °C 10 15 20 VDS - Drain-to-Source Voltage - V 25 G004 Figure 5. Capacitance 125 175 RDS(on) - Drain-Source On-State Resistance - mΩ Figure 4. Gate Charge VGS(th) - Threshold Voltage - V G002 Figure 3. Transfer Characteristics 6 50 ID = 2A 45 T C = 125°C 40 35 30 T C = 25°C 25 20 0 1 2 G005 Figure 6. Threshold Voltage vs. Temperature 4 3 3 4 5 6 7 8 VGS - Gate-to-Source Voltage - V 9 10 G006 Figure 7. RDS(on) vs. Gate-to-Source Voltage Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CSD86311W1723 CSD86311W1723 www.ti.com SLPS251 – MAY 2010 TYPICAL MOSFET CHARACTERISTICS (continued) 1.6 100 ID = 2A 90 Normalized On-State Resistance RD1D2(on) - Drain-Drain On-State Resistance - mΩ (TA = 25°C unless otherwise stated) 80 70 T C = 125°C 60 50 40 30 ID = 2A VGS = 8V 1.4 1.2 1 0.8 0.6 0.4 0.2 T C = 25°C 0 -75 20 0 1 2 3 4 5 6 7 8 VGS - Gate-to-Source Voltage - V 9 10 25 75 T C - Case Temperature - °C 125 175 G007 G013 Figure 8. RD1D2(on) vs. Gate-to-Source Voltage Figure 9. On Resistance vs. Temperature 10 IDS - Drain-to-Source Current - A 10 ISD - Source-to-Drain Current - A -25 1 T C = 125°C 0.1 T C = 25°C 0.01 0.001 0.0001 0 0.2 0.4 0.6 0.8 VSD - Source-to-Drain Voltage - V 1 1.2 1ms 1 10ms 0.1 Area May be Limited by RDS(on) Single Pulse Typical R θJA = 132°C/W (min Cu) 0.01 0.01 1s DC 0.1 1 10 VDS - Drain-to-Source Voltage - V G008 Figure 10. Typical Diode Forward Voltage 11110 100ms 100 G009 Figure 11. Maximum Safe Operating Area 5 4.5 ID - Drain Current - A 4 3.5 3 2.5 2 1.5 1 0.5 0 -50 -25 0 25 50 75 100 125 T J - Junction Temperature - °C 150 175 G011 Figure 12. Maximum Drain Current vs. Temperature Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CSD86311W1723 5 CSD86311W1723 SLPS251 – MAY 2010 www.ti.com MECHANICAL DATA CSD86311W1723 Package Dimensions Pin A1 Mark 1 3 2 4 +0.00 –0.08 A 1.74 B C 2.32 +0.00 –0.08 0.62 Max Top View Side View 0.04 0.62 Max 0.35 ±0.10 Seating Plate Front View 1.50 0.50 Solder Ball Ø 0.31 ±0.015 0.50 0.50 C 1.00 0.50 Pinout B A Pin A1 Mark (Hidden) 1 2 3 Position Designation A2, A3, A4 Drain 1 C2, C3, C4 Drain 2 A1 Gate 1 C1 Gate 2 B1, B2, B3, B4 Source 4 Bottom View M0184-01 NOTE: All dimensions are in mm (unless otherwise specified) 6 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CSD86311W1723 CSD86311W1723 www.ti.com SLPS251 – MAY 2010 Land Pattern Recommendation 1.50 0.50 0.50 0.50 Ø 0.25 1.00 0.50 A B C 1 2 3 4 M0185-01 NOTE: All dimensions are in mm (unless otherwise specified) Text Added for Spacing Text Added for Spacing Tape and Reel Information 4.00 ±0.10 Ø 1.50 ±0.10 45° Max 4.00 ±0.10 1.90 ±0.05 3.50 ±0.05 8.00 +0.30 –0.10 1.75 ±0.10 2.00 ±0.05 Pin A1 Mark 0.30 0.80 ±0.05 0.254 ±0.02 45° Max 2.45 ±0.05 M0186-01 NOTE: All dimensions are in mm (unless otherwise specified) Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CSD86311W1723 7 PACKAGE MATERIALS INFORMATION www.ti.com 9-Aug-2022 TAPE AND REEL INFORMATION REEL DIMENSIONS TAPE DIMENSIONS K0 P1 B0 W Reel Diameter Cavity A0 B0 K0 W P1 A0 Dimension designed to accommodate the component width Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Sprocket Holes Q1 Q2 Q1 Q2 Q3 Q4 Q3 Q4 User Direction of Feed Pocket Quadrants *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) CSD86311W1723 DSBGA YZG 12 3000 180.0 8.4 CSD86311W1723 DSBGA YZG 12 3000 179.0 14.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2.38 1.8 0.69 4.0 8.0 Q2 2.45 1.9 0.8 4.0 8.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 9-Aug-2022 TAPE AND REEL BOX DIMENSIONS Width (mm) W L H *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CSD86311W1723 DSBGA YZG 12 3000 182.0 182.0 20.0 CSD86311W1723 DSBGA YZG 12 3000 199.0 211.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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