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CSD87331Q3D
SLPS283B – SEPTEMBER 2011 – REVISED FEBRUARY 2017
CSD87331Q3D Synchronous Buck NexFET™ Power Block
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
•
•
The CSD87331Q3D NexFET™ power block is an
optimized design for synchronous buck applications
offering high-current, high-efficiency, and highfrequency capability in a small 3.3-mm × 3.3-mm
outline. Optimized for 5-V gate drive applications, this
product offers a flexible solution capable of offering a
high-density power supply when paired with any 5-V
gate drive from an external controller/driver.
Half-Bridge Power Block
Up to 27-V VIN
Up to 15-A Operation
91% System Efficiency at 10 A
High-Frequency Operation (up to 1.5 MHz)
High Density SON 3.3-mm × 3.3-mm Footprint
Optimized for 5-V Gate Drive
Low-Switching Losses
Ultra-Low-Inductance Package
RoHS Compliant
Halogen Free
Lead-Free Terminal Plating
Top View
8
VSW
7
VSW
3
6
VSW
4
5
VIN
1
VIN
2
TG
TGR
PGND
(Pin 9)
2 Applications
•
•
•
•
BG
P0116-01
Synchronous Buck Converters
– High-Frequency Applications
– High-Current, Low-Duty Cycle Applications
Multiphase Synchronous Buck Converters
POL DC-DC Converters
IMVP, VRM, and VRD Applications
Device Information(1)
DEVICE
MEDIA
QTY
PACKAGE
SHIP
CSD87331Q3D
13-Inch Reel
2500
CSD87331Q3DT
7-Inch Reel
250
SON
3.30-mm × 3.30-mm
Plastic Package
Tape
and
Reel
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Power Block Efficiency
and Power Loss
Efficiency (%)
Typical Circuit
96
6
88
5
VGS = 5V
VIN = 12V
VOUT = 1.3V
LOUT = 1.0µH
fSW = 500kHz
TA = 25ºC
80
72
64
4
3
2
56
48
Power Loss (W)
1
1
0
5
10
Output Current (A)
15
0
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CSD87331Q3D
SLPS283B – SEPTEMBER 2011 – REVISED FEBRUARY 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Specifications.........................................................
1
1
1
2
3
5.1
5.2
5.3
5.4
5.5
5.6
5.7
3
3
3
3
4
5
7
Absolute Maximum Ratings ......................................
Recommended Operating Conditions.......................
Power Block Performance ........................................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Power Block Device Characteristics.............
Typical Power Block MOSFET Characteristics.........
Application and Implementation ........................ 10
6.1 Application Information............................................ 10
6.2 Typical Application .................................................. 13
7
Layout ................................................................... 15
7.1 Layout Guidelines ................................................... 15
7.2 Layout Example ...................................................... 16
8
Device and Documentation Support.................. 17
8.1
8.2
8.3
8.4
8.5
8.6
9
Documentation Support .......................................... 17
Receiving Notification of Documentation Updates.. 17
Community Resources............................................ 17
Trademarks ............................................................. 17
Electrostatic Discharge Caution .............................. 17
Glossary .................................................................. 17
Mechanical, Packaging, and Orderable
Information ........................................................... 18
9.1 Q3D Package Dimensions...................................... 18
9.2 Land Pattern Recommendation .............................. 19
9.3 Q3D Tape and Reel Information ............................. 19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (January 2012) to Revision B
Page
•
Added note for IDM in the Absolute Maximum Ratings table .................................................................................................. 3
•
Added Application and Implementation section note ........................................................................................................... 10
•
Changed Recommended PCB Design Overview section to Layout section ........................................................................ 15
•
Added the Device and Documentation Support section....................................................................................................... 17
Changes from Original (September 2011) to Revision A
•
2
Page
Added Feature Bullet: Up to 15 A Operation. ........................................................................................................................ 1
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SLPS283B – SEPTEMBER 2011 – REVISED FEBRUARY 2017
5 Specifications
5.1 Absolute Maximum Ratings
TA = 25°C (unless otherwise noted) (1)
PARAMETER
Voltage
CONDITIONS
MIN
MAX
VIN to PGND
30
VSW to PGND
30
VSW to PGND (10 ns)
UNIT
32
TG to TGR
–8
10
BG to PGND
–8
10
V
Pulsed current rating, IDM (2)
45
A
Power dissipation, PD
6
W
Avalanche energy, EAS
Sync FET, ID = 42 A, L = 0.1 mH
88
Control FET, ID = 24 A, L = 0.1 mH
29
mJ
Operating junction, TJ
–55
150
°C
Storage temperature, TSTG
–55
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated in the Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Pulse duration ≤ 50 µs, Duty cycle ≤ 0.01%.
5.2 Recommended Operating Conditions
TA = 25°C (unless otherwise noted)
PARAMETER
CONDITIONS
Gate drive voltage, VGS
MIN
MAX
4.5
8
Input supply voltage, VIN
Switching frequency, ƒSW
UNIT
V
27
CBST = 0.1 µF (min)
V
1500
Operating current
Operating temperature, TJ
kHz
15
A
125
°C
MAX
UNIT
5.3 Power Block Performance (1)
TA = 25°C (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
Power loss, PLOSS (1)
VIN = 12 V, VGS = 5 V, VOUT = 1.3 V,
IOUT = 10 A, ƒSW = 500 kHz,
LOUT = 1 µH, TJ = 25°C
1.3
W
VIN quiescent current, IQVIN
TG to TGR = 0 V BG to PGND = 0 V
10
µA
(1)
Measurement made with six 10-µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins and
using a high current 5-V driver IC.
5.4 Thermal Information
TA = 25°C (unless otherwise stated)
THERMAL METRIC
RθJA
RθJC
(1)
(2)
Junction-to-ambient thermal resistance (min Cu)
(1)
MIN
TYP
MAX
149
Junction-to-ambient thermal resistance (max Cu) (1) (2)
80
Junction-to-case thermal resistance (top of package) (1)
36
Junction-to-case thermal resistance (PGND pin)
(1)
3.1
UNIT
°C/W
°C/W
RθJC is determined with the device mounted on a 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu pad on a 1.5-in × 1.5-in
(3.81-cm × 3.81-cm), 0.06-in (1.52-mm) thick FR4 board. RθJC is specified by design while RθJA is determined by the user’s board
design.
Device mounted on FR4 material with 1-in2 (6.45-cm2) Cu.
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5.5 Electrical Characteristics
TA = 25°C (unless otherwise stated)
PARAMETER
Q1 Control FET
TEST CONDITIONS
MIN
TYP
Q2 Sync FET
MAX
MIN
TYP
MAX
UNIT
STATIC CHARACTERISTICS
BVDSS
Drain-to-source voltage
VGS = 0 V, IDS = 250 µA
IDSS
Drain-to-source leakage
current
30
30
VGS = 0 V, VDS = 20 V
IGSS
Gate-to-source leakage
current
VDS = 0 V, VGS = +10 / –8 V
VGS(th)
Gate-to-source threshold
voltage
VDS = VGS, IDS = 250 µA
ZDS(on)
Effective AC on-impedance
VIN = 12 V, VGS = 5 V,
VOUT = 1.3 V, IOUT = 10 A,
ƒSW = 500 kHz,
LOUT = 1 µH
18
5.5
mΩ
gfs
Transconductance
VDS = 15 V, IDS = 8A
26
48
S
1
V
1
1
µA
100
100
nA
1.2
V
2.1
0.8
DYNAMIC CHARACTERISTICS
CISS
Input capacitance
COSS
Output capacitance
432
518
926
1110
pF
158
190
378
454
CRSS
Reverse transfer capacitance
pF
7
9
24
30
pF
RG
Qg
Series gate resistance
5.2
6.5
0.7
1.5
Ω
Gate charge total (4.5 V)
2.7
3.2
6.4
7.7
nC
Qgd
Gate charge gate-to-drain
Qgs
Gate charge gate-to-source
Qg(th)
Gate charge at Vth
QOSS
Output charge
td(on)
Turnon delay time
tr
Rise time
td(off)
Turnoff delay time
tf
Fall time
VGS = 0 V, VDS = 15 V,
ƒ = 1 MHz
VDS = 15 V,
IDS = 8 A
VDS = 14 V, VGS = 0 V
VDS = 15 V, VGS = 4.5 V,
IDS = 8 A, RG = 2 Ω
0.4
1.1
nC
0.9
1.5
nC
0.5
0.8
nC
3.6
7.7
nC
3.4
3.8
ns
4.5
4.7
ns
7.4
11.2
ns
1.3
2.4
ns
DIODE CHARACTERISTICS
VSD
Diode forward voltage
Qrr
Reverse recovery charge
trr
Reverse recovery time
IDS = 8 A, VGS = 0 V
0.85
VDS = 14 V, IF = 8 A,
di/dt = 300 A/µs
4
5.9
nC
10
13
ns
LD
HD
LS
LG
HG
M0205-01
4
1
V
Max RθJA = 149°C/W
when mounted on
minimum pad area of
2-oz (0.071-mm) thick
Cu.
MIN Rev0
MIN Rev0
HS
86330Q3D 3.3x3.3
86330Q3D 3.3x3.3
LG
0.85
LD
HD
Max RθJA = 80°C/W
when mounted on 1 in2
(6.45 cm2) of 2-oz
(0.071-mm) thick Cu.
HG
1
HS
LS
M0206-01
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5.6 Typical Power Block Device Characteristics
Test conditions: VIN = 12 V, VDD = 5 V, ƒSW = 500 kHz, VOUT = 1.3 V, LOUT = 1 µH, IOUT = 15 A, TJ = 125°C, unless stated
otherwise.
1.4
3.5
1.3
Power Loss, Normalized
4
Power Loss (W)
3
2.5
2
1.5
1
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0
0.5
1
3
5
7
9
Output Current (A)
11
13
0.4
−50
15
20
20
15
15
10
5
0
10
20
30
40
50
60
Ambient Temperature (ºC)
70
80
25
50
75
100
Junction Temperature (ºC)
125
150
10
5
400LFM
200LFM
100LFM
Nat Conv
0
0
Figure 2. Power Loss vs Temperature
Output Current (A)
Output Current (A)
Figure 1. Power Loss vs Output Current
−25
90
Figure 3. Safe Operating Area – PCB Vertical Mount(1)
0
400LFM
200LFM
100LFM
Nat Conv
0
10
20
30
40
50
60
Ambient Temperature (ºC)
70
80
90
Figure 4. Safe Operating Area – PCB Horizontal Mount(1)
20
Output Current (A)
15
10
5
0
0
20
40
60
80
100
Board Temperature (ºC)
120
140
Figure 5. Typical Safe Operating Area(1)
(1)
The typical power block system characteristic curves are based on measurements made on a PCB design with
dimensions of 4 in (W) × 3.5 in (L) × 0.062 in (H) and 6 copper layers of 1-oz copper thickness. See Application and
Implementation section for detailed explanation.
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Typical Power Block Device Characteristics (continued)
1.6
17.1
14.3
1.5
14.3
1.4
11.4
1.4
11.4
1.3
8.6
1.3
8.6
1.2
5.7
1.2
5.7
1.1
2.9
1.1
2.9
1
0.0
1
0.0
−2.9
0.8
−5.7
0.7
−8.6
0.6
200
350
0.9
−2.9
0.8
−5.7
0.7
−8.6
0.6
−11.4
500 650 800 950 1100 1250 1400 1550
Switching Frequency (kHz)
3
9
11
13
15
Input Voltage (V)
17
19
21
23
−11.4
Figure 7. Normalized Power Loss vs Input Voltage
1.6
16.9
19.7
1.5
14.1
1.6
16.9
1.4
11.2
1.5
14.1
1.3
8.4
1.4
11.2
1.2
5.6
1.3
8.4
1.1
2.8
1.2
5.6
1.1
2.8
0.8
0.5
1
1.5
2
2.5
3
3.5
Output Voltage (V)
4
4.5
5
1
0
0.9
−2.8
0.8
−5.6
−2.8
0.7
−8.4
−5.6
5.5
0.6
0
0.9
Power Loss, Normalized
22.5
1.7
1
Figure 8. Normalized Power Loss vs Output Voltage
6
7
1.8
SOA Temperature Adj (ºC)
Power Loss, Normalized
Figure 6. Normalized Power Loss vs Switching Frequency
5
0
0.1
0.2
0.3
0.4 0.5 0.6 0.7 0.8
Output Inductance (µH)
0.9
1
SOA Temperature Adj (ºC)
0.9
SOA Temperature Adj (ºC)
17.2
1.5
Power Loss, Normalized
1.6
SOA Temperature Adj (ºC)
Power Loss, Normalized
Test conditions: VIN = 12 V, VDD = 5 V, ƒSW = 500 kHz, VOUT = 1.3 V, LOUT = 1 µH, IOUT = 15 A, TJ = 125°C, unless stated
otherwise.
−11.2
1.1
Figure 9. Normalized Power Loss vs Output Inductance
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5.7 Typical Power Block MOSFET Characteristics
TA = 25°C, unless stated otherwise.
50
IDS - Drain-to-Source Current - A
IDS - Drain-to-Source Current - A
50
40
30
20
10
0
VGS = 8.0V
VGS = 4.5V
VGS = 4.0V
0
0.2
0.4
0.6
0.8
1
1.2
40
30
20
10
0
1.4
VGS = 8.0V
VGS = 4.5V
VGS = 4.0V
0
0.1
VDS - Drain-to-Source Voltage - V
Figure 10. Control MOSFET Saturation
IDS - Drain-to-Source Current - A
IDS - Drain-to-Source Current - A
0.5
0.6
VDS = 3V
10
1
0.1
0.01
TC = 125°C
TC = 25°C
TC = −55°C
1
1.5
2
2.5
3
3.5
VGS - Gate-to-Source Voltage - V
4
10
1
0.1
0.01
0.001
TC = 125°C
TC = 25°C
TC = −55°C
0
0.5
Figure 12. Control MOSFET Transfer
1
1.5
2
2.5
VGS - Gate-to-Source Voltage - V
3
Figure 13. Sync MOSFET Transfer
8
8
ID = 8A
VDD = 15V
7
VGS - Gate-to-Source Voltage (V)
VGS - Gate-to-Source Voltage (V)
0.4
100
VDS = 3V
6
5
4
3
2
1
0
0.3
Figure 11. Sync MOSFET Saturation
100
0.001
0.2
VDS - Drain-to-Source Voltage - V
0
1
2
3
4
5
ID = 8A
VDD = 15V
7
6
5
4
3
2
1
0
0
2
Qg - Gate Charge - nC (nC)
4
6
8
10
Qg - Gate Charge - nC (nC)
Figure 14. Control MOSFET Gate Charge
Figure 15. Sync MOSFET Gate Charge
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Typical Power Block MOSFET Characteristics (continued)
1
10
0.1
1
C − Capacitance − nF
C − Capacitance − nF
TA = 25°C, unless stated otherwise.
0.01
0.001
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
0.0001
0
5
10
0.1
0.01
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
f = 1MHz
VGS = 0V
15
20
25
30
0.001
0
5
10
VDS - Drain-to-Source Voltage - V
f = 1MHz
VGS = 0V
15
20
25
Figure 16. Control MOSFET Capacitance
Figure 17. Sync MOSFET Capacitance
2
1.6
1.8
ID = 250µA
VGS(th) - Threshold Voltage - V
VGS(th) - Threshold Voltage - V
ID = 250µA
1.6
1.4
1.2
1
0.8
0.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0.4
−75
−25
25
75
125
0
−75
175
−25
TC - Case Temperature - ºC
25
75
125
Figure 18. Control MOSFET VGS(th)
Figure 19. Sync MOSFET VGS(th)
15
50
40
30
20
10
TC = 25°C
TC = 125ºC
0
1
2
3
4
5
6
7
8
9
10
ID = 8A
RDS(on) - On-State Resistance - mΩ
RDS(on) - On-State Resistance - mΩ
ID = 8A
12
9
6
3
TC = 25°C
TC = 125ºC
0
0
1
VGS - Gate-to- Source Voltage - V
Figure 20. Control MOSFET RDS(on) vs VGS
8
175
TC - Case Temperature - ºC
60
0
30
VDS - Drain-to-Source Voltage - V
2
3
4
5
6
7
8
9
10
VGS - Gate-to- Source Voltage - V
Figure 21. Sync MOSFET RDS(on) vs VGS
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Typical Power Block MOSFET Characteristics (continued)
TA = 25°C, unless stated otherwise.
1.8
1.8
Normalized On-State Resistance
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
−75
−25
25
75
125
ID = 8A
VGS = 8V
1.6
Normalized On-State Resistance
ID = 8A
VGS = 8V
1.4
1.2
1
0.8
0.6
0.4
0.2
0
−75
175
−25
TC - Case Temperature - ºC
Figure 22. Control MOSFET Normalized RDS(on)
0.1
0.01
0.001
TC = 25°C
TC = 125°C
0.4
0.6
0.8
1
1.2
ISD − Source-to-Drain Current - A
ISD − Source-to-Drain Current - A
1
175
10
1
0.1
0.01
0.001
0.0001
TC = 25°C
TC = 125°C
0
0.2
VSD − Source-to-Drain Voltage - V
0.4
0.6
0.8
1
VSD − Source-to-Drain Voltage - V
Figure 24. Control MOSFET Body Diode
Figure 25. Sync MOSFET Body Diode
100
I(AV) - Peak Avalanche Current - A
100
I(AV) - Peak Avalanche Current - A
125
100
10
10
TC = 25°C
TC = 125°C
1
0.01
75
Figure 23. Sync MOSFET Normalized RDS(on)
100
0.0001
0.2
25
TC - Case Temperature - ºC
0.1
1
10
10
TC = 25°C
TC = 125°C
1
0.01
t(AV) - Time in Avalanche - ms
Figure 26. Control MOSFET Unclamped Inductive Switching
0.1
1
10
t(AV) - Time in Avalanche - ms
Figure 27. Sync MOSFET Unclamped Inductive Switching
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6 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
6.1 Application Information
6.1.1 Equivalent System Performance
Many of today’s high-performance computing systems require low power consumption in an effort to reduce
system operating temperatures and improve overall system efficiency. This has created a major emphasis on
improving the conversion efficiency of today’s synchronous buck topology. In particular, there has been an
emphasis in improving the performance of the critical power semiconductor in the power stage of this application
(see Figure 28). As such, optimization of the power semiconductors in these applications, needs to go beyond
simply reducing RDS(ON).
Figure 28. Equivalent System Schematic
The CSD87331Q3D is part of TI’s power block product family which is a highly optimized product for use in a
synchronous buck topology requiring high current, high efficiency, and high frequency. It incorporates TI’s latest
generation silicon which has been optimized for switching performance, as well as minimizing losses associated
with QGD, QGS, and QRR. Furthermore, TI’s patented packaging technology has minimized losses by nearly
eliminating parasitic elements between the control FET and sync FET connections (see Figure 29). A key
challenge solved by TI’s patented packaging technology is the system level impact of Common Source
Inductance (CSI). CSI greatly impedes the switching characteristics of any MOSFET which in turn increases
switching losses and reduces system efficiency. As a result, the effects of CSI need to be considered during the
MOSFET selection process. In addition, standard MOSFET switching loss equations used to predict system
efficiency need to be modified in order to account for the effects of CSI. Further details behind the effects of CSI
and modification of switching loss equations are outlined in Power Loss Calculation With Common Source
Inductance Consideration for Synchronous Buck Converters (SLPA009).
10
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Application Information (continued)
Figure 29. Elimination of Parasitic Inductances
96
4
94
3.5
92
3
90
VGS = 5V
VIN = 12V
VOUT = 1.3V
LOUT = 1µH
fSW = 500kHz
TA = 25ºC
88
86
84
0
2
4
PowerBlock HS/LS RDS(ON) = 18mΩ/6.7mΩ
Discrete HS/LS RDS(ON) = 18mΩ/6.7mΩ
Discrete HS/LS RDS(ON) = 18mΩ/5.5mΩ
VGS = 5V
VIN = 12V
VOUT = 1.3V
LOUT = 1µH
fSW = 500kHz
TA = 25ºC
2.5
2
1.5
1
PowerBlock HS/LS RDS(ON) = 18mΩ/6.7mΩ
Discrete HS/LS RDS(ON) = 18mΩ/6.7mΩ
Discrete HS/LS RDS(ON) = 18mΩ/5.5mΩ
82
80
Power Loss (W)
Efficiency (%)
The combination of TI’s latest generation silicon and optimized packaging technology has created a
benchmarking solution that outperforms industry standard MOSFET chipsets of similar RDS(ON) and MOSFET
chipsets with lower RDS(ON). Figure 30 and Figure 31 compare the efficiency and power loss performance of the
CSD87331Q3D versus industry standard MOSFET chipsets commonly used in this type of application. This
comparison purely focuses on the efficiency and generated loss of the power semiconductors only. The
performance of CSD87331Q3D clearly highlights the importance of considering the effective AC on-impedance
(ZDS(ON)) during the MOSFET selection process of any new design. Simply normalizing to traditional MOSFET
RDS(ON) specifications is not an indicator of the actual in-circuit performance when using TI’s power block
technology.
6
8
10
Output Current (A)
12
0.5
14
16
0
0
Figure 30. Efficiency
2
4
6
8
10
Output Current (A)
12
14
16
Figure 31. Power Loss
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Application Information (continued)
The chart below compares the traditional DC measured RDS(ON) of CSD87331Q3D versus its ZDS(ON). This
comparison takes into account the improved efficiency associated with TI’s patented packaging technology. As
such, when comparing TI’s power block products to individually packaged discrete MOSFETs or dual MOSFETs
in a standard package, the in-circuit switching performance of the solution must be considered. In this example,
individually packaged discrete MOSFETs or dual MOSFETs in a standard package would need to have DC
measured RDS(ON) values that are equivalent to CSD87331Q3D’s ZDS(ON) value in order to have the same
efficiency performance at full load. Mid to light-load efficiency will still be lower with individually packaged discrete
MOSFETs or dual MOSFETs in a standard package.
Table 1. Comparison of RDS(ON) vs ZDS(ON)
HS
PARAMETER
LS
TYP
MAX
TYP
MAX
Effective AC on-impedance ZDS(ON) (VGS = 5 V)
18
—
5.5
—
DC measured RDS(ON) (VGS = 4.5 V)
18
22
6.7
8
The CSD87331Q3D NexFET™ power block is an optimized design for synchronous buck applications using 5-V
gate drive. The control FET and sync FET silicon are parametrically tuned to yield the lowest power loss and
highest system efficiency. As a result, a new rating method is needed which is tailored towards a more systemscentric environment. System-level performance curves such as power loss, Safe Operating Area, and normalized
graphs allow engineers to predict the product performance in the actual application.
6.1.2 Power Loss Curves
MOSFET centric parameters such as RDS(ON) and Qgd are needed to estimate the loss generated by the devices.
In an effort to simplify the design process for engineers, Texas Instruments has provided measured power loss
performance curves. Figure 1 plots the power loss of the CSD87331Q3D as a function of load current. This curve
is measured by configuring and running the CSD87331Q3D as it would be in the final application (see
Figure 32).The measured power loss is the CSD87331Q3D loss and consists of both input conversion loss and
gate drive loss. Equation 1 is used to generate the power loss curve.
Power loss = (VIN × IIN) + (VDD × IDD) – (VSW_AVG × IOUT)
(1)
The power loss curve in Figure 1 is measured at the maximum recommended junction temperatures of 125°C
under isothermal test conditions.
6.1.3 Safe Operating Area (SOA) Curves
The SOA curves in the CSD87331Q3D data sheet provides guidance on the temperature boundaries within an
operating system by incorporating the thermal resistance and system power loss. Figure 3 to Figure 5 outline the
temperature and airflow conditions required for a given load current. The area under the curve dictates the safe
operating area. All the curves are based on measurements made on a PCB design with dimensions of 4 in (W) ×
3.5 in (L) × 0.062 in (T) and 6 copper layers of 1-oz copper thickness.
6.1.4 Normalized Curves
The normalized curves in the CSD87331Q3D data sheet provides guidance on the power loss and SOA
adjustments based on their application specific needs. These curves show how the power loss and SOA
boundaries will adjust for a given set of systems conditions. The primary Y-axis is the normalized change in
power loss and the secondary Y-axis is the change is system temperature required in order to comply with the
SOA curve. The change in power loss is a multiplier for the power loss curve and the change in temperature is
subtracted from the SOA curve.
12
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6.2 Typical Application
Figure 32. Typical Application
6.2.1 Calculating Power Loss and SOA
The user can estimate product loss and SOA boundaries by arithmetic means (see Design Example section).
Though the power loss and SOA curves in this data sheet are taken for a specific set of test conditions, the
following procedure will outline the steps the user should take to predict product performance for any set of
system conditions.
6.2.1.1 Design Example
Operating conditions:
• Output current = 10 A
• Input voltage = 10 V
• Output voltage = 1 V
• Switching frequency = 1000 kHz
• Inductor = 0.4 µH
6.2.1.2 Calculating Power Loss
•
•
•
•
•
•
Power loss at 10 A = 1.8 W (Figure 1)
Normalized power loss for input voltage ≈ 1 (Figure 7)
Normalized power loss for output voltage ≈ 0.95 (Figure 8)
Normalized power loss for switching frequency ≈ 1.15 (Figure 6)
Normalized power loss for output inductor ≈ 1.04 (Figure 9)
Final calculated power loss = 1.8 W × 1.0 × 0.95 × 1.15 × 1.04 ≈ 2.05 W
6.2.1.3 Calculating SOA Adjustments
•
•
•
•
•
SOA adjustment for input voltage ≈ 0.1°C (Figure 7)
SOA adjustment for output voltage ≈ –1.3°C (Figure 8)
SOA adjustment for switching frequency ≈ 4.2°C (Figure 6)
SOA adjustment for output inductor ≈ 1°C (Figure 9)
Final calculated SOA adjustment = 0.1 + (–1.3) + 4.2 + 1 ≈ 4.8°C
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Typical Application (continued)
In the design example above, the estimated power loss of the CSD87331Q3D would increase to 2.05 W. In
addition, the maximum allowable board and/or ambient temperature would have to decrease by 4.8°C. Figure 33
graphically shows how the SOA curve would be adjusted accordingly.
1. Start by drawing a horizontal line from the application current to the SOA curve.
2. Draw a vertical line from the SOA curve intercept down to the board/ambient temperature.
3. Adjust the SOA board/ambient temperature by subtracting the temperature adjustment value.
In the design example, the SOA temperature adjustment yields a reduction in allowable board/ambient
temperature of 4.8°C. In the event the adjustment value is a negative number, subtracting the negative number
would yield an increase in allowable board/ambient temperature.
20
Output Current (A)
15
1
10
2
5
3
0
0
20
40
60
80
100
Board Temperature (°C)
120
140
Figure 33. Power Block SOA
14
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7 Layout
7.1 Layout Guidelines
There are two key system-level parameters that can be addressed with a proper PCB design: electrical and
thermal performance. Properly optimizing the PCB layout will yield maximum performance in both areas. A brief
description on how to address each parameter is provided.
7.1.1 Electrical Performance
The power block has the ability to switch voltages at rates greater than 10 kV/µs. Special care must be then
taken with the PCB layout design and placement of the input capacitors, driver IC, and output inductor.
• The placement of the input capacitors relative to the power block’s VIN and PGND pins should have the
highest priority during the component placement routine. It is critical to minimize these node lengths. As such,
ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see Figure 34).
The example in Figure 34 uses 6 × 10-µF ceramic capacitors (TDK C3216X5R1C106KT or equivalent).
Notice there are ceramic capacitors on both sides of the board with an appropriate amount of vias
interconnecting both layers. In terms of priority of placement next to the power block, C5, C7, C19, and C8
should follow in order.
• The driver IC should be placed relatively close to the power block gate pins. TG and BG should connect to the
outputs of the driver IC. The TGR pin serves as the return path of the high-side gate drive circuitry and should
be connected to the phase pin of the IC (sometimes called LX, LL, SW, PH, etc.). The bootstrap capacitor for
the driver IC will also connect to this pin.
• The switching node of the output inductor should be placed relatively close to the power block VSW pins.
Minimizing the node length between these two components will reduce the PCB conduction losses and
actually reduce the switching noise level. In the event the switch node waveform exhibits ringing that reaches
undesirable levels, the use of a boost resistor or RC snubber can be an effective way to easily reduce the
peak ring level. The recommended boost resistor value will range between 1 Ω to 4.7 Ω depending on the
output characteristics of driver IC used in conjunction with the power block. The RC snubber values can
range from 0.5 Ω to 2.2 Ω for the R and 330 pF to 2200 pF for the C. Please refer to Snubber Circuits:
Theory , Design and Application (SLUP100) for more details on how to properly tune the RC snubber values.
The RC snubber should be placed as close as possible to the Vsw node and PGND see Figure 34. (1)
7.1.2 Thermal Performance
The power block has the ability to utilize the GND planes as the primary thermal path. As such, the use of
thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder
voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount
of solder attach that will wick down the via barrel:
• Intentionally space out the vias from each other to avoid a cluster of holes in a given area.
• Use the smallest drill size allowed in your design. The example in Figure 34 uses vias with a 10-mil drill hole
and a 16-mil capture pad.
• Tent the opposite side of the via with solder-mask.
In the end, the number and drill size of the thermal vias should align with the end user’s PCB design rules and
manufacturing capabilities.
(1)
(1) Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University
of Missouri – Rolla
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7.2 Layout Example
Figure 34. Recommended PCB Layout (Top Down)
16
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8 Device and Documentation Support
8.1 Documentation Support
8.1.1 Related Documentation
For related documentation see the following:
• Power Loss Calculation With Common Source Inductance Consideration for Synchronous Buck Converters
(SLPA009)
• Snubber Circuits: Theory, Design and Application (SLUP100)
8.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
8.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
8.4 Trademarks
NexFET, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
8.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
8.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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9 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
9.1 Q3D Package Dimensions
A
E2
E1
5
9
2
7
2
D2
7
D1
E
d
e
8
1
1
8
Top View
Side View
d2
Pin 1
Designation
VIN
Pin 2
VIN
Pin 3
TG
Pin 4
TGR
Pin 5
BG
Pin 6
VSW
Pin 7
VSW
Pin 8
VSW
Pin 9
PGND
DIM
d3
c
Exposed tie clips may vary
q
M0192-01
MILLIMETERS
INCHES
MIN
MAX
MIN
MAX
A
1.400
1.500
0.055
0.059
b
0.280
0.400
0.011
0.016
c
0.150
0.250
0.006
0.010
c1
0.150
0.250
0.006
0.010
d
0.940
1.040
0.037
0.041
d1
0.160
0.260
0.006
0.010
d2
0.150
0.250
0.006
0.010
d3
0.250
0.350
0.010
0.014
D1
3.200
3.400
0.126
0.134
D2
2.650
2.750
0.104
0.108
E
3.200
3.400
0.126
0.134
E1
3.200
3.400
0.126
0.134
E2
1.750
1.850
0.069
0.073
e
0.650 TYP
0.026 TYP
L
0.400
0.500
0.016
0.020
θ
0.000
—
—
—
K
18
K
Bottom View
Pinout
Position
b
6
4
3
6
4
5
3
q
L
d1
L
c1
0.300 TYP
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9.2 Land Pattern Recommendation
1.900 (0.075)
0.200
(0.008)
0.210
(0.008)
4
0.350 (0.014)
5
0.440
(0.017)
0.650
(0.026)
2.800
(0.110)
2.390
(0.094)
8
0.210
(0.008)
1
1.090
(0.043)
0.300 (0.012)
0.650 (0.026)
0.650 (0.026)
3.600 (0.142)
M0193-01
NOTE: Dimensions are in mm (in).
9.3 Q3D Tape and Reel Information
9.3.1 Stencil Recommendation
0.160 (0.005)
0.550 (0.022)
0.200 (0.008)
5
4
0.300 (0.012)
0.300
(0.012)
0.340
(0.013)
2.290
(0.090)
0.333
(0.013)
8
1
0.990
(0.039)
0.100
(0.004)
0.300 (0.012)
0.350 (0.014)
0.850 (0.033)
3.500 (0.138)
M0207-01
NOTE: Dimensions are in mm (in).
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Q3D Tape and Reel Information (continued)
1.75 ±0.10
For recommended circuit layout for PCB designs, see Reducing Ringing Through PCB Layout Techniques
(SLPA005).
4.00 ±0.10 (See Note 1)
2.00 ±0.05
Ø 1.50
+0.10
–0.00
1.30
3.60
5.50 ±0.05
12.00
+0.30
–0.10
8.00 ±0.10
3.60
M0144-01
NOTES: 1. 10-sprocket hole-pitch cumulative tolerance ±0.2.
2. Camber not to exceed 1 mm in 100 mm, noncumulative over 250 mm.
3. Material: black static-dissipative polystyrene.
4. All dimensions are in mm, unless otherwise specified.
5. Thickness: 0.3 ±0.05 mm.
6. MSL1 260°C (IR and convection) PbF reflow compatible.
20
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
CSD87331Q3D
ACTIVE
LSON-CLIP
DQZ
8
2500
RoHS-Exempt
& Green
NIPDAU
Level-1-260C-UNLIM
-55 to 150
87331D
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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