CY74FCT827ATQCT

CY54FCT827T, CY74FCT827T 10-BIT BUFFERS WITH 3-STATE OUTPUTS SCCS034A – SEPTEMBER 1994 – REVISED OCTOBER 2001 D D D D D D description The ’FCT827T devices are 10-bit bus drivers that provide high-performance bus-interface buffering for wide data/address paths or buses carrying parity. The 10-bit buffers have NANDed output enables for maximum control flexibility. The ’FCT827T devices are designed for high-capacitance-load drive capability, while providing low-capacitance bus loading at both inputs and outputs. All outputs are designed for low-capacitance bus loading in the high-impedance state. 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 OE2 CY74FCT827T . . . L PACKAGE (TOP VIEW) 4 D2 D3 D4 NC D5 D6 D7 5 3 2 1 28 27 26 25 6 24 7 23 8 22 9 21 10 20 19 11 12 13 14 15 16 17 18 Y2 Y3 Y4 NC Y5 Y6 Y7 Y8 D OE1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 GND GND NC OE2 Y9 D CY74FCT827T . . . Q OR SO PACKAGE (TOP VIEW) D1 D0 OE1 NC VCC Y0 Y1 D Function, Pinout, and Drive Compatible With FCT, F, and AM29827 Logic Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics Ioff Supports Partial-Power-Down Mode Operation ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) 3-State Outputs Matched Rise and Fall Times Fully Compatible With TTL Input and Output Logic Levels CY54FCT827T – 32-mA Output Sink Current – 12-mA Output Source Current CY74FCT827T – 64-mA Output Sink Current – 32-mA Output Source Current D8 D9 D NC – No internal connection This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2001, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 CY54FCT827T, CY74FCT827T 10-BIT BUFFERS WITH 3-STATE OUTPUTS SCCS034A – SEPTEMBER 1994 – REVISED OCTOBER 2001 ORDERING INFORMATION QSOP – Q SOIC – SO 40°C to 85°C –40°C SPEED (ns) PACKAGE† TA QSOP – Q SOIC – SO ORDERABLE PART NUMBER Tape and reel 4.4 CY74FCT827CTQCT Tube 4.4 CY74FCT827CTSOC Tape and reel 4.4 CY74FCT827CTSOCT Tape and reel 8 CY74FCT827ATQCT Tube 8 CY74FCT827ATSOC Tape and reel 8 CY74FCT827ATSOCT TOP-SIDE MARKING FCT827C FCT827C FCT827A FCT827A –55°C to 125°C LCC – L Tube 9 CY54FCT827ATLMB † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE INPUTS D OUTPUT Y OE1 OE2 L L L L L L H H H X X Z X H X Z FUNCTION Transparent 3 state 3-state H = High logic level, L = Low logic level, X = Don’t care, Z = High-impedance state logic diagram (positive logic) OE1 OE2 D0 1 13 2 23 Y0 To Nine Other Channels Pin numbers shown are for the Q and SO packages. absolute maximum rating over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V DC input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V DC output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V DC output current (maximum sink current/pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 mA Package thermal impedance, θJA (see Note 1): Q package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61°C/W SO package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W Ambient temperature range with power applied, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 135°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CY54FCT827T, CY74FCT827T 10-BIT BUFFERS WITH 3-STATE OUTPUTS SCCS034A – SEPTEMBER 1994 – REVISED OCTOBER 2001 recommended operating conditions (see Note 2) CY54FCT827T CY74FCT827T MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.75 5 5.25 UNIT VCC VIH Supply voltage VIL IOH Low-level input voltage 0.8 0.8 V High-level output current –12 –32 mA IOL TA Low-level output current 32 64 mA 85 °C High-level input voltage 2 Operating free-air temperature 2 –55 125 V V –40 NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH CY54FCT827T TYP† MAX TEST CONDITIONS VCC = 4.5 V, VCC = 4.75 V, IIN = –18 mA IIN = –18 mA VCC = 4.5 V, IOH = –12 mA IOH = –32 mA VCC = 4 4.75 75 V MIN –0.7 –1.2 –0.7 2.4 2.4 Vhys All inputs II VCC = 5.5 V, VCC = 5.25 V, VIN = VCC VIN = VCC 5 IIH VCC = 5.5 V, VCC = 5.25 V, VIN = 2.7 V VIN = 2.7 V ±1 IIL VCC = 5.5 V, VCC = 5.25 V, VIN = 0.5 V VIN = 0.5 V ±1 IOZH VCC = 5.5 V, VCC = 5.25 V, VOUT = 2.7 V VOUT = 2.7 V 10 IOZL VCC = 5.5 V, VCC = 5.25 V, VOUT = 0.5 V VOUT = 0.5 V –10 IOS‡ VCC = 5.5 V, VCC = 5.25 V, VOUT = 0 V VOUT = 0 V VCC = 0 V, VCC = 5.5 V, VOUT = 4.5 V VIN ≤ 0.2 V, ∆ICC 0.3 3.3 0.55 IOL = 64 mA 0.3 0.2 0.55 0.2 ±1 ±1 10 –10 –120 –225 –60 –120 ±1 VIN ≥ VCC – 0.2 V VIN ≥ VCC – 0.2 V VCC = 5.25 V, VIN ≤ 0.2 V, VCC = 5.5 V, VIN = 3.4 V§, f1 = 0, Outputs open VCC = 5.25 V, VIN = 3.4 V§, f1 = 0, Outputs open 0.1 0.5 V V 5 –60 V V 2 IOH = –15 mA IOL = 32 mA VCC = 4.5 V, VCC = 4.75 V, ICC –1.2 UNIT 3.3 VOL Ioff CY74FCT827T TYP† MAX MIN –225 ±1 0.2 0.1 0.2 0.5 2 2 µA µA µA µA µA mA µA mA mA † Typical values are at VCC = 5 V, TA = 25°C. ‡ Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample-and-hold techniques are preferable to minimize internal chip heating and more accurately reflect operational values. Otherwise, prolonged shorting of a high output can raise the chip temperature well above normal and cause invalid readings in other parametric tests. In any sequence of parameter tests, IOS tests should be performed last. § Per TTL-driven input (VIN = 3.4 V); all other inputs at VCC or GND POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 CY54FCT827T, CY74FCT827T 10-BIT BUFFERS WITH 3-STATE OUTPUTS SCCS034A – SEPTEMBER 1994 – REVISED OCTOBER 2001 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) PARAMETER ICCD¶ IC# CY54FCT827T TYP† MAX TEST CONDITIONS MIN VCC = 5.5 V, One input switching at 50% duty cycle, Outputs open, OE1 or OE2 = GND, VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V VCC = 5.25 V, One input switching at 50% duty cycle, Outputs open, OE1 or OE2 = GND, VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V One bit switching VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V at f1 = 10 MHz VCC = 5.5 V, at 50% duty cycle V = 3.4 V or GND IN Outputs open, open V 10 bits switching IN ≤ 0.2 V or OE1 or OE2 = GND VIN ≥ VCC – 0.2 V at f1 = 2.5 MHz at 50% duty cycle V = 3.4 V or GND IN V One bit switching IN ≤ 0.2 V or VIN ≥ VCC – 0.2 V at f1 = 10 MHz VCC = 5.25 V, at 50% duty cycle V = 3.4 V or GND IN Outputs open, open OE1 or OE2 = GND 10 bits switching VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V at f1 = 2.5 MHz at 50% duty cycle V = 3.4 V or GND IN UNIT 0.12 mA/ MHz 0.7 1.4 1 2.4 1.6 3.2|| 4.1 13.2|| 0.06 0.12 0.7 1.4 1 2.4 1.6 3.2|| 4.1 13.2|| mA Ci 5 10 5 10 pF Co 9 12 9 12 pF ¶ This parameter is derived for use in total power-supply calculations. # IC = ICC + ∆ICC × DH × NT + ICCD (f0/2 + f1 × N1) Where: IC = Total supply current ICC = Power-supply current with CMOS input levels ∆ICC = Power-supply current for a TTL high input (VIN = 3.4 V) DH = Duty cycle for TTL inputs high NT = Number of TTL inputs at DH ICCD = Dynamic current caused by an input transition pair (HLH or LHL) f0 = Clock frequency for registered devices, otherwise zero f1 = Input signal frequency N1 = Number of inputs changing at f1 All currents are in milliamperes and all frequencies are in megahertz. || Values for these conditions are examples of the ICC formula. 4 0.06 CY74FCT827T TYP† MAX MIN POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CY54FCT827T, CY74FCT827T 10-BIT BUFFERS WITH 3-STATE OUTPUTS SCCS034A – SEPTEMBER 1994 – REVISED OCTOBER 2001 switching characteristics over operating free-air temperature range (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) TEST LOAD tPLH tPHL D Y tPLH tPHL D tPZH tPZL CY54FCT827AT CY74FCT827AT CY74FCT827CT MIN MAX MIN MAX MIN MAX CL = 50 pF,, RL = 500 Ω 1.5 9 1.5 8 1.5 4.4 1.5 9 1.5 8 1.5 4.4 Y CL = 300 pF,, RL = 500 Ω 1.5 17 1.5 15 1.5 10 1.5 17 1.5 15 1.5 10 OE Y CL = 50 pF,, RL = 500 Ω 1.5 13 1.5 12 1.5 7 1.5 13 1.5 12 1.5 7 tPZH tPZL OE Y CL = 300 pF,, RL = 500 Ω 1.5 25 1.5 23 1.5 14 1.5 25 1.5 23 1.5 14 tPHZ tPHL OE Y CL = 5 pF,, RL = 500 Ω 1.5 9 1.5 9 1.5 5.7 1.5 9 1.5 9 1.5 5.7 tPHZ tPHL OE Y CL = 50 pF, RL = 500 Ω 1.5 10 1.5 10 1.5 6 1.5 10 1.5 10 1.5 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT ns ns ns ns ns ns 5 CY54FCT827T, CY74FCT827T 10-BIT BUFFERS WITH 3-STATE OUTPUTS SCCS034A – SEPTEMBER 1994 – REVISED OCTOBER 2001 PARAMETER MEASUREMENT INFORMATION 7V From Output Under Test From Output Under Test Test Point CL = 50 pF (see Note A) Open TEST GND CL = 50 pF (see Note A) 500 Ω S1 500 Ω S1 Open 7V Open tPLH/tPHL tPLZ/tPZL tPHZ/tPZH 500 Ω LOAD CIRCUIT FOR 3-STATE OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS 3V 1.5 V Timing Input 0V tw tsu 3V 1.5 V Input 1.5 V th 3V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V Input 1.5 V 0V tPLH tPHL 1.5 V 1.5 V VOL tPHL Out-of-Phase Output tPLZ ≈3.5 V 1.5 V tPZH VOH 1.5 V VOL 1.5 V 0V Output Waveform 1 (see Note B) tPLH 1.5 V 1.5 V tPZL VOH In-Phase Output 3V Output Control Output Waveform 2 (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOL + 0.3 V VOL tPHZ 1.5 V VOH – 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) 5962-9224701M3A ACTIVE LCCC FK 28 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 59629224701M3A Samples CY74FCT827ATQCT ACTIVE SSOP DBQ 24 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 FCT827A Samples CY74FCT827ATSOC ACTIVE SOIC DW 24 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 FCT827A Samples CY74FCT827ATSOCT ACTIVE SOIC DW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 FCT827A Samples CY74FCT827CTQCT ACTIVE SSOP DBQ 24 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 FCT827C Samples CY74FCT827CTSOC ACTIVE SOIC DW 24 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 FCT827C Samples CY74FCT827CTSOCT ACTIVE SOIC DW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 FCT827C Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of