DAC34SH84IZAY

Product Folder Sample & Buy Tools & Software Technical Documents Support & Community Reference Design DAC34SH84 SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 DAC34SH84 Quad-Channel, 16-Bit, 1.5 GSPS Digital-to-Analog Converter (DAC) • • • • • • • • • • Low Power: 1.8 W at 1.5 GSPS, Full Operating Condition Multi-DAC Synchronization Selectable 2×, 4×, 8×, 16× Interpolation Filter – Stop-Band Attenuation > 90 dBc Flexible On-Chip Complex Mixing – Two Independent Fine Mixers With 32-Bit NCOs – Power-Saving Coarse Mixers: ±n × fS / 8 High-Performance, Low-Jitter Clock-Multiplying PLL Digital I and Q Correction – Gain, Phase and Offset Digital Inverse Sinc Filters 32-Bit DDR Flexible LVDS Input Data Bus – 8-Sample Input FIFO – Supports Data Rates up to 750 MSPS – Data Pattern Checker – Parity Check Temperature Sensor Differential Scalable Output: 10 mA to 30 mA 196-Ball, 12-mm × 12-mm NFBGA Digital data is input to the device through a 32-bit wide LVDS data bus with on-chip termination. The wide bus allows the processing of high-bandwidth signals. The device includes a FIFO, data pattern checker, and parity test to ease the input interface. The interface also allows full synchronization of multiple devices. The device is characterized for operation over the entire industrial temperature range of –40°C to 85°C and is available in a 196-ball, 12-mm × 12-mm, 0.8mm pitch NFBGA package. The DAC34SH84 low-power, high-bandwidth support, superior crosstalk, high dynamic range, and features are an ideal fit for next-generation communication systems. Device Information(1) PART NUMBER DAC34SH84 Simplified Schematic The DAC34SH84 is a very low-power, high-dynamic range, quad-channel, 16-bit digital-to-analog converter (DAC) with a sample rate as high as 1.5 GSPS. The device includes features that simplify the design of complex transmit architectures: 2× to 16× digital interpolation filters with over 90 dB of stop-band attenuation simplify the data interface and reconstruction filters. Independent complex mixers allow flexible carrier placement. xN LVDS Interface 3 Description DAC34SH84 32-Bit LVDS Input Data Bus Cellular Base Stations Diversity Transmit Wideband Communications BODY SIZE (NOM) 12.00 mm x 12.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 2 Applications • • • PACKAGE NFBGA (196) Complex Mixer (32-bit NCO) • 1 A high-performance low-jitter clock multiplier simplifies clocking of the device without significant impact on the dynamic range. The digital quadrature modulator correction (QMC) enables complete IQ compensation for gain, offset and phase between channels in direct upconversion applications. 16-bit DAC RF 16-bit DAC xN xN Complex Mixer (32-bit NCO) 1 Features 16-bit DAC RF 16-bit DAC xN 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DAC34SH84 SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 7 1 1 1 2 3 6 Absolute Maximum Ratings ...................................... 6 ESD Ratings.............................................................. 6 Recommended Operating Conditions....................... 7 Thermal Information .................................................. 7 Electrical Characteristics – DC Specifications .......... 7 Electrical Characteristics – Digital Specifications ..... 9 Electrical Characteristics – AC Specifications ........ 10 Timing Requirements – Digital Specifications......... 11 Switching Characteristics – AC Specifications........ 12 Typical Characteristics .......................................... 13 Detailed Description ............................................ 21 7.1 Overview ................................................................. 21 7.2 Functional Block Diagram ....................................... 22 7.3 7.4 7.5 7.6 8 Feature Description................................................. Device Functional Modes........................................ Programming .......................................................... Register Map........................................................... 23 49 53 57 Application and Implementation ........................ 74 8.1 Application Information............................................ 74 8.2 Typical Applications ............................................... 75 9 Power Supply Recommendations...................... 81 10 Layout................................................................... 82 10.1 Layout Guidelines ................................................. 82 10.2 Layout Examples................................................... 83 11 Device and Documentation Support ................. 86 11.1 11.2 11.3 11.4 11.5 11.6 Device Support...................................................... Documentation Support ....................................... Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 86 86 87 87 87 87 12 Mechanical, Packaging, and Orderable Information ........................................................... 87 4 Revision History Changes from Revision D (October 2012) to Revision E • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1 Changes from Revision C (October 2012) to Revision D • Page Page Changed from ADVANCE INFORMATION to PRODUCTION DATA .................................................................................... 1 Changes from Revision B (July 2012) to Revision C Page • Added Phase-Locked Loop section to Electrical Characteristics — Digital table................................................................. 10 • Revised the text in the Bypass Mode section ...................................................................................................................... 28 • Added reference to new PLL section in Electrical Characteristics – Digital table ................................................................ 30 • Added a sentence to the last paragraph in the Data Pattern Checker section .................................................................... 41 • Changed version register ..................................................................................................................................................... 58 • Changed contents of version register................................................................................................................................... 73 Changes from Revision A (June 2012) to Revision B Page • Added thermal information to the Absolute Maximum Ratings table ..................................................................................... 6 • Added Recommended Operating Conditions table ................................................................................................................ 7 • Deleted OPERATING RANGE section from bottom of Electrical Characteristics - DC Specifications table ......................... 9 • Changed DAC Wake-up Time in Electrical Characteristics – AC Specifications ................................................................. 12 2 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 DAC34SH84 www.ti.com SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 5 Pin Configuration and Functions ZAY Package 196-Pin NFBGA Top View A B C D E F G H J K L M N P 14 GND IOUT AP IOUT AN GND IOUT BN IOUT BP GND GND IOUT CP IOUT CN GND IOUT DN IOUT DP GND 13 GND GND GND GND GND GND GND GND GND GND GND GND GND GND 12 DAC CLKP GND CLK VDD LPF GND GND EXTIO BIASJ GND CLK VDD IO VDD2 GND ALARM SDO 11 DAC CLKN GND PLL AVDD PLL AVDD AVDD AVDD AVDD AVDD AVDD AVDD TEST MODE GND SLEEP SDIO 10 GND GND GND AVDD DAC VDD DAC VDD DAC VDD DAC VDD DAC VDD DAC VDD AVDD GND RESET SDENB B 9 OSTR P OSTR N GND DAC VDD DAC VDD GND GND GND GND DAC VDD DAC VDD GND TXENA 8 SYNC P SYNC N GND GND GND GND GND GND GND GND GND GND PARITY PARITY CDP CDN 7 DAB 15P DAB 15N GND VFUSE DIG VDD GND GND GND GND DIG VDD VFUSE GND DCD 0P DCD 0N 6 DAB 14P DAB 14N GND IO VDD DIG VDD GND GND GND GND DIG VDD IO VDD GND DCD 1P DCD 1N 5 DAB 13P DAB 13N GND IO VDD DIG VDD DIG VDD IO VDD IO VDD DIG VDD DIG VDD IO VDD GND DCD 2P DCD 2N 4 DAB 12P DAB 12N DAB 8P DAB 6P DAB 4P DAB 2P DAB 0P DCD 15P DCD 14P DCD 12P DCD 10P DCD 8P DCD 3P DCD 3N 3 DAB 11P DAB 11N DAB 8N DAB 6N DAB 4N DAB 2N DAB 0N DCD 15N DCD 14N DCD 12N DCD 10N DCD 8N DCD 4P DCD 4N 2 DAB 10P DAB 10N DAB 7P DAB 5P DAB 3P DAB 1P ISTR/ DATA PARITY CLKP ABP DCD 13P DCD 11P DCD 9P DCD 7P DCD 5P DCD 5N 1 DAB 9P DAB 9N DAB 7N DAB 5N DAB 3N DAB 1N ISTR/ DATA PARITY CLKN ABN DCD 13N DCD 11N DCD 9N DCD 7N DCD 6P DCD 6N DAC Output Data Input 3.3V Supply Clock Input CMOS Pins 1.2V Supply (except for IOVDD2) Sync/Parity Input Miscellaneous Ground SCLK P0134-01 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 3 DAC34SH84 SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 www.ti.com Pin Functions PIN I/O DESCRIPTION NAME NO. AVDD D10, E11, F11, G11, H11, J11, K11, L10 I Analog supply voltage. (3.3 V) ALARM N12 O CMOS output for ALARM condition. The ALARM output functionality is defined through the config7 register. Default polarity is active-high, but can be changed to active-low via the config0 alarm_out_pol control bit. BIASJ H12 O Full-scale output current bias. For 30-mA full-scale output current, connect 1.28 kΩ to ground. Change the full-scale output current through coarse_dac(3:0) in config3, bit. C12, K12 I Internal clock buffer supply voltage. (1.35 V). It is recommended to isolate this supply from DIGVDD and DACVDD. CLKVDD LVDS positive input data bits 0 through 15 for the AB-channel path. Internal 100-Ω termination resistor. Data format relative to DATACLKP/N clock is double data rate (DDR). A7, A6, A5, A4, A3, A2, A1, C4, C2, D4, D2, E4, E2, F4, F2, G4 I DAB[15..0]N B7, B6, B5, B4, B3, B2, B1, C3, C1, D3, D1, E3, E1, F3, F1, G3 I DCD[15..0]P H4, J4, J2, K4, K2, L4, L2, M4, M2, N1, N2, N3, N4, N5, N6, N7 I H3, J3, J1, K3, K1, L3, L1, M3, M1, P1, P2, P3, P4, P5, P6, P7 I LVDS negative input data bits 0 through 15 for the CD-channel path. (See the preceding DCD[15:0]P description.) DACCLKP A12 I Positive external LVPECL clock input for DAC core with a self-bias DACCLKN A11 I Complementary external LVPECL clock input for DAC core. (See the DACCLKP description.) DACVDD D9, E9, E10, F10, G10, H10, J10, K10, K9, L9 I DAC core supply voltage. (1.35 V). It is recommended to isolate this supply from CLKVDD and DIGVDD. DATACLKP G2 I LVDS positive input data clock. Internal 100-Ω termination resistor. Input data DAB[15:0]P/N and DCD[15:0]P/N are latched on both edges of DATACLKP/N (double data rate). DATACLKN G1 I LVDS negative input data clock. (See the DATACLKP description.) E5, E6, E7, F5, J5, K5, K6, K7 I Digital supply voltage. (1.3 V). It is recommended to isolate this supply from CLKVDD and DACVDD. G12 I/O DAB[15..0]P DCD[15..0]N DIGVDD EXTIO DAB15P is the most-significant data bit (MSB). DAB0P is the least-significant data bit (LSB). The order of the bus can be reversed via the config2 revbus bit. LVDS negative input data bits 0 through 15 for the AB-channel path. (See the preceding DAB[15:0]P description.) LVDS positive input data bits 0 through 15 for the CD-channel path. Internal 100-Ω termination resistor. Data format relative to DATACLKP/N clock is double data rate (DDR). DCD15P is the most-significant data bit (MSB). DCD0P is the least-significant data bit (LSB). The order of the bus can be reversed via the config2 revbus bit. Used as an external reference input when the internal reference is disabled through config27 extref_ena = 1. Used as an internal reference output when config27 extref_ena = 0 (default). Requires a 0.1-μF decoupling capacitor to AGND when used as a reference output. ISTRP/ PARITYABP H2 I LVDS input strobe positive input. Internal 100-Ω termination resistor The main functions of this input are to sync the FIFO pointer, to provide a sync source to the digital blocks, and/or to act as a parity input for the AB-data bus. These functions are captured with the rising edge of DATACLKP/N. This signal should be edgealigned with DAB[15:0]P/N and DCD[15:0]P/N. The PARITY, SYNC, and ISTR inputs are rotated to allow complete reversal of the data interface when setting the rev_interface bit in register config1. ISTRN/ PARITYABN H1 I LVDS input strope negative input. (See the ISTRP/PARITYABP description.) 4 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 DAC34SH84 www.ti.com SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 Pin Functions (continued) PIN NAME NO. I/O DESCRIPTION A10, A13, A14, B10, B11, B12, B13, C5, C6, C7, C8, C9, C10, C13, D8, D13, D14, E8, E12, E13, F6, F7, F8, F9, F12, F13, G6, G7, G8, G9, G13, G14, H6, H7, H8, H9, H13, H14, J6, J7, J8, J9, J12, J13, K8, K13, L8, L13, L14, M5, M6, M7, M8, M9, M10, M11, M12, M13, N13, P13, P14 I These pins are ground for all supplies. IOUTAP B14 O A-channel DAC current output. Connect directly to ground if unused. IOUTAN C14 O A-channel DAC complementary current output. Connect directly to ground if unused. IOUTBP F14 O B-channel DAC current output. Connect directly to ground if unused. IOUTBN E14 O B-channel DAC complementary current output. Connect directly to ground if unused. IOUTCP J14 O C-channel DAC current output. Connect directly to ground if unused. IOUTCN K14 O C-channel DAC complementary current output. Connect directly to ground if unused. IOUTDP N14 O D-channel DAC current output. Connect directly to ground if unused. IOUTDN M14 O D-channel DAC complementary current output. Connect directly to ground if unused. IOVDD D5, D6, G5, H5, L5. L6 I Supply voltage for all LVDS I/O. (3.3 V) IOVDD2 L12 I Supply voltage for all CMOS I/O. (1.8 V to 3.3 V) This supply can range from 1.8 V to 3.3 V to change the input and output levels of the CMOS I/O. LPF D12 I/O PLL loop filter connection. If not using the clock-multiplying PLL, the LPF pin can be left unconnected. OSTRP A9 I Optional LVPECL output strobe positive input. This positive-negative pair is captured with the rising edge of DACCLKP/N. It is used to sync the divided-down clocks and FIFO output pointer in dualsync-sources mode. If unused it can be left unconnected. OSTRN B9 I Optional LVPECL output strobe negative input. (See the OSTRP description.) PARITYCDP N8 I Optional LVDS positive input parity bit for the CD-data bus. The PARITYCDP/N LVDS pair has an internal 100-Ω termination resistor. If unused, it can be left unconnected. The PARITY, SYNC, and ISTR inputs are rotated to allow complete reversal of the data interface when setting the rev_interface bit in register config1. PARITYCDN P8 I Optional LVDS negative input parity bit for the CD-data bus. GND PLLAVDD C11, D11 I PLL analog supply voltage (3.3 V) SCLK P9 I Serial interface clock. Internal pulldown SDENB P10 I Active-low serial data enable, always an input to the DAC34SH84. Internal pullup SDIO P11 I/O Serial interface data. Bidirectional in 3-pin mode (default) and unidirectional 4-pin mode. Internal pulldown SDO P12 O Unidirectional serial interface data in 4-pin mode. The SDO pin is in the high-impedance state in 3-pin interface mode (default). SLEEP N11 I Active-high asynchronous hardware power-down input. Internal pulldown Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 5 DAC34SH84 SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 www.ti.com Pin Functions (continued) PIN I/O DESCRIPTION NAME NO. SYNCP A8 I LVDS SYNC positive input. Internal 100-Ω termination resistor. If unused it can be left unconnected. The PARITY, SYNC, and ISTR inputs are rotated to allow complete reversal of the data interface when setting the rev_interface bit in register config1. SYNCN B8 I LVDS SYNC negative input RESETB N10 I Active-low input for chip RESET. Internal pullup TXENA N9 I Transmit enable active-high input. Internal pulldown To enable analog output data transmission, set sif_txenable in register config3 to 1 or pull the CMOS TXENA pin to high. To disable analog output, set sif_txenable to 0 and pull the CMOS TXENA pin to low. The DAC output is forced to midscale. TESTMODE L11 I This pin is used for factory testing. Internal pulldown. Leave unconnected for normal operation D7, L7 I Digital supply voltage. This supply pin is also used for factory fuse programming. Connect to DACVDD or DIGVDD for normal operation VFUSE 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) Supply voltage range (2) Pin voltage range (2) MIN MAX UNIT DACVDD, DIGVDD, CLKVDD –0.5 1.5 V VFUSE –0.5 1.5 V IOVDD, IOVDD2 –0.5 4 V AVDD, PLLAVDD –0.5 4 V DAB[15..0]P/N, DCD[15..0]P/N, DATACLKP/N, ISTRP/N, PARITYCDP/N, SYNCP/N –0.5 IOVDD + 0.5 V DACCLKP/N, OSTRP/N –0.5 CLKVDD + 0.5 V ALARM, SDO, SDIO, SCLK, SDENB, SLEEP, RESETB, TESTMODE, TXENA –0.5 IOVDD2 + 0.5 V IOUTAP/N, IOUTBP/N, IOUTCP/N, IOUTDP/N –1.0 AVDD + 0.5 V EXTIO, BIASJ –0.5 AVDD + 0.5 V LPF –0.5 PLLAVDD + 0.5 V Peak input current (any input) 20 mA Peak total input current (all inputs) –30 mA 150 °C 150 °C Absolute maximum junction temperature, TJ Storage temperature range, Tstg (1) (2) –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Measured with respect to GND 6.2 ESD Ratings VALUE V(ESD) (1) (2) 6 Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 DAC34SH84 www.ti.com SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 6.3 Recommended Operating Conditions MIN TJ TA (1) NOM MAX Recommended operating junction temperature UNIT 105 Maximum rated operating junction temperature (1) 125 Recommended free-air temperature –40 25 °C 85 °C Prolonged use at this junction temperature may increase the device failure-in-time (FIT) rate. 6.4 Thermal Information DAC34SH84 THERMAL METRIC (1) ZAY (NFBGA) UNIT 196 PINS RθJA Junction-to-ambient thermal resistance 37.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 6.8 °C/W RθJB Junction-to-board thermal resistance 16.8 °C/W ψJT Junction-to-top characterization parameter 0.2 °C/W ψJB Junction-to-board characterization parameter 16.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance NA °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 6.5 Electrical Characteristics – DC Specifications over recommended operating free-air temperature range, nominal supplies, IOUTFS = 20 mA (unless otherwise noted) (1) PARAMETER TEST CONDITIONS Resolution MIN TYP MAX UNIT 16 Bits DC ACCURACY DNL Differential nonlinearity INL Integral nonlinearity 1 LSB = IOUTFS / 216 ±2 LSB ±4 LSB ANALOG OUTPUT Coarse gain linearity Offset error Gain error Gain mismatch ±0.04 LSB ±0.001 %FSR With external reference ±2 %FSR With internal reference ±2 %FSR With internal reference ±2 Mid-code offset Full-scale output current 10 Output compliance range 20 –0.5 Output resistance Output capacitance %FSR 30 0.6 mA V 300 kΩ 5 pF REFERENCE OUTPUT VREF Reference output voltage 1.2 V Reference output current (2) 100 nA REFERENCE INPUT VEXTIO Input voltage range Input resistance (1) (2) External reference mode 0.6 1.2 1.25 V 1 MΩ Small-signal bandwidth 472 kHz Input capacitance 100 pF Measured differentially across IOUTP/N with 25 Ω each to GND. Use an external buffer amplifier with high-impedance input to drive any external load. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 7 DAC34SH84 SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 www.ti.com Electrical Characteristics – DC Specifications (continued) over recommended operating free-air temperature range, nominal supplies, IOUTFS = 20 mA (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEMPERATURE COEFFICIENTS Offset drift Gain drift ±1 ppm / °C With external reference ±15 ppm / °C With internal reference ±30 ppm / °C ±8 ppm / °C Reference voltage drift POWER SUPPLY (3) AVDD, IOVDD, PLLAVDD 3.14 DIGVDD CLKVDD, DACVDD IOVDD2 PSRR Power-supply rejection ratio DC tested 3.3 3.46 V 1.25 1.3 1.35 V 1.3 1.35 1.4 V 1.71 3.3 3.45 V ±0.25 %FSR / V POWER CONSUMPTION Analog supply current (4) I(AVDD) I(DIGVDD) Digital supply current I(DACVDD) DAC supply current I(CLKVDD) Clock supply current P Power dissipation I(AVDD) Analog supply current (4) I(DIGVDD) Digital supply current I(DACVDD) DAC supply current I(CLKVDD) Clock supply current P Power dissipation I(AVDD) Analog supply current (4) I(DIGVDD) Digital supply current I(DACVDD) DAC supply current I(CLKVDD) Clock supply current P Power dissipation I(AVDD) Analog supply current (4) I(DIGVDD) Digital supply current I(DACVDD) DAC supply current I(CLKVDD) Clock supply current P Power dissipation I(AVDD) Analog supply current (4) I(DIGVDD) Digital supply current I(DACVDD) DAC supply current I(CLKVDD) Clock supply current P Power dissipation I(AVDD) Analog supply current (4) I(DIGVDD) Digital supply current I(DACVDD) DAC supply current I(CLKVDD) Clock supply current P Power dissipation (3) (4) 8 Mode 1 fDAC = 1.5 GSPS, 2× interpolation, mixer on, QMC on, invsinc on, PLL enabled, 20-mA FS output, IF = 200 MHz Mode 2 fDAC = 1.47456 GSPS, 2× interpolation, mixer on, QMC on, invsinc on, PLL disabled, 20-mA FS output, IF = 7.3 MHz Mode 3 fDAC = 737.28 MSPS, 2x interpolation, mixer on, QMC on, invsinc off, PLL disabled, 20-mA FS output, IF = 7.3 MHz Mode 4 fDAC = 1.47456 GSPS, 2× interpolation, mixer on, QMC on, invsinc on, PLL enabled, IF = 7.3 MHz, channels A/B/C/D output sleep Mode 5 Power-down mode: no clock, DAC on sleep mode (clock receiver sleep), channels A/B/C/D output sleep, static data pattern Mode 6 fDAC = 1 GSPS, 2x interpolation, mixer off, QMC off, invsinc off, PLL enabled, 20-mA FS output, IF = 7.3 MHz 135 165 mA 885 950 mA 45 60 mA 127 145 mA 1828 2056 mW 115 mA 770 mA 40 mA 95 mA 1562 mW 115 mA 470 mA 21 mA 55 mA 1093 mW 40 mA 710 mA 50 mA 90 mA 1160 mW 28 mA 17 mA 0 mA 20 mA 142 mW 130 mA 570 mA 25 mA 98 mA 1336 mA To ensure power supply accuracy and to account for power supply filter network loss at operating conditions, the use of the ATEST function in register config27 to check the internal power supply nodes is recommended. Includes AVDD, PLLAVDD, and IOVDD Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 DAC34SH84 www.ti.com SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 Electrical Characteristics – DC Specifications (continued) over recommended operating free-air temperature range, nominal supplies, IOUTFS = 20 mA (unless otherwise noted) PARAMETER TEST CONDITIONS I(AVDD) Analog supply current I(DIGVDD) Digital supply current I(DACVDD) DAC supply current I(CLKVDD) Clock supply current P Power dissipation I(AVDD) Analog supply current (4) I(DIGVDD) Digital supply current I(DACVDD) DAC supply current I(CLKVDD) Clock supply current P Power dissipation MIN TYP MAX (4) Mode 7 fDAC = 1 GSPS, 2x interpolation, mixer off,QMC off, invsinc off, PLL disabled, 20-mA FS output, IF = 7.3 MHz Mode 8 fDAC = 1.47456 GSPS, 2× interpolation, mixer on, QMC on, invsinc on, PLL disabled, IF = 7.3 MHz, channels A/B/C/D output sleep UNIT 115 mA 335 mA 23 mA 70 mA 940 mW 45 mA 655 mA 30 mA 95 mA 1169 mW 6.6 Electrical Characteristics – Digital Specifications over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LVDS INPUTS: DAB[15:0]P/N, DCD[15:0]P/N, DATACLKP/N, ISTRP/N, SYNCP/N, PARITYCDP/N (1) VA,B+ Logic-high differential input voltage threshold VA,B– Logic-low differential input voltage threshold VCOM Input common mode 1 1.2 1.6 V ZT Internal termination 85 110 135 Ω CL LVDS input capacitance fINTERL Interleaved LVDS data transfer rate fDATA Input data rate 200 mV –200 2 mV pF 1500 MSPS 750 MSPS CLOCK INPUT (DACCLKP/N) Differential voltage (2) |DACCLKP - DACCLKN| 0.4 Internally biased common-mode voltage Single-ended swing level 1 V 0.2 V –0.4 V OUTPUT STROBE (OSTRP/N) Differential voltage |OSTRP-OSTRN| 0.4 Internally biased common-mode voltage Single-ended swing level 1.0 V 0.2 V –0.4 V 0.7 × IOVDD2 V CMOS INTERFACE: ALARM, SDO, SDIO, SCLK, SDENB, SLEEP, RESETB, TXENA VIH High-level input voltage VIL Low-level input voltage IIH High-level input current (1) (2) –40 0.3 × IOVDD2 V 40 µA See LVDS Inputs section for terminology. Driving the clock input with a differential voltage lower than 1 V may result in degraded performance. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 9 DAC34SH84 SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 www.ti.com Electrical Characteristics – Digital Specifications (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER IIL Low-level input current CI CMOS input capacitance TEST CONDITIONS MIN Iload = –2 mA ALARM, SDO, SDIO 40 2 ALARM, SDO, SDIO VOL MAX –40 Iload = –100 μA VOH TYP UNIT µA pF IOVDD2 – 0.2 V 0.8 × IOVDD2 V Iload = 100 μA 0.2 V Iload = 2 mA 0.5 V PHASE-LOCKED LOOP PLL/VCO operating frequency PLL_vco = 011110 (30) 2940 2957 PLL_vco = 100010 (34) 2957 3000 PLL_vco = 100110 (38) 3000 3043 PLL_vco = 101010 (42) 3034 3086 PLL_vco = 101110 (46) 3069 3120 PLL_vco = 110010 (50) 3103 3163 PLL_vco = 110110 (54) 3128 3215 PLL_vco = 111010 (58) 3170 3257 PLL_vco = 111111 (63) 3215 3300 MHz 6.7 Electrical Characteristics – AC Specifications over recommended operating free-air temperature range, nominal supplies, IOUTFS = 20 mA (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AC PERFORMANCE (1) Spurious-free dynamic range, (0 to fDAC / 2) tone at 0 dBFS SFDR fDAC = 1.5 GSPS, fOUT = 20 MHz 78 fDAC = 1.5 GSPS, fOUT = 50 MHz 74 fDAC = 1.5 GSPS, fOUT = 70 MHz 71 Third-order two-tone intermodulation distortion, each tone at –12 dBFS fDAC = 1.5 GSPS, fOUT = 30 ± 0.5 MHz 87 IMD3 fDAC = 1.5 GSPS, fOUT = 50 ± 0.5 MHz 85 NSD Noise spectral density, (2) tone at 0 dBFS fDAC = 1.5 GSPS, fOUT = 10 MHz 160 fDAC = 1.5 GSPS, fOUT = 80 MHz 158 Adjacent-channel leakage ratio, single carrier fDAC = 1.47456 GSPS, fOUT = 30 MHz 76 fDAC = 1.47456 GSPS, fOUT = 153 MHz 75 Alternate-channel leakage ratio, single carrier fDAC = 1.47456 GSPS, fOUT = 30 MHz 86 Channel isolation fDAC = 1.5 GSPS, fOUT = 40 MHz ACLR (2) (1) (2) 10 fDAC = 1.5 GSPS, fOUT = 100 ± 0.5 MHz fDAC = 1.47456 GSPS, fOUT = 153 MHz dBc dBc 78 dBc / Hz dBc 82 101 dBc 4:1 transformer output termination, 50-Ω doubly terminated load Single carrier, W-CDMA with 3.84-MHz BW, 5-MHz spacing, centered at IF, PAR = 12 dB. TESTMODEL 1, 10 ms Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 DAC34SH84 www.ti.com SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 6.8 Timing Requirements – Digital Specifications MIN NOM MAX UNIT CLOCK INPUT (DACCLKP/N) Duty cycle 40% 60% DACCLKP/N input frequency 1500 MHz fDACCLK / (8 x interp) MHz OUTPUT STROBE (OSTRP/N) fOSTR Frequency fOSTR = fDACCLK / (n x 8 x Interp) where n is any positive integer, fDACCLK is DACCLK frequency in MHz Duty cycle 50% DIGITAL INPUT TIMING SPECIFICATIONS Timing LVDS inputs: DAB[15:0]P/N, DCD[15:0]P/N, ISTRP/N, SYNCP/N, PARITYCDP/N, double edge latching Config36 Setting ts(DATA) Setup time, DAB[15:0]P/N, DCD[15:0]P/N, ISTRP/N, SYNCP/N and PARITYP/N, valid to either edge of DATACLKP/N ISTRP/N and SYNCP/N reset latched only on rising edge of DATACLKP/N datadly clkdly 0 0 30 0 1 –10 0 2 –50 0 3 –90 0 4 –130 0 5 –170 0 6 –210 0 7 –250 1 0 50 2 0 90 3 0 130 4 0 170 5 0 210 6 0 250 7 0 290 ps Config36 Setting th(DATA) t(ISTR_SYNC) Hold time, DAB[15:0]P/N, DCD[15:0]P/N, ISTRP/N, ISTRP/N and SYNCP/N reset latched SYNCP/N and only on rising edge of DATACLKP/N PARITYP/N, valid after either edge of DATACLKP/N ISTRP/N and SYNCP/N pulse width datadly clkdly 0 0 200 0 1 240 0 2 280 0 3 320 0 4 360 0 5 400 0 6 440 0 7 480 1 0 190 2 0 150 3 0 110 4 0 70 5 0 30 6 0 –10 7 0 –50 fDATACLK is DATACLK frequency in MHz 1/2fDATACLK Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 ps ns 11 DAC34SH84 SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 www.ti.com Timing Requirements – Digital Specifications (continued) MIN NOM MAX UNIT TIMING OUTPUT STROBE INPUT: DACCLKP/N rising edge LATCHING (1) ts(OSTR) Setup time, OSTRP/N valid to rising edge of DACCLKP/N –80 ps th(OSTR) Hold time, OSTRP/N valid after rising edge of DACCLKP/N 220 ps TIMING SYNC INPUT: DACCLKP/N rising edge LATCHING (2) ts(SYNC_PLL) Setup time, SYNCP/N valid to rising edge of DACCLKP/N 150 ps th(SYNC_PLL) Hold time, SYNCP/N valid after rising edge of DACCLKP/N 250 ps TIMING SERIAL PORT ts(SDENB) Setup time, SDENB to rising edge of SCLK 20 ns ts(SDIO) Setup time, SDIO valid to rising edge of SCLK 10 ns th(SDIO) Hold time, SDIO valid to rising edge of SCLK 5 ns 1 µs 100 ns Register config6 read (temperature sensor read) t(SCLK) Period of SCLK td(Data) Data output delay after falling edge of SCLK 10 ns tRESET Minimum RESETB pulse width 25 ns (1) (2) All other registers OSTR is required in Dual Sync Sources mode. In order to minimize the skew it is recommended to use the same clock distribution device such as Texas Instruments CDCE62005 to provide the DACCLK and OSTR signals to all the DAC34H84 devices in the system. Swap the polarity of the DACCLK outputs with respect to the OSTR ones to establish proper phase relationship. SYNC is required to synchronize the PLL circuit in multiple devices. The SYNC signal must meet the timing relationship with respect to the reference clock (DACCLKP/N) of the on-chip PLL circuit. 6.9 Switching Characteristics – AC Specifications over recommended operating free-air temperature range, nominal supplies, IOUTFS = 20 mA (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG OUTPUT (1) ts(DAC) Output settling time to 0.1% Transition: Code 0x0000 to 0xFFFF 10 ns tpd Output propagation delay 2 ns tr(IOUT) Output rise time 10% to 90% 220 ps tf(IOUT) Output fall time 90% to 10% 220 ps Digital latency Power-up Time DAC outputs are updated on the falling edge of DAC clock. Does not include Digital Latency (see below). No interpolation, FIFO on, Mixer off, QMC off, Inverse sinc off 128 2x Interpolation 216 4x Interpolation 376 8x Interpolation 726 16x Interpolation 1427 Fine mixer 24 QMC 16 Inverse sinc 20 DAC wake-up time IOUT current settling to 1% of IOUTFS from output sleep 2 DAC sleep time IOUT current settling to less than 1% of IOUTFS in output sleep 2 (1) Measured single ended into 50-Ω load. 12 Submit Documentation Feedback DAC clock cycles µs Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 DAC34SH84 www.ti.com SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 6.10 Typical Characteristics 6 5 5 4 Differential Nonlinearity Error (LSB) Integral Nonlinearity Error (LSB) All plots are at 25°C, nominal supply voltage, fDAC = 1500 MSPS, 2× interpolation, NCO enabled, mixer gain disabled, QMC enabled with gain set at 1446 for both I/Q channels, 0-dBFS digital input, 20-mA full-scale output current with 4:1 transformer (unless otherwise noted) 4 3 2 1 0 −1 −2 −3 −4 −5 −6 0 10k 20k 30k Code 40k 50k 3 2 1 0 −1 −2 −3 −4 −5 60k 0 Figure 1. Integral Nonlinearity SFDR (dBc) Second Order Harmonic Distortion (dB) 0dBFS −6dBFS −12dBFS 70 60 50 40 30 20 10 0 100 200 300 400 Output Frequency (dB) 500 600 40k 50k 60k 0dBFS −6dBFS −12dBFS 90 80 70 60 50 40 30 20 0 100 200 300 400 Output Frequency (MHz) 500 600 G004 Figure 4. Second-Harmonic Distortion vs Output Frequency Over Input Scale 110 110 0dBFS −6dBFS −12dBFS 100 90 90 80 70 60 80 70 60 50 50 40 40 0 100 200 300 400 Output Frequency (MHz) 500 FDAC = 750 MSPS, 1x interpolation FDAC = 1500 MSPS, 2x interpolation FDAC = 1500 MSPS, 4x interpolation FDAC = 1500 MSPS, 8x interpolation FDAC = 1500 MSPS, 16x interpolation 100 SFDR (dBc) Third−Order Harmonic Distortion (dB) 30k Code 100 G003 Figure 3. SFDR vs Output Frequency Over Input Scale 30 20k Figure 2. Differential Nonlinearity 90 80 10k 600 30 0 G005 Figure 5. Third Harmonic Distortion vs Output Frequency Over Input Scale 100 200 300 400 Output Frequency (MHz) 500 600 G006 Figure 6. SFDR vs Output Frequency Over Interpolation Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 13 DAC34SH84 SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 www.ti.com Typical Characteristics (continued) All plots are at 25°C, nominal supply voltage, fDAC = 1500 MSPS, 2× interpolation, NCO enabled, mixer gain disabled, QMC enabled with gain set at 1446 for both I/Q channels, 0-dBFS digital input, 20-mA full-scale output current with 4:1 transformer (unless otherwise noted) 100 100 fDAC = 800 MSPS fDAC = 1000 MSPS fDAC = 1200 MSPS fDAC = 1500 MSPS 90 80 SFDR (dBc) SFDR (dBc) 80 70 60 50 60 50 40 30 30 0 100 200 300 Output Frequency (MHz) 400 20 500 −10 −10 −20 −30 −40 500 G008 −50 −30 −40 −50 −60 −60 −70 −70 −80 −80 10 110 210 310 410 510 Frequency (MHz) 610 710 −90 800 10 110 210 G009 Figure 9. Single-Tone Spectral Plot 310 410 510 Frequency (MHz) 610 710 800 G010 Figure 10. Single-Tone Spectral Plot 10 10 fDAC = 1500 MSPS fout = 150 MHz 0 −10 −10 −20 −20 −30 −40 −50 −30 −40 −50 −60 −60 −70 −70 −80 −80 10 110 210 310 410 510 Frequency (MHz) 610 710 fDAC = 1500 MSPS fout = 200 MHz 0 Power (dBm) Power (dBm) 400 NCO bypassed QMC bypassed fDAC = 1500 MSPS fout = 70 MHz 0 Power (dBm) −20 800 −90 10 G011 Figure 11. Single-Tone Spectral Plot 14 200 300 Output Frequency (MHz) 10 NCO bypassed QMC bypassed fDAC = 1500 MSPS fout = 20 MHz 0 −90 100 Figure 8. SFDR vs Output Frequency Over IOUTFS 10 −90 0 G007 Figure 7. SFDR vs Output Frequency Over fDAC Power (dBm) 70 40 20 Iout FS = 10 mA, 4:1 Transformer Iout FS = 20 mA, 4:1 Transformer Iout FS = 30 mA, 2:1 Transformer 90 Submit Documentation Feedback 110 210 310 410 510 Frequency (MHz) 610 710 800 G012 Figure 12. Single-Tone Spectral Plot Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 DAC34SH84 www.ti.com SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 Typical Characteristics (continued) All plots are at 25°C, nominal supply voltage, fDAC = 1500 MSPS, 2× interpolation, NCO enabled, mixer gain disabled, QMC enabled with gain set at 1446 for both I/Q channels, 0-dBFS digital input, 20-mA full-scale output current with 4:1 transformer (unless otherwise noted) 100 10 PLL enabled w/ PFD of 46.875 MHz fDAC = 1500 MSPS fout = 200 MHz 0 −10 80 SFDR (dBc) Power (dBm) −20 −30 −40 −50 −60 10 110 210 310 410 510 Frequency (MHz) 610 710 50 20 800 200 300 400 Output Frequency (MHz) 500 600 G014 100 0dB FS −6dB FS −12dB FS 90 80 90 80 IMD3 (dB) 70 60 50 70 60 50 40 40 30 30 0 100 200 300 400 Output Frequency (MHz) 500 20 600 90 90 80 80 70 70 IMD3 (dBc) 100 60 50 fDAC = 800 MSPS fDAC = 1000 MSPS fDAC = 1200 MSPS fDAC = 1500 MSPS 30 0 100 200 300 Output Frequency (MHz) 0 100 200 300 400 Output Frequency (MHz) 500 600 G016 Figure 16. IMD3 vs Output Frequency Over Interpolation 100 40 FDAC = 750 MSPS, 1x interpolation FDAC = 1500 MSPS, 2x interpolation FDAC = 1500 MSPS, 4x interpolation FDAC = 1500 MSPS, 8x interpolation FDAC = 1500 MSPS, 16x interpolation G015 Figure 15. IMD3 vs Output Frequency Over Input Scale 20 100 Figure 14. SFDR vs Output Frequency Over Clocking Options 100 20 0 G013 Figure 13. Single-Tone Spectral Plot IMD3 (dBc) 60 30 −80 IMD3 (dB) 70 40 −70 −90 PLL disabled PLL enabled w/ PFD of 46.875 MHz 90 Iout FS = 10 mA, 4:1 Transformer Iout FS = 20 mA, 4:1 Transformer Iout FS = 30 mA, 2:1 Transformer 60 50 40 30 400 500 20 0 G017 Figure 17. IMD3 vs Output Frequency Over fDAC 100 200 300 Output Frequency (MHz) 400 500 G018 Figure 18. IMD3 vs Output Frequency Over IOUTFS Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 15 DAC34SH84 SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 www.ti.com Typical Characteristics (continued) All plots are at 25°C, nominal supply voltage, fDAC = 1500 MSPS, 2× interpolation, NCO enabled, mixer gain disabled, QMC enabled with gain set at 1446 for both I/Q channels, 0-dBFS digital input, 20-mA full-scale output current with 4:1 transformer (unless otherwise noted) 0 −20 Power (dBm) −30 −40 Power (dBm) NCO bypassed QMC bypassed fDAC = 1500 MSPS fout = 70 MHz Tone spacing = 1 MHz −10 −50 −60 −70 −80 −90 −100 −110 64 66 68 70 72 Frequency (MHz) 74 76 10 0 −10 −20 −30 −40 −50 −60 NCO bypassed QMC bypassed fDAC = 1500 MSPS fout = 200 MHz Tone spacing = 1 MHz −70 −80 −90 −100 −110 194 196 G019 Figure 19. Two-Tone Spectral Plot 198 200 202 Frequency (MHz) 206 G020 Figure 20. Two-Tone Spectral Plot 100 170 PLL disabled PLL enabled w/ PFD of 46.875 MHz 90 0dBFS −6dBFS −12dBFS 160 NSD (dBc/Hz) 80 IMD3 (dBc) 204 70 60 50 150 140 130 40 120 30 20 0 100 200 300 Output Frequency (MHz) 400 110 500 170 170 160 160 150 140 120 FDAC = 750 MSPS, 1x interpolation FDAC = 1500 MSPS, 2x interpolation FDAC = 1500 MSPS, 4x interpolation FDAC = 1500 MSPS, 8x interpolation FDAC = 1500 MSPS, 16x interpolation 0 100 200 300 400 Output Frequency (MHz) 500 600 200 300 400 Output Frequency (dB) 500 600 G022 150 140 fDAC = 800 MSPS fDAC = 1000 MSPS fDAC = 1200 MSPS fDAC = 1500 MSPS 130 120 0 G023 Figure 23. NSD vs Output Frequency Over Interpolation 16 100 Figure 22. NSD vs Output Frequency Over Input Scale NSD (dBc/Hz) NSD (dBc/Hz) Figure 21. IMD3 vs Output Frequency Over Clocking Options 130 0 G021 100 200 300 Output Frequency (MHz) 400 500 G024 Figure 24. NSD vs Output Frequency Over fDAC Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 DAC34SH84 www.ti.com SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 Typical Characteristics (continued) All plots are at 25°C, nominal supply voltage, fDAC = 1500 MSPS, 2× interpolation, NCO enabled, mixer gain disabled, QMC enabled with gain set at 1446 for both I/Q channels, 0-dBFS digital input, 20-mA full-scale output current with 4:1 transformer (unless otherwise noted) 180 170 Iout FS = 10 mA, 4:1 Transformer Iout FS = 20 mA, 4:1 Transformer Iout FS = 30 mA, 2:1 Transformer 160 NSD (dBc) NSD (dBc/Hz) 170 PLL disabled PLL enabled w/ PFD of 46.875 MHz 160 150 140 130 140 130 0 100 200 300 Output Frequency (MHz) 400 120 500 0 200 300 400 Output Frequency (MHz) 500 600 G026 Figure 26. NSD vs Output Frequency Over Clocking Options −20 −30 PLL disabled PLL enabled w/ PFD of 46.08 MHz −30 PLL disabled PLL enabled w/ PFD of 46.08 MHz −40 −50 ACLR (dBc) −40 −50 −60 −70 −60 −70 −80 −80 −90 fDAC = 1474.56 MSPS −90 100 G025 Figure 25. NSD vs Output Frequency Over IOUTFS ACLR (dBc) 150 0 100 200 300 Output Frequency (MHz) fDAC = 1474.56 MSPS 400 500 −100 0 100 G027 Figure 27. Single-Carrier WCDMA ACLR (Adjacent) vs Output Frequency Over Clocking Options 4´ Interpolation fDAC = 1474.56 MSPS fOUT = 70 MHz 200 300 Output Frequency (MHz) 400 500 G028 Figure 28. Single-Carrier WCDMA ACLR (Alternate) vs Output Frequency Over Clocking Options 4´ Interpolation fDAC = 1474.56 MSPS fOUT = 120 MHz Figure 29. Single-Carrier WCDMA Test Mode1 Figure 30. Single-Carrier WCDMA Test Mode1 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 17 DAC34SH84 SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 www.ti.com Typical Characteristics (continued) All plots are at 25°C, nominal supply voltage, fDAC = 1500 MSPS, 2× interpolation, NCO enabled, mixer gain disabled, QMC enabled with gain set at 1446 for both I/Q channels, 0-dBFS digital input, 20-mA full-scale output current with 4:1 transformer (unless otherwise noted) 4´ Interpolation fDAC = 1474.56 MSPS fOUT = 200 MHz 4´ Interpolation fDAC = 1474.56 MSPS fOUT = 70 MHz Figure 31. Single-Carrier WCDMA Test Mode1 4´ Interpolation fDAC = 1474.56 MSPS fOUT = 200 MHz 4´ Interpolation fDAC = 1474.56 MSPS fOUT = 120 MHz Figure 33. Four-Carrier WCDMA Test Mode1 4´ Interpolation fDAC = 1474.56 MSPS fOUT = 140 MHz Figure 34. Four-Carrier WCDMA Test Mode1 4´ Interpolation fDAC = 1474.56 MSPS fOUT = 240 MHz Figure 35. 10-MHz Single-Carrier LTE Test Mode3.1 18 Figure 32. Four-Carrier WCDMA Test Mode1 Figure 36. 10-MHz Single-Carrier LTE Test Mode3.1 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 DAC34SH84 www.ti.com SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 Typical Characteristics (continued) All plots are at 25°C, nominal supply voltage, fDAC = 1500 MSPS, 2× interpolation, NCO enabled, mixer gain disabled, QMC enabled with gain set at 1446 for both I/Q channels, 0-dBFS digital input, 20-mA full-scale output current with 4:1 transformer (unless otherwise noted) 4´ Interpolation fDAC = 1474.56 MSPS fOUT = 140 MHz 4´ Interpolation fDAC = 1474.56 MSPS fOUT = 240 MHz Figure 37. 20-MHz Single-Carrier LTE Test Mode3.1 Figure 38. 20-MHz Single-Carrier LTE Test Mode3.1 1800 1800 1x interpolation 2x interpolation 4x interpolation 8x interpolation 16x interpolation Power (mW) 1400 1400 1200 1000 800 1200 1000 800 Baseband input = 10 MHz NCO disabled QMC disabled 600 400 300 500 700 900 1100 1300 fDAC (MHz) 400 300 1500 500 700 900 1100 1300 fDAC (MHz) G039 1500 G040 Figure 40. Power vs fDAC Over Interpolation 200 QMC enabled NCO enabled 180 DIGVDD current (mA) 260 240 220 200 180 160 140 120 100 80 60 40 20 0 300 Baseband input = 0 MHz NCO enabled w/ 10 MHz mixing QMC enabled 600 Figure 39. Power vs fDAC Over Interpolation Power consumption (mW) 1x interpolation 2x interpolation 4x interpolation 8x interpolation 16x interpolation 1600 Power (mW) 1600 QMC enabled NCO enabled 160 140 120 100 80 60 40 20 500 700 900 1100 fDAC (dB) 1300 1500 0 300 Figure 41. Power Consumption vs fDAC Over Digital Processing Functions 500 700 900 1100 1300 fDAC (dB) G041 1500 G042 Figure 42. DIGVDD Current vs fDAC Over Digital Processing Functions Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 19 DAC34SH84 SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 www.ti.com Typical Characteristics (continued) All plots are at 25°C, nominal supply voltage, fDAC = 1500 MSPS, 2× interpolation, NCO enabled, mixer gain disabled, QMC enabled with gain set at 1446 for both I/Q channels, 0-dBFS digital input, 20-mA full-scale output current with 4:1 transformer (unless otherwise noted) 800 600 500 400 300 Baseband input = 10 MHz NCO disabled QMC disabled 200 100 300 500 700 1x interpolation 2x interpolation 4x interpolation 8x interpolation 16x interpolation 700 DIGVDD current (mA) DIGVDD current (mA) 700 800 1x interpolation 2x interpolation 4x interpolation 8x interpolation 16x interpolation 900 1100 1300 fDAC (MHz) 600 500 400 300 Baseband input = 0 MHz NCO enabled w/ 10 MHz mixing QMC enabled 200 100 300 1500 500 700 900 1100 1300 1500 fDAC (MHz) G043 Figure 43. DIGVDD Current vs fDAC Over Interpolation G044 Figure 44. DIGVDD Current vs fDAC Over Interpolation 100 40 CLKVDD current (mA) DACVDD current (mA) 90 30 20 10 80 70 60 50 40 30 0 300 500 700 900 1100 1300 fDAC (MHz) 20 300 1500 130 110 120 100 Isolation (dBc) AVDD current (mA) 120 110 100 90 50 1300 fDAC (MHz) 1500 G046 NCO Enabled Channel AB and CD Outputs Are 1 MHz Apart Measured With TSW30SH84 EVM 40 Channel AB Suppressing Channel CD Channel CD Suppressing Channel AB 0 G047 Figure 47. AVDD Current vs fDAC 20 1500 70 70 1100 1300 80 60 900 1100 90 80 700 900 Figure 46. CLKVDD Current vs fDAC 140 500 700 fDAC (MHz) Figure 45. DACVDD Current vs fDAC Over Interpolation 60 300 500 G045 Submit Documentation Feedback 100 200 300 IF (MHz) 400 500 G048 Figure 48. Channel Isolation vs IF Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 DAC34SH84 www.ti.com SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 7 Detailed Description 7.1 Overview The DAC34SH84 includes a quad-channel, 16-bit digital-to-analog converter (DAC) with up to 1.5 GSPS sample rate, a 32-bit LVDS data bus with on-chip termination, FIFO, data pattern checker, and parity test. The device includes 2x to 16x digital interpolation filters with over 90dB of stop-band attenuation, reconstruction filters, independent complex mixers, a low jitter clock multiplier, and digital Quadrature Modulator Correction (QMC). Full synchronization of multiple devices is possible with the DAC3484. It is an ideal device for next generation communication systems. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 21 DAC34SH84 SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 www.ti.com PARITYCDN ISTR/PARITYABP ISTR/PARITYABN 100 DACVDD VFUSE DIGVDD 11 taps 11 taps x2 x2 x2 x2 16 8 Sample FIFO 16 AB-QMC Gain and Phase 23 taps BIASJ 16-b DACA IOUTA1 IOUTA2 9 taps x sin(x) 16-b DACB IOUTB1 IOUTB2 QMC B-offset CMIX Control (±n*Fs/8) 2x–16x Interpolation FIR0 FIR1 FIR2 DAC Gain FIR3 x2 QMC C-offset FIR4 x2 x2 x2 59 taps 23 taps 11 taps 11 taps x2 x2 x2 x2 LVDS CD-Channel LVDS LVDS cos x sin(x) 16-b DACC IOUTC1 IOUTC2 9 taps x sin(x) 16-b DACD IOUTD1 IOUTD2 QMC D-offset sin CD 32-Bit NCO OSTRP Temp Sensor Control Interface LVPECL TESTMODE ALARM SLEEP RESETB TXENB SCLK SDENB SDIO SDO IOVDD2 OSTRN AVDD IOVDD PARITYCDP 59 taps x sin(x) GND SYNCN x2 CD-QMC Gain and Phase SYNCP x2 FIR4 x2 EXTIO QMC A-offset sin FIR3 x2 100 DCD0N LVDS • • • FIR2 Complex Mixer (FMIX or CMIX) 100 • • • 100 DCD0P 16 LVDS • • • FIR1 AB-Channel De-interleave DCD15N • • • Programmable Delay DCD15P LVDS 16 Pattern Test • • • 100 DAB0N CD-Data Bus LVDS • • • DAB0P cos FIR0 Pattern Test DAB15N Programmable Delay 100 AB-Data Bus DAB15P 1.2-V Reference AB 32-Bit NCO LVDS 100 DATACLKN Clock Distribution 100 DATACLKP LPF Low Jitter PLL LVPECL DACCLKN Complex Mixer (FMIX or CMIX) DACCLKP PLLAVDD CLKVDD 7.2 Functional Block Diagram B0460-01 22 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 DAC34SH84 www.ti.com SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 7.3 Feature Description 7.3.1 Serial Interface The serial port of the DAC34SH84 is a flexible serial interface which communicates with industry-standard microprocessors and microcontrollers. The interface provides read/write access to all registers used to define the operating modes of the DAC34SH84. It is compatible with most synchronous transfer formats and can be configured as a three- or four-pin interface by sif4_ena in register config2. In both configurations, SCLK is the serial-interface input clock and SDENB is serial-interface enable. For the three-pin configuration, SDIO is a bidirectional pin for both data in and data out. For the four-pin configuration, SDIO is data-in only and SDO is data-out only. Data is input into the device with the rising edge of SCLK. Data is output from the device on the falling edge of SCLK. Each read/write operation is framed by the serial-data enable bar (SDENB) signal asserted low. The first frame byte is the instruction cycle which identifies the following data transfer cycle as read or write as well as the 7-bit address to be accessed. Table 1 indicates the function of each bit in the instruction cycle and is followed by a detailed description of each bit. The data transfer cycle consists of two bytes. Table 1. Instruction Byte of the Serial Interface BIT 7 (MSB) 6 5 4 3 2 1 0 (LSB) Description R/W A6 A5 A4 A3 A2 A1 A0 R/W Identifies the following data transfer cycle as a read or write operation. A high indicates a read operation from the DAC34SH84 and a low indicates a write operation to the DAC34SH84. [A6 : A0] Identifies the address of the register to be accessed during the read or write operation. Figure 49 shows the serial interface timing diagram for a DAC34SH84 write operation. SCLK is the serial interface clock input to DAC34SH84. Serial data enable SDENB is an active low input to DAC34SH84. SDIO is serial data in. Input data to DAC34SH84 is clocked on the rising edges of SCLK. Instruction Cycle Data Transfer Cycle SDENB SCLK SDIO rwb A6 A5 A4 tS(SDENB) A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 t(SCLK) SDENB SCLK SDIO tH(SDIO) tS(SDIO) T0521-01 Figure 49. Serial-Interface Write Timing Diagram Figure 50 shows the serial interface timing diagram for a DAC34SH84 read operation. SCLK is the serial interface clock input to the DAC34SH84. Serial-data enable SDENB is an active-low input to the DAC34SH84. SDIO is serial data-in during the instruction cycle. In the three-pin configuration, SDIO is data out from the DAC34SH84 during the data transfer cycle, whereas SDO is in a high-impedance state. In the four-pin configuration, SDO is data-out from the DAC34SH84 during the data transfer cycle. At the end of the data transfer, SDIO and SDO output low on the final falling edge of SCLK until the rising edge of SDENB, when SDO goes into the high-impedance state. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 23 DAC34SH84 SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 www.ti.com Instruction Cycle Data Transfer Cycle SDENB SCLK SDIO rwb A6 A5 A4 A3 A2 A1 SDO A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SDENB SCLK SDIO SDO Data n Data n – 1 td(Data) T0522-01 Figure 50. Serial-Interface Read Timing Diagram 7.3.2 Data Interface The DAC34SH84 has a 32-bit LVDS bus that accepts quad, 16-bit data in word-wide format. The quad, 16-bit data can be input to the device using a dual-bus, 16-bit interface. The bus accepts LVDS transfer rates up to 1.5 GSPS, which corresponds to a maximum data rate of 750 MSPS per data channel. The default LVDS bus input assignment is shown in Table 2. Table 2. LVDS Bus Input Assignment DATA PATHS PINS A and B DAB[15..0] C and D DCD[15..0] Data is sampled by the LVDS double-data-rate (DDR) clock DATACLK. Setup and hold requirements must be met for proper sampling. A and C data are captured on the rising edge of DATACLK. B and D data are captured on the falling edge of DATACLK. For both input bus modes, a sync signal, either ISTR or SYNC, is required to sync the FIFO read and/or write pointers. The sync signal, either ISTR or SYNC, can be either a pulse or a periodic signal where the sync period corresponds to multiples of eight samples. ISTR or SYNC is sampled by a rising edge in DATACLK. The pulse duration t(ISTR_SYNC) must be at least equal to one-half of the DATACLK period. 7.3.3 Data Format The 16-bit data for channels A and B is interleaved in the form A0[15:0], B0[15:0], A1[15:0], B1[15:0], A2[15:0]… into the DAB[15:0]P/N LVDS inputs. Similarly, data for channels C and D is interleaved into the DCD[15:0]P/N LVDS inputs. Data into the DAC34SH84 is formatted according to the diagram shown in Figure 51, where index 0 is the data LSB and index 15 is the data MSB. 24 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 DAC34SH84 www.ti.com SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 SAMPLE 0 SAMPLE 1 SAMPLE 2 SAMPLE 3 DAB[15:0]P/N A0 [15:0] B0 [15:0] A1 [15:0] B1 [15:0] A2 [15:0] B2 [15:0] A3 [15:0] B3 [15:0] DCD[15:0]P/N C0 [15:0] D0 [15:0] C1 [15:0] D1 [15:0] C2 [15:0] D2 [15:0] C3 [15:0] D3 [15:0] DATACLKP/N (DDR) t(ISTR_SYNC) Sync Option #1 ISTRP/N t(ISTR_SYNC) Sync Option #2 SYNCP/N T0530-01 Figure 51. Data Transmission Format The FIFO read and write pointer can also be synced by SIF SYNC as the third sync option if multi-device synchronization is not needed. In this sync mode, the syncsel_fifoin(3:0) and syncsel_fifoout(3:0) in register config32 need to be both set to 1000 for the SIF SYNC option. 7.3.4 Input FIFO The DAC34SH84 includes a 4-channel, 16-bit-wide and 8-sample-deep input FIFO which acts as an elastic buffer. The purpose of the FIFO is to absorb any timing variations between the input data and the internal DAC data-rate clock, such as the ones resulting from clock-to-data variations from the data source. Figure 52 shows a simplified block diagram of the FIFO. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 25 DAC34SH84 SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 www.ti.com Clock Handoff Input Side Clocked by DATACLK Output Side Clocked by FIFO Out Clock (DACCLK/Interpolation Factor) FIFO: 4 x 16-Bits Wide 8-Samples deep 16-Bit DAB[15:0] B-Data, 16-Bit 16-Bit 16-Bit DCD[15:0] De-Interleave C-Data, 16-Bit D-Data, 16-Bit 0 ... 7 Write Pointer A-Data, 16-Bit 16-Bit Write Pointer Reset ISTR/ SYNC 0 Sample 0 A0[15:0], B0[15:0], C0[15:0], D0[15:0] 0 1 Sample 0 A1[15:0], B1[15:0], C1[15:0], D1[15:0] 1 2 Sample 0 A2[15:0], B2[15:0], C2[15:0], D2[15:0] 2 3 Sample 0 A3[15:0], B3[15:0], C3[15:0], D3[15:0] 3 4 Sample 0 A4[15:0], B4[15:0], C4[15:0], D4[15:0] 4 5 Sample 0 A5[15:0], B5[15:0], C5[15:0], D5[15:0] 5 6 Sample 0 A6[15:0], B6[15:0], C6[15:0], D6[15:0] 6 7 Sample 0 A7[15:0], B7[15:0], C7[15:0], D7[15:0] 7 64-Bit FIFO Reset 16-Bit 64-Bit Initial Position 0 ... 7 Read Pointer Initial Position 16-Bit 16-Bit 16-Bit FIFO A Output FIFO B Output FIFO C Output FIFO D Output Read Pointer Reset fifo_offset(2:0) S M syncsel_fifoout OSTR syncsel_fifoin S (Single Sync Sources Mode): Reset handoff from input side to output side M (Dual Sync Source Mode): OSTR resets read pointer. Allows Multi-DAC synchronization B0461-01 Figure 52. DAC34SH84 FIFO Block Diagram Data is written to the device 32 bits at a time on the rising and falling edges of DATACLK. In order to form a complete 64-bit wide sample (16-bit A-data, 16-bit B-data, 16-bit C-data, and 16-bit D-data) one DATACLK period is required. Each 64-bit-wide sample is written into the FIFO at the address indicated by the write pointer. Similarly, data from the FIFO is read by the FIFO-out clock 64 bits at a time from the address indicated by the read pointer. The FIFO-out clock is generated internally from the DACCLK signal and its rate is equal to DACCLK / interpolation. Each time a FIFO write or FIFO read is done, the corresponding pointer moves to the next address. The reset position for the FIFO read and write pointers is set by default to addresses 0 and 4 as shown in Figure 52. This offset gives optimal margin within the FIFO. The default read pointer location can be set to another value using fifo_offset(2:0) in register config9 (address 4 by default). Under normal conditions, data is written to and read from the FIFO at the same rate and consequently, the write and read pointer gap remains constant. If the FIFO write and read rates are different, the corresponding pointers cycle at different speeds, which could result in pointer collision. Under this condition, the FIFO attempts to read and write data from the same address at the same time, which results in errors and thus must be avoided. The write pointer sync source is selected by syncsel_fifoin(3:0) in register config32. In most applications either ISTR or SYNC are used to reset the write pointer. Unlike DATA, the sync signal is latched only on the rising edges of DATACLK. A rising edge on the sync signal source causes the pointer to return to its original position. Similarly, the read pointer sync source is selected by syncsel_fifoout(3:0). The write pointer sync source can be set to reset the read pointer as well. In this case, the FIFO-out clock recaptures the write pointer sync signal to reset the read pointer. This clock domain transfer (DATACLK to FIFO Out Clock) results in phase ambiguity of the sync signal. This limits the precise control of the output timing and makes full synchronization of multiple devices difficult. 26 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 DAC34SH84 www.ti.com SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 To alleviate this, the device offers the alternative of resetting the FIFO read pointer independently of the write pointer by using the OSTR signal. The OSTR signal is sampled by DACCLK and must satisfy the timing requirements in the specifications table. In order to minimize the skew it is recommended to use the same clock distribution device such as Texas Instruments CDCE62005 to provide the DACCLK and OSTR signals to all the DAC34SH84 devices in the system. Swapping the polarity of the DACCLK outputs with respect to the OSTR ones establishes proper phase relationship. The FIFO pointers reset procedure can be done periodically or only once during initialization as the pointers automatically return to the initial position when the FIFO has been filled. To reset the FIFO periodically, it is necessary to have the ISTR, SYNC, and OSTR signals to repeat at multiples of 8 FIFO samples. To disable FIFO reset, set syncsel_fifoin(3:0) and syncsel_fifoout(3:0) to 0000. The frequency limitation for ISTR and SYNC signals are the following: fsync = fDATACLK / (n × 8), where n = 1, 2, … The frequency limitation for the OSTR signal is the following: fOSTR = fDAC / (n × interpolation × 8) where n = 1, 2, … The frequencies above are at maximum when n = 1. This is when the ISTR, SYNC, or OSTR have a rising edge transition every 8 FIFO samples. The occurrence can be made less frequent by setting n > 1, for example, every n × 8 FIFO samples. LVDS Pairs (Data Source) D[15:0]P/N tS(DATA) tH(DATA) DATACLKP/N (DDR) tH(DATA) tS(DATA) ISTRP/N SYNCP/N LVPECL Pairs (Clock Source) tS(DATA) tH(DATA) Resets Write Pointer to Position 0 DACCLKP/N 2x Interpolation tS(OSTR) tH(OSTR) OSTRP/N (optionally internal sync from Write Reset) Resets Read Pointer to Position Set by fifo_offset (4 by Default) T0531-01 Figure 53. FIFO Write and Read Descriptions 7.3.5 FIFO Modes of Operation The DAC34SH84 input FIFO can be completely bypassed through registers config0 and config32. The register configuration for each mode is described in Table 3. Register Control Bits config0 fifo_ena config32 syncsel_fifoout(3:0) Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 27 DAC34SH84 SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 www.ti.com Table 3. FIFO Operation Modes config0 AND config32 FIFO Bits FIFO MODE Dual Sync Sources fifo_ena syncsel_fifoout BIT 3: sif_sync BIT 2: OSTR BIT 1: ISTR 0 1 0 0 1 or 0 Depends on the sync source X 1 Single Sync Source 1 0 0 1 or 0 Depends on the sync source Bypass 0 X X X BIT 0: SYNC 7.3.5.1 Dual-Sync-Sources Mode This is the recommended mode of operation for those applications that require precise control of the output timing. In Dual Sync Sources mode, the FIFO write and read pointers are reset independently. The FIFO write pointer is reset using the LVDS ISTR or SYNC signal, and the FIFO read pointer is reset using the LVPECL OSTR signal. This allows LVPECL OSTR signal to control the phase of the output for either a single chip or multiple chips. Multiple devices can be fully synchronized in this mode. 7.3.5.2 Single-Sync-Source Mode In single-sync-source mode, the FIFO write and read pointers are reset from the same source, either LVDS ISTR or LVDS SYNC signal. This mode has a possibility of up to 2 DAC clocks offset between the multiple DAC outputs. Applications requiring exact output timing control need dual-sync-sources mode instead of single-syncsource mode. A single rising edge for FIFO and clock divider sync is recommended. Periodic sync signal is not recommended due to the non-deterministic latency of the sync signal through the clock domain transfer. In this mode, there is a chance for FIFO pointers 2 away alarm (or possibly 1 away alarm) to occur at initial setup or syncing. This is the result of single-sync-source mode having 0 to 3 address location slip, which is caused by the asynchronous handoff of the sync signal occurring between the DATACLK zone and the DACCLK zone. The asynchronous relationship between the clock domains means there could be a slip (from nominal) in the READ and WRITE pointers at initial syncing. For example, with the default programming of FIFO offset of 4, the actual FIFO offset may be 3, 2, or in some instances, 1. Please note that in this mode, the nominal address location slip is 0 with the possibility getting less for each increase in slip amount. Also, the slip does not continue to occur as the device functions, but the READ/WRITE pointers may not be at optimal settings. If an alarm occurs: 1. Adjust the FIFO offset accordingly and resynchronize the FIFO, data formatter, etc., such that there are no alarms reported or at least only the 2-away alarm is reported. 2. The FIFO collision alarm is a warning of the system, because the read and write processes occur at the same pointer. However, the FIFO 1-away and 2-away alarms are informational for the system designer. The important thing for these two alarms is that the alarm should not get closer to collision during normal operation. If the 1-away alarm or collision alarm starts to occur, it is a warning to check for system errors. The system should have an interrupt or algorithm to fix the error and resynchronize the alarm appropriately. 7.3.5.3 Bypass Mode In FIFO bypass mode, the FIFO block is not used. As a result, the input data is handed off from the DATACLK to the DACCLK domain without any compensation. In this mode, the relationship between DATACLK and DACCLK is critical and used as a synchronizing mechanism for the internal logic. Due to this constraint, this mode is not recommended. In bypass mode, the pointers have no effect on the data path or handoff. Because this mode does not require synchronization of the FIFO, the ISTR and SYNC signals are also bypassed. Therefore, the ISTR and SYNC LVDS pairs can be left unconnected. 7.3.6 Clocking Modes The DAC34SH84 has a dual-clock setup in which a DAC clock signal is used to clock the DAC cores and internal digital logic, and a separate DATA clock is used to clock the input LVDS receivers and FIFO input. The DAC34SH84 DAC clock signal can be sourced directly or generated through an on-chip low-jitter phase-locked loop (PLL). 28 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 DAC34SH84 www.ti.com SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 In those applications requiring extremely low noise it is recommended to bypass the PLL and source the DAC clock directly from a high-quality external clock to the DACCLK input. In most applications, system clocking can be simplified by using the on-chip PLL to generate the DAC core clock while still satisfying performance requirements. In this case, the DACCLK pins are used as the reference frequency input to the PLL. 16-Bit DACI PLL DACCLK Clock Distribution to Digital VCO/ Dividers 16-Bit DACQ pll_ena B0452-01 Figure 54. Top-Level Clock Diagram 7.3.6.1 PLL Bypass Mode In PLL bypass mode, a very high-quality clock is sourced to the DACCLK inputs. This clock is used to directly source the DAC34SH84 DAC sample-rate clock. This mode gives the device best performance and is recommended for extremely demanding applications. The bypass mode is selected by setting the following: 1. pll_ena bit in register config24 to 0 to bypass the PLL circuitry. 2. pll_sleep bit in register config26 to 1 to put the PLL and VCO into sleep mode. 7.3.6.2 PLL Mode In this mode, the clock at the DACCLKP/N input functions as a reference clock source to the on-chip PLL. The on-chip PLL then multiplies this reference clock to supply a higher-frequency DAC sample-rate clock. Figure 55 shows the block diagram of the PLL circuit. OSTR (Internally Generated) External Loop Filter DACCLKP REFCLK DACCLKN N Divider SYNCP SYNC_PLL PFD and CP Prescaler Internal Loop Filter SYNCN Note: The PLL generates internal OSTR signal. In this mode external LVPECL OSTR signal is not required. DACCLK VCO M Divider If the DAC is configured with PLL enabled with Dual Sync Sources mode, then the PFD frequency has to be the predefined OSTR frequency. B0453-01 Figure 55. PLL Block Diagram Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 29 DAC34SH84 SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 www.ti.com The DAC34SH84 PLL mode is selected by setting the following: 1. pll_ena bit in register config24 to 1 to route to the PLL clock path. 2. pll_sleep bit in register config26 to 0 to enable the PLL and VCO. The output frequency of the VCO is designed to be the in the range from 2.7 GHz to 3.3 GHz. The prescaler value, pll_p(2:0) in register config24, should be chosen such that the product of the prescaler value and DAC sample rate clock is within the VCO range. To maintain optimal PLL loop, the coarse-tuning bits, pll_vco(5:0) in register config26, can adjust the center frequency of the VCO toward the product of the prescaler value and DAC sample-rate clock. Figure 56 shows a typical relationship between the coarse-tuning bits and VCO center frequency. See the Electrical Characteristics Table for recommended pll_vco(5:0) setting and the corresponding VCO frequency range. Following the recommended settings ensures optimal PLL lock range over operating temperature and voltage specifications. 3300 Coarse-Tuning Bits @ VCO Frequency (MHz ) - 2673 9.7 VCO Frequency (MHz) 3200 3100 3000 2900 2800 2700 0 8 16 32 24 40 48 56 64 Coarse-Tuning Bits Figure 56. Typical PLL/VCO Lock Range vs Coarse-Tuning Bits Common wireless infrastructure frequencies (614.4MHz, 737.28MHz, 983.04 MHz, and so forth) are generated from this VCO frequency in conjunction with the prescaler setting as shown in Table 4. Table 4. VCO Operation VCO FREQUENCY (MHz) PRE-SCALE DIVIDER DESIRED DACCLK (MHz) pll_p(2:0) 2949.12 6 491.52 110 3072 5 614.4 101 2949.12 4 737.28 100 2949.12 3 983.04 011 2949.12 2 1474.56 010 The M divider is used to determine the phase-frequency-detector (PFD) and charge-pump (CP) frequency. Table 5. PFD and CP Operation 30 DACCLK FREQUENCY (MHz) M DIVIDER PFD UPDATE RATE (MHz) pll_m(7:0) 491.52 4 122.88 0000 0100 491.52 8 61.44 0000 1000 491.52 16 30.72 0001 0000 491.52 32 15.36 0010 0000 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 DAC34SH84 www.ti.com SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 The N divider in the loop allows the PFD to operate at a lower frequency than the reference clock. Both M and N dividers can keep the PFD frequency below 155 MHz for peak operation. The overall divide ratio inside the loop is the product of the pre-scale and M dividers (P × M), and the following guidelines should be followed: • The overall divide ratio range is from 24 to 480. • When the overall divide ratio is less than 120, the internal loop filter can assure a stable loop. • When the overall divide ratio is greater than 120, an external loop filter or double charge pump is required to ensure loop stability. The single- and double-charge-pump current options are selected by setting pll_cp in register config24 to 01 and 11, respectively. When using the double-charge-pump setting, an external loop filter is not required. If an external loop filter is required, the following filter should be connected to the LPF pin (A1): LPF R = 1 kΩ C2 = 1 nF C1 = 100 nF S0514-01 Figure 57. Recommended External Loop Filter The PLL generates an internal OSTR signal and does not require the external LVPECL OSTR signal. The OSTR signal is buffered from the N-divider output in the PLL block, and the frequency of the signal is the same as the PFD frequency. Therefore, using the PLL with dual-sync-sources mode would require the PFD frequency to be the pre-defined OSTR frequency. This allows the FIFO to be synced correctly by the internal OSTR. 7.3.7 FIR Filters Figure 58 through Figure 61 show the magnitude spectrum response for the FIR0, FIR1, FIR2 and FIR3 interpolating filters where fIN is the input data rate to the FIR filter. Figure 62 to Figure 65 show the composite filter response for 2x, 4x, 8x and 16x interpolation. The transition band for all interpolation settings is from 0.4 to 0.6 x fDATA (the input data rate to the device) with < 0.001dB of pass-band ripple and > 90 dB stop-band attenuation. The DAC34SH84 also has a 9-tap inverse sinc filter (FIR4) that runs at the DAC update rate (fDAC) that can be used to flatten the frequency response of the sample-and-hold output. The DAC sample-and-hold output sets the output current and holds it constant for one DAC clock cycle until the next sample, resulting in the well-known sin(x) / x or sinc(x) frequency response (Figure 66, red line). The inverse sinc filter response (Figure 66, blue line) has the opposite frequency response from 0 to 0.4 x Fdac, resulting in the combined response (Figure 66, green line). Between 0 to 0.4 x fDAC, the inverse sinc filter compensates the sample-and-hold roll-off with less than 0.03 dB error. The inverse sinc filter has a gain > 1 at all frequencies. Therefore, the signal input to FIR4 must be reduced from full scale to prevent saturation in the filter. The amount of back-off required depends on the signal frequency, and is set such that at the signal frequencies the combination of the input signal and filter response is less than 1 (0 dB). For example, if the signal input to FIR4 is at 0.25 x fDAC, the response of FIR4 is 0.9 dB, and the signal must be backed off from full scale by 0.9 dB to avoid saturation. The gain function in the QMC blocks can be used to reduce the amplitude of the input signal. The advantage of FIR4 having a positive gain at all frequencies is that the user is then able to optimize the back-off of the signal based on its frequency. The filter taps for all digital filters are listed in Table 3. Note that the loss of signal amplitude may result in lower SNR due to decrease in signal amplitude. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 31 DAC34SH84 www.ti.com 20 20 0 0 –20 –20 –40 –40 Magnitude (dB) Magnitude (dB) SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 –60 –80 –100 –60 –80 –100 –120 –120 –140 –140 –160 –160 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 0.1 0.2 0.3 0.4 f/fIN 0.5 0.6 0.7 0.8 0.9 f/fIN G048 G049 Figure 59. Magnitude Spectrum for FIR1 20 20 0 0 –20 –20 –40 –40 Magnitude (dB) Magnitude (dB) Figure 58. Magnitude Spectrum for FIR0 –60 –80 –100 –60 –80 –100 –120 –120 –140 –140 –160 –160 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 0.1 0.2 0.3 0.4 f/fIN 0.5 0.6 0.7 0.8 0.9 G050 G051 Figure 61. Magnitude Spectrum for FIR3 20 20 0 0 –20 –20 –40 –40 Magnitude (dB) Magnitude (dB) 1 f/fIN Figure 60. Magnitude Spectrum for FIR2 –60 –80 –100 –60 –80 –100 –120 –120 –140 –140 –160 –160 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 f/fDATA f/fDATA G053 G052 Figure 62. 2x Interpolation Composite Response 32 1 Figure 63. 4x Interpolation Composite Response Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 DAC34SH84 SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 20 20 0 0 –20 –20 –40 –40 Magnitude (dB) Magnitude (dB) www.ti.com –60 –80 –100 –60 –80 –100 –120 –120 –140 –140 –160 –160 0 0.5 1 1.5 2 2.5 3 3.5 4 0 1 2 3 f/fDATA 4 5 6 7 8 f/fDATA G054 G055 Figure 64. 8x Interpolation Composite Response Figure 65. 16x Interpolation Composite Response 4 3 FIR4 Magnitude (dB) 2 1 Corrected 0 –1 –2 sin(x)/x –3 –4 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 f/fDAC G056 Figure 66. Magnitude Spectrum for Inverse Sinc Filter Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 33 DAC34SH84 SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 www.ti.com Table 6. FIR Filter Coefficients NON-INTERPOLATING INVERSE-SINC FILTER INTERPOLATING HALF-BAND FILTERS FIR0 FIR1 59 TAPS FIR2 23 TAPS FIR3 11 TAPS FIR4 11 TAPS 9 TAPS 6 6 –12 –12 29 29 3 3 1 1 0 0 0 0 0 0 0 0 –4 –4 –19 –19 84 84 –214 –214 –25 –25 13 13 0 0 0 0 0 0 0 0 –50 –50 47 47 –336 –336 1209 1209 150 150 592 (1) 0 0 0 0 2048 (1) –100 –100 1006 1006 0 0 0 0 192 192 –2691 –2691 0 0 0 0 –342 –342 10141 10141 0 0 16,384 (1) 572 572 0 0 –914 –914 0 0 1409 1409 0 0 –2119 –2119 0 0 3152 3152 0 0 –4729 –4729 0 0 7420 7420 0 0 –13,334 –13,334 0 0 41,527 41,527 256 (1) 65,536 (1) (1) Center taps are highlighted in BOLD 34 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 DAC34SH84 www.ti.com SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 7.3.8 Complex Signal Mixer The DAC34SH84 has two paths of complex signal mixer blocks that contain two full complex mixer (FMIX) blocks and power saving coarse mixer (CMIX) blocks. The signal path is shown in Figure 67. I Data In (A) Q Data In (B) 16 16 Fs/2 Mixer 16 16 ±Fs/4 Mixer 16 CMIX 16 Complex Signal Multiplier 16 sine 16 CMIX CMIX I Data Out (A) 16 Q Data Out (B) cosine 16 CMIX sine 16 cosine sine 16 16 (AB) Numerically Controlled Oscillator NCO_ENA cosine 16 Fixed Fs/8 Oscillator B0471-02 Note: Channel CD data path not shown Figure 67. Path of Complex Signal Mixer 7.3.8.1 Full Complex Mixer The two FMIX blocks operate with independent Numerically Controlled Oscillators (NCOs) and enable flexible frequency placement without imposing additional limitations in the signal bandwidth. The NCOs have 32-bit frequency registers (phaseaddAB(31:0) and phaseaddCD(31:0)) and 16-bit phase registers (phaseoffsetAB(15:0) and phaseoffsetCD(15:0)) that generate the sine and cosine terms for the complex mixing. The NCO block diagram is shown in Figure 68. 32 16 Frequency Register 32 Σ 32 Accumulator CLK 32 16 16 Σ sin Look-Up Table 16 cos RESET 16 fDAC NCO SYNC via syncsel_NCO[3:0] Phase Register B0026-03 Figure 68. NCO Block Diagram Synchronization of the NCOs occurs by resetting the NCO accumulators to zero. The synchronization source is selected by syncsel_NCO(3:0) in config31. The frequency word in the phaseaddAB(31:0) and phaseaddCD(31:0) registers is added to the accumulators every clock cycle, fDAC. The output frequency of the NCO is: freq ´ fNCO _ CLK fNCO = 232 (1) Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 35 DAC34SH84 SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 www.ti.com With the complex mixer enabled, the two channels in the mixer path are treated as complex vectors of the form IIN(t) + j QIN(t). The complex signal multiplier (shown in Figure 69) will multiply the complex channels with the sine and cosine terms generated by the NCO. The resulting output, IOUT(t) + j QOUT(t), of the complex signal multiplier is: IOUT(t) = (IIN(t)cos(2πfNCOt + δ) – QIN(t)sin(2πfNCOt + δ)) × 2(mixer_gain – 1) QOUT(t) = (IIN(t)sin(2πfNCOt + δ) + QIN(t)cos(2πfNCOt + δ)) × 2(mixer_gain – 1) where t is the time since the last resetting of the NCO accumulator, δ is the phase offset value and mixer_gain is either 0 or 1. δ is given by: δ = 2π × phase_offsetAB/CD(15:0) / 216 The mixer_gain option allows the output signals of the multiplier to reduce by half (6 dB). See Mixer Gain section for details. 16 IIN(t) QIN(t) ( 16 IOUT(t) 16 16 16 cosine QOUT(t) 16 sine B0472-02 Figure 69. Complex Signal Multiplier 7.3.8.2 Coarse Complex Mixer In addition to the full complex mixers, the DAC34SH84 also has coarse mixer blocks capable of shifting the input signal spectrum by the fixed mixing frequencies ±n × fS / 8. Using the coarse mixer instead of the full mixers lowers power consumption. The output of the fS / 2, fS / 4, and –fS / 4 mixer block is: IOUT(t) = I(t)cos(2πfCMIXt) – Q(t)sin(2πfCMIXt) QOUT(t) = I(t)sin(2πfCMIXt) + Q(t)cos(2πfCMIXt) Since the sine and the cosine terms are a function of fS / 2, fS / 4, or –fS / 4 mixing frequencies, the possible resulting value of the terms can only be 1, –1, or 0. The simplified mathematics allows the complex signal multiplier to be bypassed in any one of the modes, thus mixer gain is not available. The fS / 2, fS / 4, and –fS / 4 mixer blocks performs mixing through negating and swapping of I/Q channel on certain sequence of samples. Table 7 shows the algorithm used for those mixer blocks. Table 7. fS / 2, fS / 4, and –fS / 4 Mixing Sequence MODE Normal (mixer bypassed) fS / 2 fS / 4 –fS / 4 36 MIXING SEQUENCE Iout = {I1, I2, I3, I4…} Qout = {Q1, Q2, Q3, Q4…} Iout = {I1, –I2, I3, –I4…} Qout = {Q1, –Q2, Q3, –Q4…} Iout = {I1, –Q2, –I3, Q4…} Qout = {Q1, I2, –Q3, –I4…} Iout = {I1, Q2, –I3, –Q4…} Qout = {Q1, –I2, –Q3, I4…} Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 DAC34SH84 www.ti.com SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 The fS / 8 mixer can be enabled along with various combinations of fS / 2, fS / 4, and –fS / 4 mixer. Because the fS / 8 mixer uses the complex signal multiplier block with fixed fS / 8 sine and cosine term, the output of the multiplier is: IOUT(t) = (IIN(t)cos(2πfNCOt + δ) – QIN(t)sin(2πfNCOt + δ)) × 2(mixer_gain – 1) QOUT(t) = (IIN(t)sin(2πfNCOt + δ) + QIN(t)cos(2πfNCOt + δ)) × 2(mixer_gain – 1) where fCMIX is the fixed mixing frequency selected by cmix(3:0). The mixing combinations are described in Table 8. The mixer_gain option allows the output signals of the multiplier to reduce by half (6dB). See Mixer Gain section for details. Table 8. Coarse Mixer Combinations cmix(3:0) fS / 8 MIXER cmix(3) fS / 4 MIXER cmix(2) fS / 2 MIXER cmix(1) –fS / 4 MIXER cmix(0) MIXING MODE 0000 Disabled Disabled Disabled Disabled No mixing 0001 Disabled Disabled Disabled Enabled –fS / 4 0010 Disabled Disabled Enabled Disabled fS / 2 0100 Disabled Enabled Disabled Disabled fS / 4 1000 Enabled Disabled Disabled Disabled fS / 8 1010 Enabled Disabled Enabled Disabled –3fS / 8 1100 Enabled Enabled Disabled Disabled 3fS / 8 1110 Enabled Enabled Enabled Disabled –fS / 8 All others – – – – Not recommended 7.3.8.3 Mixer Gain The maximum output amplitude out of the complex signal multiplier (for example, FMIX mode or CMIX mode with fS / 8 mixer enabled) occurs if IIN(t) and QIN(t) are simultaneously full scale amplitude and the sine and cosine arguments are equal to 2π x fMIXt + δ (2N-1) x π / 4, where N = 1, 2, 3, ... cosine sine Max output occurs when both sine and cosine are 0.707 M0221-01 Figure 70. Maximum Output of the Complex Signal Multiplier With mixer_gain = 1 and both IIN(t) and QIN(t) are simultaneously full scale amplitude, the maximum output possible out of the complex signal multiplier is 0.707 + 0.707 = 1.414 (or 3dB). This configuration can cause clipping of the signal and should therefore be used with caution. With mixer_gain = 0 in config2, the maximum output possible out of the complex signal multiplier is 0.5 × (0.707 + 0.707) = 0.707 (or –3 dB). This loss in signal power is in most cases undesirable, and it is recommended that the gain function of the QMC block be used to increase the signal by 3 dB to compensate. 7.3.8.4 Real Channel Upconversion The mixer in the DAC34SH84 treats the A, B, C, and D inputs are complex input data and produces a complex output for most mixing frequencies. The real input data for each channel can be isolated only when the mixing frequency is set to normal mode or fS / 2 mode. See Table 7 for details. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 37 DAC34SH84 SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 www.ti.com 7.3.9 Quadrature Modulation Correction (QMC) 7.3.9.1 Gain and Phase Correction The DAC34SH84 includes a Quadrature Modulator Correction (QMC) block. The QMC blocks provide a mean for changing the gain and phase of the complex signals to compensate for any I and Q imbalances present in an analog quadrature modulator. The block diagram for the QMC block is shown in Figure 71. The QMC block contains 3 programmable parameters. Registers qmc_gainA/B(10:0) and qmc_gainC/D(10:0) controls the I and Q path gains and is an 11-bit unsigned value with a range of 0 to 1.9990 and the default gain is 1.0000. The implied decimal point for the multiplication is between bit 9 and bit 10. Register qmc_phaseAB/CD(11:0) control the phase imbalance between I and Q and are a 12-bit values with a range of –0.5 to approximately 0.49975. The QMC phase term is not a direct phase rotation but a constant that is multiplied by each Q sample then summed into the I sample path. This is an approximation of a true phase rotation in order to keep the implementation simple. LO feed-through can be minimized by adjusting the DAC offset feature described below. qmc_gainA[10:0] 11 16 Σ I Data In (A) 16 I Data Out (A) 12 qmc_phaseAB[11:0] 16 16 Q Data In (B) Q Data Out (B) 11 qmc_gainB[10:0] qmc_gainC[10:0] 11 16 Σ I Data In (C) 16 I Data Out (C) 12 qmc_phaseCD[11:0] 16 16 Q Data In (D) Q Data Out (D) 11 qmc_gainD[10:0] B0164-03 Figure 71. QMC Block Diagram 38 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 DAC34SH84 www.ti.com SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 7.3.9.2 Offset Correction Registers qmc_offsetA(12:0), qmc_offsetB(12:0), qmc_offsetC(12:0) and qmc_offsetD(12:0) can be used to independently adjust the dc offsets of each channel. The offset values are in represented in 2s-complement format with a range from –4096 to 4095. The offset value adds a digital offset to the digital data before digital-to-analog conversion. Because the offset is added directly to the data it may be necessary to back off the signal to prevent saturation. Both data and offset values are LSB aligned. qmc_offsetA {–4096, –4095, ..., 4095} 13 16 A Data In 16 B Data In 16 Σ A Data Out 16 Σ B Data Out 13 qmc_offsetB {–4096, –4095, ..., 4095} qmc_offsetC {–4096, –4095, ..., 4095} 13 16 C Data In 16 D Data In 16 Σ C Data Out 16 Σ D Data Out 13 qmc_offsetD {–4096, –4095, ..., 4095} B0165-03 Figure 72. Digital Offset Block Diagram 7.3.10 Temperature Sensor The DAC34SH84 incorporates a temperature sensor block which monitors the temperature by measuring the voltage across 2 transistors. The voltage is converted to an 8-bit digital word using a successive-approximation (SAR) analog to digital conversion process. The result is scaled, limited and formatted as a 2s-complement value representing the temperature in degrees Celsius. The sampling is controlled by the serial interface signals SDENB and SCLK. If the temperature sensor is enabled (tsense_sleep = 0 in register config26) a conversion takes place each time the serial port is written or read. The data is only read and sent out by the digital block when the temperature sensor is read in tempdata(7:0) in config6. The conversion uses the first eight clocks of the serial clock as the capture and conversion clock, the data is valid on the falling eighth SCLK. The data is then clocked out of the chip on the rising edge of the ninth SCLK. No other clocks to the chip are necessary for the temperature sensor operation. As a result the temperature sensor is enabled even when the device is in sleep mode. In order for the process described above to operate properly, the serial port read from config6 must be done with an SCLK period of at least 1 μs. If this is not satisfied the temperature sensor accuracy is greatly reduced. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 39 DAC34SH84 SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 www.ti.com 7.3.11 Data Pattern Checker The DAC34SH84 incorporates a simple pattern checker test in order to determine errors in the data interface. The main cause of failures is setup and/or hold timing issues. The test mode is enabled by asserting iotest_ena in register config1. In test mode the analog outputs are deactivated regardless of the state of TXENA or sif_texnable in register config3. The data pattern key used for the test is 8 words long and is specified by the contents of iotest_pattern[0:7] in registers config37 through config44. The data pattern key can be modified by changing the contents of these registers. The first word in the test frame is determined by a rising edge transition in ISTR or SYNC, depending on the syncsel_fifoin(3:0) setting in config32. At this transition, the pattern0 word should be input to the data DAB[15:0] pins, and pattern2 should be input to the data DCD[15:0] pins. Patterns 1, 4, and 5 of DAB[15:0] bus and pattern 3, 6, and 7 of DCD[15:0] bus should follow sequentially on each edge of DATACLK (rising and falling). The sequence should be repeated until the pattern checker test is disabled by setting iotest_ena back to 0. It is not necessary to have a rising ISTR or SYNC edge aligned with every four DATACLK cycle, just the first one to mark the beginning of the series. Start cycle again with optional rising edge of ISTR or SYNC DAB[15:0]P/N Pattern 0 Pattern 1 Pattern 4 Pattern 5 Pattern 0 Pattern 1 Pattern 4 Pattern 5 [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] DCD[15:0]P/N Pattern 2 Pattern 3 Pattern 6 Pattern 7 Pattern 2 Pattern 3 Pattern 6 Pattern 7 [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] DATACLKP/N (DDR) Sync Option #1 ISTRP/N Sync Option #2 SYNCP/N T0532-01 Figure 73. I/O Pattern Checker Data Transmission Format The test mode determines if the all the patterns on the two 16-bit LVDS data buses (DAB[15:0]P/N and DCD[15:0]P/N) were received correctly by comparing the received data against the data pattern key. If any bits in either of the two 16-bit data buses were received incorrectly, the corresponding bits in iotest_results(15:0) in register config4 will be set to 1 to indicate bit error location. The user can check the corresponding bit location on both 16-bit data buses and implement the fix accordingly. Furthermore, the error condition will trigger the alarm_from_iotest bit in register config5 to indicate a general error in the data interface. When data pattern checker mode is enabled, this alarm in register config5, bit7 is the only valid alarm. Other alarms in register config5 are not valid and can be disregarded. For instance, pattern0 is programmed to the default of 0x7A7A. If the received Pattern 0 is 0x7A7B, then bit 0 in iotest_results(15:0) will be set to 1 to indicate an error in bit 0 location. The alarm_from_iotest will also be set to 1 to report the data transfer error. Note that iotest_results(15:0) does not indicate which of the 16-bit buses has the error. The user needs to check both 16-bit buses and then narrow down the error from the bit location information. The alarms can be cleared by writing 0x0000 to iotest_results(15:0) and 0 to alarm_from_iotest through the serial interface. The serial interface will read back 0s if there are no errors or if the errors are cleared. The corresponding alarm bit will remain a 1 if the errors remain. 40 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 DAC34SH84 www.ti.com SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 It is recommended to enable the pattern checker and then run the pattern sequence for 100 or more complete cycles before clearing the iotest_results(15:0) and alarm_from_iotest. This will eliminate the possibility of false alarms generated during the setup sequence. Based on the pattern test result, the user can adjust the data source output timing, PCB traces delay, or DAC34SH84 CONFIG36 LVDS programmable delay to help optimize the setup and hold time of the transmitter system. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 41 DAC34SH84 SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 ISTR or SYNC 32-Bit 32-Bit LVDS Drivers Only one Data Format edge needed DATACLK Pattern 0 ... 7 DAB[15:0] DCD[15:0] www.ti.com 0 Pattern 0 Bit-by-Bit Compare 0 1 Pattern 1 Bit-by-Bit Compare 1 2 Pattern 2 Bit-by-Bit Compare 2 3 Pattern 3 Bit-by-Bit Compare 3 4 Pattern 4 Bit-by-Bit Compare 4 5 Pattern 5 Bit-by-Bit Compare 5 6 Pattern 6 Bit-by-Bit Compare 6 7 Pattern 7 Bit-by-Bit Compare 7 16-Bit 16-Bit iotest_pattern0 iotest_pattern1 iotest_pattern2 8-Bit Input iotest_results[15] iotest_pattern3 iotest_pattern4 iotest_pattern5 iotest_pattern6 iotest_pattern7 16-Bit Input Bit 15 Results • • • 8-Bit Input • • • • • • iotest_results[0] alarm_from_iotest All Bits Results Bit 0 Results Go back to 0 after cycle or new rising edge on ISTR or SYNC B0462-01 Figure 74. DAC34SH84 Pattern Check Block Diagram 42 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 DAC34SH84 www.ti.com SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 7.3.12 Parity Check Test The DAC34SH84 has a parity check test that enables continuous validity monitoring of the data received by the DAC. Parity check testing in combination with the data pattern checker offer an excellent solution for detecting board assembly issues due to missing pad connections. For the parity check test, an extra parity bit is added to the data bits to ensure that the total number of set bits (bits with value 1) is even or odd. This simple scheme is used to detect single or any other odd number of data transfer errors. Parity testing is implemented in the DAC34SH84 in two ways: 32-bit parity and dual 16-bit parity. 7.3.12.1 32-Bit Parity In the 32-bit mode the additional parity bit is sourced to the parity input (PARITYP/N) for the 32-bit data transfer into the DAB[15:0]P/N and DCD[15:0]P/N inputs. This mode is enabled by setting parity_ena = 1 and single_dual_parity = 0 in register config1. The input parity value is defined to be the total number of logic 1s on the 33-bit data bus – the DAB[15:0]P/N inputs, the DCD[15:0]P/N inputs, and the PARITYP/N input. This value, the total number of logic 1s, must match the parity test selected in the oddeven_parity bit in register config1. For example, if the oddeven_parity bit is set to 1 for odd parity, then the number of 1s on the 33-bit data bus should be odd. The DAC will check the data transfer through the parity input. If the data received has odd number of 1s, then the parity is correct. If the data received has even number of 1s, then the parity is incorrect. The corresponding alarm for parity error will be set accordingly. Figure 75 shows the simple XOR structure used to check word parity. Parity is tested independently for data captured on both rising and falling edges of DATACLK (alarm_Aparity and alarm_Bparity, respectively). Testing on both edges helps in determining a possible setup or hold issue. Both alarms are captured individually in register config5. PARITY alarm_Aparity oddeven_parity DAB[15:0] DCD[15:0] Parity Block alarm_Bparity DATACLK B0458-02 Figure 75. DAC34SH84 32-Bit Parity Check 7.3.12.2 Dual 16-Bit Parity In the dual 16-bit mode, each 16-bit LVDS data bus input will be accompanied by a parity bit for error checking. The DAB[15:0]P/N and ISTRP/N are one 17-bit data path, and the DCD[15:0]P/N and PARITYP/N are another path. This mode is enabled by setting parity_ena = 1 and single_dual_parity = 1 in register config1. The input parity value is defined to be the total number of logic 1s on each 17-bit data bus. This value, the total number of logic 1s, must match the parity test selected in the oddeven_parity bit in register config1. For example, if the oddeven_parity bit is set to 1 for odd parity, then the number of 1s on each 17-bit data bus should be odd. The DAC will check the data transfer through the parity input. If the data received has odd number of 1s, then the parity is correct. If the data received has even number of 1s, then the parity is incorrect. The corresponding alarm for parity error will be set accordingly. Figure 76 shows the simple XOR structure used to check word parity. Parity is tested independently for data captured on both rising and falling edges of DATACLK for each data path (alarm_Aparity, alarm_Bparity, alarm_Cparity, and alarm_Dparity, respectively). Testing on both edges and both data buses helps in determining a possible setup or hold issue. All of the alarms are captured individually in register config5. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 43 DAC34SH84 SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 www.ti.com In this mode the ISTR signal functions as a parity signal and cannot be used to sync the FIFO pointer simultaneously. It is recommended to use the SYNC to sync the FIFO pointer. If ISTR has to be used to sync the FIFO pointer, the ISTR sync can only be possible upon start-up when dual 16-bit parity function is disabled. Once the initialization is finished, disable the FIFO pointer sync through ISTR (by configuring syncsel_fifoin and syncsel_fifoout in config32) and enable the dual 16-bit parity function afterwards. alarm_Aparity ISTR oddeven_parity DAB[15:0] alarm_Bparity Parity Block DATACLK alarm_Cparity PARITY oddeven_parity DCD[15:0] Parity Block alarm_Dparity DATACLK B0463-01 Figure 76. DAC34SH84 Dual 16-Bit Parity Check 7.3.13 DAC34SH84 Alarm Monitoring The DAC34SH84 includes a flexible set of alarm monitoring that can be used to alert of a possible malfunction scenario. All the alarm events can be accessed either through the config5 register or through the ALARM pin. Once an alarm is set, the corresponding alarm bit in register config5 must be reset through the serial interface to allow further testing. The set of alarms includes the following conditions: Zero check alarm • Alarm_from_zerochk. Occurs when the FIFO write pointer has an all zeros pattern. Since the write pointer is a shift register, all zeros will cause the input point to be stuck until the next sync event. When this happens a sync to the FIFO block is required. FIFO alarms • alarm_from_fifo. Occurs when there is a collision in the FIFO pointers or a collision event is close. – alarm_fifo_2away. Pointers are within two addresses of each other. – alarm_fifo_1away. Pointers are within one address of each other. – alarm_fifo_collision. Pointers are equal to each other. Clock alarms • clock_gone. Occurs when either the DACCLK or DATACLOCK have been stopped. – alarm_dacclk_gone. Occurs when the DACCLK has been stopped. – alarm_dataclk_gone. Occurs when the DATACLK has been stopped. Pattern checker alarm • alarm_from_iotest. Occurs when the input data pattern does not match the pattern key. 44 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 DAC34SH84 www.ti.com SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 PLL alarm • alarm_from_pll. Occurs when the PLL is out of lock. Parity alarms • alarm_Aparity: In dual parity mode, alarm indicating a parity error on the A word. In single parity mode, alarm on the 32-bit data captured on the rising edge of DATACLKP/N. • alarm_Bparity: In dual parity mode, alarm indicating a parity error on the B word. In single parity mode, alarm on the 32-bit data captured on the falling edge of DATACLKP/N. • alarm_Cparity: In dual parity mode, alarm indicating a parity error on the C word. • alarm_Dparity: In dual parity mode, alarm indicating a parity error on the D word. To prevent unexpected DAC outputs from propagating into the transmit channel chain, the clock and alarm_ fifo_collision alarms can be set in config2 to shut-off the DAC output automatically regardless of the state of TXENA or sif_txenable. Alarm monitoring is implemented as follows: • Power up the device using the recommended power-up sequence. • Clear all the alarms in config5 by setting them to zeros. • Unmask those alarms that will generate a hardware interrupt through the ALARM pin in config7. • Enable automatic DAC shut-off in register config2 if required. • In the case of an alarm event, the ALARM pin will trigger. If automatic DAC shut-off has been enabled the DAC outputs will be disabled. • Read registers config5 to determine which alarm triggered the ALARM pin. • Correct the error condition and re-synchronize the FIFO. • Clear the alarms in config5. • Re-read config5 to ensure the alarm event has been corrected. • Keep clearing and reading config5 until no error is reported. 7.3.14 LVPECL Inputs Figure 77 shows an equivalent circuit for the DAC input clock (DACCLKP/N) and the output strobe clock (OSTRP/N). CLKVDD 250 Ω 2 kΩ 2 kΩ DACCLKN OSTRN DACCLKP OSTRP 250 Ω Internal Digital In SLEEP GND S0515-01 Figure 77. DACCLKP/N and OSTRP/N Equivalent Input Circuit Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 45 DAC34SH84 SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 www.ti.com Figure 78 shows the preferred configuration for driving the CLKIN/CLKINC input clock with a differential ECL or PECL source. CAC 0.1 μF Differential ECL or (LV)PECL Source + CLKIN CAC 0.1 μF 100 Ω CLKINC – RT 150 Ω RT 150 Ω S0029-02 Figure 78. Preferred Clock Input Configuration With a Differential ECL or PECL Clock Source 7.3.15 LVDS Inputs The DAB[15:0]P/N, DCD[15:0]P/N, DATACLKP/N, SYNCP/N, PARITYP/N, and ISTRP/N LVDS pairs have the input configuration shown in Figure 79. Figure 80 shows the typical input levels and common-move voltage used to drive these inputs. IOVDD 100 Ω LVDS Receiver Internal Digital In GND S0516-01 Figure 79. DAB[15:0]P/N, DCD[15:0]P/N, DATACLKP/N, ISTRP/N, SYNCP/N and PARITYP/N LVDS Input Configuration 46 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 DAC34SH84 www.ti.com SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 Example DAC34SH84 VA, B VCOM = (VA + VB)/2 VA 1.4 V VB 1V LVDS Receiver 100 Ω 400 mV VA, B VA 0V –400 mV VB GND 1 Logical Bit Equivalent 0 B0459-04 Figure 80. LVDS Data Input Levels Table 9. Example LVDS Data Input Levels APPLIED VOLTAGES RESULTING DIFFERENTIAL VOLTAGE RESULTING COMMONMODE VOLTAGE VA,B VCOM VA VB 1.4 V 1.0 V 400 mV 1.0 V 1.4 V –400 mV 1.2 V 0.8 V 400 mV 0.8 V 1.2 V –400 mV LOGICAL BIT BINARY EQUIVALENT 1 1.2 V 0 1 1.0 V 0 7.3.16 CMOS Digital Inputs Figure 81 shows a schematic of the equivalent CMOS digital inputs of the DAC34SH84. SDIO, SCLK, SLEEP and TXENA have pull-down resistors while SDENB and RESETB have pull-up resistors internal to the DAC34SH84. All the CMOS digital inputs and outputs are referred to the IOVDD2 supply, which can vary from 1.8 V to 3.3 V. This facilitates the I/O interface and eliminates the need of level translation. See Electrical Characteristics – Digital Specifications for logic thresholds. The pull-up and pull-down circuitry is approximately equivalent to 100 kΩ. IOVDD2 IOVDD2 100 kΩ SDIO SCLK SLEEP TXENA 100 kΩ 400 Ω Internal Digital In SDENB RESETB GND 400 Ω Internal Digital In GND S0027-04 Figure 81. CMOS Digital Equivalent Input 7.3.17 Reference Operation The DAC34SH84 uses a bandgap reference and control amplifier for biasing the full-scale output current. The full-scale output current is set by applying an external resistor RBIAS to pin BIASJ. The bias current IBIAS through resistor RBIAS is defined by the on-chip bandgap reference voltage and control amplifier. The default full-scale output current equals 64 times this bias current and can thus be expressed as: IOUTFS = 64 × IBIAS = 64 × (VEXTIO / RBIAS ) / 2 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 47 DAC34SH84 SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 www.ti.com The DAC34SH84 has a 4-bit coarse gain control coarse_dac(3:0) in the config3 register. Using gain control, the IOUTFS can be expressed as: IOUTFS = (coarse_dac + 1) / 16 × IBIAS × 64 = (coarse_dac + 1) / 16 × (VEXTIO / RBIAS) / 2 × 64 where VEXTIO is the voltage at terminal EXTIO. The bandgap reference voltage delivers an accurate voltage of 1.2 V. This reference is active when extref_ena = 0 in config27. An external decoupling capacitor CEXT of 0.1 µF should be connected externally to terminal EXTIO for compensation. The bandgap reference can additionally be used for external reference operation. In that case, an external buffer with high impedance input should be applied in order to limit the bandgap load current to a maximum of 100 nA. The internal reference can be disabled and overridden by an external reference by setting the extref_ena control bit. Capacitor CEXT may hence be omitted. Terminal EXTIO thus serves as either input or output node. The full-scale output current can be adjusted from 30 mA down to 10 mA by varying resistor RBIAS, programming coarse_dac(3:0), or changing the externally applied reference voltage. NOTE With internal reference, the minimum Rbias resistor value is 1.28 kΩ. Resistor value below 1.28 kΩ is not recommended since it will program the full-scale current to go above 30 mA and potentially damages the device. 7.3.18 DAC Transfer Function The CMOS DACs consist of a segmented array of PMOS current sources, capable of sourcing a full-scale output current up to 30 mA. Differential current switches direct the current to either one of the complementary output nodes IOUTP or IOUTN. Complementary output currents enable differential operation, thus canceling out common mode noise sources (digital feed-through, on-chip and PCB noise), dc offsets, even order distortion components, and increasing signal output power by a factor of two. The full-scale output current is set using external resistor RBIAS in combination with an on-chip bandgap voltage reference source (+1.2 V) and control amplifier. Current IBIAS through resistor RBIAS is mirrored internally to provide a maximum full-scale output current equal to 64 times IBIAS. The relation between IOUTP and IOUTN can be expressed as: IOUTFS = IOUTP + IOUTN We will denote current flowing into a node as – current and current flowing out of a node as + current. Since the output stage is a current source the current flows from the IOUTP and IOUTN pins. The output current flow in each pin driving a resistive load can be expressed as: IOUTP = IOUTFS × CODE / 65,536 IOUTN = IOUTFS × (65,535 – CODE) / 65,536 where CODE is the decimal representation of the DAC data input word For the case where IOUTP and IOUTN drive resistor loads RL directly, this translates into single ended voltages at IOUTP and IOUTN: VOUTP = IOUT1 x RL VOUTN = IOUT2 x RL Assuming that the data is full scale (65,535 in offset binary notation) and the RL is 25 Ω, the differential voltage between pins IOUTP and IOUTN can be expressed as: VOUTP = 20mA x 25 Ω = 0.5 V VOUTN = 0mA x 25 Ω = 0 V VDIFF = VOUTP – VOUTN = 0.5V Note that care should be taken not to exceed the compliance voltages at node IOUTP and IOUTN, which would lead to increased signal distortion. 48 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 DAC34SH84 www.ti.com SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 7.3.19 Analog Current Outputs The DAC34SH84 can be easily configured to drive a doubly terminated 50-Ω cable using a properly selected RF transformer. Figure 82 and Figure 83 show the 50-Ω doubly terminated transformer configuration with 1:1 and 4:1 impedance ratio, respectively. Note that the center tap of the primary input of the transformer has to be grounded to enable a DC current flow. Applying a 20-mA full-scale output current would lead to a 0.5 Vpp for a 1:1 transformer and a 1-Vpp output for a 4:1 transformer. The low dc-impedance between IOUTP or IOUTN and the transformer center tap sets the center of the ac-signal to GND, so the 1 Vpp output for the 4:1 transformer results in an output between –0.5 V and +0.5 V. 50 Ω 1:1 IOUTP 100 Ω RLOAD 50 Ω AGND IOUTN 50 Ω S0517-01 Figure 82. Driving a Doubly Terminated 50-Ω Cable Using a 1:1 Impedance Ratio Transformer 100 Ω 4:1 IOUTP AGND RLOAD 50 Ω IOUTN 100 Ω S0518-01 Figure 83. Driving a Doubly Terminated 50-Ω Cable Using a 4:1 Impedance Ratio Transformer 7.4 Device Functional Modes 7.4.1 Multi-Device Synchronization In various applications, such as multi antenna systems where the various transmit channels information is correlated, it is required that multiple DAC devices are completely synchronized such that their outputs are phase aligned. The DAC34SH84 architecture supports this mode of operation. 7.4.1.1 Multi-Device Synchronization: PLL Bypassed with Dual Sync Sources Mode For single- or multi-device synchronization it is important that delay differences in the data are absorbed by the device so that latency through the device remains the same. Furthermore, to ensure that the outputs from each DAC are phase aligned it is necessary that data is read from the FIFO of each device simultaneously. In the DAC34SH84 this is accomplished by operating the multiple devices in Dual Sync Sources mode. In this mode the additional OSTR signal is required by each DAC34SH84 to be synchronized. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 49 DAC34SH84 SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 www.ti.com Device Functional Modes (continued) Data into the device is input as LVDS signals from one or multiple baseband ASICs or FPGAs. Data into multiple DAC devices can experience different delays due to variations in the digital source output paths or board level wiring. These different delays can be effectively absorbed by the DAC34SH84 FIFO so that all outputs are phase aligned correctly. DACCLKP/N OSTRP/N DAB[15:0]P/N DCD[15:0]P/N FPGA DAC34SH84 DAC1 ISTRP/N Clock Generator PLL/ DLL LVDS Interface LVPECL Outputs Delay 1 DATACLKP/N Variable delays due to variations in the FPGA(s) output DAB[15:0]P/N paths or board level wiring or temperature/voltage deltas DCD[15:0]P/N Outputs are Phase Aligned LVPECL Outputs ISTRP/N DATACLKP/N Delay 2 DAC34SH84 DAC2 OSTRP/N DACCLKP/N B0454-04 Figure 84. Synchronization System in Dual Sync Sources Mode With PLL Bypassed For correct operation both OSTR and DACCLK must be generated from the same clock domain. The OSTR signal is sampled by DACCLK and must satisfy the timing requirements in the specifications table. If the clock generator does not have the ability to delay the DACCLK to meet the OSTR timing requirement, the polarity of the DACCLK outputs can be swapped with respect to the OSTR ones to create 180 degree phase delay of the DACCLK. This may help establish proper setup and hold time requirement of the OSTR signal. Careful board layout planning must be done to ensure that the DACCLK and OSTR signals are distributed from device to device with the lowest skew possible as this will affect the synchronization process. In order to minimize the skew across devices it is recommended to use the same clock distribution device to provide the DACCLK and OSTR signals to all the DAC devices in the system. 50 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 DAC34SH84 www.ti.com SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 LVPECL Pairs (DAC34SH84 2) LVPECL Pairs (DAC34SH84 1) Device Functional Modes (continued) DACCLKP/N(1) tS(OSTR) tH(OSTR) tSKEW ~ 0 OSTRP/N(1) DACCLKP/N(2) tS(OSTR) tH(OSTR) OSTRP/N(2) • • • • T0526-04 Figure 85. Timing Diagram for LVPECL Synchronization Signals The following steps are required to ensure the devices are fully synchronized. The procedure assumes all the DAC34SH84 devices have a DACCLK and OSTR signal and must be carried out on each device. 1. Start-up the device as described in the power-up sequence. Set the DAC34SH84 in Dual Sync Sources mode and select OSTR as the clock divider sync source (clkdiv_sync_sel in register config32). 2. Sync the clock divider and FIFO pointers. 3. Verify there are no FIFO alarms either through register config5 or through the ALARM pin. 4. Disable clock divider sync by setting clkdiv_sync_ena to 0 in register config0. After these steps all the DAC34SH84 outputs will be synchronized. 7.4.1.2 Multi-Device Synchronization: PLL Enabled with Dual Sync Sources Mode The DAC34SH84 allows exact phase alignment between multiple devices even when operating with the internal PLL clock multiplier. In PLL clock mode, the PLL generates the DAC clock and an internal OSTR signal from the reference clock applied to the DACCLK inputs so there is no need to supply an additional LVPECL OSTR signal. For this method to operate properly the SYNC signal should be set to reset the PLL N dividers to a known state by setting pll_ndivsync_ena in register config24 to 1. The SYNC signal resets the PLL N dividers with a rising edge, and the timing relationship ts(SYNC_PLL) and th(SYNC_PLL) are relative to the reference clock presented on the DACCLK pin. Both SYNC and DACCLK can be set as low frequency signals to greatly simplifying trace routing (SYNC can be just a pulse as a single rising edge is required, if using a periodic signal it is recommended to clear the pll_ndivsync_ena bit after resetting the PLL dividers). Besides the ts(SYNC_PLL) and th(SYNC_PLL) requirement between SYNC and DACCLK, there is no additional required timing relationship between the SYNC and ISTR signals or between DACCLK and DATACLK. The only restriction as in the PLL disabled case is that the DACCLK and SYNC signals are distributed from device to device with the lowest skew possible. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 51 DAC34SH84 SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 www.ti.com Device Functional Modes (continued) DACCLKP/N SYNCP/N DAB[15:0]P/N DCD[15:0]P/N FPGA DAC34SH84 DAC1 ISTRP/N Clock Generator PLL/ DLL LVDS Interface Outputs Delay 1 DATACLKP/N Variable delays due to variations in the FPGA(s) output DAB[15:0]P/N paths or board level wiring or temperature/voltage deltas DCD[15:0]P/N Outputs are Phase Aligned Outputs ISTRP/N DATACLKP/N Delay 2 DAC34SH84 DAC2 SYNCP/N DACCLKP/N B0455-04 Figure 86. Synchronization System in Dual Sync Sources Mode with PLL Enabled The following steps are required to ensure the devices are fully synchronized. The procedure assumes all the DAC34SH84 devices have a DACCLK and OSTR signal and must be carried out on each device. 1. Start up the device as described in the power-up sequence. Set the DAC34SH84 in Dual Sync Sources mode and enable SYNC to reset the PLL dividers (set pll_ndivsync_ena in register config24 to 1). 2. Reset the PLL dividers with a rising edge on SYNC. 3. Disable PLL dividers resetting. 4. Sync the clock divider and FIFO pointers. 5. Verify there are no FIFO alarms either through register config5 or through the ALARM pin. 6. Disable clock divider sync by setting clkdiv_sync_ena to 0 in register config0. After these steps all the DAC34SH84 outputs will be synchronized. 7.4.1.3 Multi-Device Operation: Single Sync Source Mode In Single Sync Source mode, the FIFO write and read pointers are reset from the same sync source, either ISTR or SYNC. Although the FIFO in this mode can still absorb the data delay differences due to variations in the digital source output paths or board level wiring it is impossible to guarantee data will be read from the FIFO of different devices simultaneously thus preventing exact phase alignment. In Single Sync Source mode the FIFO read pointer reset is handoff between the two clock domains (DATACLK and FIFO OUT CLOCK) by simply re-sampling the write pointer reset. Since the two clocks are asynchronous there is a small but distinct possibility of a meta-stability during the pointer handoff. This meta-stability can cause the outputs of the multiple devices to slip by up to 2 DAC clock cycles. When the PLL is enabled with Single Sync Source mode, the FIFO read pointer is not synchronized by the OSTR signal. Therefore, there is no restriction on the PLL PFD frequency as described in the previous section. 52 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 DAC34SH84 www.ti.com SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 Device Functional Modes (continued) DACCLKP/N DAB[15:0]P/N DCD[15:0]P/N FPGA DAC34SH84 DAC1 ISTRP/N Clock Generator PLL/ DLL LVDS Interface LVPECL Outputs Delay 1 DATACLKP/N Variable delays due to variations in the FPGA(s) output 0 to 2 DAC Clock Cycles DAB[15:0]P/N paths or board level wiring or temperature/voltage deltas DCD[15:0]P/N LVPECL Outputs ISTRP/N Delay 2 DATACLKP/N DAC34SH84 DAC2 DACCLKP/N B0456-04 Figure 87. Multi-Device Operation in Single Sync Source Mode 7.5 Programming 7.5.1 Power-Up Sequence The following startup sequence is recommended to power-up the DAC34SH84: 1. Set TXENA low 2. Supply all 1.35-V voltages (DACVDD, CLKVDD), 1.3-V voltages (DIGVDD, VFUSE), and 3.3-V voltages (AVDD, IOVDD, and PLLAVDD). The 1.2-V and 3.3-V supplies can be powered up simultaneously or in any order. There are no specific requirements on the ramp rate for the supplies. 3. Provide all LVPECL inputs: DACCLKP/N and the optional OSTRP/N. These inputs can also be provided after the SIF register programming. 4. Toggle the RESETB pin for a minimum 25 ns active low pulse width. 5. Program the SIF registers. 6. Program fuse_sleep (config27, bit) to put the internal fuses to sleep. 7. FIFO configuration needed for synchronization: (a) Program syncsel_fifoin(3:0) (config32, bit) to select the FIFO input pointer sync source. (b) Program syncsel_fifoout(3:0) (config32, bit) to select the FIFO output pointer sync source. (c) Program syncsel_fifo_input(1:0) (config31, bit) to select the FIFO input sync source. 8. Clock divider configuration needed for synchronization: (a) Program clkdiv_sync_sel (config32, bit) to select the clock divider sync source. (b) Program clkdiv_sync_ena (config0, bit) to 1 to enable clock divider sync. (c) For multi-DAC synchronization in PLL mode, program pll_ndivsync_ena (config24, bit) to 1 to synchronize the PLL N-divider. 9. Provide all LVDS inputs (D[15:0]P/N, DCD[15:0]P/N, DATACLKP/N, ISTRP/N, SYNCP/N and PARITYP/N) simultaneously. Synchronize the FIFO and clock divider by providing the pulse or periodic signals needed. (a) For Single Sync Source Mode where either ISTRP/N or SYNCP/N is used to sync the FIFO, a single rising edge for FIFO and clock divider sync is recommended. Periodic sync signal is not recommended due to the non-deterministic latency of the sync signal through the clock domain transfer. (b) For Dual Sync Sources Mode, both single pulse or periodic sync signals can be used. (c) For multi-DAC synchronization in PLL mode, the LVDS SYNCP/N signal is used to sync the PLL NSubmit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 53 DAC34SH84 SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 www.ti.com Programming (continued) divider and can be sourced from either the FPGA/ASIC pattern generator or clock distribution circuit as long as the t(SYNC_PLL) setup and hold timing requirement is met with respect to the reference clock source at DACCLKP/N pins. The LVDS SYNCP/N signal can be provided at this point. 10. FIFO and clock divider configurations after all the sync signals have provided the initial sync pulses needed for synchronization: (a) For Single Sync Source Mode where the clock divider sync source is either ISTRP/N or SYNCP/N, clock divider syncing must be disabled after DAC34SH84 initialization and before the data transmission by setting clkdiv_sync_ena (config0, bit 2) to 0. (b) For Dual Sync Sources Mode, where the clock divider sync source is from the OSTR signal (either from external OSTRP/N or internal PLL N divider output), the clock divider syncing may be enabled at all time. (c) Optionally, to prevent accidental syncing of the FIFO when sending the ISTRP/N or SYNCP/N pulse to other digital blocks such as NCO, QMC, etc, disable FIFO syncing by setting syncsel_fifoin(3:0) and syncsel_fifoout(3:0) to 0000 after the FIFO input and output pointers are initialized. If the FIFO and sync remain enabled after initialization, the ISTRP/N or SYNCP/N pulse must occur in ways to not disturb the FIFO operation. Refer to the INPUT FIFO section for detail. (d) Disable PLL N-divider syncing by setting pll_ndivsync_ena (config24, bit) to 0. 11. Enable transmit of data by asserting the TXENA pin or set sif_txenable to 1. 12. At any time, if any of the clocks (that is, DATACLK or DACCLK) is lost or a FIFO collision alarm is detected, a complete resynchronization of the DAC is necessary. Set TXENABLE low and repeat steps 7 through 11. Program the FIFO configuration and clock divider configuration per steps 7 and 8 appropriately to accept the new sync pulse or pulses for the synchronization. 7.5.2 Example Start-Up Routine 7.5.2.1 Device Configuration fDATA = 737.28 MSPS Interpolation = 2× Input data = baseband data fOUT = 122.88 MHz PLL = Enabled Full Mixer = Enabled NCO = Enabled Dual Sync Sources Mode 7.5.2.2 PLL Configuration fREFCLK = 737.28 MHz at the DACCLKP/N LVPECL pins fDACCLK = fDATA × Interpolation = 1474.56 MHz fVCO = 2 × fDACCLK = 2949.12 MHz (keep fVCO between 2.7 GHz and 3.3 GHz) PFD = fOSTR = 46.08 MHz N = 16, M = 32, P = 2, single charge pump pll_vco(5:0) = 01 1100 (28) 7.5.2.3 NCO Configuration fNCO = 122.88 MHz fNCO_CLK = 1474.56 MHz 54 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 DAC34SH84 www.ti.com SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 Programming (continued) freq = fNCO × 232 / 1228.8 = 357,913,941 = 0x1555 5555 phaseaddAB(31:0) and/or phaseaddCD(31:0) = 0x1555 5555 NCO SYNC = rising edge of LVDS SYNC 7.5.2.4 Example Start-Up Sequence Table 10. Example Start-Up Sequence Description STEP READ/WRITE ADDRESS VALUE DESCRIPTION 1 N/A N/A N/A Set TXENA low 2 N/A N/A N/A Power up the device 3 N/A N/A N/A Apply LVPECL DACCLKP/N for PLL reference clock 4 N/A N/A N/A Toggle RESETB pin 5 Write 0x00 0xF19F QMC offset and correction enabled, 2x int, FIFO enabled, Alarm enabled, clock divider sync enabled, inverse sinc filter enabled. 6 Write 0x01 0x040E Single parity enabled, FIFO alarms enabled (2 away, 1 away, and collision). 7 Write 0x02 0x7052 Output shut-off when DACCLK gone, DATACLK gone, and FIFO collision. Mixer block with NCO enabled, twos complement. 8 Write 0x03 0xA000 Output current set to 20 mAFS with internal reference and 1.28-kΩ RBIAS resistor. 9 Write 0x07 0xD8FF Un-mask FIFO collision, DACCLK-gone, and DATACLK-gone alarms to the Alarm output. 10 Write 0x08 N/A Program the desired channel A QMC offset value. (Causes auto-sync for QMC AB-channels offset block) 11 Write 0x09 N/A Program the desired FIFO offset value and channel B QMC offset value. 12 Write 0x0A N/A Program the desired channel C QMC offset value. (Causes auto-sync for QMC CD-channels offset block) 13 Write 0x0B N/A Program the desired channel D QMC offset value. 14 Write 0x0C N/A Program the desired channel A QMC gain value. 15 Write 0x0D N/A Coarse mixer mode not used. Program the desired channel B QMC gain value. 16 Write 0x0E N/A Program the desired channel B QMC gain value. 17 Write 0x0F N/A Program the desired channel C QMC gain value. 18 Write 0x10 N/A Program the desired channel AB QMC phase value. (Causes Auto-Sync QMC AB-Channels Correction Block) 19 Write 0x11 N/A Program the desired channel CD QMC phase value. (Causes Auto-Sync for the QMC CD-Channels Correction Block) 20 Write 0x12 N/A Program the desired channel AB NCO phase offset value. (Causes AutoSync for Channel AB NCO Mixer) 21 Write 0x13 N/A Program the desired channel CD NCO phase offset value. (Causes AutoSync for Channel CD NCO Mixer) 22 Write 0x14 0x5555 Program the desired channel AB NCO frequency value 23 Write 0x15 0x1555 Program the desired channel AB NCO frequency value 24 Write 0x16 0x5555 Program the desired channel CD NCO frequency value 25 Write 0x17 0x1555 Program the desired channel CD NCO frequency value 26 Write 0x18 0x2C50 PLL enabled, PLL N-dividers sync enabled, single charge pump, prescaler = 2. 27 Write 0x19 0x20F4 M = 32, N = 16, PLL VCO bias tune = 01 28 Write 0x1A 0x7010 PLL VCO coarse tune = 28 29 Write 0x1B 0x0800 Internal reference 30 Write 0x1E 0x9999 QMC offset AB, QMC offset CD, QMC correction AB, and QMC correction CD can be synced by sif_sync or auto-sync from register write Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 55 DAC34SH84 SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 www.ti.com Programming (continued) Table 10. Example Start-Up Sequence Description (continued) STEP 56 READ/WRITE ADDRESS VALUE DESCRIPTION 31 Write 0x1F 0x4440 Mixer AB and CD values synced by SYNCP/N. NCO accumulator synced by SYNCP/N. 32 Write 0x20 0x2400 FIFO Input Pointer Sync Source = ISTR FIFO Output Pointer Sync Source = OSTR (from PLL N-divider output) Clock Divider Sync Source = OSTR 33 N/A N/A N/A Provide all the LVDS DATA and DATACLK Provide rising edge ISTRP/N and rising edge SYNCP/N to sync the FIFO input pointer and PLL Ndividers. 34 Read 0x18 N/A Read back pll_lfvolt(2:0). If the value is not optimal, adjust pll_vco(5:0) in 0x1A. 35 Write 0x05 0x0000 36 Read 0x05 N/A 37 Write 0x1F 0x4442 Sync all the QMC blocks using sif_sync. These blocks can also be synced via auto-sync through appropriate register writes. 38 Write 0x00 0xF19B Disable clock divider sync. 39 Write 0x1F 0x4448 Set sif_sync to 0 for the next sif_sync event. 40 Write 0x20 0x0000 Disable FIFO input and output pointer sync. 41 Write 0x18 0x2450 Disable PLL N-dividers sync. 42 N/A N/A N/A Clear all alarms in 0x05. Read back all alarms in 0x05. Check for PLL lock, FIFO collision, DACCLKgone, DATACLK-gone, ... Fix the error appropriately. Repeat step 34 and 35 as necessary. Set TXENA high. Enable data transmission. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 DAC34SH84 www.ti.com SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 7.6 Register Map Table 11. Register Map (1) Name Address Default (MSB) Bit 15 Bit 14 Bit 13 Bit 12 config0 0x00 0x049C qmc_ offsetAB_ ena qmc_ offsetCD_ ena qmc_ corrAB_ ena qmc_ corrCD_ ena config1 0x01 0x040E iotest_ ena reserved reserved 64cnt_en a oddeven_ parity parity_ ena single_ dual_ parity config2 0x02 0x7000 reserved dacclk gone_ena dataclk gone_ena collision_ gone_ena reserved reserved reserved config3 0x03 0xF000 config4 0x04 NA NA Bit 11 Bit 10 Bit 9 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) Bit 0 fifo_ena reserved reserved alarm_out_ ena alarm_out pol clkdiv_sync_ ena invsincAB_ ena invsincCD_ ena rev_ interface dacA_ complement dacB_ complement dacC_ complement dacD_ complement alarm_ 2away_ ena alarm_ 1away_ ena alarm_ collision_ ena reserved reserved sif4_ena mixer_ena mixer_gain nco_ena revbus reserved twos Bit 8 interp(3:0) coarse_dac(3:0) reserved alarm_ from_ iotest alarm_ output_ gone 0x06 NA config7 0x07 0xFFFF config8 0x08 0x0000 config9 0x09 0x8000 config10 0x0A 0x0000 reserved config11 0x0B 0x0000 config12 0x0C 0x0400 config13 0x0D 0x0400 config14 0x0E 0x0400 config15 0x0F 0x0400 config16 0x10 0x0000 config17 0x11 0x0000 reserved config18 0x12 0x0000 phase_offsetAB(15:0) config19 0x13 0x0000 phase_offsetCD(15:0) config20 0x14 0x0000 phase_addAB(15:0) config21 0x15 0x0000 phase_addAB(31:16) config22 0x16 0x0000 phase_addCD(15:0) config23 0x17 0x0000 phase_addCD(31:16) config24 0x18 NA config25 0x19 0x0440 config27 0x1B 0x0000 config28 0x1C 0x0000 (1) alarms_from_fifo(2:0) alarm_ dataclk_ gone config6 0x0020 reserved alarm_ dacclk_ gone 0x05 0x1A sif_txenable iotest_results(15:0) alarm_ from_ zerochk config5 config26 reserved reserved reserved alarm_ from_pll tempdata(7:0) alarm_ Aparity alarm_ Bparity alarm_ Cparity reserved alarm_ Dparity reserved reserved reserved alarms_mask(15:0) reserved reserved reserved qmc_offsetA(12:0) reserved reserved qmc_offsetC(12:0) reserved reserved reserved reserved reserved reserved fifo_offset(2:0) qmc_offsetB(12:0) qmc_offsetD(12:0) reserved cmix(3:0) reserved qmc_gainA(10:0) reserved qmc_gainB(10:0) reserved reserved qmc_gainC(10:0) output_delayAB(1:0) output_delayCD(1:0) reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved pll_reset qmc_gainD(10:0) qmc_phaseAB(11:0) qmc_phaseCD(11:0) pll_ ndivsync_ ena pll_ena reserved pll_cp(1:0) pll_m(7:0) reserved reserved reserved fuse_ sleep pll_lfvolt(2:0) pll_n(3:0) pll_vco(5:0) extref_ ena pll_p(2:0) reserved reserved reserved bias_ sleep reserved reserved reserved reserved tsense_ sleep reserved pll_sleep pll_vcoitune(1:0) clkrecv_ sleep sleepA sleepB reserved sleepC sleepD reserved reserved Unless otherwise noted, all reserved registers should be programmed to default values. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 57 DAC34SH84 SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 www.ti.com Register Map (continued) Table 11. Register Map (continued) (MSB) Bit 15 Name Address Default Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 config29 0x1D 0x0000 config30 0x1E 0x1111 syncsel_qmoffsetAB(3:0) syncsel_qmoffsetCD(3:0) syncsel_qmcorrAB(3:0) config31 0x1F 0x1140 syncsel_mixerAB(3:0) syncsel_mixerCD(3:0) syncsel_nco(3:0) config32 0x20 0x2400 syncsel_fifoin(3:0) syncsel_fifoout(3:0) config33 0x21 0x0000 config34 0x22 0x1B1B config35 0x23 0xFFFF config36 0x24 0x0000 config37 0x25 0x7A7A iotest_pattern0 config38 0x26 0xB6B6 iotest_pattern1 config39 0x27 0xEAEA iotest_pattern2 config40 0x28 0x4545 iotest_pattern3 config41 0x29 0x1A1A iotest_pattern4 config42 0x2A 0x1616 iotest_pattern5 config43 0x2B 0xAAAA iotest_pattern6 config44 0x2C 0xC6C6 Bit 4 reserved Bit 3 Bit 1 (LSB) Bit 0 reserved syncsel_qmcorrCD(3:0) syncsel_fifo_input sif_sync reserved clkdiv_ sync_sel reserved reserved pathA_in_set(1:0) pathB_in_set(1:0) pathC_in_set(1:0) pathD_in_set(1:0) DACA_out_set(1:0) DACB_out_set(1:0) DACC_out_set(1:0) DACD_out_set(1:0) sleep_cntl(15:0) datadly(2:0) clkdly(2:0) reserved iotest_pattern7 reserved ostrtodig_ sel config45 0x2D 0x0004 config46 0x2E 0x0000 grp_delayA(7:0) grp_delayB(7:0) config47 0x2F 0x0000 grp_delayC(7:0) grp_delayD(7:0) config48 0x30 0x0000 version 0x7F 0x5428 58 Bit 2 ramp_ena reserved sifdac_ena sifdac(15:0) reserved reserved reserved Submit Documentation Feedback die_id_34SH84(1:0) deviceid(1:0) versionid(2:0) Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 DAC34SH84 www.ti.com SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 7.6.1 Register Descriptions Table 12. Register Name: config0 – Address: 0x00, Default: 0x049C Register Name Address Bit Name config0 0x00 15 qmc_offsetAB_ena When set, the digital quadrature modulator correction (QMC) offset correction for the AB data path is enabled. 0 14 qmc_offsetCD_ena When set, the digital QMC offset correction for the CD data path is enabled. 0 13 qmc_corrAB_ena When set, the QMC phase and gain correction circuitry for the AB data path is enabled. 0 12 qmc_corrCD_ena When set, the QMC phase and gain correction circuitry for the CD data path is enabled. 0 interp(3:0) These bits define the interpolation factor. 11:8 Default Value Function 0100 interp Interpolation Factor 0000 1× 0001 2× 0010 4× 0100 8× 1000 16× 7 fifo_ena When set, the FIFO is enabled. When the FIFO is disabled. DACCCLKP/N and DATACLKP/N must be aligned (not recommended). 1 6 Reserved Reserved for factory use 0 5 Reserved Reserved for factory use 0 4 alarm_out_ena When set, the ALARM pin becomes an output. When cleared, the ALARM pin is in the high-impedance state. 1 3 alarm_out_pol This bit changes the polarity of the ALARM signal. MM 0: Negative logic MM 1: Positive logic 1 2 clkdiv_sync_ena When set, enables the syncing of the clock divider and the FIFO output pointer using the sync source selected by register config32. The internal divided-down clocks are phase-aligned after syncing. See the Power-Up Sequence section for more detail. 1 1 invsincAB_ena When set, the inverse sinc filter for the AB data path is enabled. 0 0 invsincCD_ena When set, the inverse sinc filter for the CD data path is enabled. 0 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 59 DAC34SH84 SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 www.ti.com Table 13. Register Name: config1 – Address: 0x01, Default: 0x040E Register Name Address Bit config1 0x01 15 iotest_ena When set, enables the data pattern checker test. The outputs are deactivated regardless of the state of TXENA and sif_txenable. 0 14 Reserved Reserved for factory use 0 13 Reserved Reserved for factory use 0 12 64cnt_ena When set, enables resetting of the alarms after 64 good samples with the goal of removing unnecessary errors. For instance, when checking setup or hold through the pattern checker test, there may initially be errors. Setting this bit removes the need for a SIF write to clear the alarm register. 0 11 oddeven_parity Selects between odd and even parity check MM 0: Even parity MM 1: Odd parity 0 10 parity_ena When set, enables parity checking of each input word using the 1 PARITYP/N parity input. It should match the oddeven_parity register setting. 1 9 single_dual_parity When set, enables dual parity checking; otherwise, single parity checking. The parity bit should match the oddeven_parity register setting. parity_ena must be set for dual parity to function. 0 8 rev_interface When set, the PARITY, SYNC, and ISTR inputs are rotated to allow complete reversal of the data interface when setting the rev_interface bit. When rev_interface = 1, the following changes occurs MM 1. SYNCP/N becomes ISTRP/N. MM 2. PARITYP/N becomes SYNCP/N. MM 3. ISTRP/N becomes PARITYP/N. 0 7 dacA_complement When set, the DACA output is complemented. This allows effectively changing the + and – designations of the LVDS data lines. 0 6 dacB_complement When set, the DACB output is complemented. This allows effectively changing the + and – designations of the LVDS data lines. 0 5 dacC_complement When set, the DACC output is complemented. This allows effectively changing the + and – designations of the LVDS data lines. 0 4 dacD_complement When set, the DACD output is complemented. This allows effectively changing the + and – designations of the LVDS data lines. 0 3 alarm_2away_ena When set, the alarm from the FIFO indicating the write and read pointers being 2 away is enabled. 1 2 alarm_1away_ena When set, the alarm from the FIFO indicating the write and read pointers being 1 away is enabled. 1 1 alarm_collision_ena When set, the alarm from the FIFO indicating a collision between the write and read pointers is enabled. 1 0 Reserved Reserved for factory use 0 60 Name Function Submit Documentation Feedback Default Value Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 DAC34SH84 www.ti.com SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 Table 14. Register Name: config2 – Address: 0x02, Default: 0x7000 Register Name Address Bit config2 0x02 15 Reserved Reserved for factory use 0 14 dacclkgone_ena When set, the DACCLK-gone signal from the clock monitor circuit can be used to shut off the DAC outputs. The corresponding alarms, alarm_dacclk_gone and alarm_output_gone, must not be masked (for example, config7, bit and bit must set to 0). 1 13 dataclkgone_ena When set, the DATACLK-gone signal from the clock monitor circuit can be used to shut off the DAC outputs. The corresponding alarms, alarm_dataclk_gone and alarm_output_gone, must not be masked (for example, config7, bit and bit must set to 0). 1 12 collisiongone_ena When set, the FIFO collision alarms can be used to shut off the DAC outputs. The corresponding alarms, alarm_fifo_collision and alarm_output_gone, must not be masked (for example, config7, bit and bit must set to 0). 1 11 Reserved Reserved for factory use 0 10 Reserved Reserved for factory use 0 9 Reserved Reserved for factory use 0 8 Reserved Reserved for factory use 0 7 sif4_ena When set, the serial interface (SIF) is a 4-bit interface; otherwise, it is a 3-bit interface. 0 6 mixer_ena When set, the mixer block is enabled. 0 5 mixer_gain When set, a 6-dB gain is added to the mixer output. 0 4 nco_ena When set, the NCO is enabled. This is not required for coarse mixing. 0 3 revbus When set, the input bits for the data bus are reversed. MSB becomes LSB. 0 2 Reserved Reserved for factory use 0 1 twos When set, the input data format is expected to be 2s-complement. When cleared, the input is expected to be offset-binary. 0 0 Reserved Reserved for factory use 0 Name Default Value Function Table 15. Register Name: config3 – Address: 0x03, Default: 0xF000 Register Name Address Bit config3 0x03 15:12 Name coarse_dac(3:0) Default Value Function Scales the output current in 16 equal steps. IFS 1111 V = EXTIO ´ 2 ´ (coarse _ dac + 1) RBIAS 11:8 Reserved Reserved for factory use 0000 7:1 Reserved Reserved for factory use 0000 000 sif_txenable When set, the internal value of TXENABLE is set to 1. To enable analog output data transmission, set sif_txenable to 1 or pull the CMOS TXENA pin (N9) to high. To disable analog output, set sif_txenable to 0 and pull the CMOS TXENA pin (N9) to low. 0 0 Table 16. Register Name: config4 – Address: 0x04, Default: No RESET Value (Write to Clear) Register Name Address Bit config4 0x04 15:0 Name iotest_results(15:0) Default Value Function Bits in iotest_results with a logic value of 1 tell which bit in either DAB[15:0] bus or DCD[15:0] bus failed during the pattern checker test. iotest_results(15:8) correspond to the data bits on both DAB[15:8] and DCD[15:8]. iotest_results(7:0) correspond to the data bits on both DAB[7:0] and DCD[7:0]. No RESET value Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 61 DAC34SH84 SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 www.ti.com Table 17. Register Name: config5 – Address: 0x05, Default: Setup and Power-Up Conditions Dependent (Write to Clear) Register Name Address config5 0x05 Bit Name Function Default Value 15 alarm_from_zerochk This alarm indicates the 8-bit FIFO write pointer address has an allzeros pattern. Due to the pointer address being a shift register, this is not a valid address and causes the write pointer to be stuck until the next sync. This error is typically caused by a timing error or improper power start-up sequence. If this alarm is asserted, resynchronization of the FIFO is necessary. See the Power-Up Sequence section for more detail. NA 14 Reserved Reserved for factory use NA alarms_from_fifo(2:0) Alarm indicating FIFO pointer collisions and nearness: MM 000: All fine MM 001: Pointers are 2 away. MM 01x: Pointers are 1 away. MM 1xx: FIFO pointer collision If the FIFO pointer collision alarm is set when collisiongone_ena is enabled, the FIFO must be re-synchronized and the bits must be cleared to resume normal operation. NA 10 alarm_dacclk_gone Alarm indicating the DACCLK has been stopped. If the bit is set when dacclkgone_ena is enabled, DACCLK must resume and the bit must be cleared to resume normal operation. NA 9 alarm_dataclk_gone Alarm indicating the DATACLK has been stopped. If the bit is set when dataclkgone_ena is enabled, DATACLK must resume and the bit must be cleared to resume normal operation. NA 8 alarm_output_gone Alarm indicating either alarm_dacclk_gone, alarm_dataclk_gone, or alarm_fifo_collision are asserted. It controls the output. When high, it outputs 0x8000 for each output connected to the DAC. If the bit is set when dacclkgone_ena, dataclkgone_ena, or collisiongone_ena are enabled, then the corresponding errors must be fixed and the bits must be cleared to resume normal operation. NA 7 alarm_from_iotest Alarm indicating the input data pattern does not match the pattern in the iotest_pattern registers. When the data pattern checker mode is enabled, this alarm in register config5, bit7 is the only valid alarm. Other alarms in register config5 are not valid and can be disregarded. NA 6 Reserved Reserved for factory use NA 5 alarm_from_pll Alarm indicating the PLL has lost lock. For version ID 001, alarm_from_PLL may not indicate the correct status of the PLL. See pll_lfvolt(2:0) in register config24 for proper PLL lock indication. NA 4 alarm_Aparity In dual-parity mode, an alarm indicating a parity error on the A word. In single-parity mode, an alarm on the 32-bit data captured on the rising edge of DATACLKP/N. NA 3 alarm_Bparity In dual-parity mode, an alarm indicating a parity error on the B word. In single-parity mode, an alarm on the 32-bit data captured on the falling edge of DATACLKP/N. NA 2 alarm_Cparity In dual-parity mode, an alarm indicating a parity error on the C word. NA 1 alarm_Dparity In dual-parity mode, an alarm indicating a parity error on the D word. NA 0 Reserved Reserved for factory use NA 13:11 Table 18. Register Name: config6 – Address: 0x06, Default: No RESET Value (Read Only) Register Name Address Bit config6 0x06 15:8 tempdata(7:0) This is the output from the chip temperature sensor. The value of this register in 2s-complement format represents the temperature in degrees Celsius. This register must be read with a minimum SCLK period of 1 μs. No RESET Value 7:2 Reserved Reserved for factory use 0000 00 1 Reserved Reserved for factory use 0 0 Reserved Reserved for factory use 0 62 Name Function Submit Documentation Feedback Default Value Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 DAC34SH84 www.ti.com SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 Table 19. Register Name: config7 – Address: 0x07, Default: 0xFFFF Register Name Address Bit config7 0x07 15:0 Name alarms_mask(15:0) Default Value Function These bits control the masking of the alarms. (0 = not masked, 1 = masked) alarm_mask Alarm That Is Masked 15 alarm_from_zerochk 14 Not used 13 alarm_fifo_collision 12 alarm_fifo_1away 11 alarm_fifo_2away 10 alarm_dacclk_gone 9 alarm_dataclk_gone 8 alarm_output_gone 7 alarm_from_iotest 6 Not used 5 alarm_from_pll 4 alarm_Aparity 3 alarm_Bparity 2 alarm_Cparity 1 alarm_Dparity 0 Not used 0xFFFF Table 20. Register Name: config8 – Address: 0x08, Default: 0x0000 (Causes Auto-Sync) Register Name Address Bit config8 0x08 15 Reserved Reserved for factory use 0 14 Reserved Reserved for factory use 0 13 Reserved Reserved for factory use qmc_offsetA(12:0) DACA offset correction. The offset is measured in DAC LSBs. If enabled in config30, writing to this register causes an auto-sync to be generated. This loads the values of the QMC offset registers (config8–config9) into the offset block at the same time. When updating the offset values for the AB channel, config8 should be written last. Programming config9 does not affect the offset setting. Name 12:0 Default Value Function 0 All zeros Table 21. Register Name: config9 – Address: 0x09, Default: 0x8000 Register Name Address Bit config9 0x09 15:13 fifo_offset(2:0) When the sync to the FIFO occurs, this is the value loaded into the FIFO read pointer. With this value, the initial difference between write and read pointers can be controlled. This may be helpful in syncing multiple chips or controlling the delay through the device. 12:0 qmc_offsetB(12:0) DACB offset correction. The offset is measured in DAC LSBs. Name Default Value Function 100 All zeros Table 22. Register Name: config10 – Address: 0x0A, Default: 0x0000 (Causes Auto-Sync) Register Name Address Bit config10 0x0A 15 Reserved Reserved for factory use 0 14 Reserved Reserved for factory use 0 13 Reserved Reserved for factory use qmc_offsetC(12:0) DACC offset correction. The offset is measured in DAC LSBs. If enabled in config30 writing to this register causes an auto-sync to be generated. This loads the values of the CD-channel QMC offset registers (config10-config11) into the offset block at the same time. When updating the offset values for the CD-channel config10 should be written last. Programming config11 does not affect the offset setting. 12:0 Name Default Value Function 0 All zeros Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 63 DAC34SH84 SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 www.ti.com Table 23. Register name: config11 – Address: 0x0B, Default: 0x0000 Register Name Address Bit config11 0x0B 15 Reserved Reserved for factory use 0 14 Reserved Reserved for factory use 0 13 Reserved Reserved for factory use qmc_offsetD(12:0) DACD offset correction. The offset is measured in DAC LSBs. 12:0 Name Function Default Value 0 All zeros Table 24. Register Name: config12 – Address: 0x0C, Default: 0x0400 Register Name Address Bit config12 0x0C 15 Reserved Reserved for factory use 0 14 Reserved Reserved for factory use 0 13 Reserved Reserved for factory use 0 12 Reserved Reserved for factory use 0 11 Reserved Reserved for factory use qmc_gainA(10:0) QMC gain for DACA. The full 11-bit qmc_gainA(10:0) word is formatted as UNSIGNED with a range of 0 to 1.9990. The implied decimal point for the multiplication is between bit 9 and bit 10. 10:0 Name Function Default Value 0 100 0000 0000 Table 25. Register Name: config13 – Address: 0x0D, Default: 0x0400 Register Name Address Bit config13 0x0D 15:12 11 10:0 Name Function cmix_mode(3:0) Sets the mixing function of the coarse mixer. MM Bit 15: fS / 8 mixer MM Bit 14: fS / 4 mixer MM Bit 13: fS / 2 mixer MM Bit 12: –fS / 4 mixer The various mixers can be combined together to obtain a ±n × fS / 8 total mixing factor. Reserved Reserved for factory use qmc_gainB(10:0) QMC gain for DACB. The full 11-bit qmc_gainB(10:0) word is formatted as UNSIGNED with a range of 0 to 1.9990. The implied decimal point for the multiplication is between bit 9 and bit 10. Default Value 0000 0 100 0000 0000 Table 26. Register Name: config14 – Address: 0x0E, Default: 0x0400 Register Name Address Bit config14 0x0E 15 Reserved Reserved for factory use 0 14 Reserved Reserved for factory use 0 13 Reserved Reserved for factory use 0 12 Reserved Reserved for factory use 0 11 Reserved Reserved for factory use qmc_gainC(10:0) QMC gain for DACC. The full 11-bit qmc_gainC(10:0) word is formatted as UNSIGNED with a range of 0 to 1.9990. The implied decimal point for the multiplication is between bit 9 and bit 10. 10:0 Name Function Default Value 0 100 0000 0000 Table 27. Register Name: config15 – Address: 0x0F, Default: 0x0400 Register Name Address Bit config15 0x0F 15:14 output_ delayAB(1:0) Delays the AB data path outputs from 0 to 3 DAC clock cycles 00 13:12 output_ delayCD(1:0) Delays the CD data path outputs from 0 to 3 DAC clock cycles 00 Reserved Reserved for factory use qmc_gainD(10:0) QMC gain for DACD. The full 11-bit qmc_gainD(10:0) word is formatted as UNSIGNED with a range of 0 to 1.9990. The implied decimal point for the multiplication is between bit 9 and bit 10. 11 10:0 64 Name Function Submit Documentation Feedback Default Value 0 100 0000 0000 Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 DAC34SH84 www.ti.com SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 Table 28. Register Name: config16 – Address: 0x10, Default: 0x0000 (Causes Auto-Sync) Register Name Address Bit config16 0x10 15 Reserved Reserved for factory use 0 14 Reserved Reserved for factory use 0 13 Reserved Reserved for factory use 0 12 Reserved Reserved for factory use qmc_phaseAB(11:0) QMC correction phase for the AB data path. The 12-bit qmc_phaseAB(11:0) word is formatted as 2s-complement and scaled to occupy a range of –0.5 to 0.49975 and a default phase correction of 0.00. To accomplish QMC phase correction, this value is multiplied by the current B sample, then summed into the A sample. If enabled in config30, writing to this register causes an auto-sync to be generated. This loads the values of the QMC offset registers (config12, config13, and config16) into the QMC block at the same time. When updating the QMC values for the AB channel, config16 should be written last. Programming config12 and config13 does not affect the QMC settings. 11:0 Name Default Value Function 0 All zeros Table 29. Register Name: config17 – Address: 0x11, Default: 0x0000 (Causes Auto-Sync) Register Name Address Bit config17 0x11 15 Reserved Reserved for factory use 0 14 Reserved Reserved for factory use 0 13 Reserved Reserved for factory use 0 12 Reserved Reserved for factory use qmc_phaseCD(11:0) QMC correction phase for the CD data path. The 12-bit qmc_gainCD(11:0) word is formatted as 2s-complement and scaled to occupy a range of –0.5 to 0.49975 and a default phase correction of 0.00. To accomplish QMC phase correction, this value is multiplied by the current D sample, then summed into the C sample. If enabled in config30, writing to this register causes an auto-sync to be generated. This loads the values of the CD-channel QMC block registers (config14, config15, and config17) into the QMC block at the same time. When updating the QMC values for the CD-channel, config17 should be written last. Programming config14 and config15 does not affect the QMC settings. 11:0 Name Default Value Function 0 All zeros Table 30. Register Name: config18 – Address: 0x12, Default: 0x0000 (Causes Auto-Sync) Register Name Address Bit Name Function config18 0x12 15:0 phase_offsetAB(15:0) Phase offset added to the AB data path NCO accumulator before the generation of the SIN and COS values. The phase offset is added to the upper 16 bits of the NCO accumulator results, and these 16 bits are used in the sin and cos lookup tables. If enabled in config31, writing to this register causes an auto-sync to be generated. This loads the values of the fine mixer block registers (config18, config20, and config21) at the same time. When updating the mixer values, config18 should be written last. Programming config20 and config21 does not affect the mixer settings. Default Value 0x0000 Table 31. Register Name: config19 – Address: 0x13, Default: 0x0000 (Causes Auto-Sync) Register Name Address Bit config19 0x13 15:0 Name phase_offsetCD(15:0) Default Value Function Phase offset added to the CD data path NCO accumulator before the generation of the SIN and COS values. The phase offset is added to the upper 16 bits of the NCO accumulator results, and these 16 bits are used in the sin and cos lookup tables. If enabled in config31, writing to this register causes an auto-sync to be generated. This loads the values of the CD-channel fine mixer block registers (config19, config22, and config23) at the same time. When updating the mixer values for the CD-channel, config19 should be written last. Programming config22 and config23 does not affect the mixer settings. 0x0000 Table 32. Register Name: config20 – Address: 0x14, Default: 0x0000 Register Name Address Bit config20 0x14 15:0 Name phase_ addAB(15:0) Default Value Function The phase_addAB(15:0) value is used to determine the NCO frequency. The 2scomplement formatted value can be positive or negative. Each LSB represents an fS / (232) frequency step. 0x0000 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 65 DAC34SH84 SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 www.ti.com Table 33. Register Name: config21 – Address: 0x15, Default: 0x0000 Register Name Address Bit config21 0x15 15:0 Name phase_ addAB(31:16) Function See config20. Default Value 0x0000 Table 34. Register Name: config22 – Address: 0x16, Default: 0x0000 Register Name Address Bit config22 0x16 15:0 Name phase_ addCD(15:0) Function The phase_addCD(15:0) value is used to determine the NCO frequency. The 2scomplement formatted value can be positive or negative. Each LSB represents an fS / (232) frequency step. Default Value 0x0000 Table 35. Register Name: config23 – Address: 0x17, Default: 0x0000 Register Name Address Bit config23 0x17 15:0 Name phase_ addCD(31:16) Function See config22 above. Default Value 0x0000 Table 36. Register Name: config24 – Address: 0x18, Default: NA Register Name Address Bit config24 0x18 15:13 Reserved Reserved for factory use 12 pll_reset When set, the PLL loop filter (LPF) is pulled down to 0 V. Toggle from 1 to 0 to restart the PLL if an overspeed lockup occurs. Overspeed can happen when the process is fast, the supplies are higher than nominal, ..., resulting in the feedback dividers missing a clock. 0 11 pll_ndivsync_ena When set, the LVDS SYNC input is used to sync the PLL N dividers. 1 10 pll_ena When set, the PLL is enabled. When cleared, the PLL is bypassed. 0 9:8 Reserved Reserved for factory use 00 7:6 pll_cp(1:0) PLL pump charge select MM 00: No charge pump MM 01: Single pump charge MM 10: Not used MM 11: Dual pump charge 00 5:3 pll_p(2:0) PLL pre-scaler dividing module control MM 010: 2 MM 011: 3 MM 100: 4 MM 101: 5 MM 110: 6 MM 111: 7 MM 000: 8 001 2:0 pll_lfvolt(2:0) PLL loop filter voltage. This 3-bit read-only indicator has step size of 0.4125 V. The entire range covers from 0 V to 3.3 V. The optimal lock range of the PLL is from 010 to 101 (for example, 0.825 V to 2.063 V). Adjust pll_vco(5:0) for optimal lock range. NA 66 Name Function Submit Documentation Feedback Default Value 001 Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 DAC34SH84 www.ti.com SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 Table 37. Register Name: config25 – Address: 0x19, Default: 0x0440 Register Name Address Bit config25 0x19 15:8 pll_m(7:0) M portion of the M/N divider of the PLL. If pll_m = 0, the M divider value has the range of pll_m, spanning from 4 to 127. (for example, 0, 1, 2, and 3 are not valid.) If pll_m = 1, the M divider value has the range of 2 × pll_m, spanning from 8 to 254. (for example, 0, 2, 4, and 6 are not valid. The M divider has even values only.) 0x04 7:4 pll_n(3:0) N portion of the M/N divider of the PLL. MM 0000: 1 MM 0001: 2 MM 0010: 3 MM 0011: 4 MM 0100: 5 MM 0101: 6 MM 0110: 7 MM 0111: 8 MM 1000: 9 MM 1001: 10 MM 1010: 11 MM 1011: 12 MM 1100: 13 MM 1101: 14 MM 1110: 15 MM 1111: 16 0100 3:2 pll_vcoitune(1:0) PLL VCO bias tuning bits. Set to 01 for normal PLL operation 00 1:0 Reserved Reserved for factory use 00 Name Default Value Function Table 38. Register Name: config26 – Address: 0x1A, Default: 0x0020 Register Name Address Bit config26 0x1A 15:10 Name Default Value Function pll_vco(5:0) VCO frequency coarse-tuning bits. 9 Reserved Reserved for factory use 0000 00 0 8 Reserved Reserved for factory use 0 7 bias_sleep When set, the bias amplifier is put into sleep mode. 0 6 tsense_sleep Turns off the temperature sensor when asserted. 0 5 pll_sleep When set, the PLL is put into sleep mode. 1 4 clkrecv_sleep When asserted, the clock input receiver is put into sleep mode. This affects the OSTR receiver as well. 0 3 sleepA When set, the DACA is put into sleep mode. 0 2 sleepB When set, the DACB is put into sleep mode. 0 1 sleepC When set, the DACC is put into sleep mode. 0 0 sleepD When set, the DACD is put into sleep mode. 0 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 67 DAC34SH84 SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 www.ti.com Table 39. Register Name: config27 – Address: 0x1B, Default: 0x0000 Register Name Address Bit config27 0x1B 15 extref_ena Allows the device to use an external reference or the internal reference. 0: Internal reference 1: External reference 0 14 Reserved Reserved for factory use 0 13 Reserved Reserved for factory use 0 12 Reserved Reserved for factory use 0 11 fuse_sleep Put the fuses to sleep when set high. Note: Default value is 0. Must be set to 1 for proper operation 0 10 Reserved Reserved for factory use 0 9 Reserved Reserved for factory use 0 8 Reserved Reserved for factory use 0 7 Reserved Reserved for factory use 0 6 Reserved Reserved for factory use atest ATEST mode allows the user to check for the internal die voltages to ensure the supply voltages are within range. When the ATEST mode is programmed, the internal die voltages can be measured at the TXENA pin. The TXENA pin (N9) must be floating without any pullup or pulldown resistors. In ATEST mode, the TXENA and sif_txenable logic is bypassed, and the output is active at all times. 5:0 Name Default Value Function 0 Config27, bit Description 00 1110 DACA AVSS 0V 00 1111 DACA DVDD 1.35 V 01 0000 DACA AVDD 3.3 V 01 0110 DACB AVSS 0V 01 0111 DACB DVDD 1.35 V 01 1000 DACB AVDD 3.3 V 01 1110 DACC AVSS 0V 01 1111 DACC DVDD 1.35 V 10 0000 DACC AVDD 3.3 V 10 0110 DACD AVSS 0V 10 0111 DACD DVDD 1.35 V 10 1000 DACD AVDD 3.3 V 11 0000 1.3VDIG 1.3 V 00 0101 1.35VCLK 1.35 V 000000 Expected Nominal Voltage Table 40. Register Name: config28 – Address: 0x1C, Default: 0x0000 Register Name Address Bit config28 0x1C 15:8 Reserved Reserved for factory use 0x00 7:0 Reserved Reserved for factory use 0x00 Name Function Default Value Table 41. Register Name: config29 – Address: 0x1D, Default: 0x0000 68 Register Name Address Bit config29 0x1D 15:8 Reserved Reserved for factory use 0x00 7:0 Reserved Reserved for factory use 0x00 Name Function Submit Documentation Feedback Default Value Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 DAC34SH84 www.ti.com SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 Table 42. Register Name: config30 – Address: 0x1E, Default: 0x1111 Register Name Address Bit Name config30 0x1E 15:12 syncsel_qmoffsetAB(3:0) Selects the syncing source(s) of the AB data path double-buffered QMC offset registers. A 1 in the bit enables the signal as a sync source. More than one sync source is permitted. MM Bit 15: sif_sync (via config31) MM Bit 14: SYNC MM Bit 13: OSTR MM Bit 12: Auto-sync from register write 0001 11:8 syncsel_qmoffsetCD(3:0) Selects the syncing source(s) of the CD data path double-buffered QMC offset registers. A 1 in the bit enables the signal as a sync source. More than one sync source is permitted. MM Bit 11: sif_sync (via config31) MM Bit 10: SYNC MM Bit 9: OSTR MM Bit 8: Auto-sync from register write 0001 7:4 syncsel_qmcorrAB(3:0) Selects the syncing source(s) of the AB data path double buffered QMC correction registers. A 1 in the bit enables the signal as a sync source. More than one sync source is permitted. MM Bit 7: sif_sync (via config31) MM Bit 6: SYNC MM Bit 5: OSTR MM Bit 4: Auto-sync from register write 0001 3:0 syncsel_qmcorrCD(3:0) Selects the syncing source(s) of the CD data path double buffered QMC correction registers. A 1 in the bit enables the signal as a sync source. More than one sync source is permitted. MM Bit 3: sif_sync (via config31) MM Bit 2: SYNC MM Bit 1: OSTR MM Bit 0: Auto-sync from register write 0001 Default Value Function Table 43. Register Name: config31 – Address: 0x1F, Default: 0x1140 Register Name Address Bit config31 0x1F 15:12 syncsel_mixerAB(3:0) Selects the syncing source(s) of the AB data path double buffered mixer registers. A 1 in the bit enables the signal as a sync source. More than one sync source is permitted. MM Bit 15: sif_sync (via config31) MM Bit 14: SYNC MM Bit 13: OSTR MM Bit 12: Auto-sync from register write 0001 11:8 syncsel_mixerCD(3:0) Selects the syncing source(s) of the CD data path double buffered mixer registers. A 1 in the bit enables the signal as a sync source. More than one sync source is permitted. MM Bit 11: sif_sync (via config31) MM Bit 10: SYNC MM Bit 9: OSTR MM Bit 8: Auto-sync from register write 0001 7:4 syncsel_nco(3:0) Selects the syncing source(s) of the two NCO accumulators. A 1 in the bit enables the signal as a sync source. More than one sync source is permitted. MM Bit 7: sif_sync (via config31) MM Bit 6: SYNC MM Bit 5: OSTR MM Bit 4: ISTR 0100 3:2 syncsel_fifo_input(1:0) Selects either the ISTR or SYNC LVDS signal to be routed to the internal FIFO_ISTR path if syncsel_fifoin(3:0) is set to be ISTR (i.e. syncsel_fifoin(3:0) = 0010). In conjunction with config1 register bit(8), this allows flexibility of external LVDS signal routing to the internal FIFO. The syncsel_fifo_input(1:0) can only have one bit active at a time. MM 00: external LVDS ISTR signal to internal FIFO_ISTR path MM 01: external LVDS SYNC signal to internal FIFO_ISTR path MM 10: external LVDS ISTR signal to internal FIFO_ISTR path MM 11: external LVDS SYNC signal to internal FIFO_ISTR path 00 1 sif_sync SIF created sync signal. Set to 1 to cause a sync and then clear to 0 to remove it. 0 0 Reserved Reserved for factory use 0 Name Default Value Function Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 69 DAC34SH84 SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 www.ti.com Table 44. Register Name: config32 – Address: 0x20, Default: 0x2400 Register Name Address Bit config32 0x20 15:12 syncsel_fifoin(3:0) Selects the syncing source(s) of the FIFO input side. A 1 in the bit enables the signal as a sync source. More than one sync source is permitted. MM Bit 15: sif_sync (via config31) MM Bit 14: Always zero MM Bit 13: ISTR MM Bit 12: SYNC 0010 11:8 syncsel_fifoout(3:0) Selects the syncing source(s) of the FIFO output side. A 1 in the bit enables the signal as a sync source. More than one sync source is permitted. clkdiv_sync_ena must be set to 1 for the FIFO output pointer sync to occur. MM Bit 11: sif_sync (via config31) MM Bit 10: OSTR – Dual-sync-sources mode MM Bit 9: ISTR – Single-sync-source mode MM Bit 8: SYNC – Single-sync-source mode 0100 7:1 Reserved Reserved for factory use 0000 clkdiv_sync_sel Selects the signal source for clock divider synchronization 0 Name Default Value Function clkdiv_sync_sel 0 Sync Source 0 OSTR 1 ISTR, SYNC, or SIF SYNC, based on syncsel_fifoin source selection (config32, bits) Table 45. Register Name: config33 – Address: 0x21, Default: 0x0000 Register Name Address Bit config33 0x21 15:0 Name Reserved Function Reserved for factory use Default Value 0x0000 Table 46. Register Name: config34 – Address: 0x22, Default: 0x1B1B 70 Register Name Address Bit config34 0x22 15:14 pathA_in_sel(1:0) Selects the word used for the A channel path 00 13:12 pathB_in_sel(1:0) Selects the word used for the B channel path 01 11:10 pathC_in_sel(1:0) Selects the word used for the C channel path 10 9:8 pathD_in_sel(1:0) Selects the word used for the D channel path 11 7:6 DACA_out_sel(1:0) Selects the word used for the DACA output 00 5:4 DACB_out_sel(1:0) Selects the word used for the DACB output 01 3:2 DACC_out_sel(1:0) Selects the word used for the DACC output 10 1:0 DACD_out_sel(1:0) Selects the word used for the DACD output 11 Name Function Submit Documentation Feedback Default Value Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 DAC34SH84 www.ti.com SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 Table 47. Register Name: config35 – Address: 0x23, Default: 0xFFFF Register Name Address Bit config35 0x23 15:0 Name Default Value Function sleep_cntl(15:0) Controls the routing of the CMOS SLEEP signal (pin N11) to different blocks. When a bit in this register is set, the SLEEP signal is sent to the corresponding block. The block is only disabled when the SLEEP is logic HIGH and the corresponding bit is set to 1. 0xFFFF These bits do not override the SIF bits in config26 that control the same sleep function. sleep_cntl(bit) Function 15 DACA sleep 14 DACB sleep 13 DACC sleep 12 DACD sleep 11 Clock receiver sleep 10 PLL sleep 9 LVDS data sleep 8 LVDS control sleep 7 Temp sensor sleep 6 Reserved 5 Bias amplifier sleep All others Not used Table 48. Register Name: config36 – Address: 0x24, Default: 0x0000 Register Name Address Bit config36 0x24 15:13 datadly(2:0) Controls the delay of the data inputs through the LVDS receivers. Each LSB adds approximately 40 ps 0: Minimum 000 12:10 clkdly(2:0) Controls the delay of the data clock through the LVDS receivers. Each LSB adds approximately 40 ps 0: Minimum 000 9:0 Reserved Reserved for factory use Name Default Value Function 0x000 Table 49. Register Name: config37 – Address: 0x25, Default: 0x7A7A Register Name Address Bit config37 0x25 15:0 Name iotest_pattern0 Default Value Function Dataword0 in the IO test pattern. It is used with the seven other words to test the input data. At the start of the IO test pattern, this word should be aligned with rising edge of ISTR or SYNC signal to indicate sample 0. 0x7A7A Table 50. Register Name: config38 – Address: 0x26, Default: 0xB6B6 Register Name Address Bit config38 0x26 15:0 Name iotest_pattern1 Default Value Function Dataword1 in the IO test pattern. It is used with the seven other words to test the input data. 0xB6B6 Table 51. Register Name: config39 – Address: 0x27, Default: 0xEAEA Register Name Address Bit config39 0x27 15:0 Name iotest_pattern2 Default Value Function Dataword2 in the IO test pattern. It is used with the seven other words to test the input data. 0xEAEA Table 52. Register Name: config40 – Address: 0x28, Default: 0x4545 Register Name Address Bit config40 0x28 15:0 Name iotest_pattern3 Function Default Value Dataword3 in the IO test pattern. It is used with the seven other words to test the input data. 0x4545 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 71 DAC34SH84 SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 www.ti.com Table 53. Register Name: config41 – Address: 0x29, Default: 0x1A1A Register Name Address Bit Name config41 0x29 15:0 iotest_pattern4 Function Dataword4 in the IO test pattern. It is used with the seven other words to test the input data. Default Value 0x1A1A Table 54. Register Name: config42 – Address: 0x2A, Default: 0x1616 Register Name Address Bit config42 0x2A 15:0 Name iotest_pattern5 Function Dataword5 in the IO test pattern. It is used with the seven other words to test the input data. Default Value 0x1616 Table 55. Register Name: config43 – Address: 0x2B, Default: 0xAAAA Register Name Address Bit config43 0x2B 15:0 Name iotest_pattern6 Function Dataword6 in the IO test pattern. It is used with the seven other words to test the input data. Default Value 0xAAAA Table 56. Register Name: config44 – Address: 0x2C, Default: 0xC6C6 Register Name Address Bit config44 0x2C 15:0 Name iotest_pattern7 Function Dataword7 in the IO test pattern. It is used with the seven other words to test the input data. Default Value 0xC6C6 Table 57. Register Name: config45 – Address: 0x2D, Default: 0x0004 Register Name Address Bit config45 0x2D 15 Reserved Reserved for factory use 0 14 ostrtodig_sel When set, the OSTR signal is passed directly to the digital block. This is the signal that is used to clock the dividers. 0 Name Function 13 ramp_ena When set, a ramp signal is inserted in the input data at the FIFO input. 12:1 Reserved Reserved for factory use 0 sifdac_ena When set, the DAC output is set to the value in sifdac(15:0) in register config48. Default Value 0 0000 0000 0010 0 Table 58. Register Name: config46 – Address: 0x2E, Default: 0x0000 Register Name Address Bit config46 0x2E 15:0 Name Reserved Function Reserved for factory use Default Value 0x00 Table 59. Register Name: config47 – Address: 0x2F, Default: 0x0000 Register Name Address Bit config47 0x2F 15:0 Name Reserved Function Reserved for factory use Default Value 0x00 Table 60. Register Name: config48 – Address: 0x30, Default: 0x0000 Register Name Address Bit config48 0x30 15:0 72 Name sifdac(15:0) Function Value sent to the DACs when sifdac_ena is asserted. DATACLK must be running to latch this value into the DACs. The format would be based on twos in register config2. Submit Documentation Feedback Default Value 0x0000 Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 DAC34SH84 www.ti.com SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 Table 61. Register Name: Version– Address: 0x7F, Default: 0x5409 (Read Only) Register Name Address Bit version 0x7F 15:10 Reserved Reserved for factory use 9 Reserved Reserved for factory use 0 8:7 Reserved Reserved for factory use 00 6:5 die_id_34SH84(1:0) Returns 01 for DAC34SH84 01 4:3 deviceid(1:0) Returns 01 for DAC34SH84 01 2:0 versionid(2:0) A hardwired register that contains the version of the chip 001 Name Default Value Function 0101 01 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 73 DAC34SH84 SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The DAC34SH84 is a dual 16-bit DAC with max input data rate of up to 750 MSPS per DAC and max DAC update rate of 1.5 GSPS after the final, selectable interpolation stages. With build-in interpolation filter of 2x, 4x, 8x, and 16x options, the lower input data rate can be interpolated all the way to 1.5 GSPS. This allows the DAC to update the samples at higher rate, and pushes the DAC images further away to relax anti-image filer specification due to the increased Nyquist bandwidth. With integrated coarse and fine mixers, baseband signal can be upconverted to an intermediate frequency (IF) signal between the baseband processor and post-DAC analog signal chains. The DAC can output baseband or IF when connected to post-DAC analog signals chain components such as transformers or IF amplifiers. When used in conjunction with TI RF quadrature modulator such as the TRF3705, the DAC and RF modulator can function as a set of baseband or IF upconverter. With integrated QMC circuits, the LO offset and the sideband artifacts can be properly corrected in the direct up-conversion applications. The DAC34SH84 provides the bandwidth, performance, small footprint, and lower power consumption needed for multi-mode 2G/3G/4G cellular base stations to migrate to more advanced technologies, such as LTE-Advanced and carrier aggregation on multiple antennas. 74 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 DAC34SH84 www.ti.com SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 8.2 Typical Applications 8.2.1 IF Based LTE Transmitter Figure 88 shows an example block diagram for a direct conversion radio. The design requires a single carrier, 20-MHz LTE signal. The system has digital-predication (DPD) to correct up to 5th order distortion so the total DAC output bandwidth is 100 MHz. Interpolation is used to output the signal at highest sampling rate possible to simplify the analog filter requirements and move high order harmonics out of band (due to wider Nyquist zone). The internal PLL is used to generate the final DAC output clock from a reference clock of 491.52 MHz. DAC34SH84 Complex Mixer (48-bit NCO) FPGA 16-bit DAC TRF3705 RF TRF3705 RF 16-bit DAC xN Complex Mixer (48-bit NCO) LVDS Interface xN xN 16-bit DAC 16-bit DAC xN Clock Distribution PLL TRF3765 DACCLK SYSREF LMK04828 Figure 88. Dual Low-IF Wideband LTE Transmitter Diagram 8.2.1.1 Design Requirements For this design example, use the parameters listed in Table 62 as the input parameters. Table 62. Design Parameters DESIGN PARAMETER EXAMPLE VALUE Signal Bandwidth (BWsignal) 20 MHz Total DAC Output Bandwidth (BWtotal) 100 MHz DAC PLL On DAC PLL Reference Frequency 491.52 MHz Maximum FPGA LVDS Rate 491.52 Mbps Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 75 DAC34SH84 SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 www.ti.com 8.2.1.2 Detailed Design Procedure 8.2.1.2.1 Data Input Rate Nyquist theory states that the data rate must be at least two times the highest signal frequency. The data will be sent to the DAC as complex baseband data. Due to the quadrature nature of the signal, each in-phase (I component) and quadrature (Q component) need to have 50 MHz of bandwidth to construct 100 MHz of complex bandwidth. Since the interpolation filter design is not the ideal half-band filter design with infinite roll-off at FDATA/2 (refer to FIR Filters section for more detail), the filter limits the useable input bandwidth to about 40 percent of FDATA. Therefore, the minimum data input rate is 125 MSPS. Since the standard telecom data rate is typically multiples of 30.72 MSPS, the DAC input data rate is chosen to be eight times of 30.72 MSPS, which is 245.76 MSPS. 8.2.1.2.2 Interpolation It is desired to use the highest DAC output rate as possible to move the DAC images further from the signal of interest to ease analog filter requirement. The DAC output rate must be greater than two times the highest output frequency of 200 MHz, which is greater than 400 MHz. Table 63 shows the possible DAC output rates based on the data input rate and available interpolation settings. The DAC image frequency is also listed. Table 63. Interpolation FDATA INTERPOLATION FDAC POSSIBLE? LOWEST IMAGE FREQUENCY DISTANCE FROM BAND OF INTEREST 245.76 MSPS 1 245.76 MSPS No N/A N/A 245.76 MSPS 2 491.52 MSPS Yes 318.64 MHz 145.76 MHz 245.76 MSPS 4 983.04 MSPS Yes 810.16 MHz 637.28 MHz 245.76 MSPS 8 1966.08 MSPS No N/A N/A 245.76 MSPS 16 3932.16 MSPS No N/A N/A 8.2.1.2.3 LO Feedthrough and Sideband Correction For typical IF based systems, the IF location is selected such that the image location and the LO feedthrough location is far from the signal location. The minimum distance is based on the bandpass filter roll-off and attenuation level at the LO feedthrough and image location. If sufficient attenuation level of these two artifacts meets the system requirement, then further digital cancellation of these artifacts may not be needed. Although the I/Q modulation process will inherently reduce the level of the RF sideband signal, an IF based transmitter without sufficient RF image rejection capabilities or an zero-IF based system (detail in the next section) will likely need additional sideband suppression to maximize performance. Further, any mixing process will result in some feedthrough of the LO source. The DAC34SH84 has build-in digital features to cancel both the LO feedthrough and sideband signal. The LO feedthrough is corrected by adding a DC offset to the DAC outputs until the LO feedthrough power is suppressed. The sideband suppression can be improved by correcting the gain and phase differences between the I and Q analog outputs through the digital QMC block. Besides gain and phase differences between the I and Q analog outputs, group delay differences may also be present in the signal path and are typically contributed by group delay variations of post DAC image reject analog filters and PCB trace variations. Since delay in time translates to higher order linear phase variation, the sideband of a wideband system may not be completely suppressed by typical digital QMC block. The system designer may implement additional linear group delay compensation in the host processor to the DAC to perform higher order sideband suppression. 76 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 DAC34SH84 www.ti.com SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 8.2.1.3 Application Curves The ACPR performance for LTE 20 MHz TM1.1 are shown in Figure 89, Figure 90, Figure 90, and Figure 90. The figures provide comparisons between two major LTE bands such as 2.14 GHz and 2.655 GHz, and also comparisons between two different DAC clocking options such as DAC on-chip PLL mode and external clocking mode. DAC Output IF = 122.88 MHz, LO = 2017.12 MHz, DAC Clock = External Clock Source from LMK04806 Figure 89. 20MHz TM1.1 LTE Carrier at 2.14GHz DAC Output IF = 122.88 MHz, LO = 2532.12 MHz, DAC Clock = External Clock Source from LMK04806 Figure 91. 20MHz TM1.1 LTE Carrier at 2.655GHz DAC Output IF = 122.88 MHz, LO = 2017.12 MHz, DAC Clock = DAC34SH84 On-Chip PLL Figure 90. 20MHz TM1.1 LTE Carrier at 2.14GHz DAC Output IF = 122.88 MHz, LO = 2532.12 MHz, DAC Clock = DAC34SH84 On-Chip PLL Figure 92. 20MHz TM1.1 LTE Carrier at 2.655GHz Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 77 DAC34SH84 SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 www.ti.com 8.2.2 Direct Upconversion (Zero IF) LTE Transmitter Figure 88 shows an example block diagram for a direct conversion radio. The design specification requires that the desired output bandwidth is 100 MHz, which could be, for instance, a typical LTE signal. The system has DPD to correct up to 5th order distortion so the total DAC output bandwidth is 500 MHz. Interpolation is used to output the signal at the highest sampling rate possible to simplify the analog filtering requirements and move high order harmonics out of band (due to wider Nyquist zone). The DAC sampling clock is provided by high quality clock synthesizer such as the LMK0480x family. DAC34SH84 QMC Gain, Phase, Offset FPGA xN QMC Gain, Phase, Offset LVDS Interface xN xN xN 16-bit DAC TRF3705 RF TRF3705 RF 16-bit DAC 16-bit DAC 16-bit DAC Clock Distribution TRF3765 DACCLK SYSREF LMK04828 Figure 93. Zero LTE Transmitter Diagram 8.2.2.1 Design Requirements For this design example, use the parameters listed in Table 64 as the input parameters. Table 64. Design Parameters 78 DESIGN PARAMETER EXAMPLE VALUE Signal Bandwidth (BWsignal) 100 MHz Total DAC Output Bandwidth (BWtotal) 500 MHz DAC PLL Off Maximum FPGA LVDS Rate 1228.8 Mbps Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 DAC34SH84 www.ti.com SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 8.2.2.2 Detailed Design Procedure 8.2.2.2.1 Data Input Rate Nyquist theory states that the data rate must be at least two times the highest signal frequency. The data will be sent to the DAC as complex baseband data. Due to the quadrature nature of the signal, each in-phase (I component) and quadrature (Q component) need to have 250 MHz of bandwidth to construct 500 MHz of complex bandwidth. Since the interpolation filter design is not the ideal half-band filter design with infinite roll-off at FDATA/2 (refer to FIR Filters section for more detail), the filter limits the useable input bandwidth to about 44 percent of FDATA with less than 0.1dB of FIR filter roll-off. Therefore, the minimum data input rate is 568 MSPS. Since the standard telecom data rate is typically multiples of 30.72 MSPS, the DAC input data rate is chosen to be 20 times of 30.72 MSPS, which is 614.4 MSPS. For the DAC34SH84, input data rate of 737.28 MSPS may also be used to meet additional bandwidth demand. This particular setting requires higher speed grade ASIC/FPGA that supports LVDS bus rate of 1474.56 Mbps minimum. 8.2.2.2.2 Interpolation It is desired to use the highest DAC output rate as possible to move the DAC images further from the signal of interest to ease analog filter requirement. The DAC output rate must be greater than two times the highest output frequency of 250 MHz, which is greater than 500 MHz. The table below shows the possible DAC output rates based on the data input rate and available interpolation settings. The DAC image frequency is also listed. Table 65. Interpolation FDAC POSSIBLE? LOWEST IMAGE FREQUENCY DISTANCE FROM BAND OF INTEREST 1 614.4 MSPS Yes 364.4 MHz 114.4 MHz 2 1228.8 MSPS Yes 978.8 MHz 728.8 MHz 4 2457.6 MSPS No N/A N/A 614.4 MSPS 8 4915.2 MSPS No N/A N/A 614.4 MSPS 16 9830.4 MSPS No N/A N/A FDATA INTERPOLATION 614.4 MSPS 614.4 MSPS 614.4 MSPS 8.2.2.2.3 LO Feedthrough and Sideband Correction Refer to LO Feedthrough and Sideband Correction section of IF based LTE Transmitter design. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 79 DAC34SH84 SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 www.ti.com 8.2.2.3 Application Curves The ACPR performance for LTE 20MHz TM1.1 are shown in Figure 94 and Figure 95. The figures provide comparisons between two major LTE bands such as 2.14 GHz and 2.655 GHz with DAC clocking option set to external clocking mode. DAC Output IF = 0 MHz, LO = 2140 MHz, DAC Clock = External Clock Source from LMK04806 Figure 94. 5x20MHz TM1.1 LTE Carrier at 2.14GHz 80 DAC Output IF = 0 MHz, LO = 2655 MHz, DAC Clock = External Clock Source from LMK04806 Figure 95. 5x20MHz TM1.1 LTE Carrier at 2.655GHz Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 DAC34SH84 www.ti.com SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 9 Power Supply Recommendations Powered by CLKVDD IOUTP Sample Clock Switch Drivers Decoder Logic = Digital Input Data DAC IOUTN Analog Output As shown in Figure 96, the DAC34SH84 device has various power rails and has three primary voltages of 1.3 V, 1.35 V, and 3.3 V. Some of the DAC power rails such as CLKVDD and AVDD are more noise sensitive than other rails because they are mainly powering the switch drivers for the current switch array and the current bias circuits, respectively. These circuits are the main analog DAC core. Any power supply noises such as switching power supply ripple may be modulated directly onto the signal of interest. These two power rails should be powered by low noise power supplies such as LDO. Powering the rail directly with switching power supplies is not recommended for these two rails. Switch Array Powered by DACVDD Powered by AVDD Bias Circuit Current Source Array Figure 96. Interpolation Filters, NCOs, and QMC Blocks Powered by DIGVDD With the DAC34SH84 being a mixed signal device, the device contains circuits that bridges the digital section and the analog section. The DACVDD powers these sections. System designer can design this rail in secondary priority. Powering the rail with LDO is recommended. Unless system designer pays special care to supply filtering and power supply routing/placement, powering the rail directly with switching power supplies is not recommended for this rail. Since digital circuits have more inherent noise immunity than analog circuits, the power supply noise requirements for DIGVDD of the digital section of the device may be relaxed and placed at a lower priority. Depending on the spur level requirement, routing and placement of the power supply, power the rail directly with switching power supplies can be possible. With the digital logics running, the DIGVDD rail may draw significant current. If the power supply traces and filtering network have significant DC resistance loss (for example, DCR), then the final supply voltage seen by the DIGVDD rail may not be sufficient to meet the minimum power supply level. For instance, with 450 mA of DIGVDD current and about 0.1 Ω of DCR from the ferrite bead, the final supply voltage at the DIGVDD pins may be 1.3 V – 0.045 V = 1.255 V. This is fairly close to the minimum supply voltage range of 1.25 V. System designer may need to elevate the power supply voltage according to the DCR level or design a feedback network for the power supply to account for associated voltage drop. To ensure power supply accuracy and to account for power supply filter network loss at operating conditions, the use of the ATEST function in register config27 to check the internal power supply nodes is recommended. The table below is a summary of the various power supply nodes of the DAC. Care should be taken to keep clean power supplies routing away from noisy digital supplies. It is recommended to use at least two power layers. Power supplies for digital circuits tend to have more switching activities and are typically noisier, and system designer should avoid sharing the digital power rail (for example, power supplies for FPGA or DIGVDD of DAC34SH84) with the analog power rail (for example, CLKVDD and AVDD of DAC34SH84). Avoid placing noisy supplies and clean supplies on adjacent board layers and use a ground layer between these two supplies if possible. All supply pins should be decoupled as close to the pins as possible by using small value capacitors, with larger bulk capacitors placed further away and near the power supply source. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 81 DAC34SH84 SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 www.ti.com Table 66. Power Rails POWER RAILS TYPICAL VOLTAGE NOISE SENSITIVITY RECOMMENDATIONS POWER SUPPLY DESIGN PRIORITY CLKVDD 1.35 V High Provide clean supply to the rail. Avoid spurious noise or coupling from other supplies High AVDD 3.3 V High Provide clean supply to the rail. Avoid spurious noise or coupling from other supplies High DACVDD 1.35 V Medium Provide clean supply to the rail. Avoid spurious noise or coupling from other supplies Medium DIGVDD 1.3 V Low Keep Away from other noise sensitive nodes in placement and routing. Low 10 Layout 10.1 Layout Guidelines The design of the PCB is critical to achieve the full performance of the DAC34SH84 device. Defining the PCB stackup should be the first step in the board design. Experience has shown that at least six layers are required to adequately route all required signals to and from the device. Each signal routing layer must have an adjacent solid ground plane to control signal return paths to have minimal loop areas and to achieve controlled impedances for microstrip and stripline routing. Power planes must also have adjacent solid ground planes to control supply return paths. Minimizing the space between supply and ground planes improves performance by increasing the distributed decoupling. Although the DAC34SH84 device consists of both analog and digital circuitry, TI highly recommends solid ground planes that encompass the device and its input and output signal paths. TI does not recommend split ground planes that divide the analog and digital portions of the device. Split ground planes may improve performance if a nearby, noisy, digital device is corrupting the ground reference of the analog signal path. When split ground planes are employed, one must carefully control the supply return paths and keep the paths on top of their respective ground reference planes. Quality analog output signals and input conversion clock signal path layout is required for full dynamic performance. Symmetry of the differential signal paths and discrete components in the path is mandatory, and symmetrical shunt-oriented components should have a common grounding via. The high frequency requirements of the analog output and clock signal paths necessitate using differential routing with controlled impedances and minimizing signal path stubs (including vias) when possible. Coupling onto or between the clock and output signals paths should be avoided using any isolation techniques available including distance isolation, orientation planning to prevent field coupling of components like inductors and transformers, and providing well coupled reference planes. Via stitching around the clock signal path and the input analog signal path provides a quiet ground reference for the critical signal paths and reduces noise coupling onto these paths. Sensitive signal traces must not cross other signal traces or power routing on adjacent PCB layers, rather a ground plane must separate the traces. If necessary, the traces should cross at 90° angles to minimize crosstalk. The substrate (dielectric) material requirements of the PCB are largely influenced by the speed and length of the high speed serial lanes. Affordable and common FR4 varieties are adequate in most cases. Coupling of ambient signals into the signal path is reduced by providing quiet, close reference planes and by maintaining signal path symmetry to ensure the coupled noise is common-mode. Faraday caging may be used in very noise environment and high dynamic range applications to isolate the signal path. The following layout guidelines correspond to the layout shown in Figure 97. 1. DAC output termination resistors should be placed as close to the output pins as possible to provide a DC path to ground and set the source impedance matching. 2. For DAC on-chip PLL clocking mode, if the external loop filter is not used, leave the loop filter pin floating without any board routing nearby. Signals coupling to this node may cause clock mixing spurs in the DAC output. 3. Route the high speed LVDS lanes as impedance-controlled, tightly-coupled, differential traces. 82 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 DAC34SH84 www.ti.com SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 Layout Guidelines (continued) 4. Maintain a solid ground plane under the LVDS lanes without any ground plane splits. 5. Simulation of the LVDS channel with DAC34SH84 IBIS model is recommended to verify good eye opening of the data patterns. 6. Keep the OSTR signal routing away from the DACCLK routing to reduce coupling. 7. Keep routing for RBIAS short, for instance a resistor can be placed on the board directly connecting the RBIAS pin to the ground layer. The following layout guidelines correspond to the layouts shown in Figure 98 and Figure 99. 1. Noise power supplies should be routed away from clean supplies. Use two power plane layers, preferably with a ground layer in between. 2. As shown in Figure 98 and Figure 99, both layers three and four are designated for power supply planes. The DAC analog powers are all in the same layer to avoid coupling with each other, and the planes are copied from layer three to layer four for double the copper coverage area. 3. Decoupling capacitors should be placed as close to the supply pins as possible. For instance, a capacitor can be placed on the bottom of the board directly connecting the supply pin to a ground layer. 10.1.1 Assembly Information regarding the package and assembly of the ZAY package version of the DAC34SH84 can be found at the end of the data sheet and also on the following application note: SPRAA99 10.2 Layout Examples 6 3 2 Bottom Layer 4 1 7 Bottom Layer 5 Figure 97. Top Layer of DAC34SH84 Layout Showing High Speed Signals such as LVDS Bus, DACCLK, OSTR, and DAC Outputs. Layout Example from TSW3085EVM Rev D Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 83 DAC34SH84 SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 www.ti.com Layout Examples (continued) CLKVDD DACVDD DIGVDD Figure 98. Third Layer of DAC34SH84 Layout Showing Power Layers. Layout Example from DAC34SH84EVM Rev H 84 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 DAC34SH84 www.ti.com SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 Layout Examples (continued) PLLVDD AVDD DVDD Figure 99. Sixth Layer of DAC34SH84 Layout Showing Power Layers. Layout Example from DAC34SH84EVM Rev H Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 85 DAC34SH84 SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 www.ti.com 11 Device and Documentation Support 11.1 Device Support 11.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 11.1.2 Device Nomenclature 11.1.2.1 Definition of Specifications Adjacent-Carrier Leakage Ratio (ACLR): Defined for a 3.84-Mcps 3GPP W-CDMA input signal measured in a 3.84-MHz bandwidth at a 5-MHz offset from the carrier with a 12-dB peak-to-average ratio Analog and Digital Power Supply Rejection Ratio (APSSR, DPSSR): Defined as the percentage error in the ratio of the delta IOUT and delta supply voltage normalized with respect to the ideal IOUT current Differential Nonlinearity (DNL): Defined as the variation in analog output associated with an ideal 1-LSB change in the digital input code Gain Drift: Defined as the maximum change in gain, in terms of ppm of full-scale range (FSR) per °C, from the value at ambient (25°C) to values over the full operating temperature range Gain Error: Defined as the percentage error (in FSR%) for the ratio between the measured full-scale output current and the ideal full-scale output current Integral Nonlinearity (INL): Defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale Intermodulation Distortion (IMD3): The two-tone IMD3 is defined as the ratio (in dBc) of the third-order intermodulation distortion product to either fundamental output tone. Offset Drift: Defined as the maximum change in dc offset, in terms of ppm of full-scale range (FSR) per °C, from the value at ambient (25°C) to values over the full operating temperature range Offset Error: Defined as the percentage error (in FSR%) for the ratio between the measured mid-scale output current and the ideal mid-scale output current Output Compliance Range: Defined as the minimum and maximum allowable voltage at the output of the current-output DAC. Exceeding this limit may result in reduced reliability of the device or adversely affect distortion performance. Reference Voltage Drift: Defined as the maximum change of the reference voltage in ppm per degree Celsius from the value at ambient (25°C) to values over the full operating temperature range Spurious-Free Dynamic Range (SFDR): Defined as the difference (in dBc) between the peak amplitude of the output signal and the peak spurious signal within the first Nyquist zone Noise Spectral Density (NSD): Defined as the difference of power (in dBc) between the output tone signal power and the noise floor of 1-Hz bandwidth within the first Nyquist zone 11.2 Documentation Support 11.2.1 Related Documentation • DAC34H84 EVM User's Guide (SLAU338) • nFBGA Packaging Application Report (SPRAA99) 86 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 DAC34SH84 www.ti.com SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 11.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.4 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DAC34SH84 87 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking (4/5) (6) DAC34SH84IZAY ACTIVE NFBGA ZAY 196 160 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 85 DAC34SH84I DAC34SH84IZAYR ACTIVE NFBGA ZAY 196 1000 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 85 DAC34SH84I (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of