DAC5662MPFBREP

DAC5662-EP www.ti.com SGLS340A – JUNE 2006 – REVISED OCTOBER 2006 DUAL 12-BIT 200-MSPS DIGITAL-TO-ANALOG CONVERTER FEATURES • • • • • • • • (1) Controlled Baseline – One Assembly – One Test Site – One Fabrication Site Extended Temperature Performance of –55°C to 125°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree (1) 12-Bit Dual Transmit Digital-to-Analog Converter (DAC) 200-MSPS Update Rate Single Supply: 3 V to 3.6 V Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. • • • • • • • • • High Spurious-Free Dynamic Range (SFDR): 85 dBc at 5 MHz High Third-Order Two-Tone Intermodulation (IMD3): 78 dBc at 15.1 and 16.1 MHz WCDMA Adjacent Channel Leakage Ratio (ACLR): 70 dB at 30.72 MHz Independent or Single Resistor Gain Control Dual or Interleaved Data On-Chip 1.2-V Reference Low Power: 330 mW Power-Down Mode: 15 mW Package: 48-Pin Thin Quad Flat Pack (TQFP) APPLICATIONS • • • • • Cellular Base Transceiver Station Transmit Channel – CDMA: W-CDMA, CDMA2000, IS-95 – TDMA: GSM, IS-136, EDGE/UWC-136 Medical/Test Instrumentation Arbitrary Waveform Generators (ARB) Direct Digital Synthesis (DDS) Cable Modem Termination System (CMTS) DESCRIPTION The DAC5662 is a monolithic, dual-channel 12-bit, high-speed digital-to-analog converter (DAC) with on-chip voltage reference. Operating with update rates of up to 200 MSPS, the DAC5662 offers exceptional dynamic performance, tight gain, and offset matching characteristics that make it suitable in either I/Q baseband or direct IF communication applications. Each DAC has a high-impedance differential-current output, suitable for single-ended or differential analog-output configurations. External resistors allow scaling the full-scale output current for each DAC separately or together, typically between 2 mA and 20 mA. An accurate on-chip voltage reference is temperature compensated and delivers a stable 1.2-V reference voltage. Optionally, an external reference may be used. The DAC5662 has two 12-bit parallel input ports with separate clocks and data latches. For flexibility, the DAC5662 also supports multiplexed data for each DAC on one port when operating in the interleaved mode. The DAC5662 has been specifically designed for a differential transformer coupled output with a 50-Ω doubly terminated load. For a 20-mA full-scale output current a 4:1 impedance ratio (resulting in an output power of 4 dBm) and 1:1 impedance ratio transformer (–2-dBm output power) are supported. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006, Texas Instruments Incorporated DAC5662-EP www.ti.com SGLS340A – JUNE 2006 – REVISED OCTOBER 2006 DESCRIPTION (CONTINUED) The DAC5662 is available in a 48-pin thin quad flat pack (TQFP). Pin compatibility between family members provides 12-bit (DAC5662) and 14-bit (DAC5672) resolution. Furthermore, the DAC5662 is pin compatible to the DAC2902 and AD9765 dual DACs. The device is characterized for operation over the military temperature range of –55°C to 125°C. FUNCTIONAL BLOCK DIAGRAM WRTB WRTA CLKB CLKA DE MUX IOUTA1 Latch A 12−b DAC DA[11:0] IOUTA2 BIASJ_A IOUTB1 Latch B DB[11:0] 12−b DAC MODE IOUTB2 BIASJ_B GSET 1.2 V Reference EXTIO SLEEP DVDD DGND AVDD AGND AVAILABLE OPTIONS PACKAGED DEVICES 48-PIN TQFP TA DAC5662MPFBREP –55°C to 125°C 2 DAC5662MPFBEP Submit Documentation Feedback DAC5662-EP www.ti.com SGLS340A – JUNE 2006 – REVISED OCTOBER 2006 MODE AVDD IOUTA1 IOUTA2 BIASJ_A EXTIO GSET BIASJ_B IOUTB2 IOUTB1 AGND SLEEP DEVICE INFORMATION 48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 Top View 48-Pin TQFP PFB Package 6 7 32 31 30 8 29 9 28 10 27 11 26 25 12 13 14 15 16 17 18 19 20 21 22 23 24 NC NC DB0 (LSB) DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 NC NC DGND DVDD WRTA/WRTIQ CLKA/CLKIQ CLKB/RESETIQ WRTB/SELECTIQ DGND DVDD DB11 (MSB) DB10 DA11 (MSB) DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 (LSB) Submit Documentation Feedback 3 DAC5662-EP www.ti.com SGLS340A – JUNE 2006 – REVISED OCTOBER 2006 DEVICE INFORMATION (continued) TERMINAL FUNCTIONS TERMINAL DESCRIPTION NO. AGND 38 I Analog ground AVDD 47 I Analog supply voltage BIASJ_A 44 O Full-scale output current bias for DACA BIASJ_B 41 O Full-scale output current bias for DACB CLKA/CLKIQ 18 I Clock input for DACA, CLKIQ in interleaved mode CLKB/RESETIQ 19 I Clock input for DACB, RESETIQ in interleaved mode DA[11:0] 1–12 I Data port A. DA11 is MSB and DA0 is LSB. DB[11:0] 23–34 I Data port B. DB11 is MSB and DB0 is LSB. DGND 15, 21 I Digital ground DVDD 16, 22 I Digital supply voltage EXTIO 43 I/O GSET 42 I Gain-setting mode: H = 1 resistor, L = 2 resistors. Internal pullup IOUTA1 46 O DACA current output. Full scale with all bits of DA high. IOUTA2 45 O DACA complementary current output. Full scale with all bits of DA low. IOUTB1 39 O DACB current output. Full scale with all bits of DB high. IOUTB2 40 O DACB complementary current output. Full scale with all bits of DB low. MODE 48 I Mode select: H = dual bus, L = interleaved. Internal pullup. 13, 14, 35, 36 – No connection SLEEP 37 I Sleep function control input: H = DAC in power-down mode, L = DAC in operating mode. Internal pulldown. WRTA/WRTIQ 17 I Input write signal for PORT A (WRTIQ in interleaving mode) WRTB/SELECTIQ 20 I Input write signal for PORT B (SELECTIQ in interleaving mode) NC 4 I/O NAME Internal reference output (bypass with 0.1 µF to AGND) or external reference input Submit Documentation Feedback DAC5662-EP www.ti.com SGLS340A – JUNE 2006 – REVISED OCTOBER 2006 PFB PACKAGE THERMAL CHARACTERISTICS PARAMETER POWERPAD CONNECTED TO PCB THERMAL PLANE Thermal resistance, junction to ambient 63.7°C/W Thermal resistance, junction to case 19.6°C/W 1000 Wirebond Voiding Fail Mode Years Estimated Life 100 10 Electromigration Fail Mode 1 0.1 100 110 120 130 140 150 160 Continuous TJ − 5C Figure 1. DAC5662MPFB Operating Life Derating Chart Submit Documentation Feedback 5 DAC5662-EP www.ti.com SGLS340A – JUNE 2006 – REVISED OCTOBER 2006 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) UNIT Supply voltage range AVDD (2) –0.5 V to 4 V DVDD (3) –0.5 V to 4 V Voltage between AGND and DGND –0.5 V to 0.5 V Voltage between AVDD and DVDD Supply voltage range –0.5 V to DVDD + 0.5 V MODE, CLKA, CLKB, WRTA, WRTB (3) –0.5 V to DVDD + 0.5 V IOUTA1, IOUTA2, IOUTB1, IOUTB2 (2) –1 V to AVDD + 0.5 V EXTIO, BIASJ_A, BIASJ_B, SLEEP (2) –0.5 V to AVDD + 0.5 V Peak input current (any input) 20 mA Peak total input current (all inputs) –30 mA Operating free-air temperature range –55°C to 125°C Storage temperature range –65°C to 150°C Lead temperature (1) (2) (3) 6 –0.5 V to 0.5 V DA[11:0] and DB[11:0] (3) 1,6 mm (1/16 in) from the case for 10 s 260°C Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Measured with respect to AGND Measured with respect to DGND Submit Documentation Feedback DAC5662-EP www.ti.com SGLS340A – JUNE 2006 – REVISED OCTOBER 2006 ELECTRICAL CHARACTERISTICS over operating free-air temperature range, AVDD = DVDD = 3.3 V, IOUTFS = 20 mA, independent gain set mode (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DC Specifications Resolution 12 Bits DC Accuracy (1) INL Integral nonlinearity 1 LSB = IOUTFS/212, TA = 25°C –2   0.3 2 LSB DNL Differential nonlinearity 1 LSB = IOUTFS/212, TA = 25°C –2   0.2 2 LSB Analog Output Offset error Gain error 0.03 %FSR With external reference   0.25 %FSR With internal reference   0.5 %FSR current (2) 2 Maximum full-scale output current (2) 20 Minimum full-scale output Gain mismatch With internal reference Output voltage compliance range (3) RO Output resistance CO Output capacitance –2 0.07 –0.8 mA mA 2 1.25 %FSR V 300 kΩ 5 pF Reference Output Reference voltage 1.14 Reference output current (4) 1.2 1.26 100 V nA Reference Input VEXTIO Input voltage RI Input resistance CI 0.1 1.25 V 1 MΩ Small signal bandwidth 300 kHz Input capacitance 100 pF Temperature Coefficients Offset drift Gain drift 0 With external reference ±50 With internal reference ±50 ppm of FSR/°C ±20 ppm/°C Reference voltage drift (1) (2) (3) (4) ppm of FSR/°C Measured differentially through 50 Ω to AGND. Nominal full-scale current, IOUTFS, equals 32× the IBIAS current. The lower limit of the output compliance is determined by the CMOS process. Exceeding this limit may result in transistor breakdown, resulting in reduced reliability of the DAC5662 device. The upper limit of the output compliance is determined by the load resistors and full-scale output current. Exceeding the upper limit adversely affects distortion performance and intergral nonlinearity. Use an external buffer amplifier with high impedance input to drive any external load. Submit Documentation Feedback 7 DAC5662-EP www.ti.com SGLS340A – JUNE 2006 – REVISED OCTOBER 2006 ELECTRICAL CHARACTERISTICS over operating free-air temperature range, AVDD = DVDD = 3.3 V, IOUTFS = 20 mA, fDATA = 200 MSPS, fOUT = 1 MHz, independent gain set mode (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Power Supply AVDD Analog supply voltage 3 3.3 3.6 V DVDD Digital supply voltage 3 3.3 3.6 V Including output current through load resistor 75 90 IAVDD Supply current, analog Sleep mode with clock 2.5 6 Sleep mode without clock 2.5 IDVDD Supply current, digital 25 38 Sleep mode with clock 12.5 18 Sleep mode without clock