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DAC9881
SBAS438C – MAY 2008 – REVISED NOVEMBER 2019
DAC9881 18-Bit, Single-Channel, Low-Noise, Voltage-Output
Digital-to-Analog Converter
1 Features
3 Description
•
•
•
•
•
The DAC9881 is an 18-bit, single-channel, voltageoutput digital-to-analog converter (DAC). The device
features 18-bit monotonicity, excellent linearity, very
low-noise, and fast settling time. The on-chip
precision output amplifier allows for a rail-to-rail
output swing to be achieved over the full supply
range of 2.7 V to 5.5 V.
1
•
•
•
•
•
•
•
•
18-bit monotonic over temperature range
Relative accuracy: ±2 LSB maximum
Low-noise: 24 nV/√Hz
Fast settling: 5 μs
On-chip output buffer amplifier with rail-to-rail
operation
Single power supply: 2.7 V to 5.5 V
DAC loading control
Selectable power-on reset to zero-scale or
midscale
Power-down mode
Unipolar straight binary or
two's complement input mode
Fast SPI with Schmitt-triggered inputs: up to 50
MHz, 1.8-V, 3-V, and 5-V logic
Specified temperature range: –40°C to +105°C
Small package: VQFN-24, 4 mm × 4 mm
The device supports a standard serial peripheral
interface (SPI) capable of operating with input data
clock frequencies of up to 50 MHz. The DAC9881
requires an external reference voltage to set the
output range of the DAC channel. A programmable
power-on reset circuit is also incorporated into the
device to make sure that the DAC output powers up
at zero-scale or midscale, and remains there until a
valid write command.
Additionally, the DAC9881 has the capability to
function in either unipolar straight binary or two's
complement mode. The DAC9881 provides lowpower operation. To further save energy, power-down
mode can be achieved by accessing the PDN pin,
thereby reducing the current consumption to 25 µA at
5 V. Power consumption is 4 mW at 5 V, reducing to
125 µW in power-down mode.
2 Applications
•
•
•
•
•
Semiconductor test
Oscilloscope (DSO)
X-ray systems
Lab and field instrumentation
Data acquisition (DAQ)
Device Information(1)
PART NUMBER
DAC9881
PACKAGE
VQFN (24)
BODY SIZE (NOM)
4.00 mm × 4.00 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
Block Diagram
DGND
IOVDD
AGND
AVDD
VREFH-S VREFH-F
DAC9881
RST
Power-On
Reset
RSTSEL
Control
Logic
USB/BTC
Resistor
Network
SDI
CS
SCLK
SPI Interface
Shift Register
GAIN
PDN
Input
Register
DAC
Latch
VOUT
DAC
RFB
RFB
SDOSEL
SDO
Serial Out
Control
LDAC
VREFL-S
VREFL-F
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DAC9881
SBAS438C – MAY 2008 – REVISED NOVEMBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Electrical Characteristics: AVDD = 5 V ...................... 6
Electrical Characteristics: AVDD = 2.7 V ................... 8
Timing Requirements—Standalone Operation
Without SDO ............................................................ 10
6.8 Timing Requirements—Standalone Operation With
SDO and Daisy-Chain Mode.................................... 11
6.9 Typical Characteristics: AVDD = 5 V ....................... 15
6.10 Typical Characteristics: AVDD = 2.7 V .................. 22
7
Detailed Description ............................................ 26
7.1 Overview ................................................................. 26
7.2 Functional Block Diagram ....................................... 27
7.3 Feature Description................................................. 28
7.4 Device Functional Modes........................................ 32
8
Application and Implementation ........................ 33
8.1 Application Information............................................ 33
8.2 Typical Application .................................................. 34
8.3 System Example ..................................................... 35
9 Power Supply Recommendations...................... 36
10 Layout................................................................... 36
10.1 Layout Guidelines ................................................. 36
10.2 Layout Example .................................................... 36
11 Device and Documentation Support ................. 37
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Support Resources ...............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
37
37
37
37
37
37
12 Mechanical, Packaging, and Orderable
Information ........................................................... 37
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (March 2016) to Revision C
Page
•
Added new text to end of Hardware Reset section regarding two's complement mode...................................................... 30
•
Changed Table 3, Reset Values, to show updated content ................................................................................................. 30
Changes from Revision A (August 2008) to Revision B
•
2
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
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SBAS438C – MAY 2008 – REVISED NOVEMBER 2019
5 Pin Configuration and Functions
IOVDD
SDO
DGND
AVDD
SDOSEL
CS
24
23
22
21
20
19
RGE Package
24-Pin VQFN With Exposed Thermal Pad
Top View
SCLK
1
18
PDN
SDI
2
17
RST
LDAC
3
16
USB/BTC
AGND
4
15
GAIN
AVDD
5
14
RSTSEL
VREFL-S
6
13
NC
11
12
VREFH-F
NC
9
RFB
10
8
VOUT
VREFL-F
7
VREFH-S
Thermal pad
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NO.
NAME
1
SCLK
I
SPI bus serial clock input
2
SDI
I
SPI bus serial data input
3
LDAC
I
Load DAC latch control input (active low). When LDAC is low, the DAC latch is transparent, and the
contents of the input register are transferred to the DAC latch. The DAC output changes to the
corresponding level simultaneously when the DAC latch is updated. It is recommended to connect this
pin to IOVDD through a pullup resistor.
4
AGND
I
Analog ground
5
AVDD
I
Analog power supply
6
VREFL-S
I
Reference low input sense
7
VREFH-S
I
Reference high input sense
8
VOUT
O
Output of output buffer
9
RFB
I
Feedback resistor connected to the inverting input of the output buffer
10
VREFL-F
I
Reference low input force
11
VREFH-F
I
Reference high input force
12
NC
—
Do not connect
13
NC
—
Do not connect
14
RSTSEL
I
Selects the value of the output from the VOUT pin after power-on or hardware reset. If RSTSEL = IOVDD,
then register data = 20000h. If RSTSEL = DGND, then register data = 00000h.
15
GAIN
I
Buffer gain setting. Gain = 1 when the pin is connected to DGND; Gain = 2 when the pin is connected to
IOVDD.
16
USB/BTC
I
Input data format selection. Input data are straight binary format when the pin is connected to IOVDD,
and in two's complement format when the pin is connected to DGND.
17
RST
I
Reset input (active low). Logic low on this pin causes the device to perform a reset.
18
PDN
I
Power-down input (active high). Logic high on this pin forces the device into power-down status. In
power-down, the VOUT pin connects to AGND through a 10-kΩ resistor.
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DAC9881
SBAS438C – MAY 2008 – REVISED NOVEMBER 2019
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Pin Functions (continued)
PIN
NO.
NAME
I/O
DESCRIPTION
19
CS
I
SPI bus chip select input (active low). Data bits are not clocked into the serial shift register unless CS is
low. When CS is high, SDO is in a high-impedance state. It is recommended to connect this pin to
IOVDD through a pullup resistor.
20
SDOSEL
I
SPI serial data output selection. When SDOSEL is tied to IOVDD, the contents of the existing input
register are shifted out from the SDO pin; this is Stand-Alone mode. When SDOSEL is tied to DGND,
the contents in the SPI input shift register are shifted out from the SDO pin; this is Daisy-Chain mode for
daisy-chained communication.
21
AVDD
I
Analog power supply. Must be connected to pin 5.
22
DGND
I
Digital ground
23
SDO
O
SPI bus serial data output. Refer to the timing diagrams for further detail.
24
IOVDD
I
Interface power. Connect to 1.8 V for 1.8-V logic, 3 V for 3-V logic, and to 5 V for 5-V logic.
Thermal pad
4
—
The thermal pad is internally connected to the substrate. This pad can be connected to the analog
ground or left floating. Keep the thermal pad separate from the digital ground, if possible.
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SBAS438C – MAY 2008 – REVISED NOVEMBER 2019
6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted). (1)
MIN
MAX
AVDD to AGND
–0.3
6
V
IOVDD to DGND
–0.3
6
V
Digital input voltage to DGND
–0.3
IOVDD + 0.3
V
VOUT to AGND
–0.3
AVDD + 0.3
V
150
°C
150
°C
TJ
Maximum junction temperature
Tstg
Storage temperature
(1)
–65
UNIT
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±3000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
V
±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
AVDD
Analog power supply
IOVDD
Interface power supply
NOM
2.7
1.7
MAX
UNIT
5.5
V
AVDD
V
AVDD = 5.5 V
1.25
5
AVDD
V
AVDD = 3 V
1.25
2.5
AVDD
V
0
VREFH
Reference high input voltage
VREFL
Reference low input voltage
–0.2
TA
Specified temperature
–40
0.2
V
105
°C
6.4 Thermal Information
DAC9881
THERMAL METRIC (1)
RGE (VQFN)
UNIT
24 PINS
RθJA
Junction-to-ambient thermal resistance
33.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
37.1
°C/W
RθJB
Junction-to-board thermal resistance
11.3
°C/W
ψJT
Junction-to-top characterization parameter
0.5
°C/W
ψJB
Junction-to-board characterization parameter
11.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics: AVDD = 5 V
all specifications at TA = TMIN to TMAX, AVDD = 4.75 V to 5.5 V, IOVDD = 1.8 V to 5.5 V, VREFH = 5 V, VREFL = 0 V, and gain = 1X
mode (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ACCURACY (1)
Measured by line
passing through
codes 2048 and
260096
DAC9881S
±2
±3
LSB
Integral linearity error
DAC9881SB
±1
±2
LSB
Measured by line
passing through
codes 2048 and
260096
DAC9881S
±0.75
+2
LSB
Differential linearity error
±0.5
±1
LSB
±16
LSB
±32
LSB
DAC9881SB
Monotonicity
18
Bits
TA = 25°C, code = 2048
Zero-scale error
TMIN to TMAX, code = 2048
Zero-scale drift (2)
Code = 2048
Gain error
TA = 25°C, measured by line passing through codes 2048
and 260096
Gain temperature drift
–1
(2)
PSRR (2)
±0.25
Measured by line passing through codes 2048 and 260096
±0.8 ppm/°C of FSR
±16
±32
LSB
±0.25
±0.4
ppm/°C
32
LSB/V
VOUT = full-scale, AVDD = 5 V ±10%
ANALOG OUTPUT (2)
Voltage output (3)
Output voltage drift vs time
0
AVDD
V
Device operating for 500 hours at 25°C
0.1
ppm of FSR
Device operating for 1000 hours at 25°C
0.2
ppm of FSR
2.5
mA
Output current (4)
Maximum load capacitance
Short-circuit current
200
pF
31/–50
mA
REFERENCE INPUT (2)
VREFH input voltage range
AVDD = 5.5 V
1.25
VREFH input capacitance
5
AVDD
5
VREFH input impedance
4.5
VREFL input voltage range
–0.2
VREFL input capacitance
VREFL input impedance
0
V
pF
kΩ
0.2
V
4.5
pF
5
kΩ
5
µs
DYNAMIC PERFORMANCE (2)
Settling time
To ±0.003% FS, RL = 10 kΩ, CL = 50 pF, code 04000h to
3C000h
Slew rate
From 10% to 90% of 0 V to 5 V
Code change glitch
Digital feedthrough
Code = 1FFFFh to
20000h to 1FFFFh
2.5
V/µs
VREFH = 5 V, gain = 1X mode
37
nV-s
VREFH = 2.5 V, gain = 1X mode
18
nV-s
VREFH = 1.25 V, gain = 1X mode
9
nV-s
VREFH = 2.5 V, gain = 2X mode
21
nV-s
VREFH = 1.25 V, gain = 2X mode
10
nV-s
CS = high, fSCLK = 1 kHz
1
24
30
nV/√Hz
Gain = 2
40
48
nV/√Hz
Output noise voltage density
f = 1 kHz to 100 kHz,
full-scale output
Output noise voltage
f = 0.1 Hz to 10 Hz, full-scale output
(1)
(2)
(3)
(4)
6
nV-s
Gain = 1
2
µVPP
DAC output range is 0 V to 5 V. 1 LSB = 19 μV.
Specified by design; not production tested.
The output from the VOUT pin = [(VREFH – VREFL) / 262144] × CODE × Buffer GAIN + VREFL. The maximum range of VOUT is 0 V to
AVDD. The full-scale of the output must be less than AVDD; otherwise, output saturation occurs.
See Figure 26, Figure 27, and Figure 28 for details.
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Electrical Characteristics: AVDD = 5 V (continued)
all specifications at TA = TMIN to TMAX, AVDD = 4.75 V to 5.5 V, IOVDD = 1.8 V to 5.5 V, VREFH = 5 V, VREFL = 0 V, and gain = 1X
mode (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUTS (2)
High-level input voltage, VIH
Low-level input voltage, VIL
IOVDD = 4.5 V to 5.5 V
3.8
IOVDD + 0.3
V
IOVDD = 2.7 V to 3.3 V
2.1
IOVDD + 0.3
V
IOVDD = 1.7 V to 2 V
1.5
IOVDD + 0.3
V
IOVDD = 4.5 V to 5.5 V
–0.3
0.8
V
IOVDD = 2.7 V to 3.3 V
–0.3
0.6
V
IOVDD = 1.7 V to 2 V
–0.3
0.3
V
±10
µA
Digital input current (IIN)
±1
Digital input capacitance
5
pF
DIGITAL OUTPUT (2)
High-level output voltage, VOH
Low-level output voltage, VOL
IOVDD = 2.7 V to 5.5 V, IOH = –1 mA
IOVDD – 0.2
IOVDD = 1.7 V to 2 V, IOH = –500 μA
IOVDD – 0.2
V
V
IOVDD = 2.7V to 5.5 V, IOL = 1 mA
0.2
V
IOVDD = 1.7 V to 2 V, IOL = 500 μA
0.2
V
5.5
V
POWER SUPPLY
AVDD
4.75
IOVDD
1.7
5
AVDD
AIDD
VIH = IOVDD, VIL = DGND
IOIDD
VIH = IOVDD, VIL = DGND
AIDD power-down
PDN pin = IOVDD
Power dissipation
AVDD = 5 V
4.3
V
0.85
1.5
mA
1
10
µA
25
50
µA
7.5
mW
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6.6 Electrical Characteristics: AVDD = 2.7 V
all specifications at TA = TMIN to TMAX, AVDD = 2.7 V to 3.3 V, IOVDD = 1.8 V to AVDD, VREFH = 2.5 V, VREFL = 0 V and gain = 1X
mode (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
±2.5
±3.5
LSB
ACCURACY (1)
Measured by line
passing through
codes 2048 and
262143
DAC9881S
Integral linearity error
DAC9881SB
±2
±3
LSB
Measured by line
passing through
codes 2048 and
262143
DAC9881S
±1
±2
LSB
Differential linearity error
±0.75
±1.5
LSB
TA = 25°C, code = 2048
±32
LSB
TMIN to TMAX, code = 2048
±64
LSB
Zero-scale error
DAC9881SB
Zero-scale drift (2)
Code = 2048
±0.5
±1.6 ppm/°C of FSR
Gain error
TA = 25°C, measured by line passing through codes 2048
and 262143
±32
±64
LSB
Measured by line passing through codes 2048 and 262143
±0.5
±0.8
ppm/°C
64
LSB/V
Gain temperature drift
(2)
PSRR (2)
VOUT = full-scale, AVDD = 3 V ±10%
ANALOG OUTPUT (2)
Voltage output (3)
Output voltage drift vs time
0
AVDD
V
Device operating for 500 hours at 25°C
0.2
ppm of FSR
Device operating for 1000 hours at 25°C
0.4
ppm of FSR
Output current (4)
2.5
mA
Maximum load capacitance
200
pF
31/–50
mA
Short-circuit current
REFERENCE INPUT (2)
VREFH input voltage range
AVDD = 3 V
1.25
VREFH input capacitance
2.5
AVDD
5
VREFH input impedance
4.5
VREFL input voltage range
–0.2
VREFL input capacitance
VREFL input impedance
0
V
pF
kΩ
0.2
V
4.5
pF
5
kΩ
5
µs
DYNAMIC PERFORMANCE (2)
Settling time
To ±0.003% FS, RL = 10 kΩ, CL = 50 pF, code 04000h to
3C000h
Slew rate
From 10% to 90% of 0 V to 2.5 V
2.5
V/µs
18
nV-s
VREFH = 1.25 V, gain = 1X mode
9
nV-s
VREFH = 1.25 V, gain = 2X mode
10
nV-s
VREFH = 2.5 V, gain = 1X mode
Code change glitch
Digital feedthrough
Code = 1FFFFh to
20000h to 1FFFFh
CS = high, fSCLK = 1 kHz
1
24
30
nV/√Hz
Gain = 2
40
48
nV/√Hz
Output noise voltage density
f = 1 kHz to 100 kHz,
full-scale output
Output noise voltage
f = 0.1 Hz to 10 Hz, full-scale output
(1)
(2)
(3)
(4)
8
nV-s
Gain = 1
2
µVPP
DAC output range is 0 V to 2.5 V. 1 LSB = 9.5 µV.
Specified by design; not production tested.
The output from the VOUT pin = [(VREFH – VREFL) / 262144] × CODE × Buffer GAIN + VREFL. The maximum range of VOUT is 0 V to
AVDD. The full-scale of the output must be less than AVDD; otherwise, output saturation occurs.
See Figure 55, Figure 56, and Figure 57 for details.
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Electrical Characteristics: AVDD = 2.7 V (continued)
all specifications at TA = TMIN to TMAX, AVDD = 2.7 V to 3.3 V, IOVDD = 1.8 V to AVDD, VREFH = 2.5 V, VREFL = 0 V and gain = 1X
mode (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUTS (2)
High-level input voltage, VIH
Low-level input voltage, VIL
IOVDD = 2.7 V to 3.3 V
2.1
IOVDD + 0.3
V
IOVDD = 1.7 V to 2 V
1.5
IOVDD + 0.3
V
IOVDD = 2.7 V to 3.3 V
–0.3
0.6
V
IOVDD = 1.7 V to 2 V
–0.3
0.3
V
±10
µA
Digital input current (IIN)
±1
Digital input capacitance
5
pF
DIGITAL OUTPUT (2)
High-level output voltage, VOH
Low-level output voltage, VOL
IOVDD = 2.7 V to 3.3 V, IOH = –1 mA
IOVDD – 0.2
IOVDD = 1.7 V to 2 V, IOH = –500 μA
IOVDD – 0.2
V
V
IOVDD = 2.7 V to 3.3 V, IOL = 1 mA
0.2
V
IOVDD = 1.7 to 2 V, IOL = 500 μA
0.2
V
3.3
V
POWER SUPPLY
AVDD
2.7
IOVDD
1.7
3
AVDD
AIDD
VIH = IOVDD, VIL = DGND
IOIDD
VIH = IOVDD, VIL = DGND
AIDD power-down
PDN pin = IOVDD
Power dissipation
AVDD = 3 V
2.3
V
0.75
1.2
mA
1
10
µA
25
50
µA
3.6
mW
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6.7 Timing Requirements—Standalone Operation Without SDO
at –40°C to +105°C (unless otherwise noted); see Figure 1 (1) (2) (3)
MIN
fSCLK
Maximum clock frequency
MAX
UNIT
2.7 ≤ AVDD < 3.6 V, 2.7 ≤ IOVDD ≤ AVDD
40
MHz
3.6 ≤ AVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ AVDD
50
MHz
2.7 ≤ AVDD < 3.6 V, 2.7 ≤ IOVDD ≤ AVDD
50
ns
3.6 ≤ AVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ AVDD
30
ns
t1
Minumum CS high time
t2
Delay from CS falling edge to SCLK rising
edge
2.7 ≤ AVDD < 3.6 V, 2.7 ≤ IOVDD ≤ AVDD
10
ns
3.6 ≤ AVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ AVDD
8
ns
Delay from SCLK falling edge to CS falling
edge
2.7 ≤ AVDD < 3.6 V, 2.7 ≤ IOVDD ≤ AVDD
0
ns
3.6 ≤ AVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ AVDD
0
ns
2.7 ≤ AVDD < 3.6 V, 2.7 ≤ IOVDD ≤ AVDD
10
ns
3.6 ≤ AVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ AVDD
10
ns
2.7 ≤ AVDD < 3.6 V, 2.7 ≤ IOVDD ≤ AVDD
15
ns
3.6 ≤ AVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ AVDD
10
ns
2.7 ≤ AVDD < 3.6 V, 2.7 ≤ IOVDD ≤ AVDD
25
ns
3.6 ≤ AVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ AVDD
20
ns
2.7 ≤ AVDD < 3.6 V, 2.7 ≤ IOVDD ≤ AVDD
10
ns
3.6 ≤ AVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ AVDD
10
ns
2.7 ≤ AVDD < 3.6 V, 2.7 ≤ IOVDD ≤ AVDD
8
ns
3.6 ≤ AVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ AVDD
5
ns
2.7 ≤ AVDD < 3.6 V, 2.7 ≤ IOVDD ≤ AVDD
5
ns
3.6 ≤ AVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ AVDD
5
ns
2.7 ≤ AVDD < 3.6 V, 2.7 ≤ IOVDD ≤ AVDD
10
ns
3.6 ≤ AVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ AVDD
5
ns
2.7 ≤ AVDD < 3.6 V, 2.7 ≤ IOVDD ≤ AVDD
15
ns
3.6 ≤ AVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ AVDD
10
ns
t3
t4
SCLK low time
t5
SCLK high time
t6
SCLK cycle time
t7
Delay from SCLK rising edge to CS rising
edge
t8
Input data setup time
t9
Input data hold time
t14
Delay from CS rising edge to LDAC falling
edge
t15
(1)
(2)
(3)
10
LDAC pulse duration
All input signals are specified with tR = tF = 2ns (10% to 90% of IOVDD) and timed from a voltage level of IOVDD / 2.
Specified by design; not production tested.
Sample tested during the initial release and after any redesign or process changes that may affect these parameters.
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6.8 Timing Requirements—Standalone Operation With SDO and Daisy-Chain Mode
at –40°C to +105°C (unless otherwise noted); see Figure 2 and Figure 3 (1) (2) (3)
MIN
fSCLK
Maximum clock frequency
MAX
UNIT
2.7 ≤ AVDD < 3.6 V, 2.7 ≤ IOVDD ≤ AVDD
20
MHz
3.6 ≤ AVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ AVDD
25
MHz
2.7 ≤ AVDD < 3.6 V, 2.7 ≤ IOVDD ≤ AVDD
50
ns
3.6 ≤ AVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ AVDD
30
ns
t1
Minumum CS high time
t2
Delay from CS falling edge to SCLK rising
edge
2.7 ≤ AVDD < 3.6 V, 2.7 ≤ IOVDD ≤ AVDD
10
ns
3.6 ≤ AVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ AVDD
8
ns
Delay from SCLK falling edge to CS falling
edge
2.7 ≤ AVDD < 3.6 V, 2.7 ≤ IOVDD ≤ AVDD
0
ns
3.6 ≤ AVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ AVDD
0
ns
2.7 ≤ AVDD < 3.6 V, 2.7 ≤ IOVDD ≤ AVDD
25
ns
3.6 ≤ AVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ AVDD
20
ns
2.7 ≤ AVDD < 3.6 V, 2.7 ≤ IOVDD ≤ AVDD
25
ns
3.6 ≤ AVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ AVDD
20
ns
2.7 ≤ AVDD < 3.6 V, 2.7 ≤ IOVDD ≤ AVDD
50
ns
3.6 ≤ AVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ AVDD
40
ns
2.7 ≤ AVDD < 3.6 V, 2.7 ≤ IOVDD ≤ AVDD
10
ns
3.6 ≤ AVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ AVDD
10
ns
2.7 ≤ AVDD < 3.6 V, 2.7 ≤ IOVDD ≤ AVDD
5
ns
3.6 ≤ AVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ AVDD
5
ns
2.7 ≤ AVDD < 3.6 V, 2.7 ≤ IOVDD ≤ AVDD
5
ns
3.6 ≤ AVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ AVDD
5
ns
t3
t4
SCLK low time
t5
SCLK high time
t6
SCLK cycle time
t7
Delay from SCLK rising edge to CS rising
edge
t8
Input data setup time
t9
Input data hold time
t10
Delay from CS falling edge to SDO valid
t11
Delay from SCLK falling edge to SDO valid
t12
SDO data hold from SCLK rising edge
t13
Delay from CS rising edge to SDO high-Z
t14
Delay from CS rising edge to LDAC falling
edge
t15
LDAC pulse width
(1)
(2)
(3)
2.7 ≤ AVDD < 3.6 V, 2.7 ≤ IOVDD ≤ AVDD
15
ns
3.6 ≤ AVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ AVDD
10
ns
2.7 ≤ AVDD < 3.6 V, 2.7 ≤ IOVDD ≤ AVDD
20
ns
3.6 ≤ AVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ AVDD
15
ns
2.7 ≤ AVDD < 3.6 V, 2.7 ≤ IOVDD ≤ AVDD
t5
3.6 ≤ AVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ AVDD
t5
2.7 ≤ AVDD < 3.6 V, 2.7 ≤ IOVDD ≤ AVDD
3.6 ≤ AVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ AVDD
ns
ns
8
ns
5
ns
2.7 ≤ AVDD < 3.6 V, 2.7 ≤ IOVDD ≤ AVDD
10
ns
3.6 ≤ AVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ AVDD
5
ns
2.7 ≤ AVDD < 3.6 V, 2.7 ≤ IOVDD ≤ AVDD
15
ns
3.6 ≤ AVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ AVDD
10
ns
All input signals are specified with tR = tF = 2ns (10% to 90% of IOVDD) and timed from a voltage level of IOVDD / 2.
Specified by design; not production tested.
Sample tested during the initial release and after any redesign or process changes that may affect these parameters.
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Case 1: Standalone operation without SDO, LDAC tied low.
t1
t2
CS
t3
t4
t7
t6
t5
Input Register
and DAC Latch
Updated
SCLK
t8
Bit 23 (N)
SDI
LDAC
t9
Bit 22 (N)
Bit 1 (N)
Bit 0 (N)
Low
Case 2: Standalone operation without SDO, LDAC active.
t2
t1
CS
Input Register
Updated
t3
t4
t7
t6
t5
SCLK
t8
Bit 23 (N)
SDI
LDAC
t9
Bit 22 (N)
Bit 1 (N)
Bit 0 (N)
t14
High
t15
DAC Latch
Updated
= Don’t Care
Bit 23 = MSB
Bit 0 = LSB
Figure 1. Timing Diagram for Standalone Operation Without SDO
12
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Case 1: Standalone operation with output from SDO, LDAC tied low.
t1
t2
CS
Input Register
and DAC Latch
Updated
t3
t4
t7
t6
t5
SCLK
t8
Bit 23 (N)
SDI
t9
Bit 22 (N)
Bit 1 (N)
t11
High-Z
SDO
LDAC
Bit 23 (N - 1)
from Input Reg.
Bit 22 (N - 1)
from Input Reg.
Bit 0 (N)
t12
t13
Bit 1 (N - 1)
from Input Reg.
Bit 0 (N - 1)
from Input Reg.
High-Z
t10
Low
Case 2: Standalone operation with output from SDO, LDAC active.
t2
t1
CS
Input Register
Updated
t3
t4
t7
t6
t5
SCLK
t8
Bit 23 (N)
SDI
t9
Bit 22 (N)
Bit 1 (N)
t11
High-Z
SDO
LDAC
High
Bit 23 (N - 1)
from Input Reg.
Bit 22 (N - 1)
from Input Reg.
Bit 0 (N)
t12
t13
Bit 1 (N - 1)
from Input Reg.
Bit 0 (N - 1)
from Input Reg.
t10
t14
High-Z
t15
DAC Latch
Updated
= Don’t Care
Bit 23 = MSB
Bit 0 = LSB
Figure 2. Timing Diagram for Standalone Operation With SDO
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Case 1: Daisy Chain, LDAC tied low.
t1
t2
CS
Input Register
and DAC Latch
Updated
t3
t4
t7
t6
t5
SCLK
t8
Bit 23 (N)
SDI
t9
Bit 22 (N)
Bit 0 (N)
Bit 23 (N + 1)
t11
LDAC
t12
t13
Bit 23 (N)(1)
High-Z
SDO
Bit 0 (N + 1)
Bit 0 (N)
High-Z
t10
Low
Case 2: Daisy Chain, LDAC active.
t1
t2
CS
Input Register
Updated
t3
t4
t7
t6
t5
SCLK
t8
Bit 23 (N)
SDI
t9
Bit 22 (N)
Bit 0 (N)
Bit 23 (N + 1)
t11
LDAC
High
t12
Bit 23 (N)
High-Z
SDO
Bit 0 (N + 1)
t10
t13
(1)
Bit 0 (N)
High-Z
t14
t15
DAC Latch
Updated
= Don’t Care
Bit 23 = MSB
Bit 0 = LSB
NOTE: (1) SDO data delayed from SDI by 24 clock cycles.
Figure 3. Timing Diagram for Daisy-Chain Mode, Two Cascaded Devices
14
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6.9 Typical Characteristics: AVDD = 5 V
at TA = 25°C, VREFH = 5 V, VREFL = 0 V, and gain = 1X mode (unless otherwise noted)
2.0
TA = +25°C
1.5
1.5
1.0
1.0
DNL Error (LSB)
INL Error (LSB)
2.0
0.5
0
-0.5
-0.5
-1.5
-1.5
-2.0
32768 65536 98304 131072 163840 196608 229376 262144
Digital Input Code
0
Figure 4. Linearity Error vs Digital Input Code
2.0
2.0
TA = -40°C
1.5
1.5
1.0
1.0
0.5
0
-0.5
32768 65536 98304 131072 163840 196608 229376 262144
Digital Input Code
Figure 5. Differential Linearity Error vs Digital Input Code
DNL Error (LSB)
INL Error (LSB)
0
-1.0
0
TA = -40°C
0.5
0
-0.5
-1.0
-1.0
-1.5
-1.5
-2.0
-2.0
0
32768 65536 98304 131072 163840 196608 229376 262144
Digital Input Code
0
Figure 6. Linearity Error vs Digital Input Code
2.0
2.0
TA = +105°C
1.5
1.5
1.0
1.0
0.5
0
-0.5
TA = +105°C
0.5
0
-0.5
-1.0
-1.0
-1.5
-1.5
-2.0
32768 65536 98304 131072 163840 196608 229376 262144
Digital Input Code
Figure 7. Differential Linearity Error vs Digital Input Code
DNL Error (LSB)
INL Error (LSB)
0.5
-1.0
-2.0
TA = +25°C
-2.0
0
32768 65536 98304 131072 163840 196608 229376 262144
Digital Input Code
Figure 8. Linearity Error vs Digital Input Code
0
32768 65536 98304 131072 163840 196608 229376 262144
Digital Input Code
Figure 9. Differential Lineary Error vs Digital Input Code
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Typical Characteristics: AVDD = 5 V (continued)
at TA = 25°C, VREFH = 5 V, VREFL = 0 V, and gain = 1X mode (unless otherwise noted)
2.0
2.0
1.5
1.5
INL Max
1.0
DNL Error (LSB)
INL Error (LSB)
1.0
0.5
0
-0.5
INL Min
DNL Min
-0.5
-1.0
-1.5
-1.5
-2.0
-40
-20
0
20
40
60
Temperature (°C)
80
100
120
-40
Figure 10. Linearity Error vs Temperature
0
-20
20
40
60
Temperature (°C)
80
100
120
Figure 11. Differential Linearity Error vs Temperature
2.0
2.0
1.5
1.5
INL Max
1.0
DNL Error (LSB)
1.0
INL Error (LSB)
0
-1.0
-2.0
DNL Max
0.5
0.5
0
-0.5
INL Min
-1.0
DNL Max
0.5
0
DNL Min
-0.5
-1.0
VREFH = 2.5V
VREFL = 0V
-1.5
VREFH = 2.5V
VREFL = 0V
-1.5
-2.0
-2.0
-40
-20
0
20
40
60
Temperature (°C)
80
100
120
-40
-20
0
Gain = 2X mode
20
40
60
Temperature (°C)
80
100
120
Gain = 2X mode
Figure 12. Linearity Error vs Temperature
Figure 13. Differential Linearity Error vs Temperature
2.0
2.0
1.5
1.5
INL Max
1.0
DNL Error (LSB)
INL Error (LSB)
1.0
0.5
0
INL Min
-0.5
-1.0
-1.5
0
DNL Min
-0.5
-1.0
VREFH = 2.5V
VREFL = 0V
-1.5
-2.0
VREFH = 2.5V
VREFL = 0V
-2.0
2.5
3.0
3.5
4.0
4.5
5.0
Supply Voltage (V)
5.5
Figure 14. Linearity Error vs Supply Voltage
16
DNL Max
0.5
6.0
2.5
3.0
3.5
4.0
4.5
5.0
Supply Voltage (V)
5.5
6.0
Figure 15. Differential Linearity Error vs Supply Voltage
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Typical Characteristics: AVDD = 5 V (continued)
at TA = 25°C, VREFH = 5 V, VREFL = 0 V, and gain = 1X mode (unless otherwise noted)
2.0
2.0
1.5
1.5
INL Max
1.0
DNL Error (LSB)
INL Error (LSB)
1.0
0.5
0
INL Min
-0.5
DNL Min
-0.5
-1.0
-1.5
-1.5
-2.0
0
1.0
2.0
3.0
4.0
Reference Voltage (V)
5.0
6.0
0
Figure 16. Linearity Error vs Reference Voltage
1.0
2.0
3.0
4.0
Reference Voltage (V)
5.0
6.0
Figure 17. Differential Linearity Error vs Reference Voltage
1.0
Full-Scale and Zero-Scale Error (mV)
1.0
Full-Scale and Zero-Scale Error (mV)
0
-1.0
-2.0
DNL Max
0.5
0.8
0.6
0.4
Full-Scale Error
0.2
0
Zero-Scale Error
-0.2
-0.4
-0.6
-0.8
-1.0
VREFH = 2.5V
VREFL = 0V
0.8
0.6
0.4
Full-Scale Error
0.2
0
-0.2
Zero-Scale Error
-0.4
-0.6
-0.8
-1.0
-55
-35
-15
5
25
45
65
Temperature (°C)
85
105
125
-55
-35
5
-15
25
45
65
Temperature (°C)
85
105
125
Gain = 2X mode
Figure 18. Full-Scale and Zero-Scale Error vs Temperature
Figure 19. Full-Scale and Zero-Scale Error vs Temperature
1100
1000
AVDD = 5.0V
VREFH = 2.5V
VREFL = 0V
900
800
AVDD = 5.0V
VREFH = 5.0V
VREFL = 0V
700
AVDD = 2.7V
VREFH = 2.7V
VREFL = 0V
600
AVDD = 2.7V
VREFH = 2.5V
VREFL = 0V
500
400
AVDD = 5.0V
VREFH = 2.5V
VREFL = 0V
900
AVDD Supply Current (mA)
AVDD Supply Current (mA)
1000
300
800
700
AV
AVDD
= 2.7V
2.7V
DD =
VVREFH
= 1.25V
1.25V
REFH =
VVREFL
= 0V
0V
REFL =
600
500
400
300
200
100
200
0
0
65536
131072
Digital Input Code
196608
262144
0
65536
131072
Digital Input Code
196608
262144
Gain = 2X mode
Figure 20. AVDD Supply Current vs Digital Input Code
Figure 21. AVDD Supply Current vs Digital Input Code
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Typical Characteristics: AVDD = 5 V (continued)
at TA = 25°C, VREFH = 5 V, VREFL = 0 V, and gain = 1X mode (unless otherwise noted)
50
AVDD Power-Down Current (mA)
AVDD Supply Current (mA)
1200
1000
800
VREFH = 5.0V
VREFL = 0V
Gain = 1X Mode
600
VREFH = 2.5V
VREFL = 0V
Gain = 2X Mode
400
200
40
30
AVDD = 5.0V
20
AVDD = 2.7V
10
DAC Code Set to 3F000h
0
0
-55
-35
-15
5
25
45
65
Temperature (°C)
85
105
125
-55
Figure 22. AVDD Supply Current vs Temperature
5
-15
25
45
65
Temperature (°C)
1.5
VREFH Current
0.5
0
VREFL Current
-0.5
105
125
VREFH = 2.5V
VREFL = 0V
1.0
Reference Current (mA)
1.0
85
Figure 23. AVDD Power-Down Current vs Temperature
1.5
Reference Current (mA)
-35
-1.0
VREFH Current
0.5
0
-0.5
VREFL Current
-1.0
-1.5
-1.5
0
65536
131072
Digital Input Code
196608
262144
0
65536
131072
Digital Input Code
196608
262144
Gain = 2X mode
Figure 24. Reference Current vs Digital Input Code
Figure 25. Reference Current vs Digital Input Code
5.0
5.00
DAC Loaded with 3FFFFh
4.5
DAC Loaded with 3FFFFh
4.95
Output Voltage (V)
Output Voltage (V)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0
4.85
DAC Loaded with 3E000h
4.75
0
3
6
9
I(SOURCE/SINK) (mA)
12
15
Figure 26. Output Voltage vs Drive Current Capability
18
DAC Loaded with 3F000h
4.80
DAC Loaded with 00000h
0.5
DAC Loaded with 3F800h
4.90
0
1
2
3
ISOURCE (mA)
4
5
Figure 27. Output Voltage vs Drive Current Capability
(Operation Near AVDD Rail)
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Typical Characteristics: AVDD = 5 V (continued)
at TA = 25°C, VREFH = 5 V, VREFL = 0 V, and gain = 1X mode (unless otherwise noted)
200
0.25
IOVDD Supply Current (mA)
180
Output Voltage (V)
0.20
DAC Loaded with 02000h
0.15
DAC Loaded with 01000h
0.10
DAC Loaded with 00800h
0.05
IOVDD = 5V
160
140
120
100
80
60
40
IOVDD = 2.7V
20
DAC Loaded with 00000h
0
0
1
2
3
0
4
0
5
ISINK (mA)
Figure 28. Output Voltage vs Drive Current Capability
(Operation Near AGND Rail)
0.5
1.0
1.5 2.0 2.5 3.0 3.5
Logic Input Voltage (V)
4.0
4.5
5.0
Figure 29. IOVDD Supply Current vs Logic Input Voltage
Large-Signal Output
2V/div
LargeSignal
Output
Small-Signal Error
2V/div
5V/div
1mV/div
LDAC
Signal
Code Change: 00000h to 3FFFFh
Output Loaded with 10kW and
50pF to AGND
Small-Signal Error
5V/div
LDAC
Signal
Time (2ms/div)
1mV/div
Code Change: 3FFFFh to 00000h
Output Loaded with 10kW and
50pF to AGND
Time (2ms/div)
Figure 30. Large-Signal Settling Time
Figure 31. Large-Signal Settling Time
Large-Signal Output
2V/div
Large-Signal Output
Small-Signal Error
2V/div
1mV/div
1mV/div
Small-Signal Error
5V/div
LDAC
Signal
Code Change: 04000h to 3C000h
Output Loaded with 10kW and
50pF to AGND
5V/div
LDAC
Signal
Time (2ms/div)
Code Change: 3C000h to 04000h
Output Loaded with 10kW and
50pF to AGND
Time (2ms/div)
Figure 32. Large-Signal Settling Time
Figure 33. Large-Signal Settling Time
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Typical Characteristics: AVDD = 5 V (continued)
at TA = 25°C, VREFH = 5 V, VREFL = 0 V, and gain = 1X mode (unless otherwise noted)
VREFH = 2.5V
VREFH = 2.5V
Large-Signal Output
2V/div
LargeSignal
Output
Small-Signal Error
2V/div
5V/div
1mV/div
LDAC
Signal
Code Change: 00000h to 3FFFFh
Output Loaded with 10kW and
50pF to AGND
Small-Signal Error
5V/div
1mV/div
LDAC
Signal
Code Change: 3FFFFh to 00000h
Output Loaded with 10kW and
50pF to AGND
Time (2ms/div)
Time (2ms/div)
Gain = 2X mode
Gain = 2X mode
Figure 34. Large-Signal Settling Time
VREFH = 2.5V
Figure 35. Large-Signal Settling Time
VREFH = 2.5V
Large-Signal Output
2V/div
Large-Signal Output
Small-Signal Error
2V/div
1mV/div
1mV/div
Small-Signal Error
5V/div
LDAC
Signal
Code Change: 04000h to 3C000h
Output Loaded with 10kW and
50pF to AGND
5V/div
LDAC
Signal
Code Change: 3C000h to 04000h
Output Loaded with 10kW and
50pF to AGND
Time (2ms/div)
Time (2ms/div)
Gain = 2X mode
Gain = 2X mode
Figure 36. Large-Signal Settling Time
Gain = 1X Mode
VREFH = +5V
Figure 37. Large-Signal Settling Time
Code Change: 1FFFFh to 20000h
Output Loaded with 10kW and
50pF to AGND
Gain = 1X Mode
VREFH = +5V
Integrated Glitch Energy (28nV-s)
100mV/div
VOUT Signal
100mV/div
VOUT Signal
Integrated Glitch Energy (38nV-s)
5V/div
LDAC
Signal
5V/div
Time (2ms/div)
Code Change: 20000h to 1FFFFh
Output Loaded with 10kW and
50pF to AGND
Time (2ms/div)
Figure 38. Major Carry Glitch
20
LDAC
Signal
Figure 39. Major Carry Glitch
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Typical Characteristics: AVDD = 5 V (continued)
at TA = 25°C, VREFH = 5 V, VREFL = 0 V, and gain = 1X mode (unless otherwise noted)
Code Change: 1FFFFh to 20000h
Output Loaded with 10kW and
50pF to AGND
Gain = 1X Mode
VREFH = +2.5V
Gain = 1X Mode
VREFH = +2.5V
Integrated Glitch Energy (15nV-s)
100mV/div
VOUT Signal
100mV/div
VOUT Signal
Integrated Glitch Energy (17nV-s)
5V/div
LDAC
Signal
5V/div
Time (2ms/div)
Code Change: 20000h to 1FFFFh
Output Loaded with 10kW and
50pF to AGND
Time (2ms/div)
Figure 40. Major Carry Glitch
Figure 41. Major Carry Glitch
180
DAC Code Set to 20000h
Output Unloaded
160
140
120
2mV/div
Output Voltage Noise Density (nV/ÖHz)
LDAC
Signal
100
80
60
Gain = 2X Mode
40
20
Gain = 1X Mode
0
1
10
100
1k
Frequency (Hz)
10k
Time (1s/div)
100k
Figure 42. Output Noise Density vs Frequency
Figure 43. Low-Frequency Output Noise (0.1 Hz to 10 Hz)
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6.10 Typical Characteristics: AVDD = 2.7 V
at TA = 25°C, VREFH = 2.5 V, VREFL = 0 V, and gain = 1X mode (unless otherwise noted)
3.0
2.0
TA = +25°C
TA = +25°C
1.5
2.0
DNL Error (LSB)
INL Error (LSB)
1.0
1.0
0
-1.0
0.5
0
-0.5
-1.0
-2.0
-1.5
-3.0
-2.0
0
32768 65536 98304 131072 163840 196608 229376 262144
Digital Input Code
0
Figure 44. Linearity Error vs Digital Input Code
3.0
32768 65536 98304 131072 163840 196608 229376 262144
Digital Input Code
Figure 45. Differential Linearity Error vs Digital Input Code
2.0
TA = -40°C
TA = -40°C
1.5
2.0
DNL Error (LSB)
INL Error (LSB)
1.0
1.0
0
-1.0
0.5
0
-0.5
-1.0
-2.0
-1.5
-3.0
-2.0
0
32768 65536 98304 131072 163840 196608 229376 262144
Digital Input Code
0
Figure 46. Linearity Error vs Digital Input Code
3.0
32768 65536 98304 131072 163840 196608 229376 262144
Digital Input Code
Figure 47. Differential Linearity Error vs Digital Input Code
2.0
TA = +105°C
TA = +105°C
1.5
2.0
DNL Error (LSB)
INL Error (LSB)
1.0
1.0
0
-1.0
0.5
0
-0.5
-1.0
-2.0
-1.5
-3.0
-2.0
0
32768 65536 98304 131072 163840 196608 229376 262144
Digital Input Code
Figure 48. Linearity Error vs Digital Input Code
22
0
32768 65536 98304 131072 163840 196608 229376 262144
Digital Input Code
Figure 49. Differential Linearity Error vs Digital Input Code
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Typical Characteristics: AVDD = 2.7 V (continued)
at TA = 25°C, VREFH = 2.5 V, VREFL = 0 V, and gain = 1X mode (unless otherwise noted)
4.0
2.0
3.0
1.5
INL Max
DNL Max
1.0
DNL Error (LSB)
INL Error (LSB)
2.0
1.0
0
INL Min
-1.0
0
DNL Min
-0.5
-2.0
-1.0
-3.0
-1.5
-4.0
-2.0
0
0.5
1.0
1.5
2.0
Reference Voltage (V)
2.5
3.0
0
Figure 50. Linearity Error vs Reference Voltage
1.0
1.5
2.0
Reference Voltage (V)
2.5
3.0
1.00
900
700
Reference Current (mA)
800
VREF = 1.25V, Gain = 2X Mode
600
VREFH = 2.5V
VREFL = 0V
0.75
VREF = 2.5V, Gain = 1X Mode
500
400
300
200
100
VREFH Current
0.50
0.25
0
VREFL Current
-0.25
-0.50
-0.75
DAC Code Set to 3FFFFh
0
-1.00
-55
-35
5
-15
25
45
65
Temperature (°C)
85
105
0
125
Figure 52. AVDD Supply Current vs Temperature
65536
131072
Digital Input Code
196608
262144
Figure 53. Reference Current vs Digital Input Code
1.00
3.0
DAC Loaded with 3FFFFh, VREFH = 2.7V
VREFH = 1.25V
VREFL = 0V
0.75
0.50
VREFH Current
0.25
0
2.5
Output Voltage (V)
Reference Current (mA)
0.5
Figure 51. Differential Linearity Error vs Reference Voltage
1000
AVDD Supply Current (mA)
0.5
VREFL Current
-0.25
DAC Loaded with 3FFFFh, VREFH = 2.5V
2.0
1.5
1.0
-0.50
0.5
-0.75
DAC Loaded with 00000h
0
-1.00
0
65536
131072
Digital Input Code
196608
262144
0
3
6
9
I(SOURCE/SINK) (mA)
12
15
Gain = 2X mode
Figure 54. Reference Current vs Digital Input Code
Figure 55. Output Voltage vs Drive Current Capability
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Typical Characteristics: AVDD = 2.7 V (continued)
at TA = 25°C, VREFH = 2.5 V, VREFL = 0 V, and gain = 1X mode (unless otherwise noted)
2.70
0.25
DAC Loaded with 3FFFFh
0.20
2.60
DAC Loaded
with 3F800h
2.55
DAC Loaded
with 3F000h
2.50
Output Voltage (V)
Output Voltage (V)
2.65
DAC Loaded
with 3E000h
DAC Loaded with 3FFFFh, VREFH = 2.5V
2.45
DAC Loaded
with 01000h
0.15
0.10
0.05
VREFH = 2.7V, unless otherwise noted.
2.40
DAC Loaded with 00000h
0
0
1
2
3
ISOURCE (mA)
DAC Loaded
with 02000h
DAC Loaded
with 00800h
4
5
0
1
2
3
4
5
ISINK (mA)
Figure 56. Output Voltage vs Drive Current Capability
(Operation Near AVDD Rail)
Large-Signal Output
Figure 57. Output Voltage vs Drive Current Capability
(Operation Near AGND Rail)
Code Change: 3FFFFh to 00000h
Output Loaded with 10kW and
50pF to AGND
1V/div
Large-Signal Output
Small-Signal Error
1V/div
1mV/div
1mV/div
Small-Signal Error
5V/div
LDAC
Signal
Code Change: 00000h to 3FFFFh
Output Loaded with 10kW and
50pF to AGND
5V/div
LDAC
Signal
Time (2ms/div)
Time (2ms/div)
Figure 58. Large-Signal Settling Time
Figure 59. Large-Signal Settling Time
Large-Signal Output
1V/div
Large-Signal Output
Small-Signal Error
1V/div
1mV/div
1mV/div
Small-Signal Error
5V/div
LDAC
Signal
Code Change: 04000h to 3C000h
Output Loaded with 10kW and
50pF to AGND
5V/div
LDAC
Signal
Time (2ms/div)
Time (2ms/div)
Figure 60. Large-Signal Settling Time
24
Code Change: 3C000h to 04000h
Output Loaded with 10kW and
50pF to AGND
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Figure 61. Large-Signal Settling Time
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Typical Characteristics: AVDD = 2.7 V (continued)
at TA = 25°C, VREFH = 2.5 V, VREFL = 0 V, and gain = 1X mode (unless otherwise noted)
Gain = 1X Mode
VREFH = +2.5V
Code Change: 1FFFFh to 20000h
Output Loaded with 10kW and
50pF to AGND
Gain = 1X Mode
VREFH = +2.5V
Integrated Glitch Energy (17.5nV-s)
100mV/div
VOUT Signal
100mV/div
VOUT Signal
Integrated Glitch Energy (16.5nV-s)
5V/div
LDAC
Signal
5V/div
Time (2ms/div)
LDAC
Signal
Code Change: 20000h to 1FFFFh
Output Loaded with 10kW and
50pF to AGND
Time (2ms/div)
Figure 62. Major Carry Glitch
Figure 63. Major Carry Glitch
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7 Detailed Description
7.1 Overview
The DAC9881 is a single-channel, 18-bit, serial-input, voltage-output digital-to-analog converter (DAC). The
architecture is an R-2R ladder configuration with the four MSBs segmented, followed by an operational amplifier
that serves as a buffer, as shown in Figure 64. The on-chip output buffer allows rail-to-rail output swings while
providing a low output impedance to drive loads. The DAC9881 operates from a single analog power supply that
ranges from 2.7 V to 5.5 V, and typically consumes 850 μA when operating with a 5-V supply. Data are written to
the device in a 24-bit word format, using an SPI serial interface. To enable compatibility with 1.8-V, 3-V, or 5-V
logic families, an IOVDD supply pin is provided. This pin allows the DAC9881 input and output logic to be
powered from the same logic supply used to interface signals to and from the device. Internal voltage translators
are included in the DAC9881 to interface digital signals to the device core. See Figure 65 for the basic
configuration of the DAC9881.
To provide a known power-up state, the DAC9881 is designed with a power-on reset function. Upon power-up,
the DAC9881 is reset to either zero-scale or midscale depending on the state of the RSTSEL pin. A hardware
reset can be performed by using the RST and RSTSEL pins.
RFB(1)
RFB
R
VOUT
2R
2R
2R
2R
2R
2R
2R
2R
2R
5kW
VREFH
5kW
NOTE: (1) RFB = 5kW for gain = 1
RFB = 10kW for gain = 2.
VREFH-F
VREFH-S
VREFL-F
VREFL-S
Figure 64. DAC9881 Architecture
26
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Overview (continued)
SDI
Serial Data In
LDAC
SDOSEL
Chip-Select
CS
19
SDOSEL
20
21
AVDD
DGND
SDO
24
SCLK
Clock
23
1 F
IOVDD
1
18
2
17
3
Load DAC Registers
AGND
AVDD
RST
GAIN
RSTSEL
14
12
11
NC
13
NC
VREFH-F
9
VREFL-F
VOUT
VREFH-S
7
6
10
(Thermal Pad)
Reset DAC Registers
USB/BTC
15
5
VREFL-S
PDN
16
DAC9881
4
8
+
0.1 F
22
1.8V to 5V
1 F
RFB
+
0.1 F
Serial Data Out
+5V
0V to +5.0V
External Reference
+5.0000V
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Figure 65. Basic Configuration
7.2 Functional Block Diagram
DGND
IOVDD
AGND
AVDD
VREFH-S VREFH-F
DAC9881
RST
Power-On
Reset
RSTSEL
Control
Logic
USB/BTC
Resistor
Network
SDI
CS
SCLK
SPI Interface
Shift Register
GAIN
PDN
Input
Register
DAC
Latch
VOUT
DAC
RFB
RFB
SDOSEL
SDO
Serial Out
Control
LDAC
VREFL-S
VREFL-F
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7.3 Feature Description
7.3.1 Analog Output
The DAC9881 offers a force and sense output configuration for the high open-loop gain output amplifier. This
feature allows the loop around the output amplifier to be closed at the load (as shown in Figure 66), thus
ensuring an accurate output voltage. The output buffer VOUT and RFB pins are provided so that the output op amp
buffer feedback can be connected at the load. Without a driven load, the DAC9881 output typically swings to
within 15 mV of the AGND and AVDD supply rails. Because of the high accuracy of these DACs, system design
problems such as grounding and wiring resistance become very important. A 18-bit converter with a 5-V fullscale range has an LSB value of 19 µV. The DAC9881 has a typical feedback resistor current of 0.5 mA; thus, a
series wiring resistance of only 100 mΩ (RW1) causes a voltage drop of 50 µV. In terms of a system layout, the
resistivity of a typical 1-ounce copper-clad printed circuit board (PCB) is 0.5-mΩ per square. For a 0.5-mA
current, a 0.25-mm wide printed-circuit conductor 25-mm long results in a voltage drop of 25 µV.
NOTE
the wiring resistance of RW2 is not critical as long as the feedback resistor (RFB) is
connected at the driven load.
Chip-Select
19
SDOSEL
SDOSEL
20
AVDD
21
22
SDO
CS
15
5
14
VOUT
VREFH-S
RW2
13
RST
Reset DAC Registers
USB/BTC
GAIN
RSTSEL
NC
12
6
11
(Thermal Pad)
7
VREFL-S
16
DAC9881
4
PDN
NC
AVDD
3
VREFH-F
AGND
17
10
Load DAC Registers
2
9
LDAC
18
VREFL-F
Serial Data In
1
RFB
SDI
8
SCLK
Clock
23
1 F
IOVDD
+
24
0.1 F
DGND
1 F
RW1
+
1.8V to 5V
0.1 F
Serial Data Out
+5V
VOUT
External Reference
+5.0000V
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Figure 66. Analog Output Closed-Loop Configuration
(RW1 and RW2 Represent Wiring Resistance)
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Feature Description (continued)
7.3.2 Reference Inputs
The reference high input, VREFH, can be set to any voltage in the range of 1.25 V to AVDD. The reference low
input, VREFL, can be set to any voltage in the range of –0.2 V to +0.2 V (to provide a small offset to the output of
the DAC9881, if desired). The current into VREFH and out of VREFL depends on the DAC code, and can vary from
approximately 0.5 mA to 1 mA in the gain = 1X mode of operation. The reference high and low inputs appear as
variable loads to the external reference circuit. If the external references can source or sink the required current,
and if low impedance connections are made to the VREFH and VREFL pins, external reference buffers are not
required. Figure 65 shows a simple configuration of the DAC9881 using external references without force and
sense reference buffers.
Kelvin sense connections for the reference high and low are included on the DAC9881. When properly used with
external reference buffer op amps, these reference Kelvin sense pins make sure that the driven reference high
and low voltages remain stable versus varying reference load currents. Figure 67 shows an example of a
reference force and sense configuration of the DAC9881 operating from a single analog reference voltage. Both
the VREFL and VREFH reference voltages are set to levels of 100 mV from the DAC9881 supply rails, and are
derived from a 5-V external reference. Figure 68 illustrates the effect of not using the reference force and sense
buffers to drive the DAC9881 VREFL and VREFH pins. Figure 69 shows the improvement when using the reference
buffers. A slight degradation in INL and DNL performance is seen without the use of the force and sense buffer
configuration.
SCLK
SDI
LDAC
+5V
AGND
External Reference
+5.0000V
AVDD
OPA2350
VREFL-S
2
3
4
DAC9881
5
6
11
12
NC
10
9
RFB
VREFH-F
96 k
VOUT
VREFH-S
1000pF
VREFL-F
+4.900V
8
50
7
2200pF
2k
1
+0.100V
50
2k
2200pF
1000pF
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0
32768 65536 98304 131072 163840 196608 229376 262144
LE (LSB)
2.0
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
2.0
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
DLE (LSB)
LE (LSB)
2.0
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
DLE (LSB)
Figure 67. Buffered References (VREFH = +4.900 V and VREFL = 100 mV).
2.0
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
0
32768 65536 98304 131072 163840 196608 229376 262144
Digital Input Code
Digital Input Code
Figure 68. Linearity and Differential Linearity Error
for Figure 65 Without Reference Buffers
Figure 69. Linearity and Differential Linearity Error
for Figure 67 With Reference Buffers
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Feature Description (continued)
7.3.3 Output Range
The maximum output range of the DAC9881 is VREFL to (VREFH – VREFL) × G, where G is the output buffer gain
set by the GAIN pin. When the GAIN pin is connected to DGND, the output buffer gain = 1. When the GAIN pin
is connected to IOVDD, the output buffer gain = 2. The output range must not be greater than AVDD; otherwise,
output saturation occurs. The DAC9881 output transfer function is given in Equation 1:
V
- VREFL
VOUT = REFH
´ CODE ´ Buffer Gain + VREFL
262144
where
•
•
•
•
CODE = 0 to 262143. This is the digital code loaded to the DAC
Buffer Gain = 1 or 2 (set by the GAIN pin)
VREFH = reference high voltage applied to the device
VREFL = reference low voltage applied to the device
(1)
7.3.4 Input Data Format
The USB/BTC pin defines the input data format. When this pin is connected to IOVDD, the input data format is
straight binary, as shown in Table 1. When this pin is connected to DGND, the input data format is twos
complement, as shown in Table 2.
Table 1. Output vs Straight Binary Code
USB CODE
5-V RANGE
DESCRIPTION
3FFFFh
+4.99998
+Full-scale – 1 LSB
30000h
+3.75000
3/4-scale
20000h
+2.50000
Midscale
10000h
+1.25000
1/4-scale
00000h
0.00000
Zero-scale
Table 2. Output vs Twos Complement Code
BTC CODE
5-V RANGE
DESCRIPTION
1FFFFh
+4.99998
+Full-scale – 1 LSB
10000h
+3.75000
3/4-scale
00000h
+2.50000
Midscale
3FFFFh
+2.49998
Midscale – 1LSB
30000h
+1.25000
1/4-scale
20000h
0.00000
Zero-scale
7.3.5 Hardware Reset
When the RST pin is low, the device is in hardware reset, and the input register and DAC latch are set to the
value defined by the RSTSEL pin. After RST goes high, the device is in normal operating mode, and the input
register and DAC latch maintain the reset value until new data are written. When USB/BTC is connected to
DGND, the device is in two's complement mode. In this mode, the LDAC pin cannot be kept at logic level 0 or
toggled when a hardware reset is issued before writing a valid DAC data.
7.3.6 Power-On Reset
The DAC9881 has a power-on reset feature. After power-on, the value of the input register, the DAC latch, and
the output from the VOUT pin are set to the value defined by the RSTSEL pin.
7.3.6.1 Program Reset Value
After a power-on reset or a hardware reset, the output voltage from the VOUT pin and the values of the input
register and DAC latch are determined by the status of the RSTSEL pin and the input data format, as shown in
Table 3.
30
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Table 3. Reset Values
VOUT
VALUE OF
INPUT REGISTER
AND DAC LATCH
Straight Binary
0
00000h
Straight Binary
Midscale
20000h
DGND
Twos Complement
0
00000h
DGND
Twos Complement
Midscale
20000h
LDAC PIN
RSTSEL PIN
USB/BTC PIN
INPUT FORMAT
DGND or IOVDD
DGND
IOVDD
DGND or IOVDD
IOVDD
IOVDD
IOVDD
DGND
IOVDD
IOVDD
7.3.7 Power Down
The DAC9881 has a hardware power-down feature. When the PDN pin is high, the device is in power-down
mode. When the device is in power-down, the VOUT pin is connected to ground through an internal 10kΩ resistor,
but the contents of the input register and the DAC latch do not change and SPI communication remains active.
When the PDN pin returns low, the device returns to normal operation.
7.3.8 Double-Buffered Interface
The DAC9881 has a double-buffered interface consisting of two register banks: the input register and the DAC
latch. The input register is connected directly to the input shift register and the digital code is transferred to the
input register upon completion of a valid write sequence. The DAC latch contains the digital code used by the
resistor R-2R ladder. The contents of the DAC latch defines the output from the DAC.
Access to the DAC latch is controlled by the LDAC pin. When LDAC is high, the DAC latch is latched and the
input register can change state without affecting the contents of the DAC latch. When LDAC is low, however, the
DAC latch becomes transparent and the contents of the input register is transferred to the DAC register.
7.3.8.1 Load DAC Pin (LDAC)
LDAC transfers data from the input register to the DAC latch (and, therefore, updates the DAC output). The
contents of the DAC latch (and the output from DAC) can be changed in two ways, depending on the status of
LDAC.
7.3.8.1.1 Synchronous Mode
When LDAC is tied low, the DAC latch updates as soon as new data are transferred into the input register after
the rising edge of CS.
7.3.8.1.2 Asynchronous Mode
When LDAC is high, the DAC latch is latched. The DAC latch (and DAC output) is not updated at the same time
that the input register is written to. When LDAC goes low, the DAC latch updates with the contents of the input
register.
7.3.9 1.8-V to 5-V Logic Interface
All digital input and output pins are compatible with any logic supply voltage between 1.8 V and 5 V. Connect the
interface logic supply voltage to the IOVDD pin. Although timing is specified down to 2.7 V (see the timing
diagrams), IOVDD can operate as low as 1.8 V, but with degraded timing and temperature performance. For the
lowest power consumption, logic VIH levels should be as close as possible to IOVDD, and logic VIL levels should
be as close as possible to GND.
7.3.10 Power-Supply Sequence
For the device to work properly, IOVDD must not come up before AVDD, and the reference voltage must come up
after the AVDD supply. Additionally, because the DAC input shift register is not reset during a power-on reset or
hardware reset, the CS pin must not be unintentionally asserted during power-up of the device. To avoid
improper power-up, it is recommended that the CS and LDAC pins be connected to IOVDD through pullup
resistors. To make sure that the electrostatic discharge (ESD) protection circuitry of this device is not activated,
all other digital pins must be held at ground potential until IOVDD is applied.
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7.4 Device Functional Modes
7.4.1 Serial Interface
The DAC9881 is controlled by a versatile three-wire serial interface that operates at clock rates of up to 50 MHz
and is compatible with SPI, QSPI™, MICROWIRE, and DSP interface standards.
7.4.1.1 Input Shift Register
Data are loaded into the device as a 24-bit word under the control of the serial clock input, SCLK. The timing
diagrams for this operation are shown in timing diagrams section.
The CS input is a level-triggered input that acts as a frame synchronization signal and chip enable. Data can be
transferred into the device only while CS is low. When CS is high, the SCLK and SDI signals are blocked out,
and SDO is in high-Z status. To start the serial data transfer, CS should be taken low, observing the minimum
delay from CS falling edge to SCLK rising edge, t2. After CS goes low, serial input data from SDI are clocked into
the device input shift register on the rising edges of SCLK for 24 or more clock pulses. If a frame contains less
than 24 bits of data, the frame is invalid. Invalid input data are not written into the input register and DAC,
although the input register and DAC will continue to hold data from the preceding valid data cycle. If more than
24 bits of data are transmitted in one frame, the last 24 bits are written into the shift register and DAC. CS may
be taken high after the rising edge of the 24th SCLK pulse, observing the minimum SCLK rising edge to CS
rising edge time, t7. The contents of the shift register are transferred into the input register on the rising edge of
CS. When data have been transferred into the input register of the DAC, the corresponding DAC register and
DAC output can be updated by taking the LDAC pin low. Table 4 shows the input shift register data word format.
D17 is the MSB of the 18-bit DAC data.
Table 4. Input Shift Register Data Word Format
BIT
B23
B22
B21
B20
B19
B18
B17
(MSB)
B16
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
(LSB)
DATA
X (1)
X
X
X
X
X
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
(1)
X = don't care.
7.4.1.1.1 Stand-Alone Mode
When the SDOSEL pin is tied to IOVDD, the interface is in Stand-Alone mode. This mode provides serial
readback for diagnostic purposes. The new input data (24 bits) are clocked into the device shift register and the
existing data in the input register (24 bits) are shifted out from the SDO pin. If more than 24 SCLKs are clocked
when CS is low, the contents of the input register are shifted out from the SDO pin, followed by zeroes; the last
24 bits of input data remain in the shift register. If less than 24 SCLKs are clocked while CS is low, the data from
the SDO pin are part of the data in the input register and must be ignored. Refer to Figure 2 for further details.
7.4.1.1.2 Daisy-Chain Mode
When the SDOSEL pin is tied to GND, the interface is in Daisy-Chain mode. For systems that contain several
DACs, the SDO pin may be used to daisy-chain several devices together.
In Daisy-Chain mode, SCLK is continuously applied to the input shift register while CS is low. If more than 24
clock pulses are applied, the data ripple out of the shift register and appear on the SDO line. These data are
clocked out on the falling edge of SCLK and are valid on the rising edge. By connecting this line to the SDI input
on the next DAC in the chain, a multi-DAC interface is constructed. 24 clock pulses are required for each DAC in
the chain. Therefore, the total number of clock cycles must be equal to (24 x N), where N is the total number of
devices in the chain. When the serial transfer to all devices is complete, CS should be taken high. This action
prevents any further data from being clocked into the input shift register. The contents in the shift registers are
transferred into the relevant input registers on the rising edge of the CS signal.
A continuous SCLK source may be used if CS can be held low for the correct number of clock cycles.
Alternatively, a burst clock containing the exact number of clock cycles can be used and CS can be taken high
some time later. When the transfer to all input registers is complete, a common LDAC signal updates all DAC
registers, and all analog outputs update simultaneously.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The excellent linearity as well as low-noise and fast settling time makes the DAC9881 a strong performer in
applications such as automatic test equipment, precision instrumentation and data acquisition systems.
Additionally, the energy saving feature of the device, through the PDN pin, significantly reduces power
dissipation -- this mode reduces current consumption, as low as 25 µA with a 5-V supply.
8.1.1 Bipolar Operation Using the DAC9881
The DAC9881 is designed for single-supply operation; however, a bipolar output is also possible using the circuit
shown in Figure 70. This circuit gives a bipolar output voltage of VOUT. When GAIN = 1, VOUT can be
calculated using Equation 2:
V REFL
+15 V
DAC9881 V DAC
R2
V REFH
OPA192
VOUT
- 15 V
R1
R3
V REF
Copyright © 2016, Texas Instruments Incorporated
Some pins are omitted for clarity.
Figure 70. Bipolar Output Range
éæ
R öù
CODE ö æ R R ö æ
VOUT (CODE ) = êç VREF ´ 18 ÷ ç1 + 3 + 3 ÷ - ç VREF ´ 3 ÷ ú
R1 ø û
2
ø è R2 R1 ø è
ëè
where
•
•
•
VOUT(CODE) = output voltage vs code
CODE = 0 to 262143. This is the digital code loaded to the DAC
VREF = reference voltage applied to the DAC9881
(2)
As an example, a ±8-V output span can be achieved by using values of 5 V, 6.25 kΩ, 16.67 kΩ, and 10 kΩ for
Vref, R1, R2, and R3 respectively.
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8.2 Typical Application
8.2.1 DAC9881 Sample-and-Hold Circuit
OPA192(A)
DAC9881
OPA192(B)
RS
+
RL Vout
+
Switch (NC)
TS12A4515
CH
CL
Copyright © 2016, Texas Instruments Incorporated
Figure 71. DAC9881 Sample-and-Hold Circuit
8.2.1.1 Design Requirements
The inherent architecture of the DAC9881, which consists of an R-2R architecture, enables great performance in
regards to noise and accuracy, but at a cost of large glitch area. Glitch area, also known as glitch impulse area,
is defined as the area associated with the overshoot or undershoot created by a code transition, and is generally
quantified in Volt-seconds. Different code-to-code transitions produce different levels of glitch impulses. DACs
with R-2R architectures produce large glitches during major-carry transitions.
There are two methods that can be used to reduce this glitch area:
1. Add an external RC Filter to the output of the DAC.
– The low-pass filter helps attenuate high-frequency glitches that would normally propagate to the DAC
output. Best practice is to use a small resistor value, as large resistance develops a large potential drop
and reduces the voltage seen at the load. Capacitor values can be determined from the desired cutoff
frequency of the low-pass filter, as well as settling time.
2. Another technique is to employ a Sample and Hold (S&H) circuit following the DAC output.
– In its simplest form, the sample and hold circuit can be constructed from the following components: a
capacitive element, output buffer, and switch. A schematic of the simplified S&H is shown in Figure 72.
RS
DAC
RL
+
Vout
Switch (NC)
CL
CH
Digital/Discrete
Switch Driver
Copyright © 2016, Texas Instruments Incorporated
Figure 72. Simplified Sample and Hold Circuit
8.2.1.2 Detailed Design Procedure
The Sample/Track and Hold modes of operation correspond to the state of the switch, which connects the DAC
output to the hold capacitor CH. In sample mode – also referred to as track mode -- the switch is closed, allowing
the capacitor to charge or discharge to the sampled DAC output voltage. The operational amplifier is configured
as a buffer, which tracks and relays the voltage seen across CH to the output of the circuit. In hold mode, the
switch opens, disconnecting CH from the DAC output. The DAC is updated while the circuit is in hold mode,
preventing any DAC major carry glitches from propagating to the S&H output. The capacitor retains the previous
sampled voltage, and this value is buffered to the output of the circuit. In real circuits, switch leakage and
operational amplifier input bias current must be considered as it will impact circuit performance. The switch is
generally controlled by an external discrete or digital driver.
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Typical Application (continued)
After the DAC glitch relays, the switch closes and re-enters sample or track mode.
More information related to this circuit can be found in Sample and Hold Glitch Reduction for Precision Outputs
Design Guide (TIDU022).
8.2.1.3 Application Curves
Glitch reduction and total unadjusted error (TUE) plots of the solution presented in Sample and Hold Glitch
Reduction for Precision Outputs Design Guide (TIDU022) is shown in the following plots. The glitch area is
reduced from 35.11 nVs to 2.01 nVs.
CH = 8.2 nF
Figure 73. DAC9881 Sample-and-Hold TUE Error %FSR
RS = 14.7 Ω
Figure 74. Measured Glitch Area (20000h-1FFFFh)
(Top) Digital Signal One-Shot Pulse; (Middle) DAC Output
Glitch; (Bottom) S-H Output Glitch
8.3 System Example
Figure 75 displays a typical serial interface that may be used when connecting the DAC9881's SPI serial
interface to a (master) microcontroller. The setup for the interface is as follows: The microcontroller's output SPI
CLK drives the SCLK pin of the DAC9881, while the DAC9881 SDI pin is driven by the MOSI pin of the
microcontroller. The CS pin of the DAC9881 can be asserted from a general program input/output pin of the
microcontroller. When data are to be transmitted to the DAC9881, the CS pint is taken low. The data from the
microcontroller is then transmitted to the DAC9881, totaling 24 bits latched into the DAC9881 device through the
negative edge of SCLK. CS is then brought high after the completed write. The DAC9881 requires its data with
the MSB as the first bit received.
microcontroller
DAC9881
CS
CS
SCL
K
SCLK
MOSI
SDI
MISO
SDO
Copyright © 2016, Texas Instruments Incorporated
Figure 75. Simplified Sample-and-Hold Circuit
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9 Power Supply Recommendations
The DAC9881 operates within the specified supply voltage range of 2.7 V to 5.5 V. The power applied to AVDD
should be well regulated and low noise. Switching power supplies and DC/DC converters often have highfrequency glitches or spikes riding on the output voltage. In addition, digital components can create similar high
frequency spikes. This noise can easily couple into the DAC output voltage through various paths between the
power connections and analog output. To further minimize noise from the power supply, a strong
recommendation is to include a 1-µF to 10-µF capacitor and 0.1-µF bypass capacitor. The current consumption
on the AVDD pin, the short-circuit current limit, and the load current for the device is listed in Electrical
Characteristics. The power supply must meet the aforementioned current requirements.
10 Layout
10.1 Layout Guidelines
A precision analog component requires careful layout, the list below provides some insight into good layout
practices.
• All Power Supply pins should be bypassed to ground with a low ESR ceramic bypass capacitor. The typical
recommended bypass capacitance is 0.1 µF to 0.22 µF ceramic with a X7R or NP0 dielectric.
• Power supplies and VrefH/L bypass capacitors should be placed close to terminals to minimize inductance
and optimize performance.
• A high-quality ceramic type NP0 or X7R is recommended for optimal performance across temperature, and a
very low dissipation factor.
• The digital and analog sections should have proper placement with respect to the digital pins and analog pins
of the DAC9881 device. The separation of analog and digital blocks allows for better design and practice
because of less coupling into neighboring blocks, and less interaction between analog and digital return
currents.
10.2 Layout Example
Pullup Resistors
R1 R2 R3
IOVDD
GND
GND
GND
Supply Bypass
Capacitors C1
GND
Reference Bypass
Capacitors
GND
18
12
GND
C4
GND
24
1
6
GND
C2
GND
GND
C3
DIGITAL SIDE
GND
ANALOG SIDE
Figure 76. DAC9881 Basic Layout Example
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• DAC9881 Evaluation Module user's guide
• Sample and Hold Glitch Reduction for Precision Outputs design guide
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
QSPI is a trademark of Motorola, Inc.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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7-Oct-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
DAC9881SBRGER
ACTIVE
VQFN
RGE
24
3000
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 105
DAC
9881
B
DAC9881SBRGET
ACTIVE
VQFN
RGE
24
250
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 105
DAC
9881
B
DAC9881SRGER
ACTIVE
VQFN
RGE
24
3000
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 105
DAC
9881
DAC9881SRGET
ACTIVE
VQFN
RGE
24
250
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 105
DAC
9881
DAC9881SRGETG4
ACTIVE
VQFN
RGE
24
250
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 105
DAC
9881
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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