DDC114IRTCTG3

DDC114 SBAS255C − JUNE 2004 − REVISED APRIL 2009 Quad Current Input, 20-Bit Analog-To-Digital Converter FEATURES D D D D D D D D DESCRIPTION SINGLE-CHIP SOLUTION TO DIRECTLY MEASURE FOUR LOW-LEVEL CURRENTS HIGH PRECISION, TRUE INTEGRATING FUNCTION INTEGRAL LINEARITY: ±0.01% of Reading ±0.5ppm of FSR VERY LOW NOISE: 5.2ppm of FSR LOW POWER: 13.5mW/channel ADJUSTABLE DATA RATE: Up to 3.125kSPS PROGRAMMABLE FULL SCALE DAISY-CHAINABLE SERIAL INTERFACE The DDC114 is a 20-bit, quad channel, current-input analog-to-digital (A/D) converter. It combines both current-to-voltage and A/D conversion so that four low-level current output devices, such as photodiodes, can be directly connected to its inputs and digitized. For each of the four inputs, the DDC114 provides a dual-switched integrator front-end. This design allows for continuous current integration: while one integrator is being digitized by the onboard A/D converter, the other is integrating the input current. Adjustable full-scale ranges from 12pC to 350pC and adjustable integration times from 50µs to 1s allow currents from fAs to µAs to be measured with outstanding precision. Low-level linearity is ±0.5ppm of the full-scale range and noise is 5.2ppm of the full-scale range. APPLICATIONS D D D D CT SCANNER DAS PHOTODIODE SENSORS INFRARED PYROMETERS LIQUID/GAS CHROMATOGRAPHY Two modes of operation are provided. In Low-Power mode, total power dissipation is only 13.5mW per channel with a maximum data rate of 2.5kSPS. High-Speed mode supports data rates up to 3.125kSPS with a corresponding dissipation of 18mW per channel. Protected by US Patent #5841310 AVDD VREF DVDD The DDC114 has a serial interface designed for daisy-chaining in multi-device systems. Simply connect the output of one device to the input of the next to create the chain. Common clocking feeds all the devices in the chain so that the digital overhead in a multi-DDC114 system is minimal. CLK CONV IN1 RANGE0 Dual Switched Integrator ∆Σ Modulator Digital Filter RANGE1 Control RANGE2 TEST CLK_4X IN3 HISPD/LOPWR Dual Switched Integrator RESET FORMAT DCLK The DDC114 is a single-supply device using a +5V analog supply and supporting a +2.7V to +5.25V digital supply. Operating over the industrial temperature range of −40°C to +85°C, the DDC114 is offered in a QFN-48 package. IN2 DCLK Dual Switched Integrator ∆Σ Modulator Digital Filter Digital Input/Output DVALID DOUT DOUT IN4 DIN Dual Switched Integrator AGND DIN DGND Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright  2004−2009, Texas Instruments Incorporated
          
             
 !     !    www.ti.com ""# www.ti.com SBAS255C − JUNE 2004 − REVISED APRIL 2009 PACKAGE/ORDERING INFORMATION For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS(1) Analog Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750µA AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3V to +6V AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3V to +6V DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3V to +6V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.2V VREF Input to AGND . . . . . . . . . . . . . . . . . . 2.0V to AVDD + 0.3V Analog Input to AGND . . . . . . . . . . . . . . . . . . . . . . . −0.3V to +0.7V Digital Input Voltage to DGND . . . . . . . . . . . −0.3V to DVDD + 0.3V Digital Output Voltage to DGND . . . . . . . . . −0.3V to AVDD + 0.3V Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . −40°C to +85°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . −60°C to +150°C Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. 2 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ""# www.ti.com SBAS255C − JUNE 2004 − REVISED APRIL 2009 ELECTRICAL CHARACTERISTICS At TA = +25°C, AVDD = +5V, DVDD = 3V, VREF = +4.096V, Range 5 (250pC), and continuous mode operation, unless otherwise noted. Low-Power Mode: TINT = 400µs and CLK = 4MHz; High-Speed Mode: TINT = 320µs and CLK = 4.8MHz. Low-Power Mode PARAMETER TEST CONDITIONS ANALOG INPUT RANGE Range 0 Range 1 Range 2 Range 3 Range 4 Range 5 Range 6 Range 7 Negative Full-Scale Range Input Current(2) MIN TYP 10.2 12 13.8 47.5 50 52.5 95 100 105 142.5 150 157.5 190 200 210 237.5 250 262.5 285 300 315 332.5 350 367.5 −0.4% of Positive Full-Scale Range 750 DYNAMIC CHARACTERISTICS Data Rate Integration Time, TINT High-Speed Mode MAX Continuous Mode Non-continuous Mode, Range 1 to 7 2.5 1,000,000 400 50 System Clock Input (CLK) CLK_4X = 0 CLK_4X = 1 Data Clock (DCLK) MIN TYP MAX ∗(1) ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ 4 16 16 pC pC pC pC pC pC pC pC pC µA 3.125 kSPS µS µS 4.8 19.2 MHz MHz MHz ∗ 320 UNITS ∗ ACCURACY Noise, Low-Level Input(3) CSENSOR(4) = 50pF, Range 5 (250pC) Integral Linearity Error(6) Resolution Input Bias Current Range Error Match(7) Range Sensitivity to VREF Offset Error Offset Error Match(7) DC Bias Voltage(9) Power-Supply Rejection Ratio Internal Test Signal Internal Test Accuracy FORMAT = 1 FORMAT = 0 All Ranges VREF = 4.096 ± 0.1V Low-Level Input (< 1% FSR) at dc 5.2 6.5 ±0.01% Reading ± 0.5ppm FSR, typ ±0.025% Reading ± 1.0ppm FSR, max 20 16 0.1 10 0.1 0.5 1:1 ±400 ±1000 ±100 ±0.05 ±2 ±25 ±200 11 ±10 5.5 ∗ ∗ 7 ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ppm of FSR(5), rms Bits Bits pA % of FSR ppm of FSR ppm of FSR mV ppm of FSR/V pC % PERFORMANCE OVER TEMPERATURE Offset Drift ±0.5 ±3(8) Offset Drift Stability ±0.2 ±1(8) DC Bias Voltage Drift(9) Input Bias Current Drift Range Drift(10) 3 0.01 25 1(8) REFERENCE Voltage Input Current(11) TA = +25°C to +45°C 4.000 Average Value 4.096 75 4.200 ∗ 95 ∗ ppm of FSR/°C ppm of FSR/ minute µV/°C pA/°C ppm/°C V µA (1) ∗ indicates that specification is the same as Low-Power Mode. (2) Exceeding maximum input current specification may damage device. (3) Input is less than 1% of full scale. (4) C SENSOR is the capacitance seen at the DDC114 inputs from wiring, photodiode, etc. (5) FSR is Full-Scale Range. (6) A best-fit line is used in measuring nonlinearity. (7) Matching between side A and side B of the same input. (8) Ensured by design, not production tested. (9) Voltage produced by the DDC114 at its input which is applied to the sensor. (10)Range drift does not include external reference drift. (11)Input reference current decreases with increasing TINT (see the Voltage Reference section, page 11). 3 ""# www.ti.com SBAS255C − JUNE 2004 − REVISED APRIL 2009 ELECTRICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = +5V, DVDD = 3V, VREF = +4.096V, Range 5 (250pC), and continuous mode operation, unless otherwise noted. Low-Power Mode: TINT = 400µs and CLK = 4MHz; High-Speed Mode: TINT = 320µs and CLK = 4.8MHz. Low-Power Mode PARAMETER DIGITAL INPUT/OUTPUT Logic Levels VIH VIL VOH VOL Input Current (IIN) Data Format(12) POWER-SUPPLY REQUIREMENTS Analog Power-Supply Voltage (AVDD) Digital Power-Supply Voltage (DVDD) Supply Current Total Analog Current Total Digital Current Total Power Dissipation Total Power Dissipation per Channel TEST CONDITIONS IOH = −500µA IOL = 500µA 0 < VIN < DVDD MIN TYP 0.8DVDD − 0.1 DVDD − 0.4 High-Speed Mode MAX MIN DVDD + 0.1 0.2DVDD ∗ ∗ 0.4 ±10 DVDD = +3V DVDD = +3V DVDD = +3V 5.25 5.25 10.5 0.5 54 13.5 75 18.75 ∗ ∗ 14.0 0.67 72 18 (12)Data format is Straight Binary with a small offset. The number of bits in the output word is controlled by the FORMAT pin (see text). 4 MAX ∗ ∗ ∗ Straight Binary 4.75 2.7 TYP UNITS ∗ ∗ V V V V µA ∗ ∗ V V 100 25 mA mA mW mW ""# www.ti.com SBAS255C − JUNE 2004 − REVISED APRIL 2009 DGND CONV DGND DVALID DGND CLK DGND DCLK DCLK DGND DVDD Top View DGND PIN CONFIGURATIONS 48 47 46 45 44 43 42 41 40 39 38 37 QFN DOUT 1 36 DIN DOUT 2 35 DIN CLK_4X 3 34 NC FORMAT 4 33 NC HISPD/LOPWR 5 32 RESET RANGE0 6 RANGE1 7 30 DGND RANGE2 8 29 DGND AGND 31 TEST DDC114 16 17 18 19 20 21 22 23 24 AIN2 AIN1 AGND 15 AGND 14 AGND 13 AGND 25 AGND AIN3 AGND 12 AGND 26 AGND AGND AGND 11 AIN4 27 AVDD AGND 28 AGND AGND 9 VREF 10 PIN DESCRIPTIONS PIN NUMBER FUNCTION DOUT 1 Digital Output DESCRIPTION Serial Data Output DOUT 2 Digital Output Serial Data Output: Complementary Signal CLK_4X 3 Digital Input Master Clock Divider Control: 0 = divide by 1, 1 = divide by 4 FORMAT 4 Digital Input Digital Output Word Format: 0 = 16 Bits, 1 = 20 Bits HISPD/LOPWR 5 Digital Input Mode Control: 0 = Low-Power, 1 = High-Speed RANGE0 6 Digital Input Range Control 0 (least significant bit) RANGE1 7 Digital Input Range Control 1 RANGE2 8 Digital Input Range Control 2 (most significant bit) AGND 9, 11-14, 16, 18-20, 22, 24-26, 28 Analog VREF 10 Analog Input External Voltage Reference Input, 4.096V Nominal AIN4 15 Analog Input Analog Input 4 AIN3 17 Analog Input Analog Input 3 AIN2 21 Analog Input Analog Input 2 AIN1 23 Analog Input Analog Input 1 AVDD 27 Analog Analog Power Supply, 5V Nominal DGND 29, 30, 38, 41, 43, 45, 47, 48 Digital Digital Ground TEST 31 Digital Input Test Mode Control RESET 32 Digital Input Resets the Digital Circuitry, Active Low NC 33, 34 — DIN 35 Digital Input Serial Data Input: Complementary Signal (optional, see text on page 13) DIN 36 Digital Input Serial Data Input DVDD 37 Digital DCLK 39 Digital Input Serial Data Clock Input: Complementary Signal (optional, see text on page 13) DCLK 40 Digital Input Serial Data Clock Input CLK 42 Digital Input Master Clock Input DVALID 44 Digital Output CONV 46 Digital Input Analog Ground No Connection Digital Power Supply, 3V Nominal Data Valid Output, Active Low Conversion Control Input: 0 = Integrate on Side B, 1 = Integrate on Side A 5 ""# www.ti.com SBAS255C − JUNE 2004 − REVISED APRIL 2009 TYPICAL CHARACTERISTICS At TA = +25°C, characterization done with Range 5 (250pC), AVDD = +5V, DVDD = 3V, VREF = +4.096V, Low Power Mode: TINT = 400µs and CLK = 4MHz, unless otherwise noted. NOISE vs CSENSOR Noise (ppm of FSR, rms) NOISE vs CSENSOR 45 Noise (ppm of FSR, rms) 40 CSENSOR Range Range Range Range Range Range Range Range 5 7 (pF) 0 1 2 3 4 6 Range 1 35 0 23.6 7.3 5.2 4.4 4.2 4.0 3.8 3.7 24 30.8 10.4 6.7 5.5 4.9 4.5 4.3 4.1 50 36.3 12.3 8.2 6.5 5.6 5.1 4.8 4.4 20 75 41.3 14.4 8.9 7.2 6.0 5.4 5.1 4.7 15 100 46.1 16.0 10.0 8.0 6.7 5.9 5.4 5.0 150 57.0 18.8 11.9 9.2 7.8 6.8 6.1 5.7 200 68.1 21.7 13.5 10.2 8.6 7.6 6.8 6.4 300 89.3 27.7 16.3 12.5 10.6 9.0 8.1 7.4 500 134.0 38.9 22.4 16.6 13.5 11.7 10.4 9.5 30 25 Range 2 10 5 Range 7 0 0 100 200 300 400 500 CSENSOR (pF) NOISE vs TINT 6 NOISE vs INPUT LEVEL 8 7 Noise (ppm of FSR, rms) Noise (ppm of FSR, rms) CSENSOR = 50pF 5 4 CSENSOR = 0pF 3 2 1 6 CSENSOR = 50pF 5 CSENSOR = 0pF 4 3 2 1 Range 5 Range 5 0 0 0.1 1 10 100 1000 0 10 20 TINT (µs) 50 60 70 80 90 100 2000 CSENSOR = 50pF All Ranges 1500 12 Range 1 10 Range Drift (ppm) Noise (ppm of FSR, rms) 40 RANGE DRIFT vs TEMPERATURE NOISE vs TEMPERATURE 14 Range 3 Range 2 8 6 4 1000 500 0 −500 −1000 Range 7 2 −1500 −2000 0 −40 −15 10 35 Temperature (_C) 6 30 Input Level (% of Full−Scale) 60 85 −40 −15 10 35 Temperature (_ C) 60 85 ""# www.ti.com SBAS255C − JUNE 2004 − REVISED APRIL 2009 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, characterization done with Range 5 (250pC), AVDD = +5V, DVDD = 3V, VREF = +4.096V, Low Power Mode: TINT = 400µs and CLK = 4MHz, unless otherwise noted. IB vs TEMPERATURE OFFSET DRIFT vs TEMPERATURE 10 100 Offset Drift (ppm of FSR) All Ranges IB (pA) 1 0.1 50 0 −50 −100 0.01 25 35 45 55 65 75 25 85 35 45 Temperature (_ C) 55 65 75 85 Temperature (_ C) DIGITAL SUPPLY CURRENT vs TEMPERATURE ANALOG SUPPLY CURRENT vs TEMPERATURE 14 1.2 Low Power−Mode Low−Power Mode DVDD = 5V 12 1.0 Current (mA) Current (mA) 10 8 6 4 0.8 0.6 DVDD = 3V 0.4 0.2 2 0 −40 0 −15 10 35 60 −40 85 Temperature (_C) 35 500 30 Occurences 25 20 15 60 85 Repeated measurement of offset drift over a one minute interval. Range 5 400 300 200 10 100 5 Power per Channel (mW) 16.00 15.75 15.50 15.25 15.00 14.75 14.50 14.25 14.00 13.75 13.50 13.25 13.00 12.75 12.50 12.25 0 12.00 Occurences (%) 35 OFFSET DRIFT OVER TIME HISTOGRAM 600 Low−Power Mode Data collected from multiple lots. 10 Temperature (_C) POWER CONSUMPTION HISTOGRAM 40 −15 0 −1.0 −0.8 −0.6 −0.4 −0.2 0 0.2 0.4 0.6 0.8 1.0 Offset Drift (ppm of FSR/minute) 7 ""# www.ti.com SBAS255C − JUNE 2004 − REVISED APRIL 2009 THEORY OF OPERATION The block diagram of the DDC114 is shown in Figure 1. The device contains four identical input channels that perform the function of current-to-voltage integration followed by a multiplexed A/D conversion. Each input has two integrators so that the current-to-voltage integration can be continuous in time. The output of the eight integrators are switched to two delta-sigma (∆Σ) converters via two four-input multiplexers. With the AVDD VREF DDC114 in the continuous integration mode, the output of the integrators from one side of both of the inputs will be digitized while the other two integrators are in the integration mode, as illustrated in the timing diagram in Figure 2. This integration and A/D conversion process is controlled by the system clock, CLK. The results from side A and side B of each signal input are stored in a serial output shift register. The DVALID output goes low when the shift register contains valid data. DVDD CLK CONV IN1 RANGE0 Dual Switched Integrator ∆Σ RANGE1 Digital Filter Modulator RANGE2 Control TEST CLK_4X IN3 HISPD/LOPWR Dual Switched Integrator RESET FORMAT DCLK IN2 DCLK Dual Switched Integrator ∆Σ Digital Filter Modulator DVALID Digital Input/Output DOUT DOUT IN4 DIN Dual Switched Integrator DIN AGND DGND Figure 1. DDC114 Block Diagram IN1 and IN2, Integrator A Integrate Integrate IN1 and IN2, Integrator B Integrate IN3 and IN4, Integrator A Integrate Integrate Integrate IN3 and IN4, Integrator B Conversion in Progress Integrate IN1B IN2B IN3B IN4B IN1A IN2A IN3A IN4A Integrate IN1B IN2B IN3B IN4B IN1A IN2A IN3A IN4A DVALID Figure 2. Basic Integration and Conversion Timing for the DDC114 (continuous mode) 8 ""# www.ti.com SBAS255C − JUNE 2004 − REVISED APRIL 2009 The digital interface of the DDC114 provides the digital results via a synchronous serial interface consisting of differential data clocks (DCLK and DCLK), a valid data pin (DVALID), differential serial data output pins (DOUT and DOUT), and differential serial data input pins (DIN and DIN). The DDC114 contains only two A/D converters, so the conversion process is interleaved (see Figure 2). The integration and conversion process is fundamentally independent of the data retrieval process. Consequently, the CLK frequency and DCLK frequencies need not be the same. DIN and DIN are only used when multiple converters are cascaded, and otherwise should both be tied to DGND. implement the integration cycle. The timing relationships of all of the switches shown in Figure 3 are illustrated in Figure 4. Figure 4 is used to conceptualize the operation of the integrator input stage of the DDC114 and should not be used as an exact timing tool for design. See Figure 5 for the block diagrams of the reset, integrate, wait and convert states of the integrator section of the DDC114. This internal switching network is controlled externally with the convert pin (CONV), range selection pins (RANGE0−RANGE2), and the system clock (CLK). For the best noise performance, CONV must be synchronized with the rising edge of CLK. It is recommended that CONV toggle within ±10ns of the rising edge of CLK. DEVICE OPERATION The noninverting inputs of the integrators are connected to ground. Consequently, the DDC114 analog ground should be as clean as possible. The range switches, along with the internal and external capacitors (CF), are shown in parallel between the inverting input and output of the operational amplifier. At the beginning of a conversion, the switches SA/D, SINTA, SINTB, SREF1, SREF2, and SRESET are set (see Figure 4). Basic Integration Cycle The topology of the front end of the DDC114 is an analog integrator, as shown in Figure 3. In this diagram, only Input IN1 is shown. This representation of the input stage consists of an operational amplifier, a selectable feedback capacitor network (CF), and several switches that SREF1 VREF 3pF 50pF RANGE2 25pF RANGE1 12.5pF RANGE0 Input Current SINTA SREF2 IN1 SA/D1A SRESET Photodiode ESD Protection Diodes SINTB To Converter Integrator A Integrator B (same as A) Figure 3. Basic Integration Configuration for Input 1, Shown with a 250pC (CF = 62.5pF) Input Range 9 ""# www.ti.com SBAS255C − JUNE 2004 − REVISED APRIL 2009 CONV CLK SINTA SINTB SREF1 SREF2 SRESET Integrate Convert Wait W a it Wait R e se t Convert W a it Configuration of Integrator A R e se t SA/D1A VREF Integrator A Voltage Output Figure 4. Basic Integration Timing Diagram (as shown in Figure 3) SREF1 CF VREF SINT SREF2 CF IN SREF1 VREF To Converter SRESET SA/D SINT SREF2 IN To Converter SRESET SA/D a) Reset Configuration CF SREF1 b) Wait Configuration VREF SINT SREF2 CF IN SRESET SREF1 VREF To Converter SA/D SINT SREF2 IN SRESET c) Integrate Configuration To Converter SA/D d) Convert Configuration Figure 5. Diagrams for the Four Configurations of the Front End Integrators of the DDC114 10 ""# www.ti.com SBAS255C − JUNE 2004 − REVISED APRIL 2009 Voltage Reference At the completion of an A/D conversion, the charge on the integration capacitor (CF) is reset with SREF1 and SRESET (see Figure 4 and Figure 5a). In this manner, the selected capacitor is charged to the reference voltage, VREF. Once the integration capacitor is charged, SREF1 and SRESET are switched so that VREF is no longer connected to the amplifier circuit while it waits to begin integrating (see Figure 5b). With the rising edge of CONV, SINTA closes, which begins the integration of side A. This process puts the integrator stage into its integrate mode (see Figure 5c). The external voltage reference is used to reset the integration capacitors before an integration cycle begins. It is also used by the ∆Σ converter while the converter is measuring the voltage stored on the integrators after an integration cycle ends. During this sampling, the external reference must supply the charge needed by the ∆Σ converter. For an integration time of 400µs, this charge translates to an average VREF current of approximately 75µA. The amount of charge needed by the ∆Σ converter is independent of the integration time; therefore, increasing the integration time lowers the average current. For example, an integration time of 800µs lowers the average VREF current to 37.5µA. Charge from the input signal is collected on the integration capacitor, causing the voltage output of the amplifier to decrease. The falling edge of CONV stops the integration by switching the input signal from side A to side B (SINTA and SINTB). Prior to the falling edge of CONV, the signal on side B was converted by the A/D converter and reset during the time that side A was integrating. With the falling edge of CONV, side B starts integrating the input signal. Now the output voltage of the side A operational amplifier is presented to the input of the ∆Σ A/D converter (see Figure 5d). It is critical that VREF be stable during the different modes of operation (see Figure 5). The ∆Σ converter measures the voltage on the integrator with respect to VREF. Since the integrator capacitors are initially reset to VREF, any drop in VREF from the time the capacitors are reset to the time when the converter measures the integrator output will introduce an offset. It is also important that VREF be stable over longer periods of time because changes in VREF correspond directly to changes in the full-scale range. Finally, VREF should introduce as little additional noise as possible. Integration Capacitors There are eight different capacitors available on-chip for both sides of every channel in the DDC114. These internal capacitors are trimmed in production to achieve the specified performance for range error of the DDC114. The range control pins (RANGE0−RANGE2) change the capacitor value for all four integrators. Consequently, all inputs and both sides of each input will always have the same full-scale range. Table 1 shows the capacitor value selected for each range selection. For these reasons, it is strongly recommended that the external reference source be buffered with an operational amplifier, as shown in Figure 6. In this circuit, the voltage reference is generated by a 4.096V reference. A low-pass filter to reduce noise connects the reference to an operational amplifier configured as a buffer. This amplifier should have low noise and input/output common-mode ranges that support VREF. Following the buffer are capacitors placed close to the DDC114 VREF pin. Even though the circuit in Figure 6 might appear to be unstable because of the large output capacitors, it works well for most operational amplifiers. It is NOT recommended that series resistance be placed in the output lead to improve stability since this can cause a drop in VREF, producing large offsets. Table 1. Range Selection of the DDC114 RANGE2 RANGE1 RANGE0 CF (pF, typ) INPUT RANGE (pC, typ) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 3 12.5 25 37.5 50 62.5 75 87.5 −0.048 to 12 –0.2 to 50 –0.4 to 100 –0.6 to 150 –0.8 to 200 –0.1 to 250 –1.2 to 300 –1.4 to 350 +5V +5V 0.10µF 0.47µF 7 2 1 REF3140 10kΩ 3 OPA350 + + 10µF 3 To VREF Pin 10 of the DDC114 6 2 0.10µF 10µF 0.1µF 4 Figure 6. Recommended External Voltage Reference Circuit for Best Low-Noise Operation with the DDC114 11 ""# www.ti.com SBAS255C − JUNE 2004 − REVISED APRIL 2009 DDC114 Frequency Response Test Mode The frequency response of the DDC114 is set by the front end integrators and is that of a traditional continuous time integrator, as shown in Figure 7. By adjusting TINT, the user can change the 3dB bandwidth and the location of the notches in the response. The frequency response of the ∆Σ converter that follows the front end integrator is of no consequence because the converter samples a held signal from the integrators. That is, the input to the ∆Σ converter is always a DC signal. Since the output of the front end integrators are sampled, aliasing can occur. Whenever the frequency of the input signal exceeds one-half of the sampling rate, the signal will fold back down to lower frequencies. When Test Mode is used, the inputs (IN1, IN2, IN3, and IN4) are disconnected from the DDC114 integrators to enable the user to measure a zero input signal regardless of the current supplied to the inputs. In addition, packets of charge can be transferred to the integrators in 11pC intervals to measure non-zero values. The test mode works with both the continuous and non-continuous modes. The timing diagram for the test mode is shown in Figure 8 with the timing specifications given in Table 2. To enter Test Mode, hold TEST high while CONV transitions. If TEST is held high during the entire integration period, the integrators measure a zero value. This mode can be used to help debug a design or perform diagnostic tests. To apply packets of charge during Test Mode, simply strobe TEST low then high before the next CONV transition. Each rising edge of TEST causes approximately 11pC of charge to be transferred to the integrators. This charge transfer is independent of the integration time. Data retrieval during Test Mode is identical to normal operation. To exit Test Mode, take TEST low and allow several cycles after exiting before using the data. 0 G ain (dB) −10 −20 −30 −40 −50 1 TINT 0.1 TINT 10 TINT 100 TINT Frequency Figure 7. Frequency Response of the DDC114 Test Mode Enabled: Inputs Disconnected Test Mode Disabled Test Mode Disabled Action Integrate B Integrate A 0pC into B 11pC into A 22pC into B 33pC into A Integrate B Integrate A CONV t4 t6 t2 TEST t1 t3 t5 t4 Figure 8. Timing Diagram of the Test Mode of the DDC114 Table 2. Timing for the DDC114 in the Test Mode 12 SYMBOL DESCRIPTION MIN t1 Setup Time for Test Mode Enable 100 TYP MAX UNITS ns t2 Setup Time for Test Mode Disable 100 ns t3 Hold Time for Test Mode Enable 100 ns t4 From Rising Edge of TEST to the Edge of CONV while Test Mode Enabled 1 µs t5 Falling Edge to Rising Edge of TEST 1 µs t6 Rising Edge to Falling Edge of TEST 1 µs ""# www.ti.com SBAS255C − JUNE 2004 − REVISED APRIL 2009 DIGITAL INTERFACE The digital interface of the DDC114 provides the digital results via a synchronous serial interface consisting of differential data clocks (DCLK and DCLK), a valid data pin (DVALID), differential serial data output pins (DOUT and DOUT), and differential serial data input pins (DIN and DIN). The DDC114 contains only two A/D converters, so the conversion process is interleaved (see Figure 2, page 8). The integration and conversion processes are independent of the data retrieval process. Consequently, the CLK frequency and DCLK frequencies need not be the same. DIN and DIN are used when multiple converters are cascaded. Cascading or daisy-chaining greatly simplifies the interconnection and routing of the digital outputs in cases where a large number of converters are needed. Refer to the Cascading Multiple Converters section of this data sheet for more detail. High-Speed and Low-Power Modes (HISPD/LOPWR) The HISPD/LOPWR input controls the power dissipation and in turn the maximum allowable CLK frequency and data rate, as shown in Table 4. With HISPD/LOPWR = 0, the Low-Power Mode is selected with a typical 13.5mW/ channel and a maximum data rate of 2.5kSPS. Setting HISPD/LOPWR = 1 selects the High-Speed Mode, which supports a maximum data rate of 3.125kSPS with a corresponding typical power of 18.0mW/channel. Table 4. HISPD/LOPWR Pin Operation HISPD/ LOPWR MODE TYPICAL POWER/ CHANNEL MAXIMUM CLK FREQUENCY (CLK_4X = 0) MAXIMUM DATA RATE 0 Low Power 13.5mW/ch 4.0MHz 2.5kSPS 1 High Speed 18.0mW/ch 4.8MHz 3.125kSPS Data Valid (DVALID) Complementary Signals (DCLK, DIN, and DOUT) The DDC114 provides optional complementary inputs (DCLK, DIN) to help reduce digital coupling to the analog inputs. If using these inputs, connect a complementary signal to each. If these inputs are not connected on the DDC114, they should be tied to DGND. DOUT is a complementary output designed to drive DIN. If not using DOUT, leave it floating. System and Data Clocks (CLK and CONV) The system clock is supplied to CLK and the data clock is supplied to DCLK. Make sure the clock signals are clean—avoid overshoot or ringing. For best performance, generate both clocks from the same clock source. DCLK should be disabled by taking it low after the data has been shifted out or while CONV is transitioning. When using multiple DDC114s, pay close attention to the DCLK distribution on the printed circuit board (PCB). In particular, make sure to minimize skew in the DCLK signal as this can lead to timing violations in the serial interface specifications. See the Cascading Multiple Converters section for more details. System Clock Divider (CLK_4X) The DVALID signal indicates that data is ready. Data retrieval may begin after DVALID goes low. This signal is generated using an internal clock divided down from the system clock CLK. The phase relationship between this internal clock and CLK is set when power is first applied, and is random. Since the user must synchronize CONV with CLK, the DVALID signal will have a random phase relationship with CONV. This uncertainty is ±1/fCLK. Polling DVALID eliminates any concern about this relationship. If data read back is timed from CONV, wait the maximum value of t7 or t8 to insure data is valid. Reset (RESET) The DDC114 is reset asynchronously by taking the RESET input low, as shown in Figure 9. Make sure the reset pulse is at least 50µs wide. After resetting the DDC114, wait at least four conversions before using the data. It is very important to make sure the RESET is glitch free to avoid unintended resets. The RESET pin is used during power-up; see the Power-Up Sequence section for more details. > 50µs RESET The CLK_4X input enables an internal divider on the system clock as shown in Table 3. When CLK_4X = 1, the system clock is divided by four. This allows a 4X faster system clock, which in turn provides a finer quantization of the integration time as the CONV signal needs to be synchronized with the system clock for the best performance. Table 3. CLK_4X Pin Operation CLK_4X PIN CLK DIVIDER VALUE CLK FREQUENCY INTERNAL CLOCK FREQUENCY 0 1 4MHz 4MHz 1 4 16MHz 4MHz Figure 9. Reset Timing Convert (CONV) CONV controls the integration time (TINT). For optimum analog performance, make sure CONV is synchronized to CLK. This recommendation implies that while SPEED is low, TINT needs to be adjusted in steps of 250ns if CLK_4X is low and CLK = 4MHz. If CLK_4X is high and CLK = 16MHz, this allows TINT to be adjusted in steps of 62.5ns. 13 ""# www.ti.com SBAS255C − JUNE 2004 − REVISED APRIL 2009 Conversion Rate The conversion rate of the DDC114 is set by a combination of the integration time (determined by the user) and the speed of the A/D conversion process. The A/D conversion time is primarily a function of the system clock (CLK) speed. One A/D conversion cycle encompasses the conversion of two signals (one side of each dual integrator feeding the modulator) and the reset time for each of the integrators involved in the two conversions. In most situations, the A/D conversion time is shorter than the integration time. If this condition exists, the DDC114 will operate in continuous mode. When the DDC114 is in continuous mode, the sensor output is continuously integrated by one of the two sides of each input. In the event that the A/D conversion takes longer than the integration time, the DDC114 will switch into a non-continuous mode. In non-continuous mode, the A/D converter is not able to keep pace with the speed of the integration process. Consequently, the integration process is periodically halted until the digitizing process catches up. These two basic modes of operation for the DDC114—continuous and non-continuous modes—are described below. Continuous and Non-Continuous Operational Modes Figure 10 shows the state diagram of the DDC114. In all, there are eight states. Table 5 provides a brief explanation of each state. Table 5. State Descriptions STATE MODE DESCRIPTION 1 Ncont Complete m/r/az of side A, then side B (if previous state is state 4). Initial power-up state when CONV is initially held HIGH. 2 Ncont Prepare side A for integration. 3 Cont Integrate on side A. 4 Cont Integrate on side B; m/r/az on side A. 5 Cont Integrate on side A; m/r/az on side B. 6 Cont Integrate on side B. 7 Ncont Prepare side B for integration. 8 Ncont Complete m/r/az of side B, then side A (if previous state is state 5). Initial power-up state when CONV is initially held LOW. Four signals are used to control progression around the state diagram: CONV, mbsy, and their complements. The state machine uses the level as opposed to the edges of CONV to control the progression. mbsy is an internallygenerated signal not available to the user. It is active whenever a measurement/reset/auto-zero (m/r/az) cycle is in progress. 14 CONV|mbsy 1 2 CONV × mbsy Ncont Ncont CONV 3 Int A Cont CONV × mbsy CONV 4 5 CONV × mbsy Int B/Meas A Cont CONV × mbsy Int A/Meas B Cont CONV 6 CONV × mbsy Int B Cont CONV 7 Ncont 8 CONV × mbsy Ncont CONV|mbsy Figure 10. Integrate/Measure State Diagram During cont mode, mbsy is not active when CONV toggles. The non-integrating side is always ready to begin integrating when the other side finishes its integration. Consequently, monitoring the current status of CONV is all that is needed to know the current state. Cont mode operation corresponds to states 3-6. Two of the states, 3 and 6, only perform an integration (no m/r/az cycle). mbsy becomes important when operating in the ncont mode, states 1, 2, 7, and 8. Whenever CONV is toggled while mbsy is active, the DDC114 will enter or remain in either ncont state 1 (or 8). After mbsy goes inactive, state 2 (or 7) is entered. This state prepares the appropriate side for integration. In ncont states, the inputs to the DDC114 are grounded. One interesting observation from the state diagram is that the integrations always alternate between sides A and B. This relationship holds for any CONV pattern and is independent of the mode. States 2 and 7 insure this relationship during ncont mode. When power is first applied to the DDC114, the beginning state is either 1 or 8, depending on the initial level of CONV. For CONV held high at power-up, the beginning state is 1. Conversely, for CONV held low at power-up, the beginning state is 8. In general, there is a symmetry in the state diagram between states 1-8, 2-7, 3-6, and 4-5. Inverting CONV results in the states progressing through their symmetrical match. ""# www.ti.com SBAS255C − JUNE 2004 − REVISED APRIL 2009 TIMING EXAMPLES mbsy is shown next. Finally, DVALID is given. As described in the data sheet, DVALID goes active low when data is ready to be retrieved from the DDC114. It stays low until DCLK is taken high and then back low by the user. The text below the DVALID pulse indicates the side of the data available to be read, and arrows help match the data to the corresponding integration. The signals illustrated in Figure 11 through Figure 19 are drawn at approximately the same scale. Cont Mode A few timing diagrams help illustrate the operation of the state machine. These diagrams are shown in Figure 11 through Figure 19. Table 6 gives generalized timing specifications in units of CLK periods for CLK_4X = 0. If CLK_4X = 1, these values increase by a factor of four because of the internal clock divider. Values (in µs) for Table 6 can be easily found for a given CLK. For example, if CLK = 4MHz, then a CLK period = 0.25µs. t6 in Table 6 would then be 367.50 ± 0.125µs. In Figure 11, the first state is ncont state 8. The DDC114 always powers up in the ncont mode. In this case, the first state is 8 because CONV is initially low. After the first two states, cont mode operation is reached and the states begin toggling between 4 and 5. From now on, the input is being continuously integrated, either on side A or side B. The time needed for the m/r/az cycle, or t6, is the same time that determines the boundary between the cont and ncont modes described earlier in the Overview section. DVALID goes low after CONV toggles in time t7, indicating that data is ready to be retrieved. As shown in Figure 11, there are two values for t6 and t7. The reason for this is discussed in the Special Considerations section. Table 6. Timing Specifications Generalized in CLK Periods DESCRIPTION VALUE (CLK periods with CLK_4X = 0) t6 Cont mode m/r/az cycle 1470 ± 0.5 t7 Cont mode data ready 1380 ± 0.5 t8 1st ncont mode data ready 1379 ± 1 t9 2nd ncont mode data ready 1450 t10 Ncont mode m/r/az cycle 2901 ± 1 SYMBOL Figure 11 shows a few integration cycles beginning with initial power-up for a cont mode example. The top signal is CONV and is supplied by the user. The next line indicates the current state in the state diagram. The following two traces show when integrations and measurement cycles are underway. The internal signal See Figure 12 for the timing diagram of the internal operations occurring during continuous mode operation. Table 7 gives the timing specifications in the continuous mode. CONV State 8 Integration Status 7 6 5 4 5 Integrate B Integrate A Integrate B Integrate A m/r/az Status m/r/az B m/r/az A m/r/az B t6 mbsy DVALID t7 t=0 Power−Up Side B Data Side A Data Side B Data SYMBOL DESCRIPTION VALUE (CLK = 4MHz, CLK_4X = 0) VALUE (CLK = 4.8MHz, CLK_4X = 0) t6 Cont Mode m/r/az Cycle 367.50 ± 0.125µs 306.25 ± 0.104µs t7 Cont Mode Data Ready 345.00 ± 0.125µs 287.5 ± 0.104µs Figure 11. Continuous Mode Timing 15 ""# www.ti.com SBAS255C − JUNE 2004 − REVISED APRIL 2009 End Integration Side A Start Integration Side B End Integration Side B Start Integration Side A TINT CONV TINT Side A A/D Conversion Input 1 and 2 (Internal) End Integration Side A Start Integration Side B t14 Side B Side A t 12 Side A A/D Conversion Input 3 and 4 (Internal) t 13 Side B t12 t13 t 14 DVALID Side A Data Ready Side B Data Ready Figure 12. Timing Diagram of the Internal Operation in Continuous Mode of the DDC114 Table 7. Timing for the Internal Operation in Continuous Mode CLK = 4MHz, CLK_4X = 0 SYMBOL TINT 16 DESCRIPTION MIN Integration Period (continuous mode) 400 TYP CLK = 4.8MHz, CLK_4X = 0 MAX MIN 1,000,000 320 TYP MAX UNITS 1,000,000 µs 169.5 141.25 µs A/D Conversion Reset Time (internally controlled) 4 3.333 µs Integrator and A/D Conversion Reset Time (internally controlled) 23 19.167 µs t12 A/D Conversion Time (internally controlled) t13 t14 ""# www.ti.com SBAS255C − JUNE 2004 − REVISED APRIL 2009 Ncont Mode Non-continuous (ncont) mode of operation is intended for ranges 1 to 7. It is not recommended to use Range 0 when operating in non-continuous mode. Figure 13 illustrates operation in ncont mode. The integrations come in pairs (that is, sides A/B or sides B/A) followed by a time during which no integrations occur. During that time, the previous integrations are being measured, reset and auto-zeroed. Before the DDC114 can advance to states 3 or 6, both sides A and B must be finished with the m/r/az cycle, which takes time t10. When the m/r/az cycles are completed, time t11 is needed to prepare the next side for integration. This time is required for ncont mode because the m/r/az cycle of ncont mode is slightly different from that of cont mode. After the first integration ends, DVALID goes low in time t8. This time is the same as in cont mode. The second data will be ready in time t9 after the first data is ready. One result of the naming convention used in this data sheet is that when the DDC114 is operating in ncont mode, it passes through both ncont mode states and cont mode states. For example, in Figure 13, the state pattern is 3, 4, 1, 2, 3, 4, 1, 2, 3, 4 ... where 3 and 4 are cont mode states. Ncont mode, by definition, means that for some portion of the time, neither side A nor B is integrating. States that perform an integration are labeled cont mode states, while those that do not are called ncont mode states. Since integrations are performed in ncont mode, just not continuously, some cont mode states must be used in an ncont mode state pattern. CONV State 3 4 1 2 3 4 1 2 t 11 Integration Status m/r/az Status Int A Int B Int A m/r/az A Int B m/r/az A m/r/az B m/r/az B t 10 mbsy t9 DVALID t8 Side A Data Side B Data Side A Data Side B Data SYMBOL DESCRIPTION VALUE (CLK = 4MHz, CLK_4X = 0) VALUE (CLK = 4.8MHz, CLK_4X = 0) t8 t9 t10 t11 1st ncont Mode Data Ready 2nd ncont Mode Data Ready ncont Mode m/r/az Cycle Prepare Side for Integration 344.75 ± 0.25µs 362.5µs 725.25 ± 0.25µs ≥ 18µs 287.292 ± 0.208µs 302.083µs 604.375 ± 0.208µs ≥ 15µs Figure 13. Non-Continuous Mode Timing 17 ""# www.ti.com SBAS255C − JUNE 2004 − REVISED APRIL 2009 Start Integration Side A Start Integration Side A End Integration Side A Start Integration Side B End Integration Side B Release State Wait State TINT t17 CONV TINT t16 A/D Conversion Input 1 and 2 t12 A/D Conversion Input 3 and 4 t12 t13 t15 DVALID Side A Data Ready Side B Data Ready Figure 14. Conversion Detail for the Internal Operation of Non-Continuous Mode with Side A Integrated First Table 8. Internal Timing for the DDC114 in Non-Continuous Mode CLK = 4MHz, CLK_4X = 0 SYMBOL TINT DESCRIPTION MIN Integration Time (non-continuous mode) TYP 400 t12 A/D Conversion Time (internally controlled) t13 A/D Conversion Reset Time (internally controlled) t15 Integrator and A/D Conversion Reset Time (internally controlled) t16 Total A/D Conversion and Reset Time (internally controlled) t17 Release Time CLK = 4.8MHz, CLK_4X = 0 MAX MIN 1,000,000 320 TYP MAX 1,000,000 UNITS µs 169.5 141.25 µs 4 3.333 µs 19.5 16.25 µs 604.375 ± 0.208 µs 725.25 ± 0.25 18 µs 15 Start Integration Side B Start Integration Side B End Integration Side B Start Integration Side A End Integration Side A Release State Wait State CONV TINT TINT t 17 t16 A/D Conversion Inputs 1 and 2 t12 A/D Conversion Inputs 3 and 4 t 12 t13 t 15 DVALID Side B Data Ready Side A Data Ready Figure 15. Internal Operation Timing Diagram of Non-Continuous Mode with Side B Integrated First 18 ""# www.ti.com SBAS255C − JUNE 2004 − REVISED APRIL 2009 CONV signal with TINT = 512 CLK periods. Care must be exercised when using a square wave to generate CONV. There are certain integration times that must be avoided since they produce very short intervals for state 2 (or state 7 if CONV is inverted). As seen in the state diagram, the state progresses from 2 to 3 as soon as CONV is high. The state machine does not insure that the duration of state 2 is long enough to properly prepare the next side for integration (t11). This must be done by the user with proper timing of CONV. For example, if CONV is a square wave with TINT = 970 CLK periods, state 2 will only be 9 CLK periods long; therefore, t11 will not be met. Looking at the state diagram, one can see that the CONV pattern needed to generate a given state progression is not unique. Upon entering states 1 or 8, the DDC114 remains in those states until mbsy goes low, independent of CONV. As long as the m/r/az cycle is underway, the state machine ignores CONV (see Figure 10, page 14). The top two signals in Figure 16 are different CONV patterns that produce the same state. This feature allows flexibility in generating ncont mode CONV patterns. For example, the DDC114 Evaluation Fixture operates in ncont mode by generating a square wave with pulse width < t6. Figure 17 illustrates operation in ncont mode using a 50% duty cycle CONV1 CONV2 mbsy State 3 4 1 2 3 4 1 2 Figure 16. Equivalent CONV Signals in Non-Continuous Mode CONV State Integration Status 3 4 Int A Int B 1 2 3 4 Int A Int B 1 mbsy DVALID Side A Data Side B Data Side A Data Figure 17. Non-Continuous Mode Timing with a 50% Duty Cycle CONV Signal 19 ""# www.ti.com SBAS255C − JUNE 2004 − REVISED APRIL 2009 Changing Between Modes Changing from ncont to cont mode occurs when TINT is increased so that TINT is always ≥ t6 as shown in Figure 19 (see Figure 14 and Table 8, page 18). With a longer TINT, the m/r/az cycle has enough time to finish before the next integration begins and continuous integration of the input signal is possible. For the special case of the very first integration when changing to cont mode, TINT can be < t6. This is allowed because there is no simultaneous m/r/az cycle on the side B during state 3—there is no need to wait for it to finish before ending the integration on side A. Changing from cont to ncont mode occurs whenever TINT < t6. Figure 18 shows an example of this transition. In this figure, cont mode is entered when the integration on side A is completed before the m/r/az cycle on side B is complete. The DDC114 completes the measurement on sides B and A during states 8 and 7 with the input signal shorted to ground. Ncont integration begins with state 6. CONV State 5 4 5 8 Continuous Integration Status m/r/az Status Integrate A Integrate B m/r/az B m/r/az A 7 6 5 Int B Int A Non−Continuous Int A m/r/az B m/r/az A m/r/az B mbsy Figure 18. Changing from Continuous Mode to Non-Continuous Mode CONV State 3 4 1 2 Non−Continuous Integration Status m/r/az Status Int A Int B m/r/az A 3 Continuous Integrate A m/r/az B 4 Integrate B m/r/az A mbsy Figure 19. Changing from Non-Continuous Mode to Continuous Mode 20 ""# www.ti.com SBAS255C − JUNE 2004 − REVISED APRIL 2009 DATA FORMAT (FORMAT) DATA RETRIEVAL The serial output data is provided in an offset binary code as shown in Table 9. The digital input pin FORMAT selects how many bits are used in the output word. When FORMAT is high (1), 20 bits are used. When FORMAT is low (0), the lower 4 bits are truncated so that only 16 bits are used. Note that the LSB size is 16 times bigger when FORMAT = 0. An offset is included in the output to allow slightly negative inputs, from board leakages for example, from clipping the reading. This offset is approximately 0.4% of the positive full−scale. Table 9. Ideal Output Code(1) vs Input Signal INPUT SIGNAL IDEAL OUTPUT CODE FORMAT = HIGH (1) IDEAL OUTPUT CODE FORMAT = LOW (0) ≥ 100% FS 1111 1111 1111 1111 1111 1111 1111 1111 1111 0.001531% FS 0000 0001 0000 0001 0000 0000 0001 0000 0001 0.001436% FS 0000 0001 0000 0000 1111 0000 0001 0000 0000 0.000191% FS 0000 0001 0000 0000 0010 0000 0001 0000 0000 0.000096% FS 0000 0001 0000 0000 0001 0000 0001 0000 0000 0% FS 0000 0001 0000 0000 0000 0000 0001 0000 0000 −0.3955% FS 0000 0000 0000 0000 0000 0000 0000 0000 0000 In both the continuous and non-continuous modes of operation, the data from the last conversion is available for retrieval on the falling edge of DVALID (see Figure 20 and Table 10, on page 22). Data is shifted out on the falling edge of the data clock, DCLK. Make sure not to retrieve data while CONV changes as this can introduce noise. Stop activity on DCLK at least 10µs before or after a CONV transition. Setting the FORMAT pin = 0 (16-bit output word) reduces the time needed to retrieve data by 20%, since there are fewer bits to shift out. This time reduction can be useful in multichannel systems requiring only 16 bits of resolution. (1) Excludes the effects of noise, INL, offset, and gain errors. CLK t18 DVALID t20 t20 t19 DCLK t21 DOUT Input 4 MSB Input 4 LSB Input 3 MSB Input 3 LSB Input 2 MSB Input 2 LSB Input 1 MSB Input 1 LSB Input 4 MSB Figure 20. Digital Interface Timing Diagram for Data Retrieval From a Single DDC114 Table 10. Timing for the DDC114 Data Retrieval CLK = 4MHz, CLK_4X = 0 SYMBOL DESCRIPTION MIN t18 Propagation Delay from Falling Edge of CLK to DVALID LOW 5 t19 Propagation Delay from Falling Edge of DCLK to DVALID HIGH 5 t20 Hold Time that DOUT is Valid Before the Falling Edge of DVALID t21 Hold Time that DOUT is Valid After Falling Edge of DCLK t21A(1) Propagation Delay from Falling Edge of DCLK to Valid DOUT TYP MAX CLK = 4.8MHz, CLK_4X = 0 MIN TYP MAX 5 ns 5 1.75 ns µs 1.458 5 5 10 UNITS ns 10 ns (1) With a maximum load of one DDC114 (4pF typical) with an additional load of 5pF. 21 ""# www.ti.com SBAS255C − JUNE 2004 − REVISED APRIL 2009 DOUT can be used with DIN to daisy-chain several DDC114 devices together to minimize wiring. In this mode of operation, the serial data output is shifted through multiple DDC114s, as illustrated in Figure 21. SPECIAL CONSIDERATIONS Cascading Multiple Converters Multiple DDC114 units can be connected in serial configuration, as illustrated in Figure 21. See Figure 22 for the timing diagram when the DIN input is used to daisy-chain several devices. Table 11 gives the timing specification for data retrieval using DIN. DOUT Data Retrievel Outputs DDC114 DCLK DVALID DCLK DCLK DIN DDC114 IN4 IN3 IN2 IN1 DIN IN1 DOUT IN2 DOUT DIN IN3 DIN IN4 DDC114 IN1 DOUT IN2 DOUT DIN IN3 DIN IN4 DOUT DCLK DVALID DCLK DCLK DVALID Data Clock Sensor A B C D E F G H I J K L Figure 21. Daisy-Chained DDC114s CLK t18 DVALID t20 t 20 t19 DCLK t21 t 23 t22 DIN Input A MSB DOUT Input A LSB Input B MSB Input F LSB Input G MSB Input K LSB Input L MSB Input L LSB Input A MSB Figure 22. Timing Diagram When Using the DIN Function of the DDC114 Table 11. Timing for the DDC114 Data Retrieval Using DIN 22 SYMBOL DESCRIPTION MIN TYP MAX UNITS t22 Set-Up Time From DIN to Falling Edge of DCLK 5 ns t23 Hold Time For DIN After Falling Edge of DCLK 4 ns ""# www.ti.com SBAS255C − JUNE 2004 − REVISED APRIL 2009 RETRIEVAL BEFORE CONV TOGGLES (CONTINUOUS MODE) NOTE: 64τDCLK is used for FORMAT = low. where τDCLK is the period of the data clock. For example, if TINT = 1000µs and DCLK = 10MHz, the maximum number of DDC114s (FORMAT = high) is shown in Equation 2: Data retrieval before CONV toggles is the most straightforward method. Data retrieval begins soon after DVALID goes low and finishes before CONV toggles; as shown in Figure 23. For best performance, data retrieval must stop t28 before CONV toggles. This method is most appropriate for longer integration times. The maximum time available for readback is TINT – t27 – t28. For DCLK = 10MHz and CLK = 4MHz, the maximum number of DDC114s that can be daisy-chained together (FORMAT = high) is calculated by Equation 1: T INT * 355.125ms 80tDCLK CONV DVALID 1000ms * 355.125ms + 80.60 ³ 80 DDC114s (80)(100ns) (1) TINT TINT t27 t28 DCLK … … DOUT … … Side B Data Side A Data CLK = 4MHz, CLK_4X = 0 SYMBOL (2) (or 100 for FORMAT = low). CLK = 4.8MHz, CLK_4X = 0 DESCRIPTION UNITS MIN TYP MAX MIN 345.00 ± 0.125 t27 Cont Mode Data Ready t28 Data Retrieval Shutdown Before Edge of CONV 10 TYP 287.5 ± 0.104 10 MAX µs µs Figure 23. Readback Before CONV Toggles 23 ""# www.ti.com SBAS255C − JUNE 2004 − REVISED APRIL 2009 RETRIEVAL AFTER CONV TOGGLES (CONTINUOUS MODE) of DDC114s that can be daisy-chained together (FORMAT = high) is calculated by Equation 3: For shorter integration times, more time is available if data retrieval begins after CONV toggles and ends before the new data is ready. Data retrieval must wait t29 after CONV toggles before beginning. See Figure 24 for an example of this. The maximum time available for retrieval is t27 − t29 – t26 (344.875µs – 10µs – 1.75µs for CLK = 4MHz), regardless of TINT. The maximum number TINT CONV 333.125ms 80tDCLK (3) NOTE: 64τDCLK is used for FORMAT = low. For DCLK = 10MHz, the maximum number of DDC114s is 41 (or 52 for FORMAT = low). TINT TINT DVALID t27 t29 DCLK … DOUT t26 … … … … … Side A Data Side B Data Side A Data CLK = 4MHz, CLK_4X = 0 SYMBOL DESCRIPTION MIN t26 Hold Time that DOUT is Valid Before Falling Edge of DVALID t27 Cont Mode Data Ready t29 Data Retrieval Start-Up After Edge of CONV TYP MAX MIN TYP MAX UNITS 1.75 1.458 µs 345.00 ± 0.125 287.5 ± 0.104 µs 10 Figure 24. Readback After CONV Toggles 24 CLK = 4.8MHz, CLK_4X = 0 10 µs ""# www.ti.com SBAS255C − JUNE 2004 − REVISED APRIL 2009 RETRIEVAL BEFORE AND AFTER CONV TOGGLES (CONTINUOUS MODE) RETRIEVAL: NONCONTINUOUS MODE Retrieving in noncontinuous mode is slightly different than compared with the continuous mode. As illustrated in Figure 26, DVALID goes low in time t30 after the first integration completes. If TINT is shorter than this time, all of t31 is available to retrieve data before the other side data is ready. For TINT > t30, the first integration data is ready before the second integration completes. Data retrieval must be delayed until the second integration completes, leaving less time available for retrieval. The time available is t31 – (TINT – t30). The second integration data must be retrieved before the next round of integration begins. This time is highly dependent on the pattern used to generate CONV. As with the continuous mode, data retrieval must halt before and after CONV toggles (t28, t29) and be completed before new data is ready (t26). For the absolute maximum time for data retrieval, data can be retrieved before and after CONV toggles. Nearly all of TINT is available for data retrieval. Figure 25 illustrates how this is done by combining the two previous methods. You must pause the retrieval during CONV toggling to prevent digital noise, as discussed previously, and finish before the next data is ready. The maximum number of DDC114s that can be daisy-chained together (FORMAT = high) is: T INT * 20ms * 1.75ms 80t DCLK NOTE: 64τDCLK is used for FORMAT = low. For TINT = 400µs and DCLK = 10MHz, the maximum number of DDC114s is 47 (or 59 for FORMAT = low). CONV TINT TINT t29 DVALID t26 t28 DCLK DOUT TINT … … … … … … … … … … … … Side B Data SYMBOL t26 t28 t29 Side A Data CLK = 4MHZ, CLK_4X = 0 DESCRIPTION MIN Hold Time that DOUT is Valid Before Falling Edge of DVALID Data Retrieval Shutdown Before Edge of CONV Data Retrieval Start-Up After Edge of CONV TYP CLK = 4.8MHZ, CLK_4X = 0 MAX MIN 1.75 TYP MAX 1.458 10 10 10 10 UNITS µs µs µs Figure 25. Readback Before and After CONV Toggles T IN T CONV TIN T T IN T T IN T DVALID t3 0 SYMBOL t30 t31 t3 1 DCLK … … D OUT … … Side A Data Side B Data DESCRIPTION 1st ncont Mode Data Ready 2nd ncont Mode Data Ready CLK = 4MHz, CLK_4X = 0 MIN TYP MAX CLK = 4.8MHz, CLK_4X = 0 MIN TYP MAX UNITS 344.75 ± 0.25 362.500 287.292 ± 0.208 302.083 µs µs Figure 26. Readback in Non-Continuous Mode 25 ""# www.ti.com SBAS255C − JUNE 2004 − REVISED APRIL 2009 POWER-UP SEQUENCING Prior to power-up, all digital and analog inputs must be low. After the power supplies have settled, release RESET after time t32. (See Figure 28 and Table 12.) Wait for time t33 to begin applying the digital signals CONV and CLK. The first CONV pulse will complete the release state and begin integration. VA AVDD 10µF DDC114 VD DVDD 10µF LAYOUT AGND 0.1µF DGND 0.1µF POWER SUPPLIES AND GROUNDING Separate Supplies Both AVDD and DVDD should be as quiet as possible. It is particularly important to eliminate noise from AVDD that is non-synchronous with the DDC114 operation. Figure 27 illustrates two acceptable ways to supply power to the DDC114. The first case shows two separate +5V supplies for AVDD and DVDD. In this case, each +5V supply of the DDC114 should be bypassed with 10µF solid tantalum capacitors and 0.1µF ceramic capacitors. The second case shows the DVDD power supply derived from the AVDD supply with a < 10Ω isolation resistor. In both cases, the 0.1µF capacitors should be placed as close to the DDC114 package as possible. It is recommended that both the analog and digital grounds (AGND and DGND) be connected to a single ground plane on the printed circuit board (PCB). +5V AVDD 10µF AGND 0.1µF DDC114 < 10Ω DVDD DGND 0.1µF Single +5V Supply THERMAL PAD Figure 27. Power-Supply Connection Options It is strongly recommended that the thermal pad on the DDC114 be connected to ground on the PCB. No PCB traces should be routed underneath the thermal pad. AVDD DVDD t32 Release State RESET Start Integration t 33 CONV t34 CLK … Integrate Side B Figure 28. Timing Diagram at Power-Up of the DDC114 Table 12. Timing for the DDC114 Power-Up Sequence 26 SYMBOL DESCRIPTION MIN t32 Power Supplies Settled to RESET Release 10 TYP MAX UNITS ms t33 RESET Release to CONV, CLK Begin 50 µs t34 First CONV Pulse Width 50 µs ""# www.ti.com SBAS255C − JUNE 2004 − REVISED APRIL 2009 Shielding Analog Signal Paths currents between the PCB traces can exceed the input bias current of the DDC114 if shielding is not implemented. Figure 29 illustrates an acceptable approach to this problem. A PC ground plane is placed around the inputs of the DDC114. This shield helps minimize coupled noise into the input pins. As with any precision circuit, careful PCB layout ensures the best performance. It is essential to make short, direct interconnections and avoid stray wiring capacitance—particularly at the analog input pins. Digital signals should be kept as far from the analog input signals as possible on the PCB. This approach reduces leakage effects by surrounding these sensitive pins with a low impedance analog ground. Leakage currents from other portions of the circuit will flow harmlessly to the low impedance analog ground rather than into the analog input stage of the DDC114. Input shielding practices should be taken into consideration when designing the circuit layout for the DDC114. The inputs to the DDC114 are high impedance and extremely sensitive to extraneous noise. Leakage Digital I/O and Digital Power 48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 31 DDC114 7 30 8 29 9 28 10 27 11 26 12 25 13 14 15 16 17 Analog Ground 18 19 20 21 22 23 Analog Ground IN4 24 Analog Ground IN2 IN3 Analog Power IN1 Analog Ground Figure 29. Recommended Shield for DDC114 Layout Design 27 www.ti.com SBAS255C − JUNE 2004 − REVISED APRIL 2009 Revision History DATE REV 4/09 C PAGE SECTION 1 Front Page 9 Theory of Operation DESCRIPTION Updated front page appearance. Changed last sentence of first paragraph on page 9. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. 28 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) DDC114IRTCR ACTIVE VQFN RTC 48 2500 RoHS & Green SN Level-3-260C-168 HR -40 to 85 DDC114 DDC114IRTCT ACTIVE VQFN RTC 48 250 RoHS & Green SN Level-3-260C-168 HR -40 to 85 DDC114 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of