DDC232CGXGR

DDC232 www.ti.com SBAS331D – AUGUST 2004 – REVISED APRIL 2010 32-Channel, Current-Input Analog-to-Digital Converter Check for Samples: DDC232 FEATURES 1 • 2 • • • • • • • • Single-Chip Solution to Directly Measure 32 Low-Level Currents High-Precision, True Integrating Function Integral Linearity: ±0.025% of Reading ±1.0ppm of FSR Very Low Noise: 5.3ppm of FSR Low Power: 7mW/channel Adjustable Full-Scale Range Adjustable Speed – Data Rate up to 6kSPS – Integration Times as low as 166.5ms Daisy-Chainable Serial Interface In-Package Bypass Capacitors Simplify PCB Design APPLICATIONS • • • CT Scanner DAS Photodiode Sensors X-Ray Detection Systems The DDC232 uses a +5V analog supply and a +2.7V to +3.6V digital supply. Operating over the temperature range of 0°C to +70°C, the DDC232 BGA-64 package is offered in two versions: the DDC232C for low-power applications, and the DDC232CK when higher speeds are required. AVDD VREF DVDD 0.1mF 0.1mF 0.1mF IN1 Dual Switched Integrator CLK DS ADC IN2 Dual Switched Integrator CONV Configuration and Control DIN_CFG CLK_CFG RESET IN3 Dual Switched Integrator DS ADC IN4 Dual Switched Integrator IN29 Dual Switched Integrator DVALID DESCRIPTION The DDC232 is a 20-bit, 32-channel, current-input analog-to-digital (A/D) converter. It combines both current-to-voltage and A/D conversion so that 32 separate low-level current output devices, such as photodiodes, can be directly connected to its inputs and digitized. For each of the 32 inputs, the DDC232 provides a dual-switched integrator front-end. This configuration allows for continuous current integration: while one integrator is being digitized by the onboard A/D converter, the other is integrating the input current. Adjustable integration times range from 166ms to 1s, allowing currents from fAs to mAs to be continuously measured with outstanding precision. The DDC232 has a serial interface designed for daisy-chaining in multi-device systems. Simply connect the output of one device to the input of the next to create the chain. Common clocking feeds all the devices in the chain so that the digital overhead in a multi-DDC232 system is minimal. DCLK Serial Interface DS ADC IN30 Dual Switched Integrator IN31 Dual Switched Integrator DOUT DIN DS ADC IN32 Dual Switched Integrator AGND DGND Protected by US Patent #5841310 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2010, Texas Instruments Incorporated DDC232 SBAS331D – AUGUST 2004 – REVISED APRIL 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. DEVICE FAMILY COMPARISON (1) MAXIMUM DATA RATE POWER/CHANNEL 1000pC (1) 20kSPS 40mW SO-28 2 1000pC (1) 3.3kSPS 40mW TQFP-32 4 350pC 3.3kSPS 13mW QFN-48 DDC118 8 350pC 3.3kSPS 13mW QFN-48 DDC316 16 12pC 100kSPS 28mW BGA-64 DDC232C 32 350pC 3.1kSPS 7mW BGA-64 DDC232CK 32 350pC 6.2kSPS 10mW BGA-64 PRODUCT # OF CHANNELS FULL-SCALE DDC112 2 DDC112K DDC114 PACKAGELEAD Using external integration capacitors. PACKAGE/ORDERING INFORMATION For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the device product folder on www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) AVDD to AGND –0.3V to +6V DVDD to DGND –0.3V to +3.6V AGND to DGND ±0.2V VREF Input to AGND 2.0V to AVDD + 0.3V Analog Input to AGND –0.3V to +0.7V Digital Input Voltage to DGND –0.3V to DVDD + 0.3V Digital Output Voltage to DGND –0.3V to AVDD + 0.3V Operating Temperature 0°C to +70°C Storage Temperature –60°C to +150°C Junction Temperature (TJ) (1) 2 +150°C Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): DDC232 DDC232 www.ti.com SBAS331D – AUGUST 2004 – REVISED APRIL 2010 ELECTRICAL CHARACTERISTICS At TA = +25°C, AVDD = +5V, DVDD = +3.0V, VREF = +4.096V, tINT = 333ms for DDC232C or 166ms for DDC232CK, Range 7, and continuous mode operation, unless otherwise noted. DDC232C PARAMETER TEST CONDITIONS MIN TYP DDC232CK MAX MIN TYP MAX UNIT ANALOG INPUT RANGE Range 0 12.5 12.5 pC Range 1 45 50 55 45 50 55 pC Range 2 90 100 110 90 100 110 pC Range 3 135 150 165 135 150 165 pC Range 4 180 200 220 180 200 220 pC Range 5 225 250 275 225 250 275 pC Range 6 270 300 330 270 300 330 pC Range 7 315 350 385 315 350 385 pC Negative Full-Scale Range –0.4% of Positive Full-Scale Range –0.4% of Positive Full-Scale Range pC 6 DYNAMIC CHARACTERISTICS Data Rate Integration Time, tINT System Clock (CLK) 3 3.125 Continuous Mode 320 1,000,000 Noncontinuous Mode 50 Clk_4x = 0 1 5 Clk_4x = 1 4 20 6.2 kSPS 1,000,000 ms 1 10 MHz 4 160 50 ms 40 MHz Data Clock (DCLK) 20 20 MHz Configuration Clock (CLK_CFG) 20 20 MHz 7 ppm of FSR (3), rms ACCURACY Noise, Low-Level Input (1) CSENSOR (2) = 50pF 5.3 Integral Linearity Error (4) Resolution 7 5.3 ±0.025% Reading ± 1.0ppm FSR, typ ±0.025% Reading ± 1.0ppm FSR, typ ±0.05% Reading ± 1.5ppm FSR, max ±0.05% Reading ± 1.5ppm FSR, max No Missing Codes, Format = 1 20 19 (5) No Missing Codes, Format = 0 16 16 Bits Bits Input Bias Current ±0.1 ±10 ±0.1 ±10 pA Range Error Match (6) 0.1 0.5 0.1 0.5 % of FSR ±1000 ±200 ±1000 ppm of FSR Range Sensitivity to VREF VREF = 4.096 ±0.1V 1:1 Offset Error ±200 Offset Error Match (6) ±100 DC Bias Voltage (7) Power-Supply Rejection Ratio (1) (2) (3) (4) (5) (6) (7) 1:1 ±100 ppm of FSR Low-Level Input (< 1% FSR) ±0.1 ±2 ±0.1 ±2 mV at DC 100 ±800 100 ±800 ppm of FSR/V Input is less than 1% of full-scale. CSENSOR is the capacitance seen at the DDC232 inputs from wiring, photodiode, etc. FSR is Full-Scale Range. A best-fit line is used in measuring nonlinearity. Output word is 20 bits with 19 bits no missing codes. Matching between side A and side B of the same input. Voltage produced by the DDC232 at its input that is applied to the sensor. Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): DDC232 3 DDC232 SBAS331D – AUGUST 2004 – REVISED APRIL 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = +5V, DVDD = +3.0V, VREF = +4.096V, tINT = 333ms for DDC232C or 166ms for DDC232CK, Range 7, and continuous mode operation, unless otherwise noted. DDC232C PARAMETER TEST CONDITIONS MIN DDC232CK TYP MAX Offset Drift ±0.5 Offset Drift Stability ±0.2 MIN TYP MAX UNIT 5 (8) ±0.5 5 (8) ppm of FSR/°C 2 (8) ±0.2 2 (8) ppm of FSR/minute 0.01 1 (8) 0.01 1 (8) pA/°C Range Drift (10) 25 50 25 50 ppm/°C Range Drift Match (11) ±5 PERFORMANCE OVER TEMPERATURE DC Bias Voltage Drift (9) Input Bias Current Drift ±3 TA = +25°C to +45°C ±3 mV/°C ±5 ppm/°C REFERENCE Voltage 4.000 Input Current (12) 4.096 Average Value with tINT = 333ms 4.200 4.000 4.096 4.200 325 V mA Average Value with tINT = 166.5ms 650 mA DIGITAL INPUT/OUTPUT Logic Levels VIH 0.8 DVDD DVDD + 0.1 0.8 DVDD DVDD + 0.1 V VIL –0.1 0.2 DVDD –0.1 0.2 DVDD V VOH IOH = –500mA VOL IOL = 500mA 0.4 0.4 V 0 < VIN < DVDD ±10 ±10 mA Input Current (IIN) DVDD – 0.4 Data Format (13) DVDD – 0.4 Straight Binary V Straight Binary POWER-SUPPLY REQUIREMENTS Analog Power-Supply Voltage (AVDD) 4.75 5.0 5.25 4.9 5.0 5.1 V Digital Power-Supply Voltage (DVDD) 2.7 3.0 3.6 2.7 3.0 3.6 V Supply Current Analog Current 41 60 Digital Current 3.7 8.0 mA Total Power Dissipation Per Channel Power Dissipation (8) (9) (10) (11) (12) (13) 4 mA 224 288 290 mW 7 9 10 mW/Channel Ensured by design, not production tested. Voltage produced by the DDC232 at its input that is applied to the sensor. Range drift does not include external reference drift. Matching between side A and side B of the same input. Input reference current decreases with increasing tINT (see the Voltage Reference section, page 10). Data format is Straight Binary with a small offset. The number of bits in the output word is controlled by the Format bit. Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): DDC232 DDC232 www.ti.com SBAS331D – AUGUST 2004 – REVISED APRIL 2010 PIN CONFIGURATION Top View BGA Columns H G F E D C B A IN21 IN22 IN23 IN24 IN25 IN26 IN27 IN28 1 IN5 IN6 IN8 IN7 IN9 IN10 IN11 IN12 2 IN17 IN18 IN19 IN20 IN29 IN30 IN31 IN32 3 IN1 IN2 IN3 IN4 IN13 IN14 IN15 IN16 QGND AGND AGND AGND AGND AGND AGND AGND Rows 4 5 AGND AVDD AVDD AVDD AGND DGND VREF VREF 6 DVALID DIN_CFG CLK_CFG DGND DGND RESET DVDD DGND 7 DCLK DGND CLK NC DOUT DGND DIN CONV 8 PIN DESCRIPTIONS PIN LOCATION FUNCTION IN1–32 Rows 1–4 Analog Input DESCRIPTION QGND H5 Analog Quiet Analog Ground AGND G5, F5, E5, D5, C5, B5, A5, D6, H6 Analog Analog Ground DGND A7, C6, D7, E7, C8, G8 Digital Digital Ground AVDD E6, F6, G6 Analog Analog Power Supply, +5V Nominal VREF A6, B6 Analog Input External Voltage Reference Input, +4.096V Nominal DVALID H7 Digital Output Data Valid Output, Active Low DIN_CFG G7 Digital Input Configuration Register Data Input CLK_CFG F7 Digital Input Configuration Register Clock Input RESET C7 Digital Input Digital Reset, Active Low DVDD B7 Digital CONV A8 Digital Input Conversion Control Input; 0 = Integrate on Side B, 1 = Integrate on Side A DIN B8 Digital Input Serial Data Input DOUT D8 Digital Output NC E8 No Connect Do not connect; must be left floating. CLK F8 Digital Input Master Clock Input DCLK H8 Digital Input Serial Data Clock Input Analog Inputs for Channels 1 to 32 Digital Power Supply, 3.3V Nominal Serial Data Output Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): DDC232 5 DDC232 SBAS331D – AUGUST 2004 – REVISED APRIL 2010 www.ti.com TYPICAL CHARACTERISTICS At TA = +25°C, unless otherwise indicated. Noise (ppm of FSR, rms) NOISE vs CSENSOR 150 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 Range 1 Range 2 Range 7 0 100 200 300 400 500 600 700 800 900 1000 CSENSOR (pF) Figure 1. Table 1. NOISE vs CSENSOR (ppm of FSR, rms) NOISE (ppm of FSR, rms) CSENSOR (pF) Range 0 Range 1 Range 2 Range 3 Range 4 Range 5 Range 6 Range 7 0 27 9.1 6.3 5.5 5.2 5 4.9 4.8 22 38 12 7.9 6.5 5.8 5.5 5.3 5.1 47 51 15 9.8 7.7 6.7 6.1 5.8 5.5 68 59 18 11 8.5 7.3 6.6 6.1 5.8 100 74 22 13 9.9 8.3 7.4 6.8 6.3 150 100 29 16 12 10 8.7 7.8 7.2 330 180 50 27 19 15 13 11 10 470 250 67 36 25 19 16 14 12 1000 520 130 57 49 37 30 26 22 Table 2. NOISE vs CSENSOR (fC, rms) NOISE (fC, rms) CSENSOR (pF) Range 0 Range 1 Range 2 Range 3 Range 4 Range 5 Range 6 Range 7 0 0.34 0.46 0.63 0.83 1.04 1.25 1.47 1.68 22 0.48 0.60 0.79 0.98 1.16 1.38 1.59 1.79 47 0.64 0.75 0.98 1.16 1.34 1.53 1.74 1.93 68 0.74 0.90 1.10 1.28 1.46 1.65 1.83 2.03 100 0.93 1.10 1.30 1.49 1.66 1.85 2.04 2.21 150 1.25 1.45 1.60 1.80 2.00 2.18 2.34 2.52 330 2.25 2.50 2.70 2.85 3.00 3.25 3.30 3.50 470 3.13 3.35 3.60 3.75 3.80 4.00 4.20 4.20 1000 6.50 6.50 5.70 7.35 7.40 7.50 7.80 7.70 Table 3. NOISE vs CSENSOR (electrons, rms) 6 NOISE (electrons, rms) CSENSOR (pF) Range 0 Range 1 Range 2 Range 3 Range 4 Range 5 Range 6 Range 7 0 2100 2840 3930 5140 6490 7800 9170 10400 22 2960 3740 4930 6080 7240 8580 9920 11100 47 3970 4680 6110 7200 8360 9510 10800 12000 68 4600 5610 6860 7950 9110 10200 11400 12600 100 5770 6860 8110 9260 10300 11500 12700 13700 150 7800 9050 9980 11200 12400 13500 14600 15700 330 14000 15600 16800 17700 18700 20200 20500 21800 470 19500 20900 22400 23400 23700 24900 26200 26200 1000 40500 40500 35500 45800 46100 46800 48600 48000 Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): DDC232 DDC232 www.ti.com SBAS331D – AUGUST 2004 – REVISED APRIL 2010 THEORY OF OPERATION GENERAL DESCRIPTION converters via multiplexers. With the DDC232 in the continuous integration mode, the output of the integrators from one side of the inputs will be digitized while the other 32 integrators are in the integration mode. This integration and A/D conversion process is controlled by the system clock, CLK. The results from side A and side B of each signal input are stored in a serial output shift register. The DVALID output goes low when the shift register contains valid data. The block diagram of the DDC232 is shown in Figure 2. The device contains 32 identical input channels that perform the function of current-to-voltage integration followed by a multiplexed A/D conversion. Each input has two integrators so that the current-to-voltage integration can be continuous in time. The output of the 64 integrators are switched to 16 delta-sigma (∆Σ) AVDD VREF DVDD 0.1mF 0.1mF 0.1mF IN1 Dual Switched Integrator CLK DS ADC IN2 Dual Switched Integrator CONV Configuration and Control DIN_CFG CLK_CFG RESET IN3 Dual Switched Integrator DS ADC IN4 Dual Switched Integrator IN29 Dual Switched Integrator DVALID DCLK Serial Interface DS ADC IN30 Dual Switched Integrator IN31 Dual Switched Integrator DOUT DIN DS ADC IN32 Dual Switched Integrator AGND DGND Figure 2. DDC232 Block Diagram Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): DDC232 7 DDC232 SBAS331D – AUGUST 2004 – REVISED APRIL 2010 www.ti.com DEVICE OPERATION operational amplifier. At the beginning of a conversion, the switches SA/D, SINTA, SINTB, SREF1, SREF2, and SRESET are set (see Figure 4). Basic Integration Cycle The topology of the front end of the DDC232 is an analog integrator as shown in Figure 3. In this diagram, only input IN1 is shown. The input stage consists of an operational amplifier, a selectable feedback capacitor network (CF), and several switches that implement the integration cycle. The timing relationships of all of the switches shown in Figure 3 are illustrated in Figure 4. Figure 4 conceptualizes the operation of the integrator input stage of the DDC232 and should not be used as an exact timing tool for design. At the completion of an A/D conversion, the charge on the integration capacitor (CF) is reset with SREF1 and SRESET (see Figure 4 and Figure 5a). This is done during reset. In this manner, the selected capacitor is charged to the reference voltage, VREF. Once the integration capacitor is charged, SREF1 and SRESET are switched so that VREF is no longer connected to the amplifier circuit while it waits to begin integrating (see Figure 5b). With the rising edge of CONV, SINTA closes, which begins the integration of side A. This process puts the integrator stage into its integrate mode (see Figure 5c). See Figure 5 for the block diagrams of the reset, integrate, wait, and convert states of the integrator section of the DDC232. This internal switching network is controlled externally with the convert pin (CONV) and the system clock (CLK). For the best noise performance, CONV must be synchronized with the rising edge of CLK. It is recommended that CONV toggle within ±10ns of the rising edge of CLK. Charge from the input signal is collected on the integration capacitor, causing the voltage output of the amplifier to decrease. The falling edge of CONV stops the integration by switching the input signal from side A to side B (SINTA and SINTB). Prior to the falling edge of CONV, the signal on side B was converted by the A/D converter and reset during the time that side A was integrating. With the falling edge of CONV, side B starts integrating the input signal. At this point, the output voltage of the side A operational amplifier is presented to the input of the ∆Σ A/D converter (see Figure 5d). The noninverting inputs of the integrators are connected to ground. Consequently, the DDC232 analog ground should be as clean as possible. In Figure 3, the feedback capacitors (CF) are shown in parallel between the inverting input and output of the Adjustable Feedback Capacitors (CF) SREF1 VREF 3pF 50pF Range[2] Bit 25pF Range[1] Bit 12.5pF Range[0] Bit Input Current SINTA SREF2 IN1 SADC1A SRESET Photodiode ESD Protection Diodes To Converter Integrator B (same as A) SINTB Integrator A Figure 3. Basic Integration Configuration for Input 1 8 Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): DDC232 DDC232 www.ti.com SBAS331D – AUGUST 2004 – REVISED APRIL 2010 CONV CLK SINTA SINTB SREF1 SREF2 SRESET Integrate Convert Wait W a it Wait Reset Convert W a it Configuration of Integrator A Reset SA/D1A VREF Integrator A Voltage Output Figure 4. Integration Timing (see Figure 3) SREF1 CF VREF SINT SREF2 CF IN SREF1 VREF To Converter SRESET SA/D SINT SREF2 IN To Converter SRESET SA/D a) Reset Configuration CF SREF1 b) Wait Configuration VREF SINT SREF2 CF IN SREF1 VREF To Converter SRESET SA/D SINT SREF2 IN To Converter SRESET SA/D c) Integrate Configuration d) Convert Configuration Figure 5. Four Configurations of the Front-End Integrators Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): DDC232 9 DDC232 SBAS331D – AUGUST 2004 – REVISED APRIL 2010 www.ti.com charge needed by the ∆Σ converter. For an integration time of 333ms, this charge translates to an average VREF current of approximately 325mA. The amount of charge needed by the ∆Σ converter is independent of the integration time; therefore, increasing the integration time lowers the average current. For example, an integration time of 800ms lowers the average VREF current to 135mA. Integration Capacitors There are seven different capacitors available on-chip for both sides of every channel in the DDC232. These internal capacitors are trimmed in production to achieve the specified performance for range error of the DDC232. The range control bits (Range[2:0]) change the capacitor value for all integrators. Consequently, all inputs and both sides of each input will always have the same full-scale range. Table 4 shows the capacitor value selected for each range selection. It is critical that VREF be stable during the different modes of operation (see Figure 5). The ∆Σ converter measures the voltage on the integrator with respect to VREF. Since the integrator capacitors are initially reset to VREF, any drop in VREF from the time the capacitors are reset to the time when the converter measures the integrator output will introduce an offset. It is also important that VREF be stable over longer periods of time because changes in VREF correspond directly to changes in the full-scale range. Finally, VREF should introduce as little additional noise as possible. Table 4. Range Selection RANGE CONTROL BITS CF (pF, typ) INPUT RANGE (pC, typ) –0.04 to 12.5 RANGE Range[2] Range[1] Range[0] 0 0 0 0 3 1 0 0 1 12.5 –0.2 to 50 2 0 1 0 25 –0.4 to 100 3 0 1 1 37.5 –0.6 to 150 4 1 0 0 50 –0.8 to 200 5 1 0 1 62.5 –0.1 to 250 6 1 1 0 75 –1.2 to 300 7 1 1 1 87.5 –1.4 to 350 For these reasons, it is strongly recommended that the external reference source be buffered with an operational amplifier, as shown in Figure 6. In this circuit, the voltage reference is generated by a +4.096V reference. A low-pass filter to reduce noise connects the reference to an operational amplifier configured as a buffer. This amplifier should have low noise and input/output common-mode ranges that support VREF. Even though the circuit in Figure 6 might appear to be unstable due to the large output capacitors, it works well for most operational amplifiers. It is not recommended that series resistance be placed in the output lead to improve stability since this can cause a drop in VREF, which produces large offsets. Voltage Reference The external voltage reference is used to reset the integration capacitors before an integration cycle begins. It is also used by the ∆Σ converter while the converter is measuring the voltage stored on the integrators after an integration cycle ends. During this sampling, the external reference must supply the +5V +5V 0.10mF 0.47mF 7 2 1 REF3140 6 2 10kW 3 To VREF Pin on the DDC232 OPA350 + 10mF + 10mF 0.10mF 4 3 Figure 6. Recommended External Voltage Reference Circuit for Best Low-Noise Operation 10 Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): DDC232 DDC232 www.ti.com SBAS331D – AUGUST 2004 – REVISED APRIL 2010 Frequency Response CONFIGURATION REGISTER The frequency response of the DDC232 is set by the front-end integrators and is that of a traditional continuous time integrator, as shown in Figure 7. By adjusting tINT, the user can change the 3dB bandwidth and the location of the notches in the response. The frequency response of the ∆Σ converter that follows the front-end integrator is of no consequence because the converter samples a held signal from the integrators. That is, the input to the ∆Σ converter is always a DC signal. Since the output of the front-end integrators are sampled, aliasing can occur. Whenever the frequency of the input signal exceeds one-half of the sampling rate, the signal will fold back down to lower frequencies. Some aspects of device operation are controlled by the onboard configuration register. The DIN_CFG, CLK_CFG, and RESET pins are used to write to this register. When beginning a write operation, hold CONV low and strobe RESET; see Figure 8. Then begin shifting in the configuration data on DIN_CFG. Data are written to the configuration register most significant bit first. The data are internally latched on the falling edge of CLK_CFG. Partial writes to the configuration register are not allowed—make sure to send all 12 bits when updating the register. 0 Gain (dB) −10 Optional readback of the configuration register is available immediately after the write sequence. During readback, the 12-bit configuration data followed by a 4-bit revision ID and the test pattern are shifted out on the DOUT pin on the rising edge of DCLK. NOTE: Wth Format = 1, the test pattern is 304 bits, with only the last 72 bits non-zero. This sequence of outputs is repeated twice for each DDC232 and daisy-chaining is supported in configuration readback. Table 5 shows the test pattern configuration during readback. Table 6 shows the timing for the configuration register read and write operations. Strobe CONV to begin normal operation. −20 −30 −40 −50 0.1 tINT 1 tINT 10 tINT 100 tINT Table 5. Test Pattern During Readback TEST PATTERN (Hex) TOTAL READBACK BITS 0 30F066012480F6h 512 1 30F066012480F69055h 640 Format BIT Frequency Figure 7. Frequency Response Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): DDC232 11 DDC232 SBAS331D – AUGUST 2004 – REVISED APRIL 2010 www.ti.com tRST RESET Configuration Register Operations tWTRST Normal Operation tWTWR CLK_CFG t STCF DIN_CFG t HDCF MSB LSB Write Configuration Register Data Read Configuration Register and Test Pattern DCLK DOUT MSB LSB Configuration Register Data Test Pattern CONV NOTE: CLK must be running during Configuration Register write and read operations. Figure 8. Configuration Register Write and Read Operations Table 6. Timing for the Configuration Register Read/Write 12 SYMBOL DESCRIPTION MIN tWTRST Wait Required from Reset High to First Rising Edge of CLK_CFG 2 ms tWTWR Wait Required from Last CLK-CFG of Write Operation to First CLK_CFG of Read Operation 2 ms tSTCF Set-Up Time from DIN_CFG to Falling Edge of CLK_CFG 10 ns tHDCF Hold Time for DIN_CFG After Falling Edge of CLK_CFG 10 ns tRST Pulse Width for RESET Active 1 ms Submit Documentation Feedback TYP MAX UNITS Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): DDC232 DDC232 www.ti.com SBAS331D – AUGUST 2004 – REVISED APRIL 2010 Table 7. Configuration Register Bit 11 Bit 10 Bit 9 Range[2] Range[1] Range[0] Bits 11–9 Bit 7 Version Bit 6 Clk_4x Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 Test Range[2:0]. Full-scale range. 000: 001: 010: 011: Bit 8 Bit 8 Format 12.5pC 50pC 100pC 150pC 100: 101: 110: 111: 200pC 250pC 300pC 350pC (default) Format. Data output format. This bit selects how many bits are used in the data output word. 0: 16-Bit Output 1: 20-Bit Output (default) Bit 7 Version. Device version setting. Must be set to '0' for DDC232C Must be set to '1' for DDC232CK Bit 6 Clk_4x. System clock divider. The Clk_4x input enables an internal divider on the system clock. When Clk_4x = 1, the system clock is divided by 4. This allows a 4X faster system clock, which in turn provides a finer quantization of the integration time because the CONV signal needs to be synchronized with the system clock for the best performance. 0: Internal Clock Divider = 1 (default) 1: Internal Clock Divider = 4 Clk_4x BIT CLK DIVIDER VALUE CLK FREQUENCY INTERNAL CLOCK FREQUENCY 0 1 5MHz 5MHz 1 4 20MHz 5MHz Bits 5–1 These bits must be set to '0'. Bit 0 Test. Diagnostic test mode enable. When Test mode is used, the inputs (IN1 through IN32) are disconnected from the DDC232 integrators to enable the user to measure a zero input signal regardless of the current supplied to the inputs. Test mode works with both Continuous and Noncontinuous modes. 0: Test Mode Off (default) 1: Test Mode On Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): DDC232 13 DDC232 SBAS331D – AUGUST 2004 – REVISED APRIL 2010 www.ti.com DIGITAL INTERFACE The digital interface of the DDC232 outputs the digital results via a synchronous serial interface consisting of a data clock (DCLK), a valid data pin (DVALID), a serial data output pin (DOUT), and a serial data input pin (DIN). The integration and conversion process is fundamentally independent of the data retrieval process. Consequently, the CLK and DCLK frequencies need not be the same, though for best performance, it is highly recommended that they be derived from the same clocking source to keep the phase relationship constant. DIN is only used when multiple converters are cascaded and should be tied to DGND otherwise. Depending on tINT, CLK, and DCLK, it is possible to daisy-chain multiple converters. This greatly simplifies the interconnection and routing of the digital outputs in those applications where a large number of converters are needed. Configuration of the DDC232 is set by a dedicated register addressed using the DIN_CFG and CLK_CFG pins. DVALID eliminates any concern about this relationship. If the data read back is timed from CONV, make sure to wait for the required amount of time. For Continuous mode, this time is given by tCMDR. For Noncontinuous mode, use tNCDR1 or tNCDR2, as appropriate. See Table 9 for details. Reset (RESET) The DDC232 is reset asynchronously by taking the RESET input low, as shown in Figure 9. Make sure the release pulse is at least 1ms wide. After resetting the DDC232, wait at least four conversions before using the data. It is very important that RESET is glitch-free to avoid unintentional resets. Figure 9. Reset Timing System and Data Clocks (CLK and CONV) The system clock is supplied to CLK and the data clock is supplied to DCLK. It is recommended that the CLK pin be driven by a free-running clock source (that is, do not start and stop CLK between conversions). Make sure the clock signals are clean—avoid overshoot or ringing. For best performance, generate both clocks from the same clock source. DCLK should be disabled by taking it low after the data has been shifted out or while CONV is transitioning. When using multiple DDC232s, pay close attention to the DCLK distribution on the printed circuit board (PCB). In particular, make sure to minimize skew in the DCLK signal because this can lead to timing violations in the serial interface specifications. See the Cascading Multiple Converters section for more details. Data Valid (DVALID) The DVALID signal indicates that data are ready. Data retrieval may begin after DVALID goes low. This signal is generated using an internal clock divided down from the system clock, CLK. The phase relationship between this internal clock and CLK is set when power is first applied and is random. Since the user must synchronize CONV with CLK, the DVALID signal will have a random phase relationship with CONV. This uncertainty is ±1/fCLK. Polling 14 > 1µs RESET Conversion Rate The conversion rate of the DDC232 is set by a combination of the integration time (determined by the user) and the speed of the A/D conversion process. The A/D conversion time is primarily a function of the system clock (CLK) speed. One A/D conversion cycle encompasses the conversion of two signals (one side of each dual integrator feeding the modulator) and the reset time for each of the integrators involved in the two conversions. In most situations, the A/D conversion time is shorter than the integration time. If this condition exists, the DDC232 will operate in the continuous mode. When the DDC232 is in the continuous mode, the sensor output is continuously integrated by one of the two sides of each input. In the event that the A/D conversion takes longer than the integration time, the DDC232 will switch into a Noncontinuous mode. In Noncontinuous mode, the A/D converter is not able to keep pace with the speed of the integration process. Consequently, the integration process is periodically halted until the digitizing process catches up. These two basic modes of operation for the DDC232—Continuous and Noncontinuous modes—are described below. Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): DDC232 DDC232 www.ti.com SBAS331D – AUGUST 2004 – REVISED APRIL 2010 Continuous and Noncontinuous Operational Modes Figure 10 shows the state diagram of the DDC232. In all, there are eight states. Table 8 provides a brief explanation of each state. During the Continuous (Cont) mode, mbsy is not active when CONV toggles. The nonintegrating side is always ready to begin integrating when the other side finishes its integration. Consequently, monitoring the current status of CONV is all that is needed to know the current state. Cont mode operation corresponds to states 3 to 6. Two of the states, 3 and 6, only perform an integration (that is, no m/r/az cycle). CONV|mbsy 1 2 CONV • mbsy Ncont Ncont CONV 3 CONV • mbsy CONV 4 Int A Cont 5 CONV • mbsy Int B/Meas A Cont CONV • mbsy CONV Int A/Meas B Cont CONV 6 CONV • mbsy Int B Cont 7 8 Ncont Ncont CONV • mbsy Four signals are used to control progression around the state diagram: CONV, mbsy, and their complements. The state machine uses the level as opposed to the edges of CONV to control the progression. mbsy is an internally-generated signal not available to the user. It is active whenever a measurement/reset/auto-zero (m/r/az) cycle is in progress. CONV|mbsy State Diagram Notation: CONV • mbsy = CONV high AND mbsy active. CONV|mbsy = CONV high OR mbsy active. Figure 10. Integrate/Measure State Diagram mbsy becomes important when operating in the Noncontinuous (Ncont) mode (states 1, 2, 7, and 8). Whenever CONV is toggled while mbsy is active, the DDC232 will enter or remain in either Ncont state 1 (or 8). After mbsy goes inactive, state 2 (or 7) is entered. This state prepares the appropriate side for integration. In the Ncont states, the inputs to the DDC232 are grounded. One interesting observation from the state diagram is that the integrations always alternate between sides A and B. This relationship holds for any CONV pattern and is independent of the mode. States 2 and 7 ensure this relationship during the Ncont mode. When power is first applied to the DDC232, the beginning state is either 1 or 8, depending on the initial level of CONV. For CONV held high at power-up, the beginning state is 1. Conversely, for CONV held low at power-up, the beginning state is 8. In general, there is a symmetry in the state diagram between states 1–8, 2–7, 3–6, and 4–5. Inverting CONV results in the states progressing through their symmetrical match. Table 8. State Descriptions STATE MODE DESCRIPTION 1 Ncont Complete m/r/az of side A, then side B (if previous state is state 4). Initial power-up state when CONV is initially held high. 2 Ncont Prepare side A for integration. 3 Cont Integrate on side A. 4 Cont Integrate on side B; m/r/az on side A. 5 Cont Integrate on side A; m/r/az on side B. 6 Cont Integrate on side B. 7 Ncont Prepare side B for integration. 8 Ncont Complete m/r/az of side B, then side A (if previous state is state 5). Initial power-up state when CONV is initially held low. Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): DDC232 15 DDC232 SBAS331D – AUGUST 2004 – REVISED APRIL 2010 www.ti.com TIMING EXAMPLES top signal is CONV and is supplied by the user. The next line indicates the current state in the state diagram. The following two traces show when integrations and measurement cycles are underway. The internal signal mbsy is shown next. Finally, DVALID is given. As described in the data sheet, DVALID goes active low when data are ready to be retrieved from the DDC232. It stays low until DCLK is taken high and then back low by the user. The text below the DVALID pulse indicates the side of the data available to be read and arrows help match the data to the corresponding integration. Continuous Mode A few timing diagrams help illustrate the operation of the integrate/measure state machine. These diagrams are shown in Figure 11 through Figure 16. Table 9 gives generalized timing specifications in units of CLK periods for Clk_4x = 0. If Clk_4x = 1, these values increase by a factor of 4 because of the internal clock divider. Values (in ms) for Table 9 can be easily found for a given CLK. Figure 11 shows a few integration cycles beginning with initial power-up for a Cont mode example. The CONV State 8 Integration Status 7 6 5 4 5 Integrate B Integrate A Integrate B Integrate A m/r/az Status m/r/az B m/r/az A m/r/az B tMRAZ mbsy DVALID tCMDR t=0 Power−Up Side B Data Side A Data Side B Data Figure 11. Continuous Mode Timing Table 9. Timing Specifications Generalized in CLK Periods VALUE (CLK Periods with Clk_4x = 0) SYMBOL 16 DDC232C DDC232CK tMRAZ Continuous mode, m/r/az cycle DESCRIPTION 1552 ± 2 1612 ± 2 tCMDR Continuous mode, data ready 1382 ± 2 1382 ± 2 Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): DDC232 DDC232 www.ti.com SBAS331D – AUGUST 2004 – REVISED APRIL 2010 In Figure 11, the first state is Ncont state 8. The DDC232 always powers up in the Ncont mode. In this case, the first state is 8 because CONV is initially low. After the first two states, Cont mode operation is reached and the states begin toggling between 4 and 5. From now on, the input is being continuously integrated, either on side A or side B. The time needed for the m/r/az cycle, tMRAZ, is the same time that determines the boundary between the Cont and Ncont modes described earlier in the Continuous and Noncontinuous Operational Modes section. DVALID goes low after CONV toggles in time tCMDR, indicating that data are ready to be retrieved. See Figure 12 for the timing diagram of the internal operations occurring during Continuous mode operation. Table 10 gives the timing specifications of the internal operations occurring during Continuous mode operation. End Integration Side B Start Integration Side A End Integration Side A Start Integration Side B tINT CONV t INT Side B Side A A/D Conversion Odd Channels (Internal) End Integration Side A Start Integration Side B Side A tADCONV tADRST Side A A/D Conversion Even Channels (Internal) Side B tADCONV tIRST tADRST t IRST DVALID Side B Data Ready Side A Data Ready Figure 12. Internal Operation in Continuous Mode Timing Table 10. Timing Characteristics for the Internal Operation in Continuous Mode DDC232C (CLK = 5MHz, Clk_4x = 0) SYMBOL tINT tADCONV tADRST tIRST DESCRIPTION MIN Integration Period (continuous mode) 320 A/D Conversion Time (internally controlled) TYP DDC232CK (CLK = 10MHz, Clk_4x = 0) MAX MIN 1,000,000 160 TYP MAX UNITS 1,000,000 ms 135.6 68 ms A/D Conversion Reset Time (internally controlled) 3.2 2.2 ms Integrator Reset Time (internally controlled) 36 21.8 ms Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): DDC232 17 DDC232 SBAS331D – AUGUST 2004 – REVISED APRIL 2010 www.ti.com Noncontinuous Mode Figure 13 and Figure 14 illustrate operation in Noncontinuous mode. Start Integration Side A End Integration Side A Start Integration Side B Start Integration Side A End Integration Side B Wait State Release State tINT CONV tINT A/D Conversion Odd Channels tNCRL tADCONV A/D Conversion Even Channels tADCONV tADRST DVALID tNCIRST Side A Data Ready Side B Data Ready tNCDR2 t NCDR1 Figure 13. Conversion Detail for the Internal Operation of Noncontinuous Mode with Side A Integrated First Table 11. Timing Characteristics for the Internal Operation in Noncontinuous Mode DDC232C (CLK = 5MHz, Clk_4x = 0) TYP DDC232CK (CLK = 10MHz, Clk_4x = 0) SYMBOL DESCRIPTION MIN tINT Integration Time (Noncontinuous mode) 50 MAX MIN 1,000,000 50 tADCONV A/D Conversion Time (internally controlled) 135.6 67.8 ms tADRST A/D Conversion Reset Time (internally controlled) 3.2 1.6 ms tNCIRST Noncontinuous Mode Integrator Reset Time (internally controlled) 30.4 15.2 0.4 TYP MAX UNITS 1,000,000 ms 0.2 ms tNCRL Release Time tNCDR1 1st Noncontinuous Mode Data Ready 276.5 138.2 ms tNCDR2 2nd Noncontinuous Mode Data Ready 304.8 152.4 ms ms BLANKSPACE Start Integration Side B Start Integration Side B End Integration Side B Start Integration Side A Release State End Integration Side A CONV Wait State tINT tINT A/D Conversion Odd Channels tNCRL tADCONV A/D Conversion Even Channels t ADCONV t ADRST tNCIRST DVALID Side B Data Ready Side A Data Ready Figure 14. Internal Operation Noncontinuous Mode Timing with Side B Integrated First 18 Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): DDC232 DDC232 www.ti.com SBAS331D – AUGUST 2004 – REVISED APRIL 2010 is increased so that tINT is always ≥ tMRAZ as shown in Figure 16 (see Figure 13 and Table 11, page 18). With a longer tINT, the m/r/az cycle has enough time to finish before the next integration begins and continuous integration of the input signal is possible. For the special case of the very first integration when changing to the Cont mode, tINT can be < tMRAZ. This is allowed because there is no simultaneous m/r/az cycle on the side B during state 3—therefore, there is no need to wait for it to finish before ending the integration on side A. Changing Between Modes Changing from Cont to Ncont mode occurs whenever tINT < tMRAZ. Figure 15 shows an example of this transition. In this figure, Cont mode is entered when the integration on side A is completed before the m/r/az cycle on side B is complete. The DDC232 completes the measurement on sides B and A during states 8 and 7 with the input signal shorted to ground. Ncont integration begins with state 6. Changing from Ncont to Cont mode occurs when tINT CONV State 5 4 5 8 Continuous Integration Status m/r/az Status Integrate A Integrate B m/r/az B m/r/az A 7 6 5 Int B Int A Noncontinuous Int A m/r/az B m/r/az A m/r/az B mbsy Figure 15. Changing from Continuous Mode to Noncontinuous Mode CONV State 3 4 1 2 Noncontinuous Integration Status m/r/az Status Int A Int B m/r/az A 3 4 Continuous Integrate A m/r/az B Integrate B m/r/az A mbsy Figure 16. Changing from Noncontinuous Mode to Continuous Mode Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): DDC232 19 DDC232 SBAS331D – AUGUST 2004 – REVISED APRIL 2010 www.ti.com Table 12. Ideal Output Code (1) vs Input Signal DATA FORMAT The serial output data are provided in an offset binary code as shown in Table 12. The Format bit in the configuration register selects how many bits are used in the output word. When Format = 1, 20 bits are used. When Format = 0, the lower 4 bits are truncated so that only 16 bits are used. Note that the LSB size is 16 times bigger when Format = 0. An offset is included in the output to allow slightly negative inputs (for example, from board leakages) from clipping the reading. This offset is approximately 0.4% of the positive full-scale. INPUT SIGNAL IDEAL OUTPUT CODE FORMAT = 1 IDEAL OUTPUT CODE FORMAT = 0 ≥ 100% FS 1111 1111 1111 1111 1111 1111 1111 1111 1111 0.001531% FS 0000 0001 0000 0001 0000 0000 0001 0000 0001 0.001436% FS 0000 0001 0000 0000 1111 0000 0001 0000 0000 0.000191% FS 0000 0001 0000 0000 0010 0000 0001 0000 0000 0.000096% FS 0000 0001 0000 0000 0001 0000 0001 0000 0000 0% FS 0000 0001 0000 0000 0000 0000 0001 0000 0000 –0.3955% FS 0000 0000 0000 0000 0000 0000 0000 0000 0000 (1) Excludes the effects of noise, INL, offset, and gain errors. BLANKSPACE DATA RETRIEVAL Make sure not to retrieve data around changes in CONV because this can introduce noise. Stop activity on DCLK at least 10ms before or after a CONV transition. In both the Continuous and Noncontinuous modes of operation, the data from the last conversion are available for retrieval on the falling edge of DVALID (see Figure 17 and Table 13). Data are shifted out on the falling edge of the data clock, DCLK. Setting the Format bit = 0 (16-bit output word) will reduce the time needed to retrieve data by 20% since there are fewer bits to shift out. This can be useful in multichannel systems requiring only 16 bits of resolution. CLK tPDCDV DVALID tPDDCDV tHDDODV DCLK tHDDODC Input 32 MSB DOUT Input 32 LSB tPDDCDO Input 31 MSB Input 5 LSB Input 4 MSB Input 2 LSB Input 1 MSB Input 1 LSB Input 32 MSB Figure 17. Digital Interface Timing for Data Retrieval From a Single DDC232 Table 13. Timing for DDC232 Data Retrieval SYMBOL 20 MIN tPDCDV Propagation Delay from Falling Edge of CLK to DVALID Low 10 tPDDCDV Propagation Delay from Falling Edge of DCLK to DVALID High 5 tHDDODV Hold Time that DOUT is Valid Before the Falling Edge of DVALID tHDDODC Hold Time that DOUT is Valid After Falling Edge of DCLK tPDDCDO (1) DESCRIPTION (1) Propagation Delay from Falling Edge of DCLK to Valid DOUT TYP MAX UNITS ns ns 400 ns 4 ns 25 ns With a maximum load of one DDC232 (4pF typical) with an additional load of 5pF. Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): DDC232 DDC232 www.ti.com SBAS331D – AUGUST 2004 – REVISED APRIL 2010 Cascading Multiple Converters Figure 19 shows the timing diagram when the DIN input is used to daisy-chain several devices. Table 14 gives the timing specification for data retrieval using DIN. Multiple DDC232 units can be connected in serial configuration; see Figure 18. DOUT can be used with DIN to daisy-chain multiple DDC232 devices together to minimize wiring. In this mode of operation, the serial data output is shifted through multiple DDC232s; see Figure 18. DCLK DVALID IN4 IN3 IN2 IN1 3 2 1 IN30 IN29 30 29 DIN 4 IN32 IN31 DDC232 32 DOUT 31 IN2 IN1 34 IN3 35 33 IN4 IN30 IN29 62 61 DIN 36 IN32 IN31 DDC232 64 DOUT 63 IN2 IN1 IN3 67 66 IN4 68 65 IN30 IN29 94 DIN DCLK DVALID DCLK DVALID DDC232 93 IN2 IN1 98 97 IN32 IN3 99 IN31 IN4 100 DOUT 96 IN30 IN29 126 DIN 95 DDC232 125 IN32 IN31 128 Sensor DOUT 127 Data Retrieval Output DCLK DVALID Data Clock Figure 18. Daisy-Chained DDC232s CLK DVALID DCLK tSTDIDC tHDDIDC DIN DOUT Input 128 MSB Input 128 LSB Input 127 MSB Input 3 LSB Input 2 MSB Input 2 LSB Input 1 MSB Input 128 MSB Input 1 LSB Figure 19. Timing When Using DDC232 DIN Function; See Figure 18 Table 14. Timing for DDC232 Data Retrieval Using DIN SYMBOL DESCRIPTION MIN TYP MAX UNITS tSTDIDC Set-Up Time from DIN to Falling Edge of DCLK 10 ns tHDDIDC Hold Time for DIN After Falling Edge of DCLK 10 ns Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): DDC232 21 DDC232 SBAS331D – AUGUST 2004 – REVISED APRIL 2010 www.ti.com RETRIEVAL BEFORE CONV TOGGLES (CONTINUOUS MODE) t INT * ǒt CMDR ) t SDCVǓ (20 32)t DCLK Data retrieval before CONV toggles is the most straightforward method. Data retrieval begins soon after DVALID goes low and finishes before CONV toggles, as shown in Figure 20. For best performance, data retrieval must stop tSDCV before CONV toggles. This method is most appropriate for longer integration times. The maximum time available for readback is tINT – tCMDR – tSDCV. NOTE: (16 × 32)tDCLK is used for Format = 0, where tDCLK is the period of the data clock. For example, if tINT = 1000ms and DCLK = 10MHz, the maximum number of DDC232s with Format = 1 is shown in Equation 2: 1000ms * 286.8ms + 11.14 ³ 11 DDC232 (640)(100ns) (2) For DCLK = 10MHz and CLK = 5MHz, the maximum number of DDC232s that can be daisy-chained together (Format = 1) is calculated by Equation 1: CONV DVALID (1) (or 13 for Format = 0) tINT tINT t CMDR tSDCV DCLK … … DOUT … … Side B Data Side A Data Figure 20. Readback Before CONV Toggles Table 15. Timing Characteristics for Readback SYMBOL tSDCV 22 DESCRIPTION Data Retrieval Shutdown Before or After Edge of CONV Submit Documentation Feedback MIN 10 TYP MAX UNITS ms Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): DDC232 DDC232 www.ti.com SBAS331D – AUGUST 2004 – REVISED APRIL 2010 RETRIEVAL AFTER CONV TOGGLES (CONTINUOUS MODE) 266ms (20 32)t DCLK For shorter integration times, more time is available if data retrieval begins after CONV toggles and ends before the new data are ready. Data retrieval must wait tSDCV after CONV toggles before beginning. See Figure 21 for an example of this. The maximum time available for retrieval is tCMDR – (tSDCV + tHDDODV), regardless of tINT. The maximum number of DDC232s that can be daisy-chained together with Format = 1 is calculated by Equation 3: NOTE: (16 × 32)tDCLK is for Format = 0. For DCLK = 10MHz, the maximum number of DDC232s is four (or five for Format = 0). tINT CONV (3) tINT tINT DVALID tCMDR tSDCV DCLK … DOUT tHDDODV … … … … … Side A Data Side B Data Side A Data Figure 21. Readback After CONV Toggles Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): DDC232 23 DDC232 SBAS331D – AUGUST 2004 – REVISED APRIL 2010 www.ti.com t INT * ǒt SDCV ) t SDCV ) t HDDODVǓ (20 32)t DCLK RETRIEVAL BEFORE AND AFTER CONV TOGGLES (CONTINUOUS MODE) For the absolute maximum time for data retrieval, data can be retrieved before and after CONV toggles. Nearly all of tINT is available for data retrieval. Figure 22 illustrates how this is done by combining the two previous methods. Pause the retrieval during CONV toggling to prevent digital noise, as discussed previously, and finish before the next data are ready. The maximum number of DDC232s that can be daisy-chained together with Format = 1 is: CONV tINT (4) NOTE: (16 × 32)tDCLK is used for Format = 0. For tINT = 400ms and DCLK = 10MHz, the maximum number of DDC232s is five (or seven for Format = 0). tINT tINT t SDCV DVALID tHDDODV t SDCV DCLK … … … … … … DOUT … … … … … … Side B Data Side A Data Figure 22. Readback Before and After CONV Toggles 24 Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): DDC232 DDC232 www.ti.com SBAS331D – AUGUST 2004 – REVISED APRIL 2010 RETRIEVAL: NONCONTINUOUS MODE until the second integration completes, leaving less time available for retrieval. The time available is tNCDR2 – (tINT – tNCDR1). Data from the second integration must be retrieved before the next round of integration begins. This time is highly dependent on the pattern used to generate CONV. As with the continuous mode, data retrieval must halt before and after CONV toggles (tSDCV) and be completed before new data are ready (tHDDODV). Retrieving in Noncontinuous mode is slightly different as compared with the Continuous mode. As illustrated in Figure 23, DVALID goes low in time tNCDR1 after the first integration completes. If tINT is shorter than this time, all of tNCDR2 is available to retrieve data before the other side data are ready. For tINT > tNCDR1, the first integration data are ready before the second integration completes. Data retrieval must be delayed t IN T CO NV t IN T t IN T t IN T D VALID tNCDR 1 tN C D R 2 DC LK … … DO UT … … Side A Side B Data Data Figure 23. Readback in Noncontinuous Mode Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): DDC232 25 DDC232 SBAS331D – AUGUST 2004 – REVISED APRIL 2010 www.ti.com POWER-UP SEQUENCING LAYOUT Prior to power-up, all digital and analog inputs must be low. At the time of power-up, all of these signals should remain low until the power supplies have stabilized, as shown in Figure 24. At this time, begin supplying the master clock signal to the CLK pin. Wait for time tPOR, then give a RESET pulse. After releasing RESET, the configuration register must be programmed. Table 16 shows the timing for the power-up sequence. POWER SUPPLIES AND GROUNDING tPOR Power Supplies Both AVDD and DVDD should be as quiet as possible. It is particularly important to eliminate noise from AVDD that is nonsynchronous with the DDC232 operation. Figure 25 illustrates how to supply power to the DDC232. Each supply of the DDC232 should be bypassed with 10mF solid tantalum capacitors. It is recommended that both the analog and digital grounds (AGND and DGND) be connected to a single ground plane on the printed circuit board (PCB). VA 0.1mF tRST AVDD AGND 10mF RESET DDC232 VD 0.1mF CONV DVDD DGND 10mF Figure 24. DDC232 Timing at Power-Up Figure 25. Power-Supply Connections Table 16. Timing Characteristics for DDC232 Power-Up Sequence SYMBOL DESCRIPTION tPOR Wait After Power-Up Until Reset tRST Reset Low Width MIN MAX UNITS 250 ms 1 ms BLANKSPACE BLANKSPACE BLANKSPACE BLANKSPACE 26 TYP Shielding Analog Signal Paths As with any precision circuit, careful PCB layout will ensure the best performance. It is essential to make short, direct interconnections and avoid stray wiring capacitance—particularly at the analog input pins and QGND. These analog input pins are high-impedance and extremely sensitive to extraneous noise. The QGND pin should be treated as a sensitive analog signal and connected directly to the supply ground with proper shielding. Leakage currents between the PCB traces can exceed the input bias current of the DDC232 if shielding is not implemented. Digital signals should be kept as far as possible from the analog input signals on the PCB. Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): DDC232 DDC232 www.ti.com SBAS331D – AUGUST 2004 – REVISED APRIL 2010 REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (September 2006) to Revision D Page • Revised document format to meet current standards ........................................................................................................... 1 • Updated data sheet to include new DDC232CK information ................................................................................................ 1 Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): DDC232 27 PACKAGE OPTION ADDENDUM www.ti.com 22-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) 201-000795 ACTIVE NFBGA ZXG 64 1000 RoHS & Green SNAGCU Level-3-260C-168 HR 0 to 70 DDC232 DDC232CKZXGR ACTIVE NFBGA ZXG 64 1000 RoHS & Green SNAGCU Level-3-260C-168 HR 0 to 70 DDC232K DDC232CKZXGT ACTIVE NFBGA ZXG 64 250 RoHS & Green SNAGCU Level-3-260C-168 HR 0 to 70 DDC232K DDC232CZXGR ACTIVE NFBGA ZXG 64 1000 RoHS & Green SNAGCU Level-3-260C-168 HR 0 to 70 DDC232 DDC232CZXGT ACTIVE NFBGA ZXG 64 250 RoHS & Green SNAGCU Level-3-260C-168 HR 0 to 70 DDC232 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of