DLP2010FQJ

DLP2010 DLPS123B – FEBRUARY 2019 – REVISED MAY 2022 DLP2010 .2 WVGA DMD 1 Features 3 Description • The DLP2010 digital micromirror device (DMD) is a digitally controlled micro-opto-electromechanical system (MOEMS) spatial light modulator (SLM). When coupled to an appropriate optical system, this DMD is capable of displaying images, video, and patterns. This device is a component of the chipset that includes the DLP2010 DMD, DLPC3430 or DLPC3435 controller and DLPA200x/ DLPA3000 PMIC/LED driver. The compact physical size of this DMD can be used in portable equipment where small form factor and low power is important. The compact package compliments the small size of the LEDs for space-constrained light engines. • • 0.2-Inch (5.29-mm) diagonal micromirror array – Displays 854 × 480 pixel array, in an orthogonal layout – 5.4-micron micromirror pitch – ±17° micromirror tilt (relative to flat surface) – Side illumination for optimal efficiency and optical engine size – Polarization-independent aluminum micromirror surface 4-Bit SubLVDS input data bus Dedicated DLPC3430, or DLPC3435 display controllers and DLPA200x/DLPA3000 PMIC and LED driver for reliable operation 2 Applications • • • Embedded displays for products including: – Tablets, mobile phones – Artificial intelligence (AI) assistants, smart speakers Control panels, security systems, and thermostats Wearable displays Visit the getting started with TI DLP®PicoTM display technology page to learn how to get started with the DLP2010. The ecosystem includes established resources to help the user accelerate the design cycle, which include production ready optical modules, optical modules manufactures, and design houses. Device Information PART NUMBER(1) DLP2010 (1) DLPC343x Display Controller 600-MHz SubLVDS DDR Interface FQJ (40) BODY SIZE (NOM) 15.9 mm × 5.3 mm For all available packages, see the orderable addendum at the end of the data sheet. D_P(0) D_N(0) VOFFSET D_P(1) D_N(1) VRESET VBIAS D_P(2) D_N(2) DLPA2000 (PMIC and LED Driver) DLP2010 DMD D_P(3) D_N(3) Digital Micromirror Device DCLK_P DCLK_N 120-MHz SDR Interface PACKAGE VDDI DMD_DEN_ARSTZ VDD LS_WDATA LS_CLK LS_RDATA VSS (System signal routing omitted for clarity) 0.2 WVGA Chipset An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DLP2010 www.ti.com DLPS123B – FEBRUARY 2019 – REVISED MAY 2022 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 6 Specifications.................................................................. 6 6.1 Absolute Maximum Ratings........................................ 6 6.2 Storage Conditions..................................................... 7 6.3 ESD Ratings............................................................... 7 6.4 Recommended Operating Conditions.........................7 6.5 Thermal Information....................................................9 6.6 Electrical Characteristics.............................................9 6.7 Timing Requirements................................................ 11 6.8 Switching Characteristics(1) ..................................... 14 6.9 System Mounting Interface Loads............................ 16 6.10 Physical Characteristics of the Micromirror Array... 17 6.11 Micromirror Array Optical Characteristics............... 18 6.12 Window Characteristics.......................................... 20 6.13 Chipset Component Usage Specification............... 20 6.14 Software Requirements.......................................... 20 7 Detailed Description......................................................21 7.1 Overview................................................................... 21 7.2 Functional Block Diagram......................................... 21 7.3 Feature Description...................................................22 7.4 Device Functional Modes..........................................22 7.5 Optical Interface and System Image Quality Considerations............................................................ 22 7.6 Micromirror Array Temperature Calculation.............. 23 7.7 Micromirror Landed-On/Landed-Off Duty Cycle....... 24 8 Application and Implementation.................................. 28 8.1 Application Information............................................. 28 8.2 Typical Application.................................................... 28 9 Power Supply Recommendations................................31 9.1 DMD Power Supply Power-Up Procedure................ 31 9.2 DMD Power Supply Power-Down Procedure........... 31 9.3 Power Supply Sequencing Requirements................ 32 10 Layout...........................................................................34 10.1 Layout Guidelines................................................... 34 10.2 Layout Example...................................................... 34 11 Device and Documentation Support..........................36 11.1 Device Support........................................................36 11.2 Related Links.......................................................... 36 11.3 Receiving Notification of Documentation Updates.. 36 11.4 Support Resources................................................. 37 11.5 Trademarks............................................................. 37 11.6 Electrostatic Discharge Caution.............................. 37 11.7 Glossary.................................................................. 37 12 Mechanical, Packaging, and Orderable Information.................................................................... 38 4 Revision History Changes from Revision A (January 2022) to Revision B (May 2022) Page • Updated Absolute Maximum Ratings disclosure to the latest TI standard......................................................... 6 • Updated Micromirror Array Optical Characteristics ......................................................................................... 18 • Added Third-Party Products Disclaimer ...........................................................................................................36 Changes from Revision * (February 2019) to Revision A (January 2022) Page • Updated the numbering format for tables, figures, and cross-references throughout the document..................1 • Updated |TDELTA| MAX from 30°C to 15°C..........................................................................................................7 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010 DLP2010 www.ti.com DLPS123B – FEBRUARY 2019 – REVISED MAY 2022 5 Pin Configuration and Functions Figure 5-1. FQJ Package 40-Pin Connector Bottom View Table 5-1. Pin Functions – Connector Pins(1) PIN NAME NO. TYPE SIGNAL DATA RATE DESCRIPTION PACKAGE NET LENGTH(2) (mm) DATA INPUTS D_N(0) G4 I SubLVDS Double Data, Negative 7.03 D_P(0) G3 I SubLVDS Double Data, Positive 7.03 D_N(1) G8 I SubLVDS Double Data, Negative 7.03 D_P(1) G7 I SubLVDS Double Data, Positive 7.03 D_N(2) H5 I SubLVDS Double Data, Negative 7.02 D_P(2) H6 I SubLVDS Double Data, Positive 7.02 D_N(3) H1 I SubLVDS Double Data, Negative 7.00 D_P(3) H2 I SubLVDS Double Data, Positive 7.00 DCLK_N H9 I SubLVDS Double Clock, Negative 7.03 DCLK_P H10 I SubLVDS Double Clock, Positive 7.03 CONTROL INPUTS Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010 3 DLP2010 www.ti.com DLPS123B – FEBRUARY 2019 – REVISED MAY 2022 Table 5-1. Pin Functions – Connector Pins(1) (continued) PIN SIGNAL G12 I LPSDR(1) LS_CLK G19 I LPSDR LS_WDATA G18 I LPSDR LS_RDATA G11 O LPSDR H17 Power Supply voltage for positive bias level at micromirrors NO. DMD_DEN_ARSTZ DATA RATE PACKAGE NET LENGTH(2) (mm) TYPE NAME DESCRIPTION Asynchronous reset DMD signal. A low signal places the DMD in reset. A high signal releases the DMD from reset and places it in active mode. 5.72 Single Clock for low-speed interface 3.54 Single Write data for low-speed interface 3.54 Single Read data for low-speed interface 8.11 POWER VBIAS(3) VOFFSET(3) H13 Power Supply voltage for HVCMOS core logic. Includes: supply voltage for stepped high level at micromirror address electrodes and supply voltage for offset level at micromirrors VRESET(3) H18 Power Supply voltage for negative reset level at micromirrors VDD(3) G20 Power VDD H14 Power VDD H15 Power VDD H16 Power VDD H19 Power VDD H20 Power VDDI(3) G1 Power VDDI G2 Power VDDI G5 Power VDDI G6 Power VSS(3) G9 Ground VSS G10 Ground VSS G13 Ground VSS G14 Ground VSS G15 Ground VSS G16 Ground VSS G17 Ground VSS H3 Ground VSS H4 Ground VSS H7 Ground VSS H8 Ground VSS H11 Ground VSS H12 Ground (1) (2) (3) 4 Supply voltage for micromirror low voltage CMOS core logic includes supply voltage for LPSDR inputs and supply voltage for normal high level at micromirror address electrodes. Supply voltage for SubLVDS receivers Ground. Common return for all power. Low speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard No. 209B, Low Power Double Data Rate (LPDDR) JESD209B. Net trace lengths inside the package: Relative dielectric constant for the FQJ ceramic package is 9.8. Propagation speed = 11.8 / sqrt(9.8) = 3.769 inches/ns. Propagation delay = 0.265 ns/inch = 265 ps/inch = 10.43 ps/mm. The following power supplies are all required to operate the DMD: VSS, VDD, VDDI, VOFFSET, VBIAS, VRESET. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010 DLP2010 www.ti.com DLPS123B – FEBRUARY 2019 – REVISED MAY 2022 Table 5-2. Pin Functions – Test Pads NUMBER SYSTEM BOARD NUMBER SYSTEM BOARD A2 Do not connect D2 Do not connect A3 Do not connect D3 Do not connect A4 Do not connect D17 Do not connect A5 Do not connect D18 Do not connect A6 Do not connect A7 Do not connect E2 Do not connect A8 Do not connect E3 Do not connect A9 Do not connect E17 Do not connect A10 Do not connect E18 Do not connect A11 Do not connect A12 Do not connect F1 Do not connect A13 Do not connect F2 Do not connect A14 Do not connect F3 Do not connect A15 Do not connect F4 Do not connect A16 Do not connect F5 Do not connect A17 Do not connect F6 Do not connect A18 Do not connect F7 Do not connect A19 Do not connect F8 Do not connect F9 Do not connect B2 Do not connect F10 Do not connect B3 Do not connect F11 Do not connect B17 Do not connect F12 Do not connect B18 Do not connect F13 Do not connect F14 Do not connect C2 Do not connect F15 Do not connect C3 Do not connect F16 Do not connect C17 Do not connect F17 Do not connect C18 Do not connect F18 Do not connect F19 Do not connect Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010 5 DLP2010 www.ti.com DLPS123B – FEBRUARY 2019 – REVISED MAY 2022 6 Specifications 6.1 Absolute Maximum Ratings See (1) Supply voltage MIN MAX VDD for LVCMOS core logic(2) Supply voltage for LPSDR low speed interface –0.5 2.3 VDDI for SubLVDS receivers(2) –0.5 2.3 VOFFSET for HVCMOS and micromirror electrode(2) (3) –0.5 10.6 VBIAS for micromirror electrode(2) –0.5 19 VRESET for micromirror electrode(2) –15 0.5 | VDDI–VDD | delta (absolute value)(4) 0.3 | VBIAS–VOFFSET | delta (absolute value)(5) 11 | VBIAS–VRESET | Input voltage Input pins Clock frequency –0.5 VDD + 0.5 for other inputs SubLVDS(2) (7) –0.5 VDDI + 0.5 | VID | SubLVDS input differential voltage (absolute value)(7) IID ƒclock ƒclock (1) (2) (3) (4) (5) (6) (7) (8) (9) 6 V 34 for other inputs LPSDR(2) TARRAY and TWINDOW Environmental delta (absolute value)(6) UBIT V 810 mV SubLVDS input differential current 8.1 mA Clock frequency for low speed interface LS_CLK 130 Clock frequency for high speed interface DCLK 620 Temperature – operational(8) Temperature – non-operational(8) –20 90 –40 90 TDP Dew Point Temperature - operating and non-operating (noncondensing) 81 |TDELTA| Absolute Temperature delta between any point on the window edge and the ceramic test point TP1(9) 30 MHz °C Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. All voltage values are with respect to the ground terminals (VSS). The following power supplies are all required to operate the DMD: VSS, VDD, VDDI, VOFFSET, VBIAS, and VRESET. VOFFSET supply transients must fall within specified voltages. Exceeding the recommended allowable absolute voltage difference between VDDI and VDD may result in excessive current draw. Exceeding the recommended allowable absolute voltage difference between VBIAS and VOFFSET may result in excessive current draw. Exceeding the recommended allowable absolute voltage difference between VBIAS and VRESET may result in excessive current draw. This maximum input voltage rating applies when each input of a differential pair is at the same voltage potential. Sub-LVDS differential inputs must not exceed the specified limit or damage may result to the internal termination resistors. The highest temperature of the active array (as calculated by the Section 7.6), or of any point along the Window Edge as defined in Figure 7-1. The locations of thermal test points TP2 and TP3 in Figure 7-1 are intended to measure the highest window edge temperature. If a particular application causes another point on the window edge to be at a higher temperature, that point should be used. Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in Figure 7-1. The window test points TP2 and TP3 shown in Figure 7-1 are intended to result in the worst case delta. If a particular application causes another point on the window edge to result in a larger delta temperature, that point should be used. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010 DLP2010 www.ti.com DLPS123B – FEBRUARY 2019 – REVISED MAY 2022 6.2 Storage Conditions applicable for the DMD as a component or non-operational in a system TDMD DMD storage temperature TDP-AVG Average dew point temperature, (non-condensing)(1) (non-condensing)(2) TDP-ELR Elevated dew point temperature range, CTELR Cumulative time in elevated dew point temperature range (1) (2) MIN MAX UNIT –40 85 °C 24 °C 28 36 °C 6 Months The average over time (including storage and operating) that the device is not in the elevated dew point temperature range. Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total cumulative time of CTELR. 6.3 ESD Ratings V(ESD) (1) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) VALUE UNIT ±2000 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. 6.4 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted)(1) (2) (3) MIN NOM MAX UNIT SUPPLY VOLTAGE RANGE(4) VDD Supply voltage for LVCMOS core logic Supply voltage for LPSDR low-speed interface 1.65 1.8 1.95 V VDDI Supply voltage for SubLVDS receivers 1.65 1.8 1.95 V VOFFSET Supply voltage for HVCMOS and micromirror electrode(5) 9.5 10 10.5 V VBIAS Supply voltage for mirror electrode VRESET Supply voltage for micromirror electrode 17.5 18 18.5 V –14.5 –14 –13.5 V |VDDI–VDD| Supply voltage delta (absolute value)(6) 0.3 V |VBIAS–VOFFSET| Supply voltage delta (absolute value)(7) 10.5 V value)(8) 33 V |VBIAS–VRESET| Supply voltage delta (absolute CLOCK FREQUENCY ƒclock Clock frequency for low speed interface LS_CLK(9) 108 120 MHz ƒclock Clock frequency for high speed interface DCLK(10) 300 600 MHz 44% 56% Duty cycle distortion DCLK SUBLVDS INTERFACE(10) | VID | SubLVDS input differential voltage (absolute value) Figure 6-8, Figure 6-9 150 250 350 mV VCM Common mode voltage Figure 6-8, Figure 6-9 700 900 1100 mV VSUBLVDS SubLVDS voltage Figure 6-8, Figure 6-9 575 1225 mV ZLINE Line differential impedance (PWB/trace) 90 100 110 Ω ZIN Internal differential termination resistance Figure 6-10 80 100 120 Ω 100-Ω differential PCB trace 6.35 152.4 mm Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010 7 DLP2010 www.ti.com DLPS123B – FEBRUARY 2019 – REVISED MAY 2022 6.4 Recommended Operating Conditions (continued) over operating free-air temperature range (unless otherwise noted)(1) (2) (3) MIN NOM MAX UNIT ENVIRONMENTAL Array Temperature – long-term operational(11) 0 40 to 70(13) Array Temperature - short-term operational, 25 hr max(12) (15) –20 –10 Array Temperature - short-term operational, 500 hr max(12) (15) –10 0 Array Temperature – short-term operational, 500 hr max(12) (15) 70 75 (12) (13) (14) TARRAY |TDELTA | Absolute Temperature difference between any point on the window edge and the ceramic test point TP1 (16) 15 °C TWINDOW Window temperature – operational(11) (17) 90 °C TDP-AVG Average dew point temperature (noncondensing)(18) 24 °C TDP-ELR Elevated dew point temperature range (noncondensing)(19) 36 °C CTELR Cumulative time in elevated dew point temperature range 6 Months ILLUV Illumination wavelengths < 420 nm(11) ILLVIS Illumination wavelengths between 420 nm and 700 nm ILLIR Illumination wavelengths > 700 nm ILLθ (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) 8 °C Illumination marginal ray angle(20) 28 0.68 mW/cm2 Thermally limited 10 mW/cm2 55 deg Section 6.4 are applicable after the DMD is installed in the final product. The functional performance of the device specified in this datasheet is achieved when operating the device within the limits defined by the Section 6.4. No level of performance is implied when operating the device above or below the Section 6.4 limits. The following power supplies are all required to operate the DMD: VSS, VDD, VDDI, VOFFSET, VBIAS, and VRESET. All voltage values are with respect to the ground pins (VSS). VOFFSET supply transients must fall within specified maximum voltages. To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than specified limit. To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit. To prevent excess current, the supply voltage delta |VBIAS – VRESET| must be less than specified limit. LS_CLK must run as specified to ensure internal DMD timing for reset waveform commands. Refer to the SubLVDS timing requirements in Section 6.7. Simultaneous exposure of the DMD to the maximum Section 6.4 for temperature and UV illumination will reduce device lifetime. The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1 (TP1) shown in Figure 7-1 and the Package Thermal Resistance using Section 7.6. Per Figure 6-1, the maximum operational array temperature should be derated based on the micromirror landed duty cycle that the DMD experiences in the end application. Refer to Section 7.7 for a definition of micromirror landed duty cycle. Long-term is defined as the usable life of the device Short-term is the total cumulative time over the useful life of the device. Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge shown in Figure 7-1. The window test points TP2 and TP3 shown in Figure 7-1 are intended to result in the worst case delta temperature. If a particular application causes another point on the window edge to result in a larger delta temperature, that point should be used. Window temperature is the highest temperature on the window edge shown in Figure 7-1. The locations of thermal test points TP2 and TP3 in Figure 7-1 are intended to measure the highest window edge temperature. If a particular application causes another point on the window edge to result in a larger delta temperature, that point should be used. The average over time (including storage and operating) that the device is not in the elevated dew point temperature range. Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total cumulative time of CTELR. The maximum marginal ray angle of the incoming illumination light at any point in the micromirror array, including Pond of Micromirrors (POM), should not exceed 55 degrees from the normal to the device array plane. The device window aperture has not necessarily been designed to allow incoming light at higher maximum angles to pass to the micromirrors, and the device performance has not been tested nor qualified at angles exceeding this. Illumination light exceeding this angle outside the micromirror array (including POM) will contribute to thermal limitations described in this document, and may negatively affect lifetime. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010 DLP2010 www.ti.com DLPS123B – FEBRUARY 2019 – REVISED MAY 2022 Max Recommended Array Temperature – Operational (°C) 80 70 60 50 40 30 0/100 5/95 10/90 15/85 20/80 25/75 30/70 35/65 40/60 45/55 50/50 100/0 95/5 90/10 85/15 80/20 75/25 70/30 65/35 Micromirror Landed Duty Cycle 60/40 55/45 D001 Figure 6-1. Maximum Recommended Array Temperature – Derating Curve 6.5 Thermal Information DLP2010 THERMAL METRIC(1) FQJ Package UNIT 40 PINS Thermal resistance Active area to test point 1 (TP1)(1) (1) 7.9 °C/W The DMD is designed to conduct absorbed and dissipated heat to the back of the package. The cooling system must be capable of maintaining the package within the temperature range specified in the Section 6.4. The total heat load on the DMD is largely driven by the incident light absorbed by the active area; although other contributions include light energy absorbed by the window aperture and electrical power dissipation of the array. Optical systems should be designed to minimize the light energy falling outside the window clear aperture since any additional thermal load in this area can significantly degrade the reliability of the device. 6.6 Electrical Characteristics Over operating free-air temperature range (unless otherwise noted)(1) PARAMETER TEST CONDITIONS(2) MIN TYP MAX UNIT CURRENT IDD Supply current: VDD(3) (4) IDDI Supply current: VDDI(3) (4) IOFFSET Supply current: VOFFSET(5) (6) IBIAS Supply current: VBIAS(5) (6) IRESET Supply current: VRESET(6) VDD = 1.95 V VDD = 1.8 V 34.7 27.5 VDDI = 1.95 V VDD = 1.8 V 9.4 6.6 VOFFSET = 10.5 V VOFFSET = 10 V 1.7 0.9 VBIAS = 18.5 V VBIAS = 18 V 0.4 0.2 VRESET = –14.5 V VRESET = –14 V 2 1.2 mA mA mA mA mA POWER(7) PDD Supply power dissipation: VDD(3) (4) PDDI Supply power dissipation: VDDI(3) (4) POFFSET Supply power dissipation: VOFFSET(5) (6) PBIAS Supply power dissipation: VBIAS(5) (6) VDD = 1.95 V VDD = 1.8 V 67.7 49.5 VDDI = 1.95 V VDD = 1.8 V 18.3 11.9 VOFFSET = 10.5 V VOFFSET = 10 V 17.9 9 VBIAS = 18.5 V VBIAS = 18 V 7.4 3.6 mW mW mW mW Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010 9 DLP2010 www.ti.com DLPS123B – FEBRUARY 2019 – REVISED MAY 2022 6.6 Electrical Characteristics (continued) Over operating free-air temperature range (unless otherwise noted)(1) PARAMETER PRESET Supply power dissipation: VRESET(6) PTOTAL Supply power dissipation: Total LPSDR VIH(DC) TEST CONDITIONS(2) TYP MAX 29 VRESET = –14 V 16.8 90.8 140.3 UNIT mW mW INPUT(8) DC input high voltage(9) voltage(9) VIL(DC) DC input low VIH(AC) AC input high voltage(9) voltage(9) VIL(AC) AC input low ∆VT Hysteresis ( VT+ – VT– ) Figure 6-11 IIL Low–level input current VDD = 1.95 V; VI = 0 V IIH High–level input current VDD = 1.95 V; VI = 1.95 V LPSDR MIN VRESET = –14.5 V 0.7 × VDD VDD + 0.3 V –0.3 0.3 × VDD V 0.8 × VDD VDD + 0.3 V –0.3 0.2 × VDD V 0.1 × VDD 0.4 × VDD V –100 nA 100 nA OUTPUT(10) VOH DC output high voltage IOH = –2 mA 0.8 × VDD V VOL DC output low voltage IOL = 2 mA 0.2 × VDD Input capacitance LPSDR ƒ = 1 MHz 10 Input capacitance SubLVDS ƒ = 1 MHz 20 Output capacitance ƒ = 1 MHz 10 pF Reset group capacitance ƒ = 1 MHz; (480 × 108) micromirrors 113 pF V CAPACITANCE CIN COUT CRESET 95 pF (1) (2) (3) (4) (5) (6) (7) (8) (9) Device electrical characteristics are over Section 6.4 unless otherwise noted. All voltage values are with respect to the ground pins (VSS). To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than specified limit. Supply power dissipation based on non–compressed commands and data. To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit. Supply power dissipation based on 3 global resets in 200 µs. The following power supplies are all required to operate the DMD: VSS, VDD, VDDI, VOFFSET, VBIAS, VRESET. LPSDR specifications are for pins LS_CLK and LS_WDATA. Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard No. 209B, Low-Power Double Data Rate (LPDDR) JESD209B. (10) LPSDR specification is for pin LS_RDATA. 10 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010 DLP2010 www.ti.com DLPS123B – FEBRUARY 2019 – REVISED MAY 2022 6.7 Timing Requirements Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted. MIN NOM MAX UNIT 1 3 V/ns (70% to 20%) × VDD, Figure 6-3 1 3 V/ns (20% to 80%) × VDD, Figure 6-3 0.25 (80% to 20%) × VDD, Figure 6-3 0.25 LPSDR Rise slew rate(1) tR (30% to 80%) × VDD, Figure 6-3 rate(1) tF Fall slew tR Rise slew rate(2) rate(2) tF Fall slew tC Cycle time LS_CLK, Figure 6-2 tW(H) Pulse duration LS_CLK high 50% to 50% reference points, Figure 6-2 tW(L) Pulse duration LS_CLK low 50% to 50% reference points, Figure 6-2 tSU Setup time tH tWINDOW tDERATING 7.7 V/ns V/ns 8.3 ns 3.1 ns 3.1 ns LS_WDATA valid before LS_CLK ↑, Figure 6-2 1.5 ns Hold time LS_WDATA valid after LS_CLK ↑, Figure 6-2 1.5 ns Window time(1) (3) Setup time + Hold time, Figure 6-2 3.0 ns Window time derating(1) (3) For each 0.25 V/ns reduction in slew rate below 1 V/ns, Figure 6-5 tR Rise slew rate 20% to 80% reference points, Figure 6-4 tF Fall slew rate 80% to 20% reference points, Figure 6-4 tC Cycle time LS_CLK, Figure 6-6 tW(H) Pulse duration DCLK high 50% to 50% reference points, Figure 6-6 0.71 ns tW(L) Pulse duration DCLK low 50% to 50% reference points, Figure 6-6 0.71 ns tSU Setup time D(0:3) valid before DCLK ↑ or DCLK ↓, Figure 6-6 tH Hold time D(0:3) valid after DCLK ↑ or DCLK ↓, Figure 6-6 tWINDOW Window time Setup time + Hold time, Figure 6-6, Figure 6-7 3.0 ns tLVDS- Power-up receiver(4) 0.35 ns SubLVDS ENABLE+REFGEN (1) (2) (3) (4) 0.7 1 V/ns 0.7 1 V/ns 1.61 1.67 ns 2000 ns Specification is for LS_CLK and LS_WDATA pins. Refer to LPSDR input rise slew rate and fall slew rate in Figure 6-3. Specification is for DMD_DEN_ARSTZ pin. Refer to LPSDR input rise and fall slew rate in Figure 6-3. Window time derating example: 0.5-V/ns slew rate increases the window time by 0.7 ns, from 3 to 3.7 ns. Specification is for SubLVDS receiver time only and does not take into account commanding and latency after commanding. tC tw(H) tw(L) 50% LS_CLK tSU| tH| 50% LS_WDATA tWINDOW| A. Low-speed interface is LPSDR and adheres to the Section 6.6 and AC/DC Operating Conditions table in JEDEC Standard No. 209B, Low Power Double Data Rate (LPDDR) JESD209B. Figure 6-2. LPSDR Switching Parameters Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010 11 DLP2010 www.ti.com DLPS123B – FEBRUARY 2019 – REVISED MAY 2022 LS_CLK, LS_WDATA DMD_DEN_ARSTZ 1.0 * VDD 1.0 * VDD 0.8 * VDD 0.7 * VDD VIH(AC) VIH(DC) 0.3 * VDD 0.2 * VDD VIL(DC) VIL(AC) 0.8 * VDD 0.2 * VDD 0.0 * VDD 0.0 * VDD tr tf tr tf Figure 6-3. LPSDR Input Rise and Fall Slew Rate VDCLK_P , VDCLK_N VD_P(0:7) , VD_N(0:7) 1.0 * VID 0.8 * VID VCM 0.2 * VID 0.0 * VID tr tf Figure 6-4. SubLVDS Input Rise and Fall Slew Rate VIH MIN LS_CLK Midpoint VIL MAX tSU tH VIH MIN LS_WDATA Midpoint VIL MAX tWINDOW VIH MIN LS_CLK Midpoint VIL MAX tDERATING tSU tH VIH MIN LS_WDATA Midpoint VIL MAX tWINDOW Figure 6-5. Window Time Derating Concept 12 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010 DLP2010 www.ti.com DLPS123B – FEBRUARY 2019 – REVISED MAY 2022 tC tW(L) tW(H) DCLK_P 50% DCLK_N tSU| tH| D_P(0:3) 50% D_N(0:3) tWINDOW| Figure 6-6. SubLVDS Switching Parameters tC (1) tWINDOW | DCLK_P 50% DCLK_N ¼ tC| ¼ tC| D_P(0:3) 50% D_N(0:3) (1) High-speed training scan window Note: Refer to Section 7.3.3 for details. Figure 6-7. High-Speed Training Scan Window + ± VCM = (VIP + VIN) 2 DCLK_P, D_P(0:3) VID DCLK_N, D_N(0:3) VCM VIP SubLVDS Receiver VIN Figure 6-8. SubLVDS Voltage Parameters 1.255 V VLVDS(max) VID VCM VLVDS(min) 0.575 V A. B. VSubLVDS(max) = VCM(max) + | ½ × VID(max) | VSubLVDS(min) = VCM(min) – | ½ × VID(max) | Figure 6-9. SubLVDS Waveform Parameters Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010 13 DLP2010 www.ti.com DLPS123B – FEBRUARY 2019 – REVISED MAY 2022 DCLK_P, D_P(0:3) ESD Internal Termination SubLVDS Receiver DCLK_N, D_N(0:3) ESD Figure 6-10. SubLVDS Equivalent Input Circuit VDD Voltage (%) LS_CLK and LS_WDATA VIH VT+ 'VT VT± VIL Time Figure 6-11. LPSDR Input Hysteresis LS_CLK LS_WDATA Stop Start tPD LS_RDATA Acknowledge Figure 6-12. LPSDR Read Out Data Sheet Timing Reference Point Device Pin Output Under Test Tester Channel CL A. See Section 7.3.4 for more information. Figure 6-13. Test Load Circuit for Output Propagation Measurement 6.8 Switching Characteristics(1) Over operating free-air temperature range (unless otherwise noted) PARAMETER tPD TEST CONDITIONS Output propagation, Clock to Q, rising edge of LS_CLK input to LS_RDATA output. Figure 6-12 Slew rate, LS_RDATA 14 MIN CL = 45 pF MAX 15 0.5 Submit Document Feedback TYP UNIT ns V/ns Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010 DLP2010 www.ti.com DLPS123B – FEBRUARY 2019 – REVISED MAY 2022 Over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS Output duty cycle distortion, LS_RDATA (1) MIN 40% TYP MAX UNIT 60% Device electrical characteristics are over Section 6.4 unless otherwise noted. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010 15 DLP2010 www.ti.com DLPS123B – FEBRUARY 2019 – REVISED MAY 2022 6.9 System Mounting Interface Loads PARAMETER MIN Connector area (see Figure 6-14) Maximum system mounting interface load to be applied to the: DMD mounting area uniformly distributed over 4 areas (see Figure 6-14) NOM MAX UNIT 45 N 100 N šµu Z [ Œ (3 places) šµu Z [ Œ (1 place) (4 ‰o • }‰‰}•]š DMD Mounting Area šµu• Z [ v Z [) Connector Area 16 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010 DLP2010 www.ti.com DLPS123B – FEBRUARY 2019 – REVISED MAY 2022 6.10 Physical Characteristics of the Micromirror Array PARAMETER UNIT Number of active columns See Figure 6-15 854 micromirrors Number of active rows See Figure 6-15 480 micromirrors Micromirror (pixel) pitch See Figure 6-16 5.4 µm Micromirror active array width Micromirror pitch × number of active columns; see Figure 6-15 4.6116 mm Micromirror active array height Micromirror pitch × number of active rows; see Figure 6-15 2.592 mm 20 micromirrors/side Micromirror active border (1) VALUE Pond of micromirror (POM)(1) The structure and qualities of the border around the active array includes a band of partially functional micromirrors called the POM. These micromirrors are structurally and/or electrically prevented from tilting toward the bright or ON state, but still require an electrical bias to tilt toward OFF. Width . Mirror 479 Mirror 478 Mirror 477 Mirror 476 Illumination 854 × 480 mirrors Height Mirror 3 Mirror 2 Mirror 1 Mirror 853 Mirror 852 Mirror 851 Mirror 850 Mirror 3 Mirror 2 Mirror 1 Mirror 0 Mirror 0 Figure 6-15. Micromirror Array Physical Characteristics H° H° H° H° Figure 6-16. Mirror (Pixel) Pitch Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010 17 DLP2010 www.ti.com DLPS123B – FEBRUARY 2019 – REVISED MAY 2022 6.11 Micromirror Array Optical Characteristics PARAMETER Micromirror tilt angle TEST CONDITIONS DMD landed Micromirror tilt angle tolerance(2) (3) (4) (5) Micromirror tilt direction(6) (7) 180 270 Typical Performance (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) 18 degrees degrees 3 10 Bright pixel(s) in active area (11) Gray 10 Screen (12) 0 Bright pixel(s) in the POM (13) Gray 10 Screen (12) 1 White Screen 4 Adjacent pixel(s) (15) Any Screen 0 Unstable pixel(s) in active area (16) Any Screen 0 Image performance(10) Dark pixel(s) in the active area (14) (6) 1 UNIT degrees 1.4 Landed OFF state Typical Performance MAX 17 Landed ON state Micromirror switching time(9) (5) NOM –1.4 Micromirror crossover time(8) (1) (2) (3) (4) MIN state(1) μs micromirrors Measured relative to the plane formed by the overall micromirror array. Additional variation exists between the micromirror array and the package datums. Represents the landed tilt angle variation relative to the nominal landed tilt angle. Represents the variation that can occur between any two individual micromirrors, located on the same device or located on different devices. For some applications, it is critical to account for the micromirror tilt angle variation in the overall system optical design. With some system optical designs, the micromirror tilt angle variation within a device may result in perceivable non-uniformities in the light field reflected from the micromirror array. With some system optical designs, the micromirror tilt angle variation between devices may result in colorimetry variations, system efficiency variations or system contrast variations. When the micromirror array is landed (not parked), the tilt direction of each individual micromirror is dictated by the binary contents of the CMOS memory cell associated with each individual micromirror. A binary value of 1 results in a micromirror landing in the ON state direction. A binary value of 0 results in a micromirror landing in the OFF state direction. See Figure 6-17 Micromirror tilt direction is measured as in a typical polar coordinate system: Measuring counter-clockwise from a 0° reference which is aligned with the +X Cartesian axis. The time required for a micromirror to nominally transition from one landed state to the opposite landed state. The minimum time between successive transitions of a micromirror. Conditions of Acceptance: All DMD image quality returns will be evaluated using the following projected image test conditions: Test set degamma shall be linear Test set brightness and contrast shall be set to nominal The diagonal size of the projected image shall be a minimum of 20 inches The projections screen shall be 1X gain The projected image shall be inspected from a 38 inch minimum viewing distance The image shall be in focus during all image quality tests Bright pixel definition: A single pixel or mirror that is stuck in the ON position and is visibly brighter than the surrounding pixels Gray 10 screen definition: All areas of the screen are colored with the following settings: Red = 10/255 Green = 10/255 Blue = 10/255 POM definition: Rectangular border of off-state mirrors surrounding the active area Dark pixel definition: A single pixel or mirror that is stuck in the OFF position and is visibly darker than the surrounding pixels Adjacent pixel definition: Two or more stuck pixels sharing a common border or common point, also referred to as a cluster Unstable pixel definition: A single pixel or mirror that does not operate in sequence with parameters loaded into memory. The unstable pixel appears to be flickering asynchronously with the image Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010 DLP2010 www.ti.com DLPS123B – FEBRUARY 2019 – REVISED MAY 2022 (843, 479) Incident illumination light path On-state landed edge (0, 0) Tilted axis of pixel rotation Off-state landed edge Off-state light path Figure 6-17. Landed Pixel Orientation and Tilt Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010 19 DLP2010 www.ti.com DLPS123B – FEBRUARY 2019 – REVISED MAY 2022 6.12 Window Characteristics PARAMETER(1) MIN Window material designation Window refractive index Window MAX UNIT Corning Eagle XG at wavelength 546.1 nm 1.5119 aperture(2) See (2) Illumination overfill(3) See (3) Window transmittance, single-pass through both surfaces and glass Minimum within the wavelength range 420 to 680 nm. Applies to all angles 0° to 30° AOI. 97% Window Transmittance, single-pass through both surfaces and glass Average over the wavelength range 420 to 680 nm. Applies to all angles 30° to 45° AOI. 97% (1) (2) (3) NOM See Section 7.5 for more information. See the package mechanical characteristics for details regarding the size and location of the window aperture. The active area of the DLP2010 device is surrounded by an aperture on the inside of the DMD window surface that masks structures of the DMD device assembly from normal view. The aperture is sized to anticipate several optical conditions. Overfill light illuminating the area outside the active array can scatter and create adverse effects to the performance of an end application using the DMD. The illumination optical system should be designed to limit light flux incident outside the active array to less than 10% of the average flux level in the active area. Depending on the particular system's optical architecture and assembly tolerances, the amount of overfill light on the outside of the active array may cause system performance degradation. 6.13 Chipset Component Usage Specification The DLP2010 is a component of one or more TI DLP® chipsets. Reliable function and operation of the DLP2010 requires that it be used in conjunction with the other components of the applicable DLP chipset, including those components that contain or implement TI DMD control technology. TI DMD control technology is the TI technology and devices for operating or controlling a DLP DMD. Note TI assumes no responsibility for image quality artifacts or DMD failures caused by optical system operating conditions exceeding limits described previously. 6.14 Software Requirements CAUTION The DLP2010 DMD has mandatory software requirements. Refer to Software Requirements for TI DLP®Pico® TRP Digital Micromirror Devices application report for additional information. Failure to use the specified software will result in failure at power up. 20 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010 DLP2010 www.ti.com DLPS123B – FEBRUARY 2019 – REVISED MAY 2022 7 Detailed Description 7.1 Overview The DLP2010 is a 0.2 inch diagonal spatial light modulator of aluminum micromirrors. Pixel array size is 854 columns by 480 rows in a square grid pixel arrangement. The electrical interface is sub low voltage differential signaling (SubLVDS) data. This DMD is part of the chipset that is composed of the DMD, DLPC3430 or DLPC3435 display controller and the DLPA200x/DLPA3000 PMIC and LED driver. To ensure reliable operation, the DMD must always be used with the DLPC3430 or DLPC3435 display controller and the DLPA200x/DLPA3000 PMIC and LED driver. VSS VDD VDDI VOFFSET VBIAS VRESET D_P(0:3) D_N(0:3) DCLK_P DCLK_N 7.2 Functional Block Diagram High-Speed Interface Misc Control Column Write Bit Lines (0,0) Voltage Generators Voltages SRAM Word Lines Row (479,853) Control Column Read Control VSS VDD VOFFSET VBIAS VRESET LS_RDATA LS_WDATA DMD_DEN_ARSTZ Low-Speed Interface Details omitted for clarity. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010 21 DLP2010 www.ti.com DLPS123B – FEBRUARY 2019 – REVISED MAY 2022 7.3 Feature Description 7.3.1 Power Interface The power management component DLPA200x/DLPA3000, contains three 3 regulated DC supplies for the DMD reset circuitry: VBIAS, VRESET and VOFFSET, as well as the two regulated DC supplies for the DLPC3430 or DLPC3435 controller. 7.3.2 Low-Speed Interface The low speed interface handles instructions that configure the DMD and control reset operation. LS_CLK is the low–speed clock, and LS_WDATA is the low speed data input. 7.3.3 High-Speed Interface The purpose of the high-speed interface is to transfer pixel data rapidly and efficiently, making use of high speed DDR transfer and compression techniques to save power and time. The high-speed interface uses differential SubLVDS receivers for inputs, with a dedicated clock. 7.3.4 Timing The data sheet provides timing test results at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be considered. Test Load Circuit for Output Propagation Measurement shows an equivalent test load circuit for the output under test. Timing reference loads are not intended as a precise representation of any particular system environment or depiction of the actual load presented by a production test. TI recommends that system designers use IBIS or other simulation tools to correlate the timing reference load to a system environment. The load capacitance value stated is intended for characterization and measurement of AC timing signals only. This load capacitance value does not indicate the maximum load the device is capable of driving. 7.4 Device Functional Modes DMD functional modes are controlled by the DLPC3430 or DLPC3435 controller. See the DLPC3430 or DLPC3435 controller data sheet or contact a TI applications engineer. 7.5 Optical Interface and System Image Quality Considerations Note TI assumes no responsibility for image quality artifacts or DMD failures caused by optical system operating conditions exceeding limits described previously. 7.5.1 Optical Interface and System Image Quality TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment optical performance involves making trade-offs between numerous component and system design parameters. Optimizing system optical performance and image quality strongly relate to optical system design parameter trades. Although it is not possible to anticipate every conceivable application, projector image quality and optical performance is contingent on compliance to the optical system operating conditions described in the following sections. 7.5.1.1 Numerical Aperture and Stray Light Control The angle defined by the numerical aperture of the illumination and projection optics at the DMD optical area is typically the same. Ensure this angle does not exceed the nominal device micromirror tilt angle unless appropriate apertures are added in the illumination or projection pupils to block out flat-state and stray light from the projection lens. The micromirror tilt angle defines DMD capability to separate the "ON" optical path from any other light path, including undesirable flat–state specular reflections from the DMD window, DMD border structures, or other system surfaces near the DMD such as prism or lens surfaces. If the numerical aperture exceeds the micromirror tilt angle, or if the projection numerical aperture angle is more than two degrees larger than the illumination numerical aperture angle (and vice versa), contrast degradation and objectionable artifacts in the display border and/or active area may occur. 22 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010 DLP2010 www.ti.com DLPS123B – FEBRUARY 2019 – REVISED MAY 2022 7.5.1.2 Pupil Match The optical and image quality specifications assume that the exit pupil of the illumination optics is nominally centered within 2° of the entrance pupil of the projection optics. Misalignment of pupils can create objectionable artifacts in the display border and/or active area. These artifacts may require additional system apertures to control, especially if the numerical aperture of the system exceeds the pixel tilt angle. 7.5.1.3 Illumination Overfill The active area of the device is surrounded by an aperture on the inside DMD window surface that masks structures of the DMD chip assembly from normal view, and is sized to anticipate several optical operating conditions. Overfill light illuminating the window aperture can create artifacts from the edge of the window aperture opening and other surface anomalies that may be visible on the screen. Be sure to design an illumination optical system that limits light flux incident anywhere on the window aperture from exceeding approximately 10% of the average flux level in the active area. Depending on the particular optical architecture, overfill light may require further reduction below the suggested 10% level in order to be acceptable. 7.6 Micromirror Array Temperature Calculation Illumination Direction Off-state Light Figure 7-1. DMD Thermal Test Points Micromirror array temperature can be computed analytically from measurement points on the outside of the package, the ceramic package thermal resistance, the electrical power dissipation, and the illumination heat load. The relationship between micromirror array temperature and the reference ceramic temperature is provided by the following equations: TARRAY = TCERAMIC + (QARRAY × RARRAY–TO–CERAMIC) (1) QARRAY = QELECTRICAL + QILLUMINATION (2) QILLUMINATION = (CL2W × SL) (3) where • TARRAY = Computed DMD array temperature (°C) • TCERAMIC = Measured ceramic temperature (°C), TP1 location in DMD Thermal Test Points Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010 23 DLP2010 www.ti.com DLPS123B – FEBRUARY 2019 – REVISED MAY 2022 • • • • • RARRAY–TO–CERAMIC = DMD package thermal resistance from array to outside ceramic (°C/W) specified in Thermal Information QARRAY = Total DMD power; electrical plus absorbed (calculated) (W) QELECTRICAL = Nominal DMD electrical power dissipation (W) CL2W = Conversion constant for screen lumens to absorbed optical power on the DMD (W/lm) specified below SL = Measured ANSI screen lumens (lm) Electrical power dissipation of the DMD is variable and depends on the voltages, data rates and operating frequencies. A nominal electrical power dissipation to use when calculating array temperature is 0.07 W. Absorbed optical power from the illumination source varies and depends on the operating state of the micromirrors and the intensity of the light source. Equation 1 through Equation 1 are valid for a 1-chip DMD system with total projection efficiency through the projection lens from DMD to the screen of 87%. The conversion constant CL2W is based on the DMD micromirror array characteristics. It assumes a spectral efficiency of 300 lm/W for the projected light and illumination distribution of 83.7% on the DMD active array, and 16.3% on the DMD array border and window aperture. The conversion constant is calculated to be 0.00266 W/lm. The following is a sample calculation for typical projection application: TCERAMIC = 55°C (measured) SL = 150 lm (measured) QELECTRICAL = 0.070 W CL2W = 0.00266 W/lm QARRAY = 0.070 W + (0.00266 W/lm × 150 lm) = 0.469 W TARRAY = 55°C + (0.469 W × 7.9°C/W) = 58.7°C 7.7 Micromirror Landed-On/Landed-Off Duty Cycle 7.7.1 Definition of Micromirror Landed-On and Landed-Off Duty Cycle The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the amount of time (as a percentage) that an individual micromirror is landed in the ON state versus the amount of time the same micromirror is landed in the OFF state. As an example, a landed duty cycle of 75/25 indicates that the referenced pixel is in the ON state 75% of the time (and in the OFF state 25% of the time), whereas 25/75 indicates that the pixel is in the OFF state 75% of the time. Likewise, 50/50 indicates that the pixel is ON 50% of the time and OFF 50% of the time. When assessing landed duty cycle, the time spent switching from the current state to the opposite state is considered negligible and is thus ignored. Because a micromirror can only be landed in one state or the other (ON or OFF), the two numbers (percentages) nominally add to 100.In practice, image processing algorithms in the DLP chipset can result a total of less that 100. 7.7.2 Landed Duty Cycle and Useful Life of the DMD Knowing the long-term average landed duty cycle (of the end product or application) is important because subjecting all (or a portion) of the DMD’s micromirror array (also called the active array) to an asymmetric landed duty cycle for a prolonged period of time can reduce the DMD’s usable life. It is the symmetry or asymmetry of the landed duty cycle that is relevant. The symmetry of the landed duty cycle is determined by how close the two numbers (percentages) are to being equal. For example, a landed duty cycle of 50/50 is perfectly symmetrical whereas a landed duty cycle of 100/0 or 0/100 is perfectly asymmetrical. 24 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010 DLP2010 www.ti.com DLPS123B – FEBRUARY 2019 – REVISED MAY 2022 7.7.3 Landed Duty Cycle and Operational DMD Temperature Operational DMD temperature and landed duty cycle interact to affect the usable life of the DMD. This interaction can be used to reduce the impact that an asymmetrical landed duty cycle has on the useable life of the DMD. Figure 6-1 describes this relationship. The importance of this curve is that: • • • All points along this curve represent the same usable life. All points above this curve represent lower usable life (and the further away from the curve, the lower the usable life). All points below this curve represent higher usable life (and the further away from the curve, the higher the usable life). In practice, this curve specifies the maximum operating DMD temperature that the DMD should be operated at for a give long-term average landed duty cycle. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application During a given period of time, the landed duty cycle of a given pixel depends on the image content being displayed by that pixel. In the simplest case for example, when the system displays pure-white on a given pixel for a given time period, that pixel operates very close to a 100/0 landed duty cycle during that time period. Likewise, when the system displays pure-black, the pixel operates very close to a 0/100 landed duty cycle. Between the two extremes (ignoring for the moment color and any image processing that may be applied to an incoming image), the landed duty cycle tracks one-to-one with the gray scale value, as shown in Table 7-1. Table 7-1. Grayscale Value and Landed Duty Cycle Grayscale Value Nominal Landed Duty Cycle 0% 0/100 10% 10/90 20% 20/80 30% 30/70 40% 40/60 50% 50/50 60% 60/40 70% 70/30 80% 80/20 90% 90/10 100% 100/0 To account for color rendition (and continuing to ignore image processing for this example) requires knowing both the color intensity (from 0% to 100%) for each constituent primary color (red, green, and/or blue) for the given pixel as well as the color cycle time for each primary color, where color cycle time describes the total percentage of the frame time that a given primary must be displayed in order to achieve the desired white point. During a given period of time, the nominal landed duty cycle of a given pixel can be calculated as shown in Equation 4: Landed Duty Cycle = (Red_Cycle_% × Red_Scale_Value) + (Green_Cycle_% × Green_Scale_Value) + (Blue_Cycle_% × Blue_Scale_Value) (4) where Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010 25 DLP2010 www.ti.com DLPS123B – FEBRUARY 2019 – REVISED MAY 2022 • • • Red_Cycle_% represents the percentage of the frame time that red displays to achieve the desired white point Green_Cycle_% represents the percentage of the frame time that green displays to achieve the desired white point Blue_Cycle_% represents the percentage of the frame time that blue displays to achieve the desired white point For example, assume that the ratio of red, green and blue color cycle times are as listed in Table 7-2 (in order to achieve the desired white point) then the resulting nominal landed duty cycle for various combinations of red, green, blue color intensities are as shown in Table 7-3. Table 7-2. Example Landed Duty Cycle for Full-Color Pixels Red Cycle Percentage Green Cycle Percentage Blue Cycle Percentage 50% 20% 30% Table 7-3. Color Intensity Combinations Red Scale Value Green Scale Value Blue Scale Value Nominal Landed Duty Cycle 0% 0% 0% 0/100 100% 0% 0% 50/50 0% 100% 0% 20/80 0% 0% 100% 30/70 12% 0% 0% 6/94 0% 35% 0% 7/93 0% 0% 60% 18/82 100% 100% 0% 70/30 0% 100% 100% 50/50 100% 0% 100% 80/20 12% 35% 0% 13/87 0% 35% 60% 25/75 12% 0% 60% 24/76 100% 100% 100% 100/0 The last factor to consider when estimating the landed duty cycle is any applied image processing. In the DLPC34xx controller family, the two functions which influence the actual landed duty cycle are Gamma and IntelliBright™, and bitplane sequencing rules. Gamma is a power function of the form Output_Level = A × Input_LevelGamma, where A is a scaling factor that is typically set to 1. In the DLPC34xx controller family, gamma is applied to the incoming image data on a pixel-by-pixel basis. A typical gamma factor is 2.2, which transforms the incoming data as shown in Figure 7-2. 26 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010 DLP2010 www.ti.com DLPS123B – FEBRUARY 2019 – REVISED MAY 2022 100 90 Output Level (%) 80 Gamma = 2.2 70 60 50 40 30 20 10 0 0 10 20 30 40 50 60 Input Level (%) 70 80 90 100 D002 Figure 7-2. Example of Gamma = 2.2 As shown in Figure 7-2, when the gray scale value of a given input pixel is 40% (before gamma is applied), then gray scale value is 13% after gamma is applied. Because gamma has a direct impact on the displayed gray scale level of a pixel, it also has a direct impact on the landed duty cycle of a pixel. The IntelliBright algorithms content adaptive illumination control (CAIC) and local area brightness boost (LABB) also apply transform functions on the gray scale level of each pixel. But while amount of gamma applied to every pixel (of every frame) is constant (the exponent, gamma, is constant), CAIC and LABB are both adaptive functions that can apply a different amounts of either boost or compression to every pixel of every frame. Be sure to account for any image processing which occurs before the controller. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010 27 DLP2010 www.ti.com DLPS123B – FEBRUARY 2019 – REVISED MAY 2022 8 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 8.1 Application Information The DMDs are spatial light modulators which reflect incoming light from an illumination source to one of two directions, with the primary direction being into a projection or collection optic. Each application depends primarily on the optical architecture of the system and the format of the data coming into the DLPC3430 or DLPC3435 controller. The new high-tilt pixel in the side-illuminated DMD increases brightness performance and enables a smaller system electronics footprint for thickness constrained applications. Applications include • • • • • • projection embedded in display devices – smartphones – tablets – cameras – camcorders wearable (near-eye) displays battery powered mobile accessory interactive display low-latency gaming display digital signage DMD power-up and power-down sequencing is strictly controlled by the DLPA200x/DLPA3000. Refer to Section 9 for power-up and power-down specifications. DLP2010 DMD reliability is specified when used with DLPC3430 or DLPC3435 controller and DLPA200x/DLPA3000 PMIC/LED driver only. 8.2 Typical Application This section describes a pico-projector using a DLP chipset that includes a DLP2010 DMD, DLPC3430 or DLPC3435 controller and DLPA200x/DLPA3000 PMIC/LED driver. The DLPC3430 or DLPC3435 controller does the digital image processing, the DLPA200x/DLPA3000 provides the needed analog functions for the projector, and DMD is the display device for producing the projected image. The DLPC3430 controller in the pico-projector embedded module typically receives images/video from a host processor within the product. DLPC3430 controller then drives the DMD synchronized with the R, G, B LEDs in the optical engine to display the image/video as output of the optical engine. 28 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010 DLP2010 www.ti.com DLPS123B – FEBRUARY 2019 – REVISED MAY 2022 1.1 V 1.1 Reg L3 SYSPWR DC Supplies L2 1.8 V 1.8 V external L1 DLPA200x 1.8 V VLED VSPI PROJ_ON PROJ_ON 2 I C HDMI Keypad Video Front End System Controller GPIO_8 HOST_IRQ DSI (10) SPI (4) 1.8 V TI DLP Chipset LED_SEL (2) SPI (4) INTZ VDDLP12 VDD DLPC34xx Parallel Interface (28) Flash SPI1 RESETZ PARKZ CMP_OUT SPI0 GPIO_10 Thermistor 1.1 V RC_ CHARGE Illumination optics VBIAS, VOFFSET, VCC_18 VCC_INTF VCC_FLSH RLIM VRESET DMD CTRL Sub-LVDS DATA 1.8 V Non-TI Device Figure 8-1. Typical Application 8.2.1 Design Requirements In addition to the three DLP devices in the chipset, other IC components may be needed. At a minimum, this design requires a flash device to store the software and firmware to control the DLPC3430 or DLPC3435. Red, green, and blue LEDs typically supply the illumination light that is applied to the DMD. These LEDs are often contained in three separate packages, but sometimes more than one color of LED die may be in the same package to reduce the overall size of the pico-projector. A parallel interface connects the DLPC3430 or DLPC3435 to the host processing for receiving images. When the parallel interface is used, use an I2C interface to the host processor for sending commands to the DLPC3430 or DLPC3435. The battery (SYSPWR) and a regulated 1.8-V supply are the only power supplies needed external to the projector in case of DLPA200x. The DLPA3000 supplies the 1.8V without external regulator. 8.2.2 Detailed Design Procedure For connecting together the DLPC3430 or DLPC3435, the DLPA200x/DLPA3000, and the DMD, see the reference design schematic. When a circuit board layout is created from this schematic a very small circuit board is possible. An example small board layout is included in the reference design data base. Layout guidelines should be followed to achieve a reliable projector. The optical engine that has the LED packages and the DMD mounted to it is typically supplied by an optical OEM who specializes in designing optics for DLP projectors. A miniature stepper motor can optionally be added to the optical engine for creating a motorized focus. Direct control and driving of the motor can be done by the DLPA200x/DLPA3000, and software commands sent over I2C to the DLPC3430 or DLPC3435 are available to move the motor to the desired position. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010 29 DLP2010 www.ti.com DLPS123B – FEBRUARY 2019 – REVISED MAY 2022 8.2.3 Application Curve This device drives current time-sequentially though the LEDs. As the LED currents through the red, green, and blue LEDs increases, the brightness of the projector increases. This increase is somewhat non-linear, and the curve for typical white screen lumens changes with LED currents as shown in Figure 8-2. For the LED currents shown, assumed that the same current amplitude is applied to the red, green, and blue. SPACE 1 0.9 0.8 Luminance 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 100 200 300 400 Current (mA) 500 600 700 D001 ILED(red) = ILED(green) = ILED(blue) Figure 8-2. Luminance vs Current 30 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010 DLP2010 www.ti.com DLPS123B – FEBRUARY 2019 – REVISED MAY 2022 9 Power Supply Recommendations The following power supplies are all required to operate the DMD: • • • • • • VSS VBIAS VDD VDDI VOFFSET VRESET The DLPAxxxx device strictly controls the DMD power-up and power-down sequences as described in Figure 9-1. CAUTION To ensure reliable operation of the DMD, follow the power supply sequencing requirements described in this section. Failure to adhere to any of these requirements can result in a significant reduction in the DMD reliability and lifetime. VBIAS, VDD, VDDI, VOFFSET, and VRESET power supplies must be coordinated during power-up and power-down operations . Common ground (VSS) to all lines must also be connected. 9.1 DMD Power Supply Power-Up Procedure • • • • • During the power-up sequence, VDD and VDDI must always start and settle before VOFFSET, VBIAS, and VRESET voltages are applied to the DMD. During the power-up sequence, it is a strict requirement that the voltage difference between VBIAS and VOFFSET must be within the specified limit shown in Section 6.4. Refer to Table 9-1 for the power-up sequence, delay requirements. During the power-up sequence, there is no requirement for the relative timing of VRESET with respect to VBIAS and VOFFSET. Power supply slew rates during the power-up sequence are flexible, provided that the transient voltage levels follow the requirements specified in Section 6.1, in Section 6.4, and in Section 9.3. During the power-up sequence, LPSDR input pins must not be driven high until after VDD/VDDI have settled at operating voltages listed in Section 6.4. 9.2 DMD Power Supply Power-Down Procedure • • • • • The power-down sequence is the reverse order of the previous power-up sequence. During the power-down sequence, VDD and VDDI must be supplied until after VBIAS, VRESET, and VOFFSET are discharged to within 4 V of ground. During the power-down sequence, it is a strict requirement that the voltage difference between VBIAS and VOFFSET must be within the specified limit shown in Section 6.4. During the power-down sequence, there is no requirement for the relative timing of VRESET with respect to VBIAS and VOFFSET. Power supply slew rates during the power-down sequence, are flexible, provided that the transient voltage levels follow the requirements specified in Section 6.1, inSection 6.4, and in Section 9.3. During the power-down sequence, LPSDR input pins must be less than VDD/VDDI specified in Section 6.4. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010 31 DLP2010 www.ti.com DLPS123B – FEBRUARY 2019 – REVISED MAY 2022 9.3 Power Supply Sequencing Requirements Mirror park sequence (4) VDD / VDDI VDD and VDDI VDD and VDDI VSS VSS VBIAS VBIAS VBIAS 9'' ” 9%,$6 < 6 V VSS VBIAS < 4 V ûV < Specification ûV < Specification (1)(2) VOFFSET 9'' ” 92))6(7 < 6 V VOFFSET VSS (2) VOFFSET VOFFSET < 4 V ûV < Specification(3) VSS VSS VRESET < 0.5 V VSS VSS VRESET > ±4 V VRESET VRESET VRESET VDD DMD_DEN_ARSTZ VDD VSS VSS Initialization LS_CLK LS_WDATA VSS D_P(0:3), D_N(0:3) DCLK_P, DCLK_N VSS VDD VDD VSS VID VSS t1 t2 t3 t4 DLP controller and PMIC controls start of DMD operation Mirror park sequence starts Mirror park sequence ends. DLP controller and PMIC disables VBIAS, VOFFSET, and VRESET. Power off. Refer to Table 9-1 and Figure 9-2 for critical power-up sequence delay requirements. When system power is interrupted, the ASIC driver initiates hardware the power-down sequence, that disables VBIAS, VRESET and VOFFSET after the micromirror park sequence is complete. Software the power-down sequence, disables VBIAS, VRESET, and VOFFSET after the micromirror park sequence through software control. To prevent excess current, the supply voltage delta |VBIAS – VRESET| must be less than specified limit shown in Section 6.4. Drawing is not to scale and details are omitted for clarity. Figure 9-1. Power Supply Sequencing Requirements 32 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010 DLP2010 www.ti.com DLPS123B – FEBRUARY 2019 – REVISED MAY 2022 Table 9-1. Power-Up Sequence Delay Requirement PARAMETER tDELAY MIN Delay requirement from VOFFSET power up to VBIAS power up MAX 2 UNIT ms VOFFSE Supply voltage level during power–up sequence delay (see Figure 9-2) T 6 V VBIAS 6 V VOFFSET Voltage (V) Supply voltage level during power–up sequence delay (see Figure 9-2) 12 VOFFSET 8 9'' ” 92))6(7 ” 6 V 4 0 VSS tDELAY VBIAS VBIAS Voltage (V) 20 16 12 8 9'' ” 9%,$6 ” 6 V 4 0 VSS Time Refer to Table 9-1 for VOFFSET and VBIAS supply voltage levels during power-up sequence delay. Figure 9-2. Power-Up Sequence Delay Requirement Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010 33 DLP2010 www.ti.com DLPS123B – FEBRUARY 2019 – REVISED MAY 2022 10 Layout 10.1 Layout Guidelines There are no specific layout guidelines because in most cases the DMD is connected using a board-to-board connector to a flex cable. The flex cable provides the interface of data and control signals between the DLPC3430 or DLPC3435 controller and the DLP2010 DMD. For detailed layout guidelines refer to the layout design files. Layout guidelines for the flex cable interface with DMD are: • • • • • • • • Match lengths for the LS_WDATA and LS_CLK signals. Minimize vias, layer changes, and turns for the HS bus signals. Refer Figure 10-1. Place a decoupling capacitor (minimum 100-nF) close to VBIAS. See capacitor C4 in Figure 10-2. Place a decoupling capacitor (minimum 100-nF) close to VRST. See capacitor C6 in Figure 10-2. Place a decoupling capacitor (minimum 220-nF) close to VOFS. See capacitor C7 in Figure 10-2. Place the optional decoupling capacitor (minimum between 200-nF and 220-nF) to meet the ripple requirements of the DMD. See capacitor C5 in Figure 10-2. Place a decoupling capacitor (minimum 100-nF) close to VDDI. See capacitor C1 in Figure 10-2. Place a decoupling capacitor (minimum 100-nF) close to both groups of VDD pins, for a total of 200 nF for VDD. See capacitors C2 and C3 in Figure 10-2. 10.2 Layout Example Figure 10-1. High-Speed (HS) Bus Connections 34 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010 DLP2010 www.ti.com DLPS123B – FEBRUARY 2019 – REVISED MAY 2022 Figure 10-2. Power Supply Connections Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010 35 DLP2010 www.ti.com DLPS123B – FEBRUARY 2019 – REVISED MAY 2022 11 Device and Documentation Support 11.1 Device Support 11.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 11.1.2 Device Nomenclature Figure 11-1. Part Number Description 11.1.3 Device Markings Device Marking will include the human–readable character string GHJJJJK VVVV on the electrical connector. GHJJJJK is the lot trace code. VVVV is a 4 character encoded device part number. GHJJJJKHVVVV Figure 11-2. DMD Marking 11.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 11-1. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY DLPC3430 Click here Click here Click here Click here Click here DLPC3435 Click here Click here Click here Click here Click here DLPA2000 Click here Click here Click here Click here Click here DLPA2005 Click here Click here Click here Click here Click here DLPA3000 Click here Click here Click here Click here Click here 11.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 36 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010 DLP2010 www.ti.com DLPS123B – FEBRUARY 2019 – REVISED MAY 2022 11.4 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 11.5 Trademarks IntelliBright™ and TI E2E™ are trademarks of Texas Instruments. DLP® and Pico® are registered trademarks of Texas Instruments. All trademarks are the property of their respective owners. 11.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.7 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010 37 DLP2010 www.ti.com DLPS123B – FEBRUARY 2019 – REVISED MAY 2022 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 38 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010 PACKAGE OPTION ADDENDUM www.ti.com 28-Sep-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking Samples (4/5) (6) DLP2010AFQJ ACTIVE CLGA FQJ 40 120 RoHS & Green Call TI N / A for Pkg Type 0 to 70 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of