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DLP9500UV
DLPS033C – NOVEMBER 2014 – REVISED MARCH 2017
DLP9500UV DLP® 0.95 UV 1080p 2x LVDS Type A DMD
1 Features
•
1
•
•
•
•
•
0.95-Inch Diagonal Micromirror Array
– 1920 × 1080 Array of Aluminum, MicrometerSized Mirrors (1080p Resolution)
– 10.8-µm Micromirror Pitch
– ±12° Micromirror Tilt Angle (Relative to Flat
State)
– Designed for Corner Illumination
Designed for Use with UV Light
(363 to 420 nm):
– Window Transmission 98% (Single Pass,
Through Two Window Surfaces) (Nominal)
– Micromirror Reflectivity 88% (Nominal)
– Array Diffraction Efficiency 85% (Nominal)
– Array Fill Factor 92% (Nominal)
Four 16-Bit, Low-Voltage Differential Signaling
(LVDS), Double Data Rate (DDR) Input Data
Buses
Up to 400-MHz Input Data Clock Rate
42.2-mm × 42.2-mm × 7-mm Package Footprint
Hermetic Package
2 Applications
•
•
Industrial:
– Direct Imaging Lithography
– Laser Marking and Repair Systems
– Computer to Plate Printers
– Rapid Prototype Machines
– 3D Printers
Medical:
– Opthalmology
– Photo Therapy
– Hyper-Spectral Imaging
The DLP95000UV chipset is a new digital micromirror
device (DMD) addition to the DLP® Discovery™ 4100
platform, which enables high resolution and high
performance spatial light modulation beyond the
visible spectrum into the UVA spectrum (363 nm to
420 nm). The DLP9500UV DMD is designed with a
special window that is optimized for UV transmission.
The DLP9500UV is the 0.95 1080p DMD, with a
hermetic package, that is sold with a dedicated
DLPC410 controller required for high speed pattern
rates of >23000 Hz (1-bit binary) and >1700 Hz (8-bit
gray), one unit DLPR410 (DLP Discovery 4100
Configuration PROM), and two units DLPA200 (DMD
micromirror drivers). Refer to DLPC410, DLPA200,
DLPR410, and DLP9500UV Functional Block
Diagram.
Reliable function and operation of the DLP9500UV
requires that it be used in conjunction with the other
components of the chipset. A dedicated chipset
provides developers easier access to the DMD as
well as high speed, independent micromirror control.
DLP9500UV is a digitally controlled microelectromechanical system (MEMS) spatial light
modulator (SLM). When coupled to an appropriate
optical system, the DLP9500UV can be used to
modulate the amplitude, direction, and/or phase of
incoming light.
Device Information
PART NUMBER
DLP9500UV
PACKAGE
LCCC (355)
(1)
BODY SIZE (NOM)
42.16 mm × 42.16
mm x 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Figure 1. Simplified Schematic
LED
Driver
3 Description
DLP9500UV is a digitally controlled microelectromechanical system (MEMS) spatial light
modulator (SLM). When coupled to an appropriate
optical system, the DLP9500UV can be used to
modulate the amplitude, direction, and/or phase of
incoming light.
DLP9500UV
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DLP9500UV
DLPS033C – NOVEMBER 2014 – REVISED MARCH 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features .................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Description (continued)......................................... 4
Pin Configuration and Functions ......................... 4
Specifications....................................................... 13
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
8
Absolute Maximum Ratings .................................... 13
Storage Conditions.................................................. 13
ESD Ratings............................................................ 13
Recommended Operating Conditions..................... 14
Thermal Information ................................................ 15
Electrical Characteristics......................................... 15
LVDS Timing Requirements ................................... 16
LVDS Waveform Requirements.............................. 17
Serial Control Bus Timing Requirements................ 18
Systems Mounting Interface Loads....................... 19
Micromirror Array Physical Characteristics ........... 20
Micromirror Array Optical Characteristics ............. 21
Chipset Component Usage Specification ............. 22
Detailed Description ............................................ 23
8.1 Overview ................................................................. 23
8.2 Functional Block Diagram ....................................... 23
8.3 Feature Description................................................. 25
8.4
8.5
8.6
8.7
9
Device Functional Modes........................................
Window Characteristics and Optics .......................
Micromirror Array Temperature Calculation............
Micromirror Landed-On and Landed-Off Duty
Cycle ........................................................................
32
34
35
37
Application and Implementation ........................ 39
9.1 Application Information............................................ 39
9.2 Typical Application ................................................. 41
10 Power Supply Recommendations ..................... 43
10.1 Power-Up Sequence (Handled by the DLPC410) 43
10.2 DMD Power-Up and Power-Down Procedures..... 43
11 Layout................................................................... 44
11.1 Layout Guidelines ................................................. 44
11.2 Layout Example .................................................... 46
12 Device and Documentation Support ................. 47
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Device Support ....................................................
Documentation Support ........................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
47
48
48
48
48
48
48
13 Mechanical, Packaging, and Orderable
Information ........................................................... 48
4 Revision History
Changes from Revision B (June 2015) to Revision C
Page
•
Changed the name of Micromirror clocking pulse reset in Pin Functions ............................................................................ 11
•
Changed TGRADIENT from 5°C to 10°C to accommodate increase in power density from 400 to 420 nm in Absolute
Maximum Ratings ................................................................................................................................................................. 13
•
Added RH name for relative humidity in Absolute Maximum Ratings.................................................................................. 13
•
Clarified TGRADIENT footnote in Absolute Maximum Ratings .................................................................................................. 13
•
Changed Tstg to TDMD in Storage Conditions to conform to current nomenclature ............................................................... 13
•
Added Maximum illumination power values for 363 to 400 nm, 400 to 420 nm, and 363 to 420 nm total power
values in Recommended Operating Conditions .................................................................................................................. 14
•
Changed 363 to 420 nm to 363 to 400 nm max for 2.5 W/cm2 power density and 6 W max optical power in
Recommended Operating Conditions .................................................................................................................................. 14
•
Added 400 to 420 nm max power density of 11 W/cm2 and max optical power of 26.6 W ................................................ 14
•
Added 363 to 420 nm total integrated max power density of 11 W/cm2 and total integrated max optical power of
26.6 W ................................................................................................................................................................................. 14
•
Changed typical micromirror crossover time to the time required to transition from mirror position to the other in
Micromirror Array Optical Characteristics ............................................................................................................................ 21
•
Added typical micromirror switching time - 13 µs in Micromirror Array Optical Characteristics .......................................... 21
•
Changed "Micromirror switching time" to "Array switching time" for clarity in Micromirror Array Optical Characteristics .... 21
•
Added clarification to Micromirror switching time at 400 MHz with global reset in Micromirror Array Optical
Characteristics ...................................................................................................................................................................... 21
•
Corrected number of banks of DMD mirrors to 15 in Device Description ............................................................................ 42
•
Removed link to DLP Discovery 4100 chipset datasheet in Related Documentation.......................................................... 48
•
Added Related Links table.................................................................................................................................................... 48
2
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Copyright © 2014–2017, Texas Instruments Incorporated
Product Folder Links: DLP9500UV
DLP9500UV
www.ti.com
DLPS033C – NOVEMBER 2014 – REVISED MARCH 2017
Changes from Revision A (June 2015) to Revision B
Page
•
Released full data sheet and updated device status to production data................................................................................ 1
•
Added 7.00 mm measurement to BODY SIZE in Device Information. .................................................................................. 1
•
Added environmental parameters to Absolute Maximum Ratings ...................................................................................... 13
•
Moved VESD to ESD Ratings ................................................................................................................................................ 13
•
Updated the MAX value of the illumination power density for >420 nm in Recommended Operating Conditions ............. 14
•
Added new notes to Recommended Operating Conditions . .............................................................................................. 14
•
Added new note to Thermal Information ............................................................................................................................. 15
•
Replaced Figure 4. ............................................................................................................................................................... 18
•
Changed units in Systems Mounting Interface Loads from lbs to N. .................................................................................. 19
•
Added Chipset Component Usage Specification ................................................................................................................ 22
•
Corrected 6.33 W to 6.83 W in TArray sample calculation .................................................................................................... 36
•
Updated Figure 21 ............................................................................................................................................................... 43
•
Removed Thermal Considerations ...................................................................................................................................... 46
Changes from Original (November 2014) to Revision A
Page
•
Updated device status to product preview for release .......................................................................................................... 1
•
Updated front page graphic ................................................................................................................................................... 1
•
Added Community Resources ............................................................................................................................................. 48
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3
DLP9500UV
DLPS033C – NOVEMBER 2014 – REVISED MARCH 2017
www.ti.com
5 Description (continued)
Electrically, the DLP9500UV consists of a two-dimensional array of 1-bit CMOS memory cells, organized in a grid
of 1920 memory cell columns by 1080 memory cell rows. The CMOS memory array is addressed on a row-byrow basis, over four 16-bit LVDS DDR buses. Addressing is handled by a serial control bus. The specific CMOS
memory access protocol is handled by the DLPC410 digital controller.
6 Pin Configuration and Functions
FLN Package
355-Pin LCCC
Bottom View
31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1
30 28 26 24 22 20 18 16 14 12 10 8 6 4 2
B
D
F
H
K
M
P
T
A
C
E
G
J
L
N
R
U
V
Y
AB
AD
AF
AH
AK
W
AA
AC
AE
AG
AJ
AL
4
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Product Folder Links: DLP9500UV
DLP9500UV
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DLPS033C – NOVEMBER 2014 – REVISED MARCH 2017
Pin Functions
PIN
(1)
NO.
TYPE
(I/O/P)
SIGNAL
DATA
RATE (2)
INTERNAL
TERM (3)
CLOCK
D_AN(0)
F2
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_A
512.01
D_AN(1)
H8
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_A
158.79
D_AN(2)
E5
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_A
471.24
D_AN(3)
G9
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_A
159.33
D_AN(4)
D2
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_A
585.41
D_AN(5)
G3
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_A
551.17
D_AN(6)
E11
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_A
229.41
D_AN(7)
F8
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_A
300.54
D_AN(8)
C9
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_A
346.35
D_AN(9)
H2
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_A
782.27
D_AN(10)
B10
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_A
451.52
D_AN(11)
G15
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_A
74.39
D_AN(12)
D14
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_A
194.26
D_AN(13)
F14
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_A
D_AN(14)
C17
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_A
244.9
D_AN(15)
H16
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_A
73.39
D_AP(0)
F4
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_A
509.63
D_AP(1)
H10
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_A
152.59
D_AP(2)
E3
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_A
464.09
D_AP(3)
G11
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_A
152.39
D_AP(4)
D4
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_A
591.39
D_AP(5)
G5
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_A
532.16
D_AP(6)
E9
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_A
230.78
D_AP(7)
F10
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_A
300.61
D_AP(8)
C11
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_A
338.16
D_AP(9)
H4
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_A
773.17
D_AP(10)
B8
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_A
449.57
NAME
DESCRIPTION
TRACE
(MILS)
DATA BUS A
(1)
(2)
(3)
Input data bus A
(2x LVDS)
148.29
The following power supplies are required to operate the DMD: VCC, VCC1, VCC2. VSS must also be connected.
DDR = Double Data Rate. SDR = Single Data Rate. Refer to the LVDS Timing Requirements for specifications and relationships.
Refer to Electrical Characteristics for differential termination specification.
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DLPS033C – NOVEMBER 2014 – REVISED MARCH 2017
www.ti.com
Pin Functions (continued)
PIN
(1)
NAME
NO.
TYPE
(I/O/P)
SIGNAL
DATA
RATE (2)
INTERNAL
TERM (3)
CLOCK
D_AP(11)
H14
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_A
71.7
D_AP(12)
D16
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_A
198.69
D_AP(13)
F16
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_A
D_AP(14)
C15
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_A
240.14
D_AP(15)
G17
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_A
74.05
D_BN(0)
AH2
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_B
525.25
D_BN(1)
AD8
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_B
190.59
D_BN(2)
AJ5
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_B
525.25
D_BN(3)
AE3
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_B
494.91
D_BN(4)
AG9
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_B
222.67
D_BN(5)
AE11
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_B
205.45
D_BN(6)
AH10
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_B
309.05
D_BN(7)
AF10
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_B
285.62
D_BN(8)
AK8
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_B
483.58
D_BN(9)
AG5
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_B
711.58
D_BN(10)
AL11
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_B
462.21
D_BN(11)
AE15
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_B
74.39
D_BN(12)
AH14
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_B
D_BN(13)
AF14
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_B
156
D_BN(14)
AJ17
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_B
247.9
D_BN(15)
AD16
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_B
111.52
D_BP(0)
AH4
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_B
525.02
D_BP(1)
AD10
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_B
190.61
D_BP(2)
AJ3
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_B
524.22
D_BP(3)
AE5
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_B
476.07
D_BP(4)
AG11
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_B
222.8
D_BP(5)
AE9
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_B
219.48
D_BP(6)
AH8
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_B
306.55
D_BP(7)
AF8
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_B
298.04
D_BP(8)
AK10
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_B
480.31
DESCRIPTION
Input data bus A
(2x LVDS)
TRACE
(MILS)
143.72
DATA BUS B
6
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Input data bus B
(2x LVDS)
194.26
Copyright © 2014–2017, Texas Instruments Incorporated
Product Folder Links: DLP9500UV
DLP9500UV
www.ti.com
DLPS033C – NOVEMBER 2014 – REVISED MARCH 2017
Pin Functions (continued)
PIN
(1)
NAME
NO.
TYPE
(I/O/P)
SIGNAL
DATA
RATE (2)
INTERNAL
TERM (3)
D_BP(9)
AG3
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_B
727.18
D_BP(10)
AL9
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_B
461.02
D_BP(11)
AD14
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_B
71.35
D_BP(12)
AH16
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_B
D_BP(13)
AF16
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_B
150.38
D_BP(14)
AJ15
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_B
243.14
D_BP(15)
AE17
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_B
113.36
D_CN(0)
B14
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_C
459.04
D_CN(1)
E15
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_C
342.79
D_CN(2)
A17
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_C
456.22
D_CN(3)
G21
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_C
68.24
D_CN(4)
B20
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_C
362.61
D_CN(5)
F20
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_C
163.07
D_CN(6)
D22
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_C
204.16
D_CN(7)
G23
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_C
105.59
D_CN(8)
B26
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_C
450.51
D_CN(9)
F28
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_C
302.04
D_CN(10)
C29
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_C
D_CN(11)
G27
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_C
D_CN(12)
D26
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_C
276.76
D_CN(13)
H28
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_C
186.78
D_CN(14)
E29
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_C
311.3
D_CN(15)
J29
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_C
262.62
D_CP(0)
B16
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_C
463.64
D_CP(1)
E17
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_C
347.65
D_CP(2)
A15
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_C
456.45
D_CP(3)
H20
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_C
67.72
D_CP(4)
B22
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_C
362.76
D_CP(5)
F22
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_C
161.69
CLOCK
DESCRIPTION
Input data bus B
(2x LVDS)
TRACE
(MILS)
197.69
DATA BUS C
Input data bus C
(2x LVDS)
429.8
317.1
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Pin Functions (continued)
PIN
(1)
NAME
NO.
TYPE
(I/O/P)
SIGNAL
DATA
RATE (2)
INTERNAL
TERM (3)
D_CP(6)
D20
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_C
195.09
D_CP(7)
H22
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_C
104.86
D_CP(8)
B28
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_C
451.41
D_CP(9)
F26
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_C
294.22
D_CP(10)
C27
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_C
D_CP(11)
G29
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_C
D_CP(12)
D28
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_C
276.04
D_CP(13)
H26
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_C
186.25
D_CP(14)
E27
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_C
312.07
D_CP(15)
J27
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_C
262.94
D_DN(0)
AK14
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_D
492.53
D_DN(1)
AG15
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_D
342.78
D_DN(2)
AL17
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_D
491.83
D_DN(3)
AE21
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_D
74.24
D_DN(4)
AK20
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_D
356.23
D_DN(5)
AF20
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_D
D_DN(6)
AH22
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_D
D_DN(7)
AE23
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_D
105.59
D_DN(8)
AK26
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_D
450.51
D_DN(9)
AF28
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_D
302.04
D_DN(10)
AJ29
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_D
429.8
D_DN(11)
AE27
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_D
298.87
CLOCK
DESCRIPTION
Input data bus C
(2x LVDS)
TRACE
(MILS)
429.68
314.98
DATA BUS D
8
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Input data bus D
(2x LVDS)
163.07
204.16
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Pin Functions (continued)
PIN
(1)
NO.
TYPE
(I/O/P)
SIGNAL
DATA
RATE (2)
INTERNAL
TERM (3)
D_DN(12)
AH26
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_D
276.76
D_DN(13)
AD28
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_D
186.78
D_DN(14)
AG29
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_D
311.3
D_DN(15)
AC29
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_D
262.62
D_DP(0)
AK16
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_D
495.13
D_DP(1)
AG17
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_D
342.47
D_DP(2)
AL15
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_D
492.06
D_DP(3)
AD20
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_D
67.72
D_DP(4)
AK22
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_D
356.37
D_DP(5)
AF22
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_D
D_DP(6)
AH20
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_D
D_DP(7)
AD22
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_D
102.86
D_DP(8)
AK28
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_D
451.41
D_DP(9)
AF26
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_D
296.7
D_DP(10)
AJ27
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_D
429.68
D_DP(11)
AE29
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_D
302.74
D_DP(12)
AH28
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_D
276.04
D_DP(13)
AD26
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_D
186.25
D_DP(14)
AG27
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_D
312.07
D_DP(15)
AC27
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_D
262.94
NAME
CLOCK
DESCRIPTION
Input data bus D
(2x LVDS)
TRACE
(MILS)
161.98
195.09
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Pin Functions (continued)
PIN
(1)
NO.
TYPE
(I/O/P)
SIGNAL
DATA
RATE (2)
INTERNAL
TERM (3)
CLOCK
DCLK_AN
D10
Input
LVCMOS
—
Differentially
terminated – 100 Ω
—
DCLK_AP
D8
Input
LVCMOS
—
Differentially
terminated – 100 Ω
—
DCLK_BN
AJ11
Input
LVCMOS
—
Differentially
terminated – 100 Ω
—
DCLK_BP
AJ9
Input
LVCMOS
—
Differentially
terminated – 100 Ω
—
DCLK_CN
C23
Input
LVCMOS
—
Differentially
terminated – 100 Ω
—
DCLK_CP
C21
Input
LVCMOS
—
Differentially
terminated – 100 Ω
—
DCLK_DN
AJ23
Input
LVCMOS
—
Differentially
terminated – 100 Ω
—
DCLK_DP
AJ21
Input
LVCMOS
—
Differentially
terminated – 100 Ω
—
SCTRL_AN
J3
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_A
SCTRL_AP
J5
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_A
SCTRL_BN
AF4
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_B
SCTRL_BP
AF2
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_B
SCTRL_CN
E23
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_C
SCTRL_CP
E21
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_C
SCTRL_DN
AG23
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
DCLK_D
SCTRL_DP
AG21
Input
LVCMOS
DDR
Differentially
terminated – 100 Ω
NAME
DESCRIPTION
TRACE
(MILS)
DATA CLOCKS
Input data bus A
Clock (2x LVDS)
Input data bus B
Clock (2x LVDS)
Input data bus C
Clock (2x LVDS)
Input data bus D
Clock (2x LVDS)
325.8
319.9
318.92
318.74
252.01
241.18
252.01
241.18
DATA CONTROL INPUTS
Serial control for
data bus A (2x
LVDS)
608.14
Serial control for
data bus B (2x
LVDS)
698.12
Serial control for
data bus C (2x
LVDS)
232.46
235.53
DCLK_D
Serial control for
data bus D (2x
LVDS)
607.45
703.8
235.21
235.66
SERIAL COMMUNICATION AND CONFIGURATION
SCPCLK
AE1
Input
LVCMOS
—
SCPDO
AC3
Output
LVCMOS
—
SCPDI
AD2
Input
LVCMOS
—
SCPEN
AD4
Input
LVCMOS
PWRDN
B4
Input
MODE_A
J1
MODE_B
G1
10
pull-down
—
Serial port clock
324.26
SCP_CLK
Serial port output
281.38
pull-down
SCP_CLK
Serial port input
261.55
—
pull-down
SCP_CLK
Serial port enable
184.86
LVCMOS
—
pull-down
—
Device reset
458.78
Input
LVCMOS
—
pull-down
—
LVCMOS
—
pull-down
—
Data bandwidth
mode select
471.57
Input
—
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Pin Functions (continued)
PIN
NAME
(1)
NO.
TYPE
(I/O/P)
SIGNAL
DATA
RATE (2)
INTERNAL
TERM (3)
CLOCK
DESCRIPTION
TRACE
(MILS)
MICROMIRROR CLOCKING PULSE (BIAS RESET)
MBRST(0)
L5
Input
Analog
—
—
—
898.97
MBRST(1)
M28
Input
Analog
—
—
—
621.98
MBRST(2)
P4
Input
Analog
—
—
—
846.88
MBRST(3)
P30
Input
Analog
—
—
—
784.18
MBRST(4)
L3
Input
Analog
—
—
—
763.34
MBRST(5)
P28
Input
Analog
—
—
—
749.61
MBRST(6)
P2
Input
Analog
—
—
—
878.25
MBRST(7)
T28
Input
Analog
—
—
—
783.83
MBRST(8)
M4
Input
Analog
—
—
—
969.36
MBRST(9)
L29
Input
Analog
—
—
—
621.24
MBRST(10)
T4
Input
Analog
—
—
—
918.43
MBRST(11)
N29
Input
Analog
—
—
—
MBRST(12)
N3
Input
Analog
—
—
—
MBRST(13)
L27
Input
Analog
—
—
—
MBRST(14)
R3
Input
Analog
—
—
—
MBRST(15)
V28
Input
Analog
—
—
—
MBRST(16)
V4
Input
Analog
—
—
—
MBRST(17)
R29
Input
Analog
—
—
—
MBRST(18)
Y4
Input
Analog
—
—
—
715
MBRST(19)
AA27
Input
Analog
—
—
—
604.35
MBRST(20)
W3
Input
Analog
—
—
—
832.39
MBRST(21)
W27
Input
Analog
—
—
—
675.21
MBRST(22)
AA3
Input
Analog
—
—
—
861.18
MBRST(23)
W29
Input
Analog
—
—
—
662.66
MBRST(24)
U5
Input
Analog
—
—
—
850.06
MBRST(25)
U29
Input
Analog
—
—
—
726.56
MBRST(26)
Y2
Input
Analog
—
—
—
861.48
MBRST(27)
AA29
Input
Analog
—
—
—
683.83
MBRST(28)
U3
Input
Analog
—
—
—
878.5
MBRST(29)
Y30
Input
Analog
—
—
—
789.2
Power
Analog
—
—
—
Power for LVCMOS
logic
—
Power
Analog
—
—
—
Power supply for
LVDS Interface
—
685.14
Micromirror clocking
pulse reset MBRST
signals clock
micromirrors into
state of LVCMOS
memory cell
associated with each
mirror.
812.31
591.89
878.5
660.15
848.64
796.31
POWER
A3, A5, A7, A9,
A11, A13, A21,
A23, A25, A27,
A29, B2,
VCC
C1, C31, E31,
G31, J31, K2,
L31, N31, R31,
U31, W31,
AA31, AC1,
AC31, AE31,
AG1, AG31,
AJ31, AK2,
AK30, AL3, AL5,
AL7, AL19, AL21,
AL23, AL25,
AL27
VCCI
H6, H12, H18,
H24, M6, M26,
P6, P26, T6, T26,
V6, V26,
Y6, Y26, AD6,
AD12, AD18,
AD24
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Pin Functions (continued)
PIN
(1)
NAME
NO.
L1, N1, R1, U1,
W1, AA1
VCC2
TYPE
(I/O/P)
SIGNAL
DATA
RATE (2)
INTERNAL
TERM (3)
CLOCK
Power
Analog
—
—
—
Power for high
voltage CMOS logic
—
Power
Analog
—
—
—
Common return for
all power inputs
—
DESCRIPTION
TRACE
(MILS)
A1, B12, B18,
B24, B30, C7,
C13, C19, C25,
D6, D12,
D18, D24, D30,
E1, E7, E13, E19,
E25, F6, F12,
F18, F24,
F30, G7, G13,
G19, G25, K4,
K6, K26, K28,
K30, M2, M30,
N5, N27, R5, T2,
T30, U27, V2,
V30, W5, Y28,
AB2, AB4,
VSS
AB6, AB26,
AB28, AB30,
AD30, AE7,
AE13, AE19,
AE25, AF6,
AF12, AF18,
AF24, AF30,
AG7, AG13,
AG19, AG25,
AH6, AH12,
AH18, AH24,
AH30, AJ1,
AJ7, AJ13, AJ19,
AJ25, AK6, AK12,
AK18, AL29
RESERVED SIGNALS (NOT FOR USE IN SYSTEM)
RESERVED_FC
J7
Input
LVCMOS
—
pull-down
—
RESERVED_FD
J9
Input
LVCMOS
—
pull-down
—
RESERVED_PFE
J11
Input
LVCMOS
—
pull-down
—
RESERVED_STM
AC7
Input
LVCMOS
—
pull-down
—
—
RESERVED_AE
C3
Input
LVCMOS
—
pull-down
—
—
A19, B6, C5,
H30, J13, J15,
J17, J19, J21,
J23, J25, R27,
NO_CONNECT
AA5, AC11,
AC13, AC15,
AC17, AC19,
AC21, AC23,
—
—
—
—
—
—
—
Pins should be
connected to VSS
No connection (any
connection to these
terminals may result
in undesirable
effects)
—
—
AC25, AC5, AC9,
AK24, AK4, AL13
12
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted).
(1)
MIN
MAX
UNIT
ELECTRICAL
VCC
Voltage applied to VCC
(2) (3)
–0.5
4
V
VCCI
Voltage applied to VCCI
(2) (3)
–0.5
4
V
VCC2
Voltage applied to VVCC2
–0.5
9
V
VMBRST
Clocking pulse waveform voltage applied to MBRST[29:0] input pins (supplied
by DLPA200s)
–28
28
V
0.3
V
|VCC – VCCI|
(2) (3) (4)
Supply voltage delta (absolute value)
(4)
Voltage applied to all other input terminals
|VID|
(2)
VCC + 0.3
V
Maximum differential voltage, damage can occur to internal termination resistor
if exceeded, see Figure 3
–0.5
700
mV
Current required from a high-level output, VOH = 2.4 V
–20
mA
Current required from a low-level output, VOL = 0.4 V
15
mA
20
30
°C
–40
80
°C
ENVIRONMENTAL
Case temperature – operational
TC
(5)
Case temperature – non-operational
(5)
TGRADIENT
Device temperature gradient – operational
RH
Relative humidity (non-condensing)
(1)
(2)
(3)
(4)
(5)
(6)
(6)
10
°C
95
%RH
Stresses beyond those listed under Recommended Operating Conditions may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to VSS (ground).
Voltages VCC, VCCI, and VCC2 are required for proper DMD operation.
Exceeding the recommended allowable absolute voltage difference between VCC and VCCI may result in excess current draw. The
difference between VCC and VCCI, |VCC – VCCI|, should be less than the specified limit.
DMD Temperature is the worst-case of any test point shown in Case Temperature, or the active array as calculated by the Micromirror
Array Temperature Calculation.
As either measured, predicted, or both between any two points - measured on the exterior of the package, or as predicted at any point
inside the micromirror array cavity. Refer to Case Temperature and Micromirror Array Temperature Calculation.
7.2 Storage Conditions
applicable before the DMD is installed in the final product
TDMD
Storage temperature
RH
Storage humidity (non-condensing)
MIN
MAX
–40
80
UNIT
°C
95
%RH
7.3 ESD Ratings
VALUE
VESD
(1)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
All pins except
MBRST[29:0]
±2000
MBRST[29:0] pins
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible if necessary precautions are taken.
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7.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted).
(1)
MIN
NOM
MAX
UNIT
3
3.3
3.6
V
3
3.3
3.6
V
8.25
8.5
8.75
V
26.5
V
1334
N
156
N
712
N
ELECTRICAL
VCC
LVCMOS interface supply voltage
(2) (3)
(2) (3)
VCCI
LVCMOS logic supply voltage
VCC2
Mirror electrode and HVCMOS supply voltage
VMBRST
Clocking pulse waveform voltage applied to MBRST[29:0] input pins (supplied by DLPA200s)
(2) (3)
–27
MECHANICAL
Static load applied to electrical interface area, see
(4)
Static load applied to the thermal interface area, see
Figure 6
(5)
Figure 6
Static load applied to Datum 'A' interface area Figure 6
ENVIRONMENTAL
(6)
< 363 nm
(8)
2
2.5
363 to 400 nm (9)
Illumination power density
(7)
400 to 420 nm
(9)
6
W
W/cm2
11
(9) (10)
26.6
> 420 nm
(11) (12)
TC
Case/Array Temperature
TGRADIENT
Device temperature gradient
RH
Relative humidity (non-condensing)
Operating landed duty cycle
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
14
Thermally limited
(14)
(15)
(16)
(9)
30 (13)
20
W/cm2
11
26.6
363 to 420 nm total
mW/cm2
W
W/cm2
W
W/cm2
°C
10
°C
95
%RH
25%
The functional performance of the device specified in this data sheet is achieved when operating the device within the limits defined by
the Recommended Operating Conditions. No level of performance is implied when operating the device above or below the
Recommended Operating Conditions limits.
All voltages referenced to VSS (ground).
Voltages VCC, VCC2, and VCCI,are required for proper DMD operation. VSS must also be connected.
Load should be uniformly distributed across the entire electrical interface area.
Load should be uniformly distributed across thermal interface area. Refer to Figure 6.
Optimal, long-term performance and optical efficiency of the Digital Micromirror Device (DMD) can be affected by various application
parameters, including illumination spectrum, illumination power density, micromirror landed duty-cycle, ambient temperature (storage
and operating), DMD temperature, ambient humidity (storage and operating), and power on or off duty cycle. TI recommends that
application-specific effects be considered as early as possible in the design cycle.
Total integrated illumination power density, above or below the indicated wavelength threshold or in the indicated wavelength range.
The maximum operating conditions for operating temperature and illumination power density for wavelengths < 363nm should not be
implemented simultaneously.
Also limited by the resulting micromirror array temperature. Refer to Case Temperature and Micromirror Array Temperature Calculation
for information related to calculating the micromirror array temperature.
The total integrated illumination power density from 363 to 420 nm shall not exceed 11 W/cm2 (or 26.6 W evenly distributed on the
active array area). Therefore if 2.5 W/cm2 of illumination is used in the 363 to 400 nm range, then illumination in the 400 to 420 nm
range must be limited to 8.5 W/cm2.
In some applications, the total DMD heat load can be dominated by the amount of incident light energy absorbed. See Micromirror Array
Temperature Calculation for further details.
Temperature is the highest measured value of any test point shown in Figure 18 or the active array as calculated by the Micromirror
Array Temperature Calculation.
See the Micromirror Array Temperature Calculation for thermal test point locations, package thermal resistance, and device temperature
calculation.
As either measured, predicted, or both between any two points - measured on the exterior of the package, or as predicted at any point
inside the micromirror array cavity. Refer to Case Temperature and Micromirror Array Temperature Calculation.
Various application parameters can affect optimal, long-term performance of the DMD, including illumination spectrum, illumination
power density, micromirror landed duty cycle, ambient temperature (both storage and operating), case temperature, and power-on or
power-off duty cycle. TI recommends that application-specific effects be considered as early as possible in the design cycle. Contact
your local TI representative for additional information related to optimizing the DMD performance.
Landed duty cycle refers to the percentage of time an individual micromirror spends landed in one state (12° or –12°) versus the other
state (–12° or 12°).
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7.5 Thermal Information
DLP9500UV
THERMAL METRIC
(1) (2)
FLN (LCCC)
UNIT
355 PINS
Active micromirror array resistance to TP1
(1)
(2)
0.5
°C/W
The DMD is designed to conduct absorbed and dissipated heat to the back of the package where it can be removed by an appropriate
heat sink. The heat sink and cooling system must be capable of maintaining the package within the temperature range specified in the
Recommended Operating Conditions. The total heat load on the DMD is largely driven by the incident light absorbed by the active area;
although other contributions include light energy absorbed by the window aperture and electrical power dissipation of the array. Optical
systems should be designed to minimize the light energy falling outside the window clear aperture since any additional thermal load in
this area can significantly degrade the reliability of the device.
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.6 Electrical Characteristics
over the range of recommended supply voltage and recommended case operating temperature (unless otherwise noted);
under recommended operating conditions
PARAMETER
TEST CONDITIONS
(1)
VOH
High-level output voltage
See Figure 11
Low-level output voltage
See Figure 11
(1)
VOL
VMBRST
Clocking pulse waveform applied to
MBRST[29:0] input pins (supplied by
DLPA200s)
IOZ
High-impedance output current
IOH
IOL
,
VCC = 3 V, IOH = –20 mA
,
High-level output current
(1)
Low-level output current
(1)
MIN
–27
VCC = 3.6 V
V
10
µA
–15
VOL = 0.4 V, VCC ≥ 3 V
15
VOL = 0.4 V, VCC ≥ 2.25 V
14
Low-level input voltage
IIL
Low-level input current
(1)
IIH
High-level input current
ICC
Current into VCC pin
ICCI
Current into VOFFSET pin
ICC2
Current into VCC2 pin
PD
Power dissipation
ZIN
Internal differential impedance
95
ZLINE
Line differential impedance (PWB, trace)
90
VCC +
0.3
1.7
–0.3
VCC = 3.6 V, VI = 0 V
VCC = 3.6 V, VI = VCC
(1)
Input capacitance
CO
Output capacitance
CIM
Input capacitance for MBRST[29:0] pins
(1)
mA
mA
V
0.7
V
–60
µA
60
µA
VCC = 3.6 V,
2990
mA
VCCI = 3.6 V
910
mA
25
mA
VCC2 = 8.75 V
4.4
CI
(1)
(2)
26.5
VOH = 1.7 V, VCC ≥ 2.25 V
VIL
(2)
V
–20
(1)
(1)
0.4
VOH = 2.4 V, VCC ≥ 3 V
(1)
UNIT
V
VCC = 3.6 V, IOH = 15 mA
(1)
MAX
2.4
High-level input voltage
VIH
TYP
W
105
Ω
110
Ω
ƒ = 1 MHz
10
pF
ƒ = 1 MHz
10
pF
355
pF
ƒ = 1 MHz
270
100
Applies to LVCMOS pins only.
Exceeding the maximum allowable absolute voltage difference between VCC and VCCI may result in excess current draw (See Absolute
Maximum Ratings for details).
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7.7 LVDS Timing Requirements
over operating free-air temperature range (unless otherwise noted); see Figure 2
MIN
ƒDCLK_x
DCLK_x clock frequency (where x = [A, B, C, or D])
200
tc
Clock cycle - DLCK_x
2.5
tw
Pulse duration - DLCK_x
ts
Setup time - D_x[15:0] and SCTRL_x before DCLK_x
th
Hold time, D_x[15:0] and SCTRL_x after DCLK_x
tskew
Skew between any two buses (A ,B, C, and D)
NOM
MAX
UNIT
400
MHz
ns
1.25
ns
0.35
ns
0.35
–1.25
ns
1.25
ns
DCLK_AN
DCLK_AP
th
tw
tw
tc
ts
ts
th
SCTRL_AN
SCTRL_AP
tskew
D_AN(15:0)
D_AP(15:0)
DCLK_BN
DCLK_BP
tw
tw
ts
th
tc
ts
th
SCTRL_BN
SCTRL_BP
D_BN(15:0)
D_BP(15:0)
tw
DCLK_CN
DCLK_CP
ts
th
tw
tc
ts
th
SCTRL_CN
SCTRL_CP
tskew
D_CN(15:0)
D_CP(15:0)
DCLK_DN
DCLK_DP
tw
tw
ts
th
tc
th
ts
SCTRL_DN
SCTRL_DP
D_DN(15:0)
D_DP(15:0)
Figure 2. LVDS Timing Waveforms
16
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7.8 LVDS Waveform Requirements
over operating free-air temperature range (unless otherwise noted); see Figure 3
MIN
|VID|
Input differential voltage (absolute difference)
VCM
Common mode voltage
VLVDS
LVDS voltage
tr
tr
100
NOM
MAX
UNIT
400
600
mV
1200
mV
0
2000
mV
Rise time (20% to 80%)
100
400
ps
Fall time (80% to 20%)
100
400
ps
V LVDS max = V CM max + | 1/2 × VID max |
tf
VID
V CM
tr
VLVDS min = V CM min ± | 1/2 × VID max |
Figure 3. LVDS Waveform Requirements
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7.9 Serial Control Bus Timing Requirements
over operating free-air temperature range (unless otherwise noted); see Figure 4 and Figure 5
MIN
NOM
MAX
UNIT
50
500
kHz
–300
300
ns
960
ns
ƒSCP_CLK
SCP clock frequency
tSCP_SKEW
Time between valid SCP_DI and rising edge of SCP_CLK
tSCP_DELAY
Time between valid SCP_DO and rising edge of SCP_CLK
t SCP_EN
Time between falling edge of SCP_EN and the first rising edge of SCP_CLK
t_SCP
Rise time for SCP signals
200
ns
tƒ_SCP
Fall time for SCP signals
200
ns
tc
SCPCLK
30
ns
fclock = 1 / tc
50%
50%
tSCP_SKEW
SCPDI
50%
tSCP_DELAY
SCPD0
50%
Figure 4. Serial Communications Bus Timing Parameters
tr_SCP
tf_SCP
Input Controller VCC
SCP_CLK,
SCP_DI,
SCP_EN
VCC/2
0v
Figure 5. Serial Communications Bus Waveform Requirements
18
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7.10 Systems Mounting Interface Loads
PARAMETER
Maximum system mounting interface
load to be applied to the:
MAX
UNIT
Thermal interface area (see Figure 6)
MIN
NOM
156
N
Electrical interface area (see Figure 6)
1334
N
Datum A Interface area (see Figure 6)
712
N
Thermal Interface
Area
Electrical Interface
Area
Other Area
Datum ‘A’ Areas
Figure 6. System Interface Loads
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7.11 Micromirror Array Physical Characteristics
See Mechanical, Packaging, and Orderable Information for additional details.
M
Number of active micromirror columns
N
Number of active micromirror rows
P
Micromirror (pixel) pitch
1920
micromirrors
1080
micromirrors
(1)
(1)
Micromirror active array height
(1)
(1) (2)
10.8
µm
M×P
20.736
mm
N×P
11.664
mm
10
micromirrors/side
Pond of micromirrors (POM)
M±4
M±3
M±2
M±1
See Figure 7.
The structure and qualities of the border around the active array includes a band of partially functional micromirrors called the POM.
These micromirrors are structurally and/or electrically prevented from tilting toward the bright or ON state, but still require an electrical
bias to tilt toward OFF.
0
1
2
3
(1)
(2)
UNIT
(1)
Micromirror active array width
Micromirror array border
VALUE
(1)
0
1
2
3
DMD Active Array
NxP
M x N Micromirrors
N±4
N±3
N±2
N±1
MxP
P
Border micromirrors omitted for clarity.
Details omitted for clarity.
P
Not to scale.
P
P
Refer to the Micromirror Array Physical Characteristics table for M, N, and P specifications.
Figure 7. Micromirror Array Physical Characteristics
20
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7.12 Micromirror Array Optical Characteristics
TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment optical
performance involves making trade-offs between numerous component and system design parameters. See the related
application reports (listed in Related Documentation) for guidelines.
PARAMETER
a
Micromirror tilt angle
β
Micromirror tilt angle variation
Micromirror crossover time
(9)
Micromirror switching time
(10)
TEST CONDITIONS
(1) (4) (6) (7) (8)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
0
DMD landed state
See Figure 13
(1) (4) (5)
12
,
–1
MAX
1
13
(11)
22
0
44
µs
µs
10
Adjacent micromirrors
See Figure 13
degrees
µs
56
Non-adjacent micromirrors
(13)
UNIT
degrees
3
(12)
Orientation of the micromirror axis-of-rotation
TYP
(1) (2) (3)
See Figure 13
Array switching time at 400 MHz with global reset
Non-operating micromirrors
MIN
DMD parked state
See Figure 13
45
46
micromirrors
degrees
Measured relative to the plane formed by the overall micromirror array.
Parking the micromirror array returns all of the micromirrors to an essentially flat (0˚) state (as measured relative to the plane formed by
the overall micromirror array).
When the micromirror array is parked, the tilt angle of each individual micromirror is uncontrolled.
Additional variation exists between the micromirror array and the package datums, as shown in Mechanical, Packaging, and Orderable
Information.
When the micromirror array is landed, the tilt angle of each individual micromirror is dictated by the binary contents of the CMOS
memory cell associated with each individual micromirror. A binary value of 1 results in a micromirror landing in an nominal angular
position of +12°. A binary value of 0 results in a micromirror landing in an nominal angular position of –12°.
Represents the landed tilt angle variation relative to the nominal landed tilt angle.
Represents the variation that can occur between any two individual micromirrors, located on the same device or located on different
devices.
For some applications, it is critical to account for the micromirror tilt angle variation in the overall system optical design. With some
system optical designs, the micromirror tilt angle variation within a device may result in perceivable non-uniformities in the light field
reflected from the micromirror array. With some system optical designs, the micromirror tilt angle variation between devices may result in
colorimetry variations and/or system contrast variation.
Micromirror crossover time is the transition time from landed to landed during a crossover transition and primarily a function of the
natural response time of the micromirrors.
Micromirror switching time is the time after a micromirror clocking pulse until the micromirrors can be addressed again. It included the
micromirror settling time.
Array switching is controlled and coordinated by the DLPC410 (DLPS024) and DLPA200 (DLPS015). Nominal switching time depends
on the system implementation and represents the time for the entire micromirror array to be refreshed (array loaded plus reset and
mirror settling time).
Non-operating micromirror is defined as a micromirror that is unable to transition nominally from the –12° position to +12° or vice versa.
Measured relative to the package datums 'B' and 'C', shown in the Mechanical, Packaging, and Orderable Information.
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Micromirror Array Optical Characteristics (continued)
TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment optical
performance involves making trade-offs between numerous component and system design parameters. See the related
application reports (listed in Related Documentation) for guidelines.
PARAMETER
Micromirror array optical efficiency
TEST CONDITIONS
(14) (15)
363 to 420 nm, with all
micromirrors in the ON state
Window material
Window artifact size
MIN
TYP
MAX
UNIT
68%
Corning 7056
Within the window aperture
400
(16)
Window aperture
See
µm
(17)
(14) The minimum or maximum DMD optical efficiency observed in a specific application depends on numerous application-specific design
variables, such as:
(a) Illumination wavelength, bandwidth/line-width, degree of coherence
(b) Illumination angle, plus angle tolerance
(c) Illumination and projection aperture size, and location in the system optical path
(d) Illumination overfill of the DMD micromirror array
(e) Aberrations present in the illumination source and/or path
(f) Aberrations present in the projection path
The specified nominal DMD optical efficiency is based on the following use conditions:
(a) UV illumination (363 to 420 nm)
(b) Input illumination optical axis oriented at 24° relative to the window normal
(c) Projection optical axis oriented at 0° relative to the window normal
(d) ƒ / 3.0 illumination aperture
(e) ƒ / 2.4 projection aperture
Based on these use conditions, the nominal DMD optical efficiency results from the following four components:
(a) Micromirror array fill factor: nominally 92%
(b) Micromirror array diffraction efficiency: nominally 85%
(c) Micromirror surface reflectivity: nominally 88%
(d) Window transmission: nominally 98% (single pass, through two surface transitions)
(15) Does not account for the effect of micromirror switching duty cycle, which is application dependent. Micromirror switching duty cycle
represents the percentage of time that the micromirror is actually reflecting light from the optical illumination path to the optical projection
path. This duty cycle depends on the illumination aperture size, the projection aperture size, and the micromirror array update rate.
(16) Refers only to non-cleanable artifacts. See the DMD S4xx Glass Cleaning Procedure (DLPA025) and DMD S4xx Handling
Specifications (DLPA014) for recommended handling and cleaning processes.
(17) See Mechanical, Packaging, and Orderable Information for details regarding the size and location of the window aperture.
7.13 Chipset Component Usage Specification
The DLP9500UV is a component of one or more DLP chipsets. Reliable function and operation of the
DLP9500UV requires that it be used in conjunction with the other components of the applicable DLP chipset,
including those components that contain or implement TI DMD control technology. TI DMD control technology is
the TI technology and devices for operating or controlling a DLP DMD.
22
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8 Detailed Description
8.1 Overview
Optically, the DLP9500UV consists of 2,073,600 highly reflective, digitally switchable, micrometer-sized mirrors
(micromirrors), organized in a two-dimensional array of 1920 micromirror columns by 1080 micromirror rows.
Each aluminum micromirror is approximately 10.8 microns in size (see the Micromirror Pitch in Figure 12) and is
switchable between two discrete angular positions: –12° and 12°. The angular positions are measured relative to
a 0° flat state, which is parallel to the array plane (see Figure 13). The tilt direction is perpendicular to the hingeaxis, which is positioned diagonally relative to the overall array. The On State landed position is directed toward
row 0, column 0 (upper left) corner of the device package (see the Micromirror Hinge-Axis Orientation in
Figure 12). In the field of visual displays, the 1920 × 1080 pixel resolution is referred to as 1080p.
Each individual micromirror is positioned over a corresponding CMOS memory cell. The angular position of a
specific micromirror is determined by the binary state (logic 0 or 1) of the corresponding CMOS memory cell
contents, after the mirror clocking pulse is applied. The angular position (–12° or +12°) of the individual
micromirrors changes synchronously with a micromirror clocking pulse, rather than being synchronous with the
CMOS memory cell data update. Therefore, writing a logic 1 into a memory cell followed by a mirror clocking
pulse will result in the corresponding micromirror switching to a 12° position. Writing a logic 0 into a memory cell
followed by a mirror clocking pulse will result in the corresponding micromirror switching to a –12° position.
Updating the angular position of the micromirror array consists of two steps. First, updating the contents of the
CMOS memory. Second, application of a micromirror clocking pulse to all or a portion of the micromirror array
(depending upon the configuration of the system). Micromirror clocking pulses are generated externally by two
DLPA200s, with application of the pulses being coordinated by the DLPC410 controller.
Around the perimeter of the 1920 by 1080 array of micromirrors is a uniform band of border micromirrors. The
border micromirrors are not user-addressable. The border micromirrors land in the –12° position once power has
been applied to the device. There are 10 border micromirrors on each side of the 1920 by 1080 active array.
Figure 8 shows a DLPC410 and DLP9500UV chipset block diagram. The DLPC410 and DLPA200s control and
coordinate the data loading and micromirror switching for reliable DLP9500UV operation. The DLPR410 is the
programmed PROM required to properly configure the DLPC410 controller. For more information on the chipset
components, see Application and Implementation. For a typical system application using the DLP Discovery 4100
chipset including a DLP9500UV, see Figure 20.
8.2 Functional Block Diagram
Figure 8 shows a simplified system block diagram with the use of the DLPC410 with the following chipset
components:
DLPC410
Xilinx [XC5VLX30] FPGA configured to provide high-speed DMD data and control, and DLPA200
timing and control
DLPR410
[XCF16PFSG48C] serial flash PROM contains startup configuration information (EEPROM)
DLPA200
Two DMD micromirror drivers for the DLP9500UV DMD
DLP9500UV Spatial light modulator (DMD)
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DLPC410
PWR_FLOAT
ROWMD(1:0)
ROWAD(10:0)
RST2BLKZ
BLKMD(1:0)
BLKAD(10:0)
ECP2_FINISHED
DMD_TYPE(3:0)
Bank A Input
Bank B Input
Bank C Input
DDC_DCLKOUT_C
DDC_SCTRL_C
Bank B Input
DDC_DOUT_C(15:0)
DDC_DCLKOUT_D
DDC_SCTRL_D
DDC_DOUT_D(15:0)
DMD SCP
SCPCLK
SCPDO
SCPDI
DMD_A_SCPENZ
DMD_B_SCPENZ
DAD_A_SCPENZ
DAD_B_SCPENZ
DLPA200
DAD_A_STROBE
DAD_A_MODE(1:0)
DAD_A_SEL(1:0)
DAD_A_ADDR(3:0)
A
MBRST1_(15:0)
DAD_OEZ
DAD_INIT
PROM_CCK_DDC
PROGB_DDC
INTB_DDC
RDWR_B_0
TDO_XCF16DDC
TCK_JTAG
TCK_JTAG
TDO_DDC
DDC_M(2:0)
ECP2_M_TP(31:0)
DAD_B_STROBE
DAD_B_MODE(1:0)
DAD_B_SEL(1:0)
DAD_B_ADDR(3:0)
B
MBRST2_(15:0)
JTAG Interface
HSWAPEN_0
DLPA200
Resets Side 2
DONE_DDC
Resets
PROM_DO_DDC
CS_B_0
JTAG Header
DDC_DOUT_B(15:0)
DAD B SCP
JTAG Interface
DLPR410
TDI_JTAG
Program Interface
DDC_VERSION(2:0)
Program Interface
Info Input
INIT_ACTIVE
Info Output
RST_ACTIVE
Serial Data Bus
WDT_ENBLZ
DAD A Output
STEPVCC
DAD B Output
Control Signals Output
NS_FLIP
Control Signals Input
COMP_DATA
DDC_SCTRL_B
Resets Side 1
DDC_DIN_D(15:0)
DDC_DCLKOUT_B
Resets
DVALID_D
DDC_DOUT_A(15:0)
DAD A SCP
DDC_DCLK_D
DDC_SCTRL_A
DAD B Input
Bank D Output
DDC_DIN_C(15:0)
DDC_DCLKOUT_A
DAD A Input
DVALID_C
Bank A Output
DDC_DCLK_C
Bank B Output
Bank C Output
DDC_DIN_B(15:0)
Bank C Output
DVALID_B
Bank B Output
DDC_DCLK_B
Bank A Input
Bank B Output
DDC_DIN_A(15:0)
Bank B Input
DVALID_A
Bank C Input
DDC_DCLK_A
DLP9500UV
= LVDS Bus
Bank D Input
Bank A Output
USER INTERFACE
VLED0
VLED1
ARSTZ
OSC
50 Mhz
PWRDN
DDCSPARE(1:0)
DMD_A_RESET
CLKIN_R
Figure 8. DLPC410, DLPA200, DLPR410, and DLP9500UV Functional Block Diagram
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8.3 Feature Description
Table 1. DMD Overview
(1)
DMD
ARRAY
DLP9500UV - 0.95"
1080p
1920 × 1080
SINGLE BLOCK
MODE
(Patterns/s)
23148
GLOBAL RESET
MODE
(Patterns/s)
DATA RATE
(Giga Pixels/s)
MIRROR PITCH
17857
48
10.8 μm
(1)
This is for single block mode resets.
8.3.1 DLPC410 - Digital Controller for DLP Discovery 4100 Chipset
The DLPC410 chipset includes the DLPC410 controller which provides a high-speed LVDS data and control
interface for DMD control. This interface is also connected to a second FPGA used to drive applications (not
included in the chipset). The DLPC410 generates DMD and DLPA200 initialization and control signals in
response to the inputs on the control interface.
For more information, see the DLPC410 data sheet (DLPS024).
8.3.2 DLPA200 - DMD Micromirror Drivers
DLPA200 micromirror drivers provide the micromirror clocking pulse driver functions for the DMD. Two drivers
are required for DLP9500UV.
The DLPA200 is designed to work with multiple DLP chipsets. Although the DLPA200 contains 16 MBSRT output
pins, only 15 lines are used with the DLP9500 chipset. For more information see and the DLPA200 data sheet
(DLPS015).
8.3.3 DLPR410 - PROM for DLP Discovery 4100 Chipset
The DLPC410 controller is configured at startup from the DLPR410 PROM. The contents of this PROM can not
be altered. For more information, see the DLPR410 data sheet (DLPS027) the DLPC410 data sheet (DLPS024).
8.3.4 DLP9500 - DLP 0.95 1080p 2xLVDS UV Type-A DMD 1080p DMD
8.3.4.1 DLP9500UV 1080p Chipset Interfaces
This section will describe the interface between the different components included in the chipset. For more
information on component interfacing, see Application and Implementation.
8.3.4.1.1 DLPC410 Interface Description
8.3.4.1.1.1 DLPC410 IO
Table 2 describes the inputs and outputs of the DLPC410 to the user. For more details on these signals, see the
DLPC410 data sheet (DLPS024).
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Table 2. Input/Output Description
PIN NAME
DESCRIPTION
I/O
ARST
Asynchronous active low reset
I
CLKIN_R
Reference clock, 50 MHz
I
DIN_[A,B,C,D](15:0)
LVDS DDR input for data bus A,B,C,D (15:0)
I
DCLKIN[A,B,C,D]
LVDS inputs for data clock (200 - 400 MHz) on bus A, B, C, and D
I
DVALID[A,B,C,D]
LVDS input used to start write sequence for bus A, B, C, and D
I
ROWMD(1:0)
DMD row address and row counter control
I
ROWAD(10:0)
DMD row address pointer
I
BLK_AD(3:0)
DMD mirror block address pointer
I
BLK_MD(1:0)
DMD mirror block reset and clear command modes
I
PWR_FLOAT
Used to float DMD mirrors before complete loss of power
I
DMD_TYPE(3:0)
DMD type in use
O
RST_ACTIVE
Indicates DMD mirror reset in progress
O
INIT_ACTIVE
Initialization in progress.
O
VLED0
System “heartbeat” signal
O
VLED1
Denotes initialization complete
O
8.3.4.1.1.2 Initialization
The INIT_ACTIVE (Table 2) signal indicates that the DLP9500UV, DLPA200s, and DLPC410 are in an
initialization state after power is applied. During this initialization period, the DLPC410 is initializing the
DLP9500UV and DLPA200s by setting all internal registers to their correct states. When this signal goes low, the
system has completed initialization. System initialization takes approximately 220 ms to complete. Data and
command write cycles should not be asserted during the initialization.
During initialization the user must send a training pattern to the DLPC410 on all data and DVALID lines to
correctly align the data inputs to the data clock. For more information, see the interface training pattern
information in the DLPC410 data sheet.
8.3.4.1.1.3 DMD Device Detection
The DLPC410 automatically detects the DMD type and device ID. DMD_TYPE (Table 2) is an output from the
DLPC410 that contains the DMD information.
8.3.4.1.1.4 Power Down
To ensure long term reliability of the DLP9500UV, a shutdown procedure must be executed. Prior to power
removal, assert the PWR_FLOAT (Table 2) signal and allow approximately 300 µs for the procedure to complete.
This procedure assures the mirrors are in a flat state.
8.3.4.1.2 DLPC410 to DMD Interface
8.3.4.1.2.1 DLPC410 to DMD IO Description
Table 3 lists the available controls and status pin names and their corresponding signal type, along with a brief
functional description.
Table 3. DLPC410 to DMD I/O Pin Descriptions
PIN NAME
DESCRIPTION
I/O
DDC_DOUT_[A,B,C,D](15:0)
LVDS DDR output to DMD data bus A,B,C,D (15:0)
O
DDC_DCLKOUT_[A,B,C,D]
LVDS output to DMD data clock A,B,C,D
O
DDC_SCTRL_[A,B,C,D]
LVDS DDR output to DMD data control A,B,C,D
O
26
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8.3.4.1.2.2 Data Flow
Figure 9 shows the data traffic through the DLPC410. Special considerations are necessary when laying out the
DLPC410 to allow best signal flow.
LVDS BUS A
sDIN_A(15:0)
sDCLK_A
sDVALID_A
LVDS BUS B
sDIN_B(15:0)
sDCLK_B
sDVALID_B
LVDS BUS D
LVDS BUS C
sDIN_D(15:0)
sDCLK_D
sDVALID_D
sDIN_C(15:0)
sDCLK_C
sDVALID_C
DLPC410
LVDS BUS D
LVDS BUS A
sDOUT_D(15:0)
sDCLKOUT_D
sSCTRL_D
sDOUT_A(15:0)
sDCLKOUT_A
sSCTRL_A
LVDS BUS C
sDOUT_C(15:0)
sDCLKOUT_C
sSCTRL_C
LVDS BUS B
sDIN_B(15:0)
sDCLK_B
sDVALID_B
Figure 9. DLPC410 Data Flow
Four LVDS buses transfer the data from the user to the DLPC410. Each bus has its data clock that is input edge
aligned with the data (DCLK). Each bus also has its own validation signal that qualifies the data input to the
DLPC410 (DVALID).
Output LVDS buses transfer data from the DLPC410 to the DMD. Output buses LVDS C and LVDS D are used
in addition to LVDS A and LVDS B with the DLP9500UV.
8.3.4.1.3 DLPC410 to DLPA200 Interface
8.3.4.1.3.1 DLPA200 Operation
The DLPA200 DMD micromirror driver is a mixed-signal application-specific integrated circuit (ASIC) that
combines the necessary high-voltage power supply generation and micromirror clocking pulse functions for a
family of DMDs. The DLPA200 is programmable and controllable to meet all current and anticipated DMD
requirements.
The DLPA200 operates from a 12-V power supply input. For more detailed information on the DLPA200, see the
DLPA200 data sheet.
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8.3.4.1.3.2 DLPC410 to DLPA200 IO Description
The serial communications port (SCP) is a full duplex, synchronous, character-oriented (byte) port that allows
exchange of commands from the DLPC410 to the DLPA200s.
DLPA200
SCP bus
DLPC410
SCP bus
DLPA200
Figure 10. Serial Port System Configuration
Five signal lines are associated with the SCP bus: SCPEN, SCPCK, SCPDI, SCPDO, and IRQ.
Table 4 lists the available controls and status pin names and their corresponding signal type, along with a brief
functional description.
Table 4. DLPC410 to DLPA200 I/O Pin Descriptions
PIN NAME
DESCRIPTION
I/O
A_SCPEN
Active-low chip select for DLPA200 serial bus
O
A_STROBE
DLPA200 control signal strobe
O
A_MODE(1:0)
DLPA200 mode control
O
A_SEL(1:0)
DLPA200 select control
O
A_ADDR(3:0)
DLPA200 address control
O
B_SCPEN
Active-low chip select for DLPA200 serial bus (2)
O
B_STROBE
DLPA200 control signal strobe (2)
O
B_MODE(1:0)
DLPA200 mode control
O
B_SEL(1:0)
DLPA200 select control
O
B_ADDR(3:0)
DLPA200 address control
O
The DLPA200 provides a variety of output options to the DMD by selecting logic control inputs: MODE[1:0],
SEL[1:0] and reset group address A[3:0] (Table 4). The MODE[1:0] input determines whether a single output, two
outputs, four outputs, or all outputs, will be selected. Output levels (VBIAS, VOFFSET, or VRESET) are selected
by SEL[1:0] pins. Selected outputs are tri-stated on the rising edge of the STROBE signal and latched to the
selected voltage level after a break-before-make delay. Outputs will remain latched at the last micromirror
clocking pulse waveform level until the next micromirror clocking pulse waveform cycle.
8.3.4.1.4 DLPA200 to DLP9500UV Interface
8.3.4.1.4.1 DLPA200 to DLP9500UV Interface Overview
The DLPA200 generates three voltages: VBIAS, VRESET, and VOFFSET that are supplied to the DMD MBRST
lines in various sequences through the micromirror clocking pulse driver function. VOFFSET is also supplied
directly to the DMD as DMDVCC2. A fourth DMD power supply, DMDVCC, is supplied directly to the DMD by
regulators.
The function of the micromirror clocking pulse driver is to switch selected outputs in patterns between the three
voltage levels (VBIAS, VRESET and VOFFSET) to generate one of several micromirror clocking pulse
waveforms. The order of these micromirror clocking pulse waveform events is controlled externally by the logic
control inputs and timed by the STROBE signal. DLPC410 automatically detects the DMD type and then uses the
DMD type to determine the appropriate micromirror clocking pulse waveform.
28
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A direct micromirror clocking pulse operation causes a mirror to transition directly from one latched state to the
next. The address must already be set up on the mirror electrodes when the micromirror clocking pulse is
initiated. Where the desired mirror display period does not allow for time to set up the address, a micromirror
clocking pulse with release can be performed. This operation allows the mirror to go to a relaxed state regardless
of the address while a new address is set up, after which the mirror can be driven to a new latched state.
A mirror in the relaxed state typically reflects light into a system collection aperture and can be thought of as off
although the light is likely to be more than a mirror latched in the off state. System designers should carefully
evaluate the impact of relaxed mirror conditions on optical performance.
8.3.5 Measurement Conditions
The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be taken into account. Figure 11 shows an equivalent test load circuit for the
output under test. The load capacitance value stated is only for characterization and measurement of AC timing
signals. This load capacitance value does not indicate the maximum load the device is capable of driving. All rise
and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOL MAX and VOH
MIN for output clocks.
LOAD CIRCUIT
RL
From Output
Under Test
Tester
Channel
CL = 50 pF
CL = 5 pF for Disable Time
Figure 11. Test Load Circuit for AC Timing Measurements
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Incident
Illumination
Package Pin
A1 Corner
Details Omitted for Clarity
Not to Scale
DMD
Micromirror
Array
0
(Border micromirrors eliminated for clarity)
M±1
Active Micromirror Array
0
N±1
Micromirror Hinge-Axis Orientation
Micromirror Pitch
P (um)
45°
P (um)
P (um)
On State
Tilt Direction
Off State
Tilt Direction
P (um)
Figure 12. DMD Micromirror Array, Pitch, and Hinge-Axis Orientation
30
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Ill Inc
um id
in en
at t
io
n
www.ti.com
Package Pin
A1 Corner
Ill Inc
um id
in en
at t
io
n
DLP9500UV
Two
“On-State”
Micromirrors
For Reference
th
nt t Pa
ide gh
Inc on-Li
ati
min
Illu
ath
nt
ide ht P
Inc n-Lig
atio
min
Illu
Projected-Light
Path
Two
“Off-State”
Micromirrors
gh
Li
eat th
t
S a
ff- P
t
Flat-State
( “parked” )
Micromirror Position
O
a±b
-a ± b
Silicon Substrate
“On-State”
Micromirror
Silicon Substrate
“Off-State”
Micromirror
Figure 13. Micromirror Landed Positions and Light Paths
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8.4 Device Functional Modes
The DLP9500UV has only one functional mode; it is set to be highly optimized for low latency and high speed in
generating mirror clocking pulses and timings.
When operated with the DLPC410 controller in conjunction with the DLPA200 drivers, the DLP9500UV can be
operated in several display modes. The DLP9500UV is loaded as 15 blocks of 72 rows each. The first 64 bits of
pixel data and last 64 bits of pixel data for all rows are not visible. Below is a representation of how the image is
loaded by the different micromirror clocking pulse modes. Figure 14, Figure 15, Figure 16, and Figure 17 show
how the image is loaded by the different micromirror clocking pulse modes.
There are four micromirror clocking pulse modes that determine which blocks are reset when a micromirror
clocking pulse command is issued:
• Single block mode
• Dual block mode
• Quad block mode
• Global mode
8.4.1 Single Block Mode
In single block mode, a single block can be loaded and reset in any order. After a block is loaded, it can be reset
to transfer the information to the mechanical state of the mirrors.
Figure 14. Single Block Mode
8.4.2 Dual Block Mode
In dual block mode, reset blocks are paired together as follows (0-1), (2-3), (4-5), (6-7), (8-9), (10-11), (12-13),
and (14). These pairs can be reset in any order. After data is loaded a pair can be reset to transfer the
information to the mechanical state of the mirrors.
Figure 15. Dual Block Mode
32
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Device Functional Modes (continued)
8.4.3 Quad Block Mode
In quad block mode, reset blocks are grouped together in fours as follows (0-3), (4-7), (8-11) and (12-14). Each
quad group can be randomly addressed and reset. After a quad group is loaded, it can be reset to transfer the
information to the mechanical state of the mirrors.
Figure 16. Quad Block Mode
8.4.4 Global Block Mode
In global mode, all reset blocks are grouped into a single group and reset together. The entire DMD must be
loaded with the desired data before issuing a Global Reset to transfer the information to the mechanical state of
the mirrors.
Figure 17. Global Mode
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8.5 Window Characteristics and Optics
NOTE
TI assumes no responsibility for image quality artifacts or DMD failures caused by optical
system operating conditions exceeding limits described previously.
8.5.1 Optical Interface and System Image Quality
TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment
optical performance involves making trade-offs between numerous component and system design parameters.
Optimizing system optical performance and image quality strongly relate to optical system design parameter
trades. Although it is not possible to anticipate every conceivable application, projector image quality and optical
performance is contingent on compliance to the optical system operating conditions described in the following
sections.
8.5.2 Numerical Aperture and Stray Light Control
The angle defined by the numerical aperture of the illumination and projection optics at the DMD optical area
should be the same. This angle should not exceed the nominal device mirror tilt angle unless appropriate
apertures are added in the illumination, projection pupils, or both to block out flat-state and stray light from the
projection lens. The mirror tilt angle defines DMD capability to separate the ON optical path from any other light
path, including undesirable flat-state specular reflections from the DMD window, DMD border structures, or other
system surfaces near the DMD such as prism or lens surfaces. If the numerical aperture exceeds the mirror tilt
angle, or if the projection numerical aperture angle is more than two degrees larger than the illumination
numerical aperture angle, objectionable artifacts in the display’s border and/or active area could occur.
8.5.3 Pupil Match
TI recommends the exit pupil of the illumination is nominally centered within 2° (two degrees) of the entrance
pupil of the projection optics. Misalignment of pupils can create objectionable artifacts in the display’s border
and/or active area, which may require additional system apertures to control, especially if the numerical aperture
of the system exceeds the pixel tilt angle.
8.5.4 Illumination Overfill
The active area of the device is surrounded by an aperture on the inside DMD window surface that masks
structures of the DMD device assembly from normal view. The aperture is sized to anticipate several optical
operating conditions. Overfill light illuminating the window aperture can create artifacts from the edge of the
window aperture opening and other surface anomalies that may be visible on the screen. The illumination optical
system should be designed to limit light flux incident anywhere on the window aperture from exceeding
approximately 10% of the average flux level in the active area. Depending on the optical architecture of a
particular system, overfill light may have to be further reduced below the suggested 10% level to be acceptable.
34
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8.6 Micromirror Array Temperature Calculation
Achieving optimal DMD performance requires proper management of the maximum DMD case temperature, the
maximum temperature of any individual micromirror in the active array, the maximum temperature of the window
aperture, and the temperature gradient between case temperature and the predicted micromirror array
temperature (see Figure 18).
See the Recommended Operating Conditions for applicable temperature limits.
8.6.1 Package Thermal Resistance
The DMD is designed to conduct absorbed and dissipated heat to the back of the type A package where it can
be removed by an appropriate heat sink. The heat sink and cooling system must be capable of maintaining the
package within the specified operational temperatures, refer to Figure 18. The total heat load on the DMD is
typically driven by the incident light absorbed by the active area; although other contributions include light energy
absorbed by the window aperture and electrical power dissipation of the array.
8.6.2 Case Temperature
The temperature of the DMD case can be measured directly. For consistency, thermal test point locations 1, 2,
and 3 are defined, as shown in Figure 18.
TP2
TP2
27.80
TP3
TP3 (TP2)
TP3
TP1
21.08
Figure 18. Thermal Test Point Location
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Micromirror Array Temperature Calculation (continued)
8.6.3 Micromirror Array Temperature Calculation
Active array temperature cannot be measured directly; therefore, it must be computed analytically from
measurement points on the outside of the package, package thermal resistance, electrical power, and
illumination heat load. The relationship between array temperature and the reference ceramic temperature (test
point number 1 in Figure 18) is provided by the following equations:
TArray = Computed DMD active array temperature
TArray = Measured Ceramic temperature at location (test point number 1) + (Temperature increase due to power incident
to the array × array-to-ceramic resistance)
TArray = TCeramic+ (QArray × RArray-To-Ceramic)
where
•
•
•
TCeramic = Measured ceramic temperature (°C) at location (test point number 1)
RArray-To-Ceramic = DMD package thermal resistance from array to outside ceramic (°C/W)
QArray = Total DMD array power, which is both electrical plus absorbed on the DMD active array (W)
QArray = QElectrical + (QIllumination × DMD absorption constant (0.42))
where
•
•
•
QElectrical = Approximate nominal electrical internal power dissipation (W)
QIllumination = [Illumination power density × illumination area on DMD] (W)
DMD absorption constant = 0.42
The electrical power dissipation of the DMD is variable and depends on the voltages, data rates and operating
frequencies. The nominal electrical power dissipation of the DMD is variable and depends on the operating state
of mirrors and the intensity of the light source. The DMD absorption constant of 0.42 assumes nominal operation
with an illumination distribution of 83.7% on the active array, 11.9% on the array border, and 4.4% on the window
aperture. A system aperture may be required to limit power incident on the package aperture since this area
absorbs much more efficiently than the array.
Sample Calculation:
• Illumination power density = 2 W/cm2
• Illumination area = (2.0736 cm × 1.1664 cm) / 83.7% = 2.89 cm2 (assumes 83.7% on the active array and
16.3% overfill)
• QIllumination= 2 W/cm2 × 2.89 cm2 = 5.78 W
• QElectrical = 4.4 W
• RArray-To-Ceramic = 0.5°C/W
• TCeramic = 20°C (measured on ceramic)
• QArray = 4.4 W + (5.78 W × 0.42) = 6.83 W
• TArray = 20°C + (6.83 W × 0.5°C/W) = 23.4°C
36
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8.7 Micromirror Landed-On and Landed-Off Duty Cycle
8.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the amount of time (as a
percentage) that an individual micromirror is landed in the On–state versus the amount of time the same
micromirror is landed in the Off–state.
As an example, a landed duty cycle of 100/0 indicates that the referenced pixel is in the On-state 100% of the
time (and in the Off-state 0% of the time); whereas 0/100 would indicate that the pixel is in the Off-state 100% of
the time. Likewise, 50/50 indicates that the pixel is On 50% of the time and Off 50% of the time.
Note that when assessing landed duty cycle, the time spent switching from one state (ON or OFF) to the other
state (OFF or ON) is considered negligible and is thus ignored.
Because a micromirror can only be landed in one state or the other (on or off), the two numbers (percentages)
always add to 100.
8.7.2 Landed Duty Cycle and Useful Life of the DMD
Knowing the long-term average landed duty cycle (of the end product or application) is important because
subjecting all (or a portion) of the DMD’s micromirror array (also called the active array) to an asymmetric landed
duty cycle for a prolonged period of time can reduce the usable life of the DMD.
Note that it is the symmetry/asymmetry of the landed duty cycle that is of relevance. The symmetry of the landed
duty cycle is determined by how close the two numbers (percentages) are to being equal. For example, a landed
duty cycle of 50/50 is perfectly symmetrical whereas a landed duty cycle of 100/0 or 0/100 is perfectly
asymmetrical.
8.7.3 Landed Duty Cycle and Operational DMD Temperature
Operational DMD temperature and landed duty cycle interact to affect the usable life of the DMD, and this
interaction can be exploited to reduce the impact that an asymmetrical landed duty cycle has on the DMD’s
usable life.
In practice, this curve specifies the maximum operating DMD temperature that the DMD should be operated at
for a give long-term average landed duty.
8.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
During a given period of time, the landed duty cycle of a given pixel follows from the image content being
displayed by that pixel.
For example, in the simplest case, when displaying pure-white on a given pixel for a given time period, that pixel
will experience a 100/0 landed duty cycle during that time period. Likewise, when displaying pure-black, the pixel
will experience a 0/100 landed duty cycle.
Between the two extremes (ignoring for the moment color and any image processing that may be applied to an
incoming image), the landed duty cycle tracks one-to-one with the gray scale value, as shown in Table 5.
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Table 5. Grayscale Value and Landed Duty Cycle
38
GRAYSCALE VALUE
LANDED DUTY CYCLE
0%
0/100
10%
10/90
20%
20/80
30%
30/70
40%
40/60
50%
50/50
60%
60/40
70%
70/30
80%
80/20
90%
90/10
100%
100/0
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The DLP9500UV devices must be coupled with the DLPC410 controller to provide a reliable solution for many
different applications. The DMDs are spatial light modulators which reflect incoming light from an illumination
source to one of two directions, with the primary direction being into a projection collection optic. Each application
is derived primarily from the optical architecture of the system and the format of the data coming into the
DLPC410. Applications of interest include 3D printing, lithography, medical systems, and compressive sensing.
9.1.1 DMD Reflectivity Characteristics
TI assumes no responsibility for end-equipment reflectivity performance. Achieving the desired end-equipment
reflectivity performance involves making trade-offs between numerous component and system design
parameters. Typical DMD reflectivity characteristics over UV exposure times are represented in Figure 19.
100
90
Relative Reflectivity (%)
80
70
60
50
40
30
20
30°C
25°C
20°C
10
0
0
10000
20000
30000
Exposure Hours
40000
50000
D001
2.3 W/cm2, 363 to 400 nm, 25°C
Figure 19. Nominal DMD Relative Reflectivity Percentage vs Total Exposure Hours
DMD reflectivity includes micromirror surface reflectivity and window transmission. The DMD was characterized
for DMD reflectivity using a broadband light source (200-W metal-halide lamp). Data is based off of a 2.3 W/cm2
UV exposure at the DMD surface (365 nm peak output) using a 363 nm high pass filter between the light source
and the DMD. (Contact your local Texas Instruments representative for additional information about power
density measurements and UV filter details.)
9.1.1.1 Design Considerations Influencing DMD Reflectivity
Optimal, long-term performance of the digital micromirror device (DMD) can be affected by various application
parameters. The following is a list of some of these application parameters and includes high level design
recommendations that may help extend relative reflectivity from time zero:
• Illumination spectrum – using longer wavelengths for operation while preventing shorter wavelengths from
striking the DMD
• Illumination power density – using lower power density
• DMD case temperature – operating the DMD with the case temperature at the low end of its specification
• Cumulative incident illumination – Limiting the total hours of UV illumination exposure when the DMD is not
actively steering UV light in the application. For example, a design might include a shutter to block the
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Application Information (continued)
•
40
illumination or LED illumination where the LEDs can be strobed off during periods not requiring UV exposure.
Micromirror landed duty cycle – applying a 50/50 duty cycle pattern during periods where operational patterns
are not required.
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9.2 Typical Application
The DLP9500UV DMD is designed with a window which allows transmission of ultraviolet (UV) light. This makes it well suited for UV applications
requiring fast, spatially programmable light patterns using the micromirror array. UV wavelengths can affect the DMD differently than visible wavelengths.
There are system level considerations which should be leveraged when designing systems using this DMD.
OPTICAL
SENSOR
LED
DRIVERS
(CAMERA)
LEDS
OPTICS
LED
SENSORS
USER
INTERFACE
LVDS BUS (A,B,[C,D])
LVDS BUS (A,B,[C,D])
DDC_DCLK, DVALID, DDC_DIN(15:0)
DDC_DCLKOUT, DDCSCTRL, DDC_DOUT(15:0)
SCP BUS
ROW and BLOCK SIGNALS
SCPCLK, SCPDO, SCPDI, DMD_SCPENZ, DAD_A_SCPENZ, DAD_B_SCPENZ
ROWMD(1:0), ROWAD(10:0), BLKMD(1:0), BLKAD(3:0), RST2BLKZ
CONNECTIVITY
(USB, ETHERNET, ETC.)
CONTROL SIGNALS
COMP_DATA, NS_FLIP, WDT_ENBLZ, PWR_FLOAT
USER - MAIN
PROCESSOR / FPGA
DAD CONTROL
DAD_A_MODE(1:0), DAD_A_SEL(1:0),
DAD_A_ADDR(3:0), DAD_OEZ, DAD_INIT
DLPC410 INFO SIGNALS
RST_ACTIVE, INIT_ACTIVE, ECP2_FINISHED,
DMD_TYPE(3:0), DDC_VERSION(2:0)
MBRST1_(15:0)
DLP9500UV
DLPA200
A
DLPC410
PGM SIGNALS
VOLATILE
and
NON-VOLATILE
STORAGE
DLPR410
PROM_CCK_DDC, PROGB_DDC,
PROM_DO_DDC, DONE_DDC, INTB_DDC
JTAG
ARSTZ
CLKIN_R
OSC
50 Mhz
~
DAD CONTROL
DAD_B_MODE(1:0), DAD_B_SEL(1:0),
DAD_B_ADDR(3:0), DAD_OEZ, DAD_INIT
MBRST2_(15:0)
DLPA200
VLED0
B
VLED1
DMD_RESET
POWER MANAGMENT
Figure 20. DLPC410 and DLP9500UV Embedded Example Block Diagram
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9.2.1 Design Requirements
All applications using the DLP9500UV chipset require both the controller and the DMD components for operation.
The system also requires an external parallel flash memory device loaded with the DLPC410 configuration and
support firmware. The chipset has several system interfaces and requires some support circuitry. The following
interfaces and support circuitry are required:
• DLPC410 system interfaces:
– Control interface
– Trigger interface
– Input data interface
– Illumination interface
– Reference clock
– Program interface
• DLP9500UV interfaces:
– DLPC410 to DLP9500UV digital data
– DLPC410 to DLP9500UV control interface
– DLPC410 to DLP9500UV micromirror reset control interface
– DLPC410 to DLPA200 micromirror driver
– DLPA200 to DLP9500UV micromirror reset
9.2.1.1 Device Description
The DLP9500UV 1080p chipset offers developers a convenient way to design a wide variety of industrial,
medical, telecom and advanced display applications by delivering maximum flexibility in formatting data,
sequencing data, and light patterns.
The DLP9500UV 1080p chipset includes the following four components: DMD digital controller (DLPC410),
EEPROM (DLPR410), DMD micromirror driver (DLPA200), and a DMD (DLP9500UV).
DLPC410 Digital Controller for DLP Discovery 4100 chipset
• Provides high speed 2XLVDS data and control interface to the user
• Drives mirror clocking pulse and timing information to the DLPA200
• Supports random row addressing
• Controls illumination
DLPR410 PROM for DLP Discovery 4100 chipset
• Contains startup configuration information for the DLPC410
DLPA200 DMD Micromirror Driver
• Generates micromirror clocking pulse control (sometimes referred to as a reset) of 15 banks of DMD
mirrors. (Two are required for the DLP9500UV).
DLP9500UV DLP 0.95 1080p 2xLVDS UV Type-A DMD
• Steers light in two digital positions (+12° and –12°) using 1920 × 1080 micromirror array of aluminum
mirrors.
Table 6. DLP DLP9500UV Chipset Configurations
QUANTITY
TI PART
1
DLP9500UV
DESCRIPTION
1
DLPC410
Digital Controller for DLP Discovery 4100 chipset
1
DLPR410
PROM for DLP Discovery 4100 chipset
2
DLPA200
DMD Micromirror Driver
DLP 0.95 1080p 2xLVDS UV Type-A DMD
Reliable function and operation of DLP9500UV 1080p chipsets require the components be used in conjunction
with each other. This document describes the proper integration and use of the DLP9500UV 1080p chipset
components.
The DLP9500UV 1080p chipset can be combined with a user programmable application FPGA (not included) to
create high performance systems.
42
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DLP9500UV
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DLPS033C – NOVEMBER 2014 – REVISED MARCH 2017
9.2.2 Detailed Design Procedure
The DLP9500UV DMD is designed with a window which allows transmission of UV light. This makes it well
suited for UV applications requiring fast, spatially programmable light patterns using the micromirror array. UV
wavelengths can affect the DMD differently than visible wavelengths. There are system level considerations
which should be leveraged when designing systems using this DMD.
9.2.3 Application Curve
100
90
80
o
UV AOI = 0
Transmittance (%)
70
60
50
40
30
20
10
0
300
320
340
360
380
400
420
440
460
480
500
Wavelength (nm)
Type A UVA on 7056 glass (3 mm thick)
Figure 21. Corning 7056 UV Window Transmittance (Maximum Transmission Region)
10 Power Supply Recommendations
10.1 Power-Up Sequence (Handled by the DLPC410)
The sequence of events for DMD system power-up is:
1. Apply logic supply voltages to the DLPA200 and to the DMD according to DMD specifications.
2. Place DLPA200 drivers into high impedance states.
3. Turn on DLPA200 bias, offset, or reset supplies according to driver specifications.
4. After all supply voltages are assured to be within the limits specified and with all micromirror clocking pulse
operations logically suspended, enable all drivers to either VOFFSET or VBIAS level.
5. Begin micromirror clocking pulse operations.
10.2 DMD Power-Up and Power-Down Procedures
Failure to adhere to the prescribed power-up and power-down procedures may affect device reliability. The
DLP9500UV power-up and power-down procedures are defined by the DLPC410 data sheet (DLPS024). These
procedures must be followed to ensure reliable operation of the device.
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11 Layout
11.1 Layout Guidelines
The DLP9500UV is part of a chipset that is controlled by the DLPC410 in conjunction with the DLPA200. These
guidelines are targeted at designing a PCB board with these components.
11.1.1 Impedance Requirements
Signals should be routed to have a matched impedance of 50 Ω ±10% except for LVDS differential pairs
(DMD_DAT_Xnn, DMD_DCKL_Xn, and DMD_SCTRL_Xn) which should be matched to 100 Ω ±10% across
each pair.
11.1.2 PCB Signal Routing
When designing a PCB board for the DLP9500UV controlled by the DLPC410 in conjunction with the DLPA200s,
the following are recommended:
Signal trace corners should be no sharper than 45°. Adjacent signal layers should have the predominate traces
routed orthogonal to each other. TI recommends that critical signals be hand routed in the following order: DDR2
Memory, DMD (LVDS signals), then DLPA200 signals.
TI does not recommend signal routing on power or ground planes.
TI does not recommend ground plane slots.
High speed signal traces should not cross over slots in adjacent power and/or ground planes.
Table 7. Important Signal Trace Constraints
SIGNAL
CONSTRAINTS
LVDS (DMD_DAT_xnn,
DMD_DCKL_xn, and
DMD_SCTRL_xn)
P-to-N data, clock, and SCTRL: