DLPR910
DLPS065D – SEPTEMBER 2015 – REVISED DECEMBER 2021
DLPR910 Configuration PROM
1 Features
•
•
•
•
3 Description
Pre-programmed Xilinx® PROM configures the
DLPC910 DMD digital controller
I/O pins compatible with 1.8 V to 3.3 V
1.8 V core supply voltage
–40°C to 85°C operating temperature range
2 Applications
•
•
•
Lithography
– Direct Imaging
– Flat Panel Display
– Printed Circuit Board Manufacturing
Industrial
– 3D Printing
– 3D Scanners for Machine Vision
– Quality Control
Displays
– 3D Imaging
– Intelligent and Adaptive Lighting
– Augmented Reality and Information Overlay
The DLPR910 device is a programmed PROM used
to properly configure the DLPC910 DLPC910ZYR
Controller to operate four different digital micromirror
device (DMD) options: the DLP9000X, the
DLP9000XUV, and the DLP6500 family (S600 and
Type A packages). The firmware in this device
enables the DLPC910 DLPC910ZYRController to
provide system data throughput rates up to 61
Gigabits per second (Gbps) for the DLP9000X and
DLP9000XUV, and up to 24 Gbps for the DLP6500
family, with the options for random row addressing
and Load4 capabilities.
Get started with TI DLP® light-control technology
page to learn how to get started with the
DLPC410ZYR. The DLP advanced light control
resources on ti.com accelerate time to market, which
include evaluation modules, reference designs, optical
modules manufacturers, and DLP design network
partners.
Device Information(1)
PART
NUMBER
DLPR910
(1)
DSBGA (48)
Row and Block Signals
8.00 mm × 9.00 mm × 1.20 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
Illumination
Sensor
Control Signals
Status Signals
LVDS Interface
DLPC910
RESET Signals
SCP Interface
DLPR910
BODY SIZE (NOM)
Illumination
Driver
LVDS Interface
JTAG(3:0)
PACKAGE
DLP9000X
DLP9000XUV
DLP6500
PGM(4:0)
CTRL_RSTZ
I2C
VLED0
VLED1
OSC
50 MHz
Power Management
Figure 3-1. Simplified Application
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DLPR910
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DLPS065D – SEPTEMBER 2015 – REVISED DECEMBER 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Supply Voltage Requirements for Power-On
Reset and Power-Down................................................ 6
6.7 Timing Requirements.................................................. 6
7 Detailed Description........................................................7
7.1 Overview..................................................................... 7
7.2 Functional Block Diagram........................................... 7
7.3 Feature Description.....................................................7
7.4 Device Functional Modes............................................8
8 Application and Implementation.................................. 10
8.1 Application Information............................................. 10
8.2 Typical Application.................................................... 10
9 Power Supply Recommendations................................12
10 Layout...........................................................................12
10.1 Layout Guidelines................................................... 12
11 Device and Documentation Support..........................13
11.1 Device Support........................................................13
11.2 Documentation Support.......................................... 14
11.3 Receiving Notification of Documentation Updates.. 14
11.4 Support Resources................................................. 14
11.5 Trademarks............................................................. 14
11.6 Electrostatic Discharge Caution.............................. 14
11.7 Glossary.................................................................. 14
12 Mechanical, Packaging, and Orderable
Information.................................................................... 14
12.1 Package Option Addendum.................................... 15
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (September 2019) to Revision D (December 2021)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
Changes from Revision B (November 2016) to Revision C (September 2019)
Page
• Changed "three" to "four different DMD options"................................................................................................ 1
• Added DLP9000XUV ......................................................................................................................................... 1
• Updated Xilinx reference doc to revision v2.19 from v2.18................................................................................ 6
• Added DLP9000XUV ......................................................................................................................................... 7
• Added DLP9000XUV ....................................................................................................................................... 10
• Added DLP9000XUV to caption of Typical Application Schematic ..................................................................10
• Added DLP9000XUV ....................................................................................................................................... 11
• Updated table to indicate DLP9000XUV is not compatible with DLPR910YVA ...............................................13
• Changed Device Markings image ....................................................................................................................13
• Added DLP9000XUV datasheet ...................................................................................................................... 14
Changes from Revision A (October 2015) to Revision B (November 2016)
Page
• Updated Related Documentation to include additional supported DMD.............................................................1
• Update document to include additional supported DMD options in Section 7.................................................... 7
• Added typical application schematic for newly supported DMD in Section 8.2................................................ 10
• Updated Section 11.1.3.....................................................................................................................................13
• Added MSL Peak Temp to Section 12.1.1 ....................................................................................................... 15
Changes from Revision * (September 2015) to Revision A (October 2015)
Page
• Updated device from Product Preview to Production Data ................................................................................1
2
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5 Pin Configuration and Functions
1
2
3
4
5
6
A
B
C
D
E
F
G
H
Figure 5-1. YVA Package 48-Pin DSBGA Top View
Table 5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
GND
A1
G
Ground
GND
A2
G
Ground
OE/ RESET
A3
I/O
Output Enable/ RESET (Open-Drain I/O). When Low, this input holds the address
counter reset and the DATA and CLKOUT outputs are placed in a high-impedance state.
This is a bidirectional open-drain pin that is held Low while the PROM completes the
internal power-on reset sequence. Polarity is not programmable. Pin must be pulled
High using an external 4.7-kΩ pull-up to VCCO.
DNC
A4
—
Do Not Connect. Leave unconnected.
D6
A5
—
Do Not Connect. Leave unconnected.
D7
A6
—
Do Not Connect. Leave unconnected.
VCCINT
B1
P
Positive 1.8-V supply voltage for internal logic.
VCCO
B2
P
Positive 3.3-V and 1.8-V supply voltage connected to the output voltage drivers and
internal buffers.
CLK
B3
I
Configuration clock input. Each rising edge on the CLK input increments the internal
address counter. Pin must be pulled High and Low using an external 100-Ω pull-up
to VCCO and an external 100-Ω pull-down to Ground. Place resistors close to pin.
CE
B4
I
Chip Enable Input. When CE is High, the device is put into low-power standby mode,
the address counter is reset, and the DATA and CLKOUT outputs are placed in a high
impedance state. Pin must be pulled High using an external 4.7-kΩ pull-up to VCCO.
D5
B5
—
Do Not Connect. Leave unconnected.
GND
B6
G
Ground
BUSY
C1
—
Do Not Connect. Leave unconnected.
CLKOUT
C2
—
Do Not Connect. Leave unconnected.
DNC
C3
—
Do Not Connect. Leave unconnected.
DNC
C4
—
Do Not Connect. Leave unconnected.
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Table 5-1. Pin Functions (continued)
PIN
DESCRIPTION
NO.
D4
C5
—
Do Not Connect. Leave unconnected.
VCCO
C6
P
Positive 3.3-V and 1.8-V supply voltage connected to the output voltage drivers and
internal buffers.
CF
D1
I
Configuration pin. The CF pin must be pulled High using an external 4.7-kΩ pull-up
to VCCO. Selects serial mode configuration.
CEO
D2
—
Do Not Connect. Leave unconnected.
DNC
D3
—
Do Not Connect. Leave unconnected.
DNC
D4
—
Do Not Connect. Leave unconnected.
D3
D5
—
Do Not Connect. Leave unconnected.
VCCO
D6
P
Positive 3.3-V and 1.8-V supply voltage connected to the output voltage drivers and
internal buffers.
VCCINT
E1
P
Positive 1.8-V supply voltage for internal logic.
TMS
E2
I
JTAG Mode Select Input. TMS has an internal 50-kΩ resistive pull-up to VCCJ.
DNC
E3
—
Do Not Connect. Leave unconnected.
DNC
E4
—
Do Not Connect. Leave unconnected.
DNC
E5
—
Do Not Connect. Leave unconnected.
TDO
E6
O
JTAG Serial Data Output. TDO has an internal 50-kΩ resistive pull-up to VCCJ.
GND
F1
G
Ground
DNC
F2
—
Do Not Connect. Leave unconnected.
DNC
F3
—
Do Not Connect. Leave unconnected.
DNC
F4
—
Do Not Connect. Leave unconnected.
GND
F5
G
Ground
GND
F6
G
Ground
TDI
G1
I
JTAG Serial Data Input. TDI has an internal 50k-Ω resistive pull-up to VCCJ.
DNC
G2
—
REV_SEL0
G3
I
REV_SEL1
G4
I
VCCO
G5
P
Positive 3.3-V and 1.8-V supply voltage connected to the output voltage drivers and
internal buffers.
VCCINT
G6
P
Positive 1.8-V supply voltage for internal logic.
GND
H1
G
Ground
VCCJ
H2
P
Positive 3.3-V JTAG I/O supply voltage connected to the TDO output voltage driver and
TCK, TMS and TDI input buffers.
TCK
H3
I
JTAG Clock Input. This pin is the JTAG test clock. It sequences the TAP controller and
all the JTAG test and programming electronics.
EN_EXT_SEL
H4
I
External Selection Input. EN_EXT_SEL has an internal 50-kΩ resistive pull- up to VCCO.
The EN_EXT_SEL pin must be connected to Ground.
D1
H5
—
Do Not Connect. Leave unconnected.
D0
H6
O
DATA output pin to provide data for configuring the DLPC910 in serial mode.
(1)
4
TYPE(1)
NAME
Do Not Connect. Leave unconnected.
Revision Select [1:0] Inputs. When the EN_EXT_SEL is Low, the Revision Select pins
are used to select the design revision to be enabled. The Revision Select [1:0] inputs
have an internal 50-kΩ resistive pull-up to VCCO. The REV_SEL0 pin must be pulled
Low using an external 4.7-kΩ pull-down to Ground. The REV_SEL1 pin must be
pulled Low using an external 4.7-kΩ pull-down to Ground.
P = Power, G = Ground, I = Input, O = Output
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6 Specifications
For complete electrical and mechanical specifications of the DLPR910, see the XCF16P product specification
listed in Related Documentation.
6.1 Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted) (see (1) (2))
MIN
MAX
UNIT
VCCINT
Internal supply voltage
Relative to ground
–0.5
2.7
V
VCCO
I/O supply voltage
Relative to ground
–0.5
4.0
V
VCCO < 2.5 V
–0.5
3.6
V
VCCO ≥ 2.5 V
–0.5
3.6
V
VCCO < 2.5 V
–0.5
3.6
V
VCCO ≥ 2.5 V
–0.5
VIN
Input voltage with respect to ground
VTS
Voltage applied to high-impedance output
TJ
Junction temperature
Tstg
Storage temperature, ambient
(1)
(2)
–65
3.6
V
125
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings can cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 6.3 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods can affect device reliability.
Maximum DC undershoot below GND must be limited to either 0.5 V or 10 mA. During transitions, the device pins can undershoot to
–2 V or overshoot to 7 V, provided this overshoot or undershoot lasts less than 10 ns and with the forcing current being limited to 200
mA.
6.2 ESD Ratings
V(ESD) (1)
(1)
(2)
Electrostatic
discharge
VALUE
UNIT
2000
V
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins
(2)
Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges
in to the device.
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
1.65
1.8
2.0
V
3.0
3.3
3.6
V
VCCINT
Internal voltage supply
VCCO
Supply voltage for output drivers
3.3-V operation
VIL
Low-level input voltage
3.3-V operation
0
0.8
V
VIH
High-level input voltage
3.3-V operation
2.0
3.6
V
VO
Output voltage
0
VCCO
V
tIN
Input signal transition time (measured between 10% VCCO and 90% VCCO)
500
ns
TA
Operating ambient temperature
85
°C
–40
6.4 Thermal Information
Refer to the XCF16P product specifications.
6.5 Electrical Characteristics
Refer to the XCF16P product specifications at www.xilinx.com.
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6.6 Supply Voltage Requirements for Power-On Reset and Power-Down
(see (1))
tVCC
VCCINT rise time from 0 V to nominal voltage
VCCPOR
POR threshold for VCCINT supply
(2)
(3)
tOER
OE/ RESET release delay following POR
VCCPD
Power-down threshold for VCCINT supply
tRST
Time required to trigger a device reset when the VCCINT supply drops below the
maximum VCCPD threshold
(1)
(2)
(3)
MIN
MAX
0.2
50
ms
0.5
–
V
30
ms
0.5
V
0.5
10
UNIT
ms
VCCINT, VCCO, and VCCJ supplies can be applied in any order.
At power-up, the device requires the VCCINT power supply to monotonically rise to the nominal operating voltage within the specified
tVCC rise time. If the power supply cannot meet this requirement, then the device might not perform power-on-reset properly. See
Platform Flash PROM Power-Up Requirements, in the Xilinx XCF16P (v2.19) Product Specification for more information.
If the VCCINT and VCCO supplies do not reach their respective recommended operating conditions before the OE/ RESET pin is
released, then the configuration data from the PROM is not available at the recommended threshold levels. The configuration
sequence must be delayed until both VCCINT and VCCO have reached their recommended operating conditions.
6.7 Timing Requirements
Refer to the XCF16P product specifications at www.xilinx.com.
6
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7 Detailed Description
7.1 Overview
The configuration bit stream stored in the DLPR910 device supports reliable operation of the DLPC910 device
with the DLP9000X and DLP9000XUV DMDs, or the DLP6500 family of DMDs. The DLPC910 digital controller
loads this configuration bit stream from the DLPR910 device.
7.2 Functional Block Diagram
VCCINT
VCCO
VCCJ
TCK
TDI
TMS
CEO
OE/RESET
CLK
TDO
DLPR910
DO
CE
CF
EN_EXT_SEL
REV_SEL0
REV_SEL1
GND
Figure 7-1. Functional Block Diagram
7.3 Feature Description
7.3.1 Data Interface
7.3.1.1 Data Outputs
The DLPR910 device is configured for serial mode operation, where D0 is the data output pin. D0 output pin
provides a serial connection to the DLPC910 controller, where the configuration is read out by the DLPC910
controller.
7.3.1.2 Configuration Clock Input
The configuration CLK is connected to the DLPC910 controller in Primary Serial mode, where the DLPC910
controller provides the clock pulses to read the configuration from the DLPR910 device.
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7.3.1.3 Output Enable and Reset
When the OE/ RESET input is held low, the address counter is reset and the Data (D0) and CLKOUT outputs
are placed in high-impedance state. OE/ RESET must be pulled High using an external 4.7-kΩ pull-up to
VCCO.
7.3.1.4 Chip Enable
The CE input is asserted by the DLPC910 controller to enable the Data (D0) and CLKOUT outputs. When CE
is held high, the DLPR910 device address counter is reset, and the Data and CLKOUT outputs are placed in
high-impedance states.
7.3.1.5 Configuration Pulse
The DLPR910 device is configured in serial mode when it holds configuration pulse pin, CF, high and it enables
the CE and OE pins. New data is available a short time after each rising clock edge.
7.3.1.6 Revision Selection
The device uses the REV_SEL0, REV_SEL1, and EN_EXT_SEL signals to select a revision to act as the
default. Setting all three signals to GND defaults to revision 0 for simple DLPR910 device setup.
7.4 Device Functional Modes
To successfully program the DLPC910 controller upon power-up, the DLPR910 device must be configured and
connected to the DLPC910 controller as shown in Figure 7-2.
8
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P3P3V
Place termination near U4
R65
100
5%
P3P3V
D4
G
D
DLPC_DONE
G
D
DLPC_CCLK
S
Q4
DMN26D0UT-7
R66
100
5%
R67
100
5%
S
P3P3V
R68
4.7k
5%
10
TP39
U4
J18
L18
K11
K10
J10
J11
N18
P18
W11
DLPC_PROGB
DLPC_HSWAPEN
DLPC_DIN
DLPC_DONE
TP41 10
DLPC_CCLK
TP42 10
DLPC_INITB
DLPC_CS_B
DLPC_RDWR_B
DLPC_DOUTBUSY TP4510
DLPC_PROGB
10
R74
1k
1%
TP40
R73
0 DLPR_D0
DLPC_DONE
DLPC_CCLK
DLPC_INITB
TP43 DLPR_CLKOUT
10
TP44 DLPR_BUSY
10
R75
1k
1%
W18
M0_0
Y17
M1_0
V18
M2_0
V12
TMS_0
V11
TDI_0
W10
TDO_0
U11
TCK_0
R80
0
P3P3V
W12
VCCO_0
Y9
VCCO_0
+
C42
47uF
10V
DLPC_TDI
K18
DLPC_VBATT R81
DNC_D4
DNC_D3
DNC_G2
DNC_F4
DNC_F3
DNC_F2
DNC_E4
DNC_E3
DNC_C4
DNC_C3
DNC_A4
D0
CE
CLK
OE/RESET
CLKOUT
BUSY
D7
D6
D5
D4
D3
D2
D1
0
R82
1k
1%
DLPC910ZYR
J19
DLPR_REV_SEL1
DLPR_REV_SEL0
DLPR_ENEXTSEL_Z
DLPR_CEO
10
TP46
G4
REV_SEL1
G3
REV_SEL0
H4
EN_EXT_SEL
D2
CEO
D4
D3
G2
F4
F3
F2
E4
E3
C4
C3
A4
JTAG_TMS 3,8
E2
TMS
E6 DLPR_TDO
TDO
G1 DLPR_TDI
TDI
H3
TCK
JTAG_TMS 3,8
DLPC_TDO 3
JTAG_TCK 3,8
P3P3V
VBATT_0
H6
B4
B3
A3
C2
C1
DLPR910YVA
CF
VCCO_D6
VCCO_G5
VCCO_C6
VCCO_B2
VCCJ
D6
G5
C6
B2
H2
R76
0
R77
0
APP_TDO 3
JTAG_TCK 3,8
P3P3V
C38
0.1uF
50V
G6
VCCINT_G6
E1
VCCINT_E1
B1
VCCINT_B1
C39
0.1uF
50V
C40
0.1uF
50V
C41
0.1uF
50V
P3P3V
A1
A2
B6
F1
F5
F6
H1
DLPC_M0
DLPC_M1
DLPC_M2
D1
A6
A5
B5
C5
D5
E5
H5
R18
RSVD_R18_0
T18
RSVD_T18_0
Master Serial Config Mode
R79
0
R71
4.7k
5%
0
U3A
N14
VP_0
PROGRAM_B_0
P13
VN_0
HSWAPEN_0
D_IN_0
R14
DXP_0
DONE_0
R13
DXN_0
CCLK_0
M14
AVDD_0
INIT_B_0
M13
AVSS_0
CS_B_0
RDWR_B_0
P14
VREFP_0
D_OUT_BUSY_0
N13
VREFN_0
R78
0
R70
330
5%
GND_A1
GND_A2
GND_B6
GND_F1
GND_F5
GND_F6
GND_H1
R72
7 DLPCPROGB_BY_USB
R69
4.7k
5%
1
2
C43
0.1uF
50V
R83
10k
0.5%
P1P8V
C44
0.1uF
50V
C45
0.1uF
50V
C46
1.0uF
50V
Figure 7-2. DLPC910 and DLPR910 Connection Schematic
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The DLPR910 device configuration PROM ships pre-programmed with configuration code for the DLPC910
controller. Upon power-up, the DLPC910 controller and the DLPR910 device connect to enable configuration
information to be sent from the DLPR910 device to the DLPC910 controller, such that the DLPC910 controller
can configure itself for proper operation within the application. Without the DLPR910 device properly connected
to the DLPC910 controller in the application system, the DLPC910 controller does not boot and the system
remains inoperable.
8.2 Typical Application
A typical use case for a high speed lithography application is shown in Figure 8-1 and in Figure 8-2. Both
applications offer continuous run of printing by changing the digitally created patterns without stopping the
imaging head. The DLPR910 prom configures the DLPC910 digital controller to reliably operate with the
DLP9000X and DLP9000XUV DMDs, or the DLP6500 DMDs. These chipset combinations provide an ideal
back-end imager that takes in digital images at 2560 × 1600 and 1920 x 1080 in resolution to achieve speeds
greater than 61 Gigabits per second (Gbps) and 24 Gbps respectively. For complete details of this typical
application refer to the DLPC910 data sheet listed in Section 11.2.1.
Illumination
Driver
Illumination
Sensor
LVDS Interface
DCLKIN(A,B,C,D),DVALID(A,B,C,D),DIN(A,B,C,D)[15:])
Row and Block Signals
USER
Interface
ROWMD(1:0),ROWAD(10:0),BLKMD(1:0),BLKAD(3:0),RST2BLKZ
Control Signals
DOUT(A,B,C,D)[15:0]
COMP_DATA,NS_FLIP,WDT_ENBLZ,PWR_FLOAT
Connectivity
USB
Ethernet
DCLKOUT (A,B,C,D)
APPS
SCTRL(A,B,C,D)
Status Signals
FPGA
RESET_ADDR(3:0)
RST_ACTIVE,INIT_ACTIVE,ECP2_FINISHED
DLPC910
RESET_MODE(1:0)
RESET_SEL(1:0)
JTAG(3:0)
DLP9000XFLS
RESET_STRB
RESET_OEZ
Volatile
And
Non-volatile
Storage
DLPR910
PGM(4:0)
RESET_IRQZ
SCP BUS(3:0)
CTRL_RSTZ
RESETZ
I2C
VLED0
OSC
50 MHz
VLED1
Power Management
Figure 8-1. Typical High Speed DLP9000X (or DLP9000XUV) Application Schematic
10
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Illumination
Driver
Illumination
Sensor
LVDS Interface
DCLK(A,B), DVALID(A,B), DIN(A,B)[15:0]
USER
Interface
Connectivity
USB
Ethernet
Row and Block Signals
ROWMD(1:0), ROWAD(10:0), BLKMD(1:0), BLKAD(3:0), RST2BLKZ
APPS
FPGA
Control Signals
COMP_DATA, NS_FLIP, WDT_ENBLZ, PWR_FLOAT
Status Signals
RST_ACTIVE, INIT_ACTIVE, ECP2_FINISHED
DLPC910
JTAG(3:0)
DLPR910
Volatile
And
Non-Volatile
Storage
PGM(4:0)
DOUT(A,B)[15:0]
DCLKOUT(A,B)
SCTRL(A,B)
RESET_ADDR(3:0)
RESET_MODE(1:0)
RESET_SEL(1:0)
RESET_STRB
RESET_OEZ
RESET_IRQZ
SCP BUS(3:0)
RESET_RSTZ
DLP6500
CTRL_RSTZ
I2C
OSC
50 MHz
VLED0
VLED1
Power Management
Figure 8-2. Typical High Speed DLP6500 Application Schematic
8.2.1 Design Requirements
The DLPR910 is part of a multi-chipset solution, and it is required to be coupled with the DLPC910 controller
for reliable operation of the DLP9000X and DLP9000XUV DMDs, or the DLP6500 family of DMDs. For more
information, refer to the DLPC910 datasheet listed in Section 11.2.1.
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9 Power Supply Recommendations
The DLPR910 uses two power supply rails as shown in Table 9-1.
Table 9-1. DLPR910 Power Supply Rails
SUPPLY
POWER PINS
COMMENTS
1.8 V
VCCINT1, VCCINT2, and VCCINT3
All VCCINT pins must be connected with a 0.1-µF and a
0.047-μF decoupling capacitor to GND.
3.3 V
VCCO1,VCCO2,VCCO3, VCCO4, and VCCJ
All VCCO and VCCJ pins must be connected with a 0.1µF and a 0.047-μF decoupling capacitor to GND.
10 Layout
10.1 Layout Guidelines
The DLPR910 is part of a multi-chipset solution. It is required to be used with the DLPC910 Controller to
provide reliable control of any attached DMDs. These guidelines are targeted at designing a PCB board with the
DLPR910.
12
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Device Compatibility
TI PART NUMBER(1)
DLP9000XFLS
DLP9000XBFLS
DLP9000XUVFLS
DLP6500FYE
DLP6500FLQ
DLP6500BFYE
DLP6500BFLQ
DLPR910YVA
Compatible
Not Compatible
Not Compatible
Compatible
Not Compatible
DLPR910AYVA
Compatible
Compatible
Compatible
Compatible
Compatible
(1)
Refer to each individual DMD datasheet under Device and Documentation Support to determine location and revision of the DMD.
11.1.2 Device Nomenclature
Table 11-1. Part Number Description
TI PART NUMBER
DLPR910AYVA
DESCRIPTION
DLPR910A Configuration PROM
REFERENCE NUMBER
2514595-0002
11.1.3 Device Markings
Pin 1
DLPR910A
XXXXXXXXXXX
Figure 11-1. DLPR910 Device Markings
Where XXXXXXX-XXXX is the reference number located in Table 11-1.
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11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
• DLPC910 datasheet (DLPS064)
• DLP9000(X) datasheet (DLPS036)
• DLP9000XUV datasheet (DLPS158)
• DLP6500 Type A datasheet (DLPS040)
• DLP6500 S600 datasheet (DLPS053)
• XCF16P data sheet (www.xilinx.com)
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
Xilinx® is a registered trademark of Xilinx, Inc.
All trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this datasheet, refer to the left-hand navigation.
14
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12.1 Package Option Addendum
12.1.1 Packaging Information
(1)
(2)
(3)
(4)
(5)
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins
Package
Qty
Eco Plan (2)
Lead/Ball Finish
MSL Peak Temp (3)
Op Temp (°C)
Device Marking(4) (5)
DLPR910AYVA
ACTIVE
DSBGA
YVA
48
1
Call TI
Call TI
Level-3-260C-168 HRS
–40 to 85
Call TI
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
space
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest
availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the
requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified
lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used
between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1%
by weight in homogeneous material)
space
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
space
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device
space
Multiple Device markings will be inside parentheses. Only on Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided
by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider
certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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