DLPR410
DLPS027G – AUGUST 2012 – REVISED AUGUST 2021
DLPR410 Configuration PROM
1 Features
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•
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3 Description
Pre-programmed Xilinx® PROM configures the
DLPC410ZYR DMD digital controller
I/O pins compatible with 1.8 V to 3.3 V
1.8 V core supply voltage
–40°C to 85°C operating temperature range
The DLPR410 device is a programmed PROM used
to properly configure the DLPC410ZYR Controller
to operate five different digital micromirror device
(DMD) options: DLP650LNIRFYL, DLP7000FLP,
DLP7000UVFLP, DLP9500FLN and, DLP9500UVFLN
DMDs. The firmware in this device enables the
DLPC410ZYR Controller to provide system data
throughput rates up to 48 Gigabits per second
(Gbps) with the options for random row addressing
and Load4 capabilities. Often this family of chips is
designed into high speed UV and NIR optical systems
such as direct imaging lithography, 3D printing and
laser marking equipment that need fast throughput
and pixel accurate control.
2 Applications
Lithography
• Direct imaging
• Flat panel display
• Printed circuit board manufacturing
Industrial
• 3D printing
• 3D scanners for machine vision
• Quality control
Get started with TI DLP® light-control technology
page to learn how to get started with the
DLPC410ZYR. The DLP advanced light control
resources on ti.com accelerate time to market, which
include evaluation modules, reference designs, optical
modules manufacturers, and DLP design network
partners.
Displays
• 3D imaging
• Intelligent and adaptive lighting
• Augmented reality and information overlay
Device Information(1)
PART
NUMBER
DLPR410
(1)
PWMs/Triggers
PACKAGE
DSBGA (48)
BODY SIZE (NOM)
8.00 mm × 9.00 mm × 1.20 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
LED/LASER/Lamp Driver
Op cal Power Sense
LEDs / LASERs /
Lamp
Opcal Sensor
LVDS Data Bus(A,B)
LVDS Data Bus(C,D)
LVDS Data Bus
Row, Block Signals
Control Signals
DLPC410 Info Signals
JTAG
DLPR410
DLPC410ZYR
D0
Clk
DONE
OE
DLPA200 Control
DLPA200
MBRST
DLPA200 Control
DLPA200
MBRST
SCP Bus
DMDs
DLP650LNIR
DLP7000
DLP7000UV
DLP9500
DLP9500UV
OSC
Power Management
TI Components
Figure 3-1. Simplified Application
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DLPR410
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DLPS027G – AUGUST 2012 – REVISED AUGUST 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings........................................ 6
6.2 ESD Ratings............................................................... 6
6.3 Recommended Operating Conditions.........................6
6.4 Thermal Information....................................................6
6.5 Electrical Characteristics.............................................6
6.6 Supply Voltage Requirements for Power-On
Reset and Power-Down................................................ 7
6.7 Timing Requirements.................................................. 7
7 Detailed Description........................................................8
7.1 Overview..................................................................... 8
7.2 Functional Block Diagram........................................... 8
7.3 Feature Description.....................................................8
7.4 Device Functional Modes............................................9
8 Application and Implementation.................................. 11
8.1 Application Information..............................................11
8.2 Typical Application.................................................... 11
9 Power Supply Recommendations................................13
10 Layout...........................................................................13
10.1 Layout Guidelines................................................... 13
11 Device and Documentation Support..........................15
11.1 Device Support........................................................15
11.2 Documentation Support.......................................... 17
11.3 Receiving Notification of Documentation Updates.. 17
11.4 Support Resources................................................. 17
11.5 Trademarks............................................................. 17
11.6 Electrostatic Discharge Caution.............................. 17
11.7 Glossary.................................................................. 17
12 Mechanical, Packaging, and Orderable
Information.................................................................... 17
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (January 2020) to Revision G (August 2021)
Page
• Updated all references to DLPC410 Controller in data sheet to DLPC410ZYR Controller................................ 1
• Updated Applications List................................................................................................................................... 1
• Updated Simplified Application Diagram in Description section......................................................................... 1
• Moved Xilinx XCF specifications link to top of Specifications section.................................................................1
• Removed numbers appended to all DNC signals in Pin Functions table........................................................... 4
• Added entry for VCCJ to Absolute Maximum Ratings..........................................................................................6
• Removed footnote reference to JEDEC Standard JESD22-A114A in ESD Ratings.......................................... 6
• Added entry for VCCJ to Recommended Operating Conditions.......................................................................... 6
• Updated DLPC410ZYR and DLPR410 Connection Schematic........................................................................10
• Updated DLPR410 and DLPC410ZYR with DMD Example Block Diagram .................................................... 11
• Added Application Curves section.................................................................................................................... 12
• Added 0.047-μF decoupling capacitor to GND for all Power Pins in Power Supply Recommendations.......... 13
• Added Layout Example section........................................................................................................................ 14
• Added DLPR410BYVA to Device Compatibility table....................................................................................... 15
• Added DLPR410BYVA to Part Number Description table................................................................................ 15
• Added DLPR410B Device Markings.................................................................................................................15
Changes from Revision E (December 2018) to Revision F (January 2020)
Page
• Corrected Max Tstg per Xilinx data sheet .......................................................................................................... 6
• Pulled in specific layout information from referenced document and removed reference................................ 13
• Corrected DDC_Version(3:0) bus width to DDC_Version(2:0). ....................................................................... 15
Changes from Revision D (April 2015) to Revision E (December 2018)
Page
• Updated Applications and Description to include new DLP650LNIR, removed data transfer rate .................... 1
• Corrected Min Tstg per Xilinx data sheet ........................................................................................................... 6
• Corrected Min VCCO per Xilinx data sheet ....................................................................................................... 6
• Added support information for new DLP650LNIR DMD (multiple places).......................................................... 8
• Updated Section 7.2 .......................................................................................................................................... 8
2
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•
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DLPS027G – AUGUST 2012 – REVISED AUGUST 2021
Corrected improper "DLPC910" reference to "DLPC410" ................................................................................11
Updated Figure 8-1 .......................................................................................................................................... 11
Added Section 11.1.1 table...............................................................................................................................15
Updated Section 11.1.2 ....................................................................................................................................15
Updated Section 11.1.3 section........................................................................................................................ 15
Added DLP650LNIR to Table 11-2 section....................................................................................................... 17
Deleted DLP Discovery 4100 Chipset reference in Table 11-2 ........................................................................17
Changes from Revision C (March 2013) to Revision D (October 2015)
Page
• Updated Features, Applications, and Description ..............................................................................................1
• Deleted DLPR4101 (enhanced functionality PROM part number) throughout document ................................. 1
• Added ESD Rating table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section................... 1
• Deleted 1.8 V and 3.3 V operation values from VCCO, VIL, and VIH - this implementation is 2.5 V ....................6
• Changed Device Marking Image ..................................................................................................................... 15
• Changed Device Marking Image ..................................................................................................................... 15
• Deleted DLP® Discovery™ 4100 Chipset Datasheet from Related Documentation ....................................... 17
• Added Link to XCF16P data sheet at xilinx.com ..............................................................................................17
Changes from Revision B (March 2013) to Revision C (April 2013)
Page
• Added Top View of Device..................................................................................................................................1
• Added DLPR4101 "Load 4" enhanced functionality to Features........................................................................ 1
• Added DLPR410 and DLPR4101 (enhanced functionality PROM part number) to DLPR410 throughout
document ........................................................................................................................................................... 1
• Added a link to the data sheet............................................................................................................................ 1
• Added the Version column to the Ordering Information table............................................................................. 4
• Updated DLPC and DLP7000 / DLP7000UV Embedded Example Block Diagram.......................................... 11
• Added DLP7000UV and DLP9500UV well suited for direct imaging lithography, 3D printing, and UV
applications ......................................................................................................................................................12
• Added DLPR4101YVA as equivalent to TI part number 2510442-0006 ..........................................................15
• Added Reference to DLPC410 data sheet....................................................................................................... 15
• Added DLPR410 to Figure 11-2 .......................................................................................................................15
• Added Top View of Device to device marking ..................................................................................................15
• Added DLP7000UV Related Documentation....................................................................................................17
• Added DLP9500UV Related Documentation....................................................................................................17
Changes from Revision A (September 2012) to Revision B (March 2013)
Page
• Changed the top-side marking in the Ordering Information table....................................................................... 4
Changes from Revision * (August 2012) to Revision A (September 2012)
Page
• Changed the device From: Product Preview To: Production.............................................................................. 1
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5 Pin Configuration and Functions
1
2
3
4
5
6
A
B
C
D
E
F
G
H
Figure 5-1. YVA Package 48-Pin DSBGA Top View
Table 5-1. Pin Functions
PIN
4
TYPE(1)
DESCRIPTION
NAME
NO.
GND
A1
G
Ground
GND
A2
G
Ground
OE/ RESET
A3
I/O
Output Enable/ RESET (Open-Drain I/O). When Low, this input holds the address
counter reset and the DATA and CLKOUT outputs are placed in a high-impedance state.
This is a bidirectional open-drain pin that is held Low while the PROM completes the
internal power-on reset sequence. Polarity is not programmable. Pin must be pulled
High using an external 4.7-kΩ pull-up to VCCO.
DNC
A4
—
Do Not Connect. Leave unconnected.
D6
A5
—
Do Not Connect. Leave unconnected.
D7
A6
—
Do Not Connect. Leave unconnected.
VCCINT1
B1
P
Positive 1.8-V supply voltage for internal logic.
VCCO1
B2
P
Positive supply voltage connected to the output voltage drivers and internal buffers.
CLK
B3
I
Do Not Connect. Leave unconnected.
CE
B4
I
Chip Enable Input. When CE is High, the device is put into low-power standby mode,
the address counter is reset, and the DATA and CLKOUT outputs are placed in a high
impedance state. Pin must be pulled High using an external 4.7-kΩ pull-up to VCCO.
D5
B5
—
Do Not Connect. Leave unconnected.
GND
B6
G
Ground
BUSY
C1
—
Do Not Connect. Leave unconnected.
CLKOUT
C2
—
Configuration clock output. Each rising edge on the CLK input increments the internal
address counter. Pin must be pulled High and Low using an external 100-Ω pull-up
to VCCO and an external 100-Ω pull-down to Ground. Place resistors close to pin.
DNC
C3
—
Do Not Connect. Leave unconnected.
DNC
C4
—
Do Not Connect. Leave unconnected.
D4
C5
—
Do Not Connect. Leave unconnected.
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Table 5-1. Pin Functions (continued)
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
VCCO2
C6
P
Positive supply voltage connected to the output voltage drivers and internal buffers.
CF
D1
I
Configuration pin. The CF pin must be pulled High using an external 4.7-kΩ pull-up
to VCCO. Selects serial mode configuration.
CEO
D2
—
Do Not Connect. Leave unconnected.
DNC
D3
—
Do Not Connect. Leave unconnected.
DNC
D4
—
Do Not Connect. Leave unconnected.
D3
D5
—
Do Not Connect. Leave unconnected.
VCCO4
D6
P
Positive supply voltage connected to the output voltage drivers and internal buffers.
VCCINT2
E1
P
Positive 1.8-V supply voltage for internal logic.
TMS
E2
I
JTAG Mode Select Input. TMS has an internal 50-kΩ resistive pull-up to VCCJ.
DNC
E3
—
Do Not Connect. Leave unconnected.
DNC
E4
—
Do Not Connect. Leave unconnected.
DNC
E5
—
Do Not Connect. Leave unconnected.
TDO
E6
O
JTAG Serial Data Output. TDO has an internal 50-kΩ resistive pull-up to VCCJ.
GND
F1
G
Ground
DNC
F2
—
Do Not Connect. Leave unconnected.
DNC
F3
—
Do Not Connect. Leave unconnected.
DNC
F4
—
Do Not Connect. Leave unconnected.
GND
F5
G
Ground
GND
F6
G
Ground
TDI
G1
I
JTAG Serial Data Input. TDI has an internal 50k-Ω resistive pull-up to VCCJ.
DNC
G2
—
REV_SEL0
G3
I
REV_SEL1
G4
I
VCCO3
G5
P
Positive supply voltage connected to the output voltage drivers and internal buffers.
VCCINT3
G6
P
Positive 1.8-V supply voltage for internal logic.
GND
H1
G
Ground
VCCJ
H2
P
Positive 2.5-V JTAG I/O supply voltage connected to the TDO output voltage driver and
TCK, TMS and TDI input buffers.
TCK
H3
I
JTAG Clock Input. This pin is the JTAG test clock. It sequences the TAP controller and
all the JTAG test and programming electronics.
EN_EXT_SEL
H4
I
External Selection Input. EN_EXT_SEL has an internal 50-kΩ resistive pull- up to VCCO.
The EN_EXT_SEL pin must be connected to Ground.
D1
H5
—
Do Not Connect. Leave unconnected.
D0
H6
O
DATA output pin to provide data for configuring the DLPC410ZYR in serial mode.
(1)
Do Not Connect. Leave unconnected.
Revision Select [1:0] Inputs. When the EN_EXT_SEL is Low, the Revision Select pins
are used to select the design revision to be enabled. The Revision Select [1:0] inputs
have an internal 50-kΩ resistive pull-up to VCCO. The REV_SEL0 pin must be pulled
Low using an external 4.7-kΩ pull-down to Ground. The REV_SEL1 pin must be
pulled Low using an external 4.7-kΩ pull-down to Ground.
P = Power, G = Ground, I = Input, O = Output
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6 Specifications
For complete electrical and mechanical specifications of the DLPR410, see the XCF16P product specification
listed in Related Documentation.
6.1 Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted) (see (1) (2))
MIN
MAX
UNIT
VCCINT
Internal supply voltage
Relative to ground
–0.5
2.7
V
VCCO
I/O supply voltage
Relative to ground
–0.5
4.0
V
VCCJ
JTAG I/O supply voltage
Relative to ground
–0.5
4.0
V
VIN
Input voltage with respect to ground
VCCO < 2.5 V
–0.5
3.6
V
VCCO ≥ 2.5 V
–0.5
3.6
V
VTS
Voltage applied to high-impedance output
VCCO < 2.5 V
–0.5
3.6
V
VCCO ≥ 2.5 V
–0.5
3.6
V
TJ
Junction temperature
125
°C
Tstg
Storage temperature, ambient
150
°C
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings can cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 6.3 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods can affect device reliability.
Maximum DC undershoot below GND must be limited to either 0.5 V or 10 mA. During transitions, the device pins can undershoot to
–2 V or overshoot to 7 V, provided this overshoot or undershoot lasts less than 10 ns and with the forcing current being limited to 200
mA.
6.2 ESD Ratings
V(ESD) (1)
(1)
(2)
Electrostatic
discharge
VALUE
UNIT
2000
V
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins
(2)
Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges
in to the device.
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
1.65
1.8
2.0
V
2.5-V operation
2.3
2.5
2.7
V
2.5-V operation
2.3
2.5
2.7
V
0
0.7
V
1.7
3.6
V
VCCO
V
VCCINT
Internal voltage supply
VCCO
Supply voltage for output drivers
VCCJ
JTAG I/O Supply voltage
VIL
Low-level input voltage
2.5-V operation
VIH
High-level input voltage
2.5-V operation
VO
Output voltage
0
tIN
Input signal transition time (measured between 10% VCCO and 90% VCCO)
TA
Operating ambient temperature
–40
UNIT
500
ns
85
°C
6.4 Thermal Information
Refer to the XCF16P product specifications.
6.5 Electrical Characteristics
Refer to the XCF16P product specifications at www.xilinx.com.
6
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6.6 Supply Voltage Requirements for Power-On Reset and Power-Down
(see (1))
tVCC
VCCINT rise time from 0 V to nominal voltage
VCCPOR
POR threshold for VCCINT supply
(2)
(3)
tOER
OE/ RESET release delay following POR
VCCPD
Power-down threshold for VCCINT supply
tRST
Time required to trigger a device reset when the VCCINT supply drops below the
maximum VCCPD threshold
(1)
(2)
(3)
MIN
MAX
0.2
50
ms
0.5
–
V
30
ms
0.5
V
0.5
10
UNIT
ms
VCCINT, VCCO, and VCCJ supplies can be applied in any order.
At power-up, the device requires the VCCINT power supply to monotonically rise to the nominal operating voltage within the specified
tVCC rise time. If the power supply cannot meet this requirement, then the device might not perform power-on-reset properly. See
Platform Flash PROM Power-Up Requirements, in the Xilinx XCF16P (v2.19) Product Specification for more information.
If the VCCINT and VCCO supplies do not reach their respective recommended operating conditions before the OE/ RESET pin is
released, then the configuration data from the PROM is not available at the recommended threshold levels. The configuration
sequence must be delayed until both VCCINT and VCCO have reached their recommended operating conditions.
6.7 Timing Requirements
Refer to the XCF16P product specifications at www.xilinx.com.
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7 Detailed Description
7.1 Overview
The configuration bit stream stored in the DLPR410 device supports reliable operation of the DLPC410ZYR
device with the DLP650LNIRFYL, DLP7000FLP, DLP7000UVFLP, DLP9500FLN and, DLP9500UVFLN DMDs.
DMDs. The DLPC410ZYR digital controller loads this configuration bit stream from the DLPR410 device.
VCCJ
VCCO
VCCINT
7.2 Functional Block Diagram
TCK
TDI
TMS
OE/RESET
CEO
CLKOUT
TDO
DLPR410
CE
D0
CF
EN_EXT_SEL
REV_SEL0
GND
REV_SEL1
Figure 7-1. Functional Block Diagram
7.3 Feature Description
7.3.1 Data Interface
7.3.1.1 Data Outputs
The DLPR410 device is configured for serial mode operation, where D0 is the data output pin. D0 output
pin provides a serial connection to the DLPC410ZYR controller, where the configuration is read out by the
DLPC410ZYR controller.
7.3.1.2 Configuration Clock Input
The configuration CLK is connected to the DLPC410ZYR controller in Primary Serial mode, where the
DLPC410ZYR controller provides the clock pulses to read the configuration from the DLPR410 device.
7.3.1.3 Output Enable and Reset
When the OE/ RESET input is held low, the address counter is reset and the Data (D0) and CLKOUT outputs
are placed in high-impedance state. OE/ RESET must be pulled High using an external 4.7-kΩ pull-up to
VCCO.
7.3.1.4 Chip Enable
The CE input is asserted by the DLPC410ZYR controller to enable the Data (D0) and CLKOUT outputs. When
CE is held high, the DLPR410 device address counter is reset, and the Data and CLKOUT outputs are placed in
high-impedance states.
8
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7.3.1.5 Configuration Pulse
The DLPR410 device is configured in serial mode when it holds configuration pulse pin, CF, high and it enables
the CE and OE pins. New data is available a short time after each rising clock edge.
7.3.1.6 Revision Selection
The device uses the REV_SEL0, REV_SEL1, and EN_EXT_SEL signals to select a revision to act as the
default. Setting all three signals to GND defaults to revision 0 for simple DLPR410 device setup.
7.4 Device Functional Modes
To successfully program the DLPC410ZYR controller upon power-up, the DLPR410 device must be configured
and connected to the DLPC410ZYR controller as shown in Figure 7-2.
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VCC_1P8V
VCC_2P5V
RSVD7
RSVD8
U11
V12
V11
W10
1K
1K
DLPC410ZYR
A6
A5
B5
C5
D5
E5
H5
H6
D7
D6
D5
D4
D3
D2
D1
D0
G3
G4
H4
D2
D1
REV_SEL0
REV_SEL1
EN_EXT_SEL
CEO
CF
DLPR410
DNC11
DNC10
DNC9
DNC8
DNC7
DNC6
DNC5
DNC4
DNC3
DNC2
DNC1
D4
D3
G2
F4
F3
F2
E4
E3
C4
C3
A4
TMS
TDO
TDI
TCK
E2
E6
G1
H3
0.047µF
16V
0.1µF
16V
0.047µF
16V
0.1µF
16V
0.1µF
16V
100
4.7K
4.7K
4.7K
4.7K
4.7K
TCK_JTAG
TMS_JTAG
TDO_XCF16DDC
TDO_DDC
G6
E1
B1
R18
T18
TCK_0
TMS_0
TDI_0
TDO_0
PROGB_DDC
VCCINT3
VCCINT2
VCCINT1
VREFP_0
VREFN_0
N18
J18
P18
W11
L18
D6
G5
C6
B2
H2
P14
N13
CS_B_0
PROGRAM _B_0
RWDR_B_0
D_OUT_BUSY_0
HSWAPEN_0
VCC04
VCC03
VCC02
VCC01
VCCJ
AVDD_0
AVSS_0
PROM_D0_DDC
PROM_CCK_DDC
DONE_DDC
INTB_DDC
CLK
CLKOUT
OE/RESET
CE
BUSY
GND1
GND2
GND3
GND4
GND5
GND6
GND7
M14
M13
K11
J10
K10
J11
B3
C2
A3
B4
C1
TMS_JTAG
TDO_XCF16DDC
TDI_DDC
TCK_JTAG
A1
A2
B6
F1
F5
F6
H1
DXP_0
DXN_0
D_IN_0
CCLK_0
DONE_0
INT_B_0
PROG
JTAG
MODE
NP
0
4.7K
R14
R13
DDC_M0
4.7K
VP_0
VN_0
W18
V18
Y17
JUMPER
N14
P13
M0_0
M2_0
M1_0
100
VCC_0_1
VCC_0_2
0-1 REV SEL = 00
1-2 REV SEL = 01
Y9
W12
4.7K
4.7K
Master Serial
Config Mode
Figure 7-2. DLPC410ZYR and DLPR410 Connection Schematic
10
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The DLPR410 device configuration PROM ships pre-programmed with configuration code for the DLPC410ZYR
controller. Upon power-up, the DLPC410ZYR controller and the DLPR410 device connect to enable
configuration information to be sent from the DLPR410 device to the DLPC410ZYR controller, such that the
DLPC410ZYR controller can configure itself for proper operation within the application. Without the DLPR410
device properly connected to the DLPC410ZYR controller in the application system, the DLPC410ZYR controller
does not boot and the system remains inoperable.
8.2 Typical Application
A typical embedded system application using the DLPR410 device to program the DLPC410 controller (to drive
one of 5 different DMDs) is shown in Figure 8-1. For complete details of this typical application refer to the
DLPC410 controller data sheet listed in Table 11-2.
PWMs/Triggers
LEDs / LASERs /
Lamp
LED/LASER/Lamp Driver
Op cal Power Sense
Opcal Sensor
LVDS Data Bus(A,B)
LVDS Data Bus(C,D)
LVDS Data Bus
Row, Block Signals
Control Signals
DLPC410 Info Signals
JTAG
DLPR410
DLPC410ZYR
D0
Clk
DONE
OE
DLPA200 Control
DLPA200
MBRST
DLPA200 Control
DLPA200
MBRST
SCP Bus
DMDs
DLP650LNIR
DLP7000
DLP7000UV
DLP9500
DLP9500UV
OSC
Power Management
TI Components
Figure 8-1. DLPR410 and DLPC410ZYR with DMD Example Block Diagram
8.2.1 Design Requirements
The DLPR410 is part of a multi-chipset solution, and it is required to be coupled with the DLPC410ZYR
controller for reliable operation of the DLP650LNIRFYL, DLP7000FLP, DLP7000UVFLP, DLP9500FLN and,
DLP9500UVFLN DMDs. DMDs. For more information, refer to the DLPC410ZYR datasheet listed in Section
11.2.1.
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8.2.2 Detailed Design Procedure
The DMDs are designed to be operated by the DLPC410ZYR Digital Controller:
• The DLP7000FLP and DLP9500FLN DMDs are well suited for visible light applications requiring fast, spatially
programmable light patterns using the micromirror array.
• The DLP7000UVFLP and DLP9500UVFLN DMDs are well suited for direct imaging lithography, 3D printing
applications, and other applications requiring ultraviolet light (UVA).
• The DLP650LNIRFYL DMD enables high-power NIR laser illumination for dynamic digital printing, sintering
and marking solutions.
Connections between the DLPC410ZYR Digital Controller, the DLPR410 Configuration PROM, and the
DLPA200 DMD micromirror driver(s) must follow the layout guidelines for reliability.
8.2.3 Application Curves
Figure 8-2. DLP7000 and DLP9500 Transmittance
(Visible Window)
Figure 8-3. DLP7000UV and DLP9500UV
Transmittance (UV Window)
100
AOI = 0°
Transmittance (%)
80
60
40
20
0
600
800
1000
1200
1400
Wavelength (nm)
1600
1800
2000
Figure 8-4. DLP650LNIR Transmittance (NIR Window)
12
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9 Power Supply Recommendations
The DLPR410 uses two power supply rails as shown in Table 9-1.
Table 9-1. DLPR410 Power Supply Rails
SUPPLY
POWER PINS
COMMENTS
1.8 V
VCCINT1, VCCINT2, and VCCINT3
All VCCINT pins must be connected with a 0.1-µF and a
0.047-μF decoupling capacitor to GND.
2.5 V
VCCO1,VCCO2,VCCO3, VCCO4, and VCCJ
All VCCO and VCCJ pins must be connected with a 0.1µF and a 0.047-μF decoupling capacitor to GND.
10 Layout
10.1 Layout Guidelines
The DLPR410 is part of a multi-chipset solution. It is required to be used with the DLPC410ZYR Controller to
provide reliable control of any attached DMDs. These guidelines are targeted at designing a PCB board with the
DLPR410.
10.1.1 Component Placement
The DLPR410 must be placed adjacent to the DLPC410ZYR Controller with a maximum electrical distance of 4
inches (10 cm).
10.1.2 Impedance Requirements
Signals between the DLPR410 and the DLPC410ZYR Controller must be routed to have a matched impedance
of 50 Ω ±10%.
10.1.3 PCB Signal Routing
When designing a PCB board which includes the DLPR410 and the DLPC410ZYR Controller, the following are
recommended:
Signal trace corners must be no sharper than 45°. Adjacent signal layers must have the predominate traces
routed orthogonal to each other.
TI does not recommend signal routing on power or ground planes.
TI does not recommend ground plane slots.
High speed signal traces must not cross over slots in adjacent power and/or ground planes.
10.1.4 Fiducials
Fiducials for automatic component insertion must be 0.05-inch copper with a 0.1-inch cutout (antipad). Fiducials
for optical auto insertion are placed on three corners of both sides of the PCB.
10.1.5 PCB Decoupling Guidelines
Decoupling capacitors must be utilized to provide instantaneous current sources to components and to help
mitigate ground bounce.
10.1.5.1 Bulk Decoupling
Bulk decoupling capacitors for the board must be distributed around the PCB and be sized to handle the current
demands for the board.
10.1.5.1.1 DLPR410 Decoupling Capacitors
Decoupling capacitors (0.1 µF recommended) are placed to minimize the distance from the decoupling capacitor
to the supply and ground pins of the component. It is recommended that the placement of and routing for the
decoupling capacitors meet the following guidelines:
•
The supply voltage pin of the capacitor must be located close to the device supply voltage pin(s). The
decoupling capacitor must have vias to ground and voltage planes. The device can be connected directly to
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•
•
•
•
the decoupling capacitor (no via) if the trace length is less than 0.1 inch. Otherwise, the component must be
tied to the voltage or ground plane through separate vias.
The trace lengths of the voltage and ground connections for decoupling capacitors and components must be
less than 0.1 inch to minimize inductance.
The trace width of the power and ground connection to decoupling capacitors and components must be as
wide as possible to minimize inductance.
Connecting decoupling capacitors to ground and power planes through multiple vias can reduce inductance
and improve noise performance. Via sharing between components (discreet or integrated) is discouraged.
Decoupling performance can be improved by utilizing low ESR and low ESL capacitors.
10.1.6 Layout Example
Please refer to the DLPLCRC410EVM Design files for an example of how to layout the DLPR410 Configuration
PROM.
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Device Compatibility
TI PART NUMBER
DDC_Version(2:0)(2)
Compatible DMDs (1)
DLPR410YVA
5
DLP7000FLP, DLP7000UVFLP, DLP9500FLN and, DLP9500UVFLN DMDs.
DLPR410AYVA
7
DLP650LNIRFYL, DLP7000FLP, DLP7000UVFLP, DLP9500FLN and, DLP9500UVFLN
DMDs.
DLPR410BYVA
0
DLP650LNIRFYL, DLP7000FLP, DLP7000UVFLP, DLP9500FLN and, DLP9500UVFLN
DMDs.
(1)
(2)
Refer to each individual DMD datasheet under Device and Documentation Support for more DMD information.
Refers to the DDC_Version(2:0) output pins of the DLPC410 Controller once configured by this Configuration PROM. See the
DLPC410 datasheet (DLPS024) for more information.
11.1.2 Device Nomenclature
The device nomenclature is as shown in Figure 11-1. The part number description for previously and currently
available part numbers is shown in Table 11-1.
DLPR410 A YVA
Package Type
Revision
Device Descriptor
Figure 11-1. Device Nomenclature
Table 11-1. Part Number Description
TI PART NUMBER
DESCRIPTION
REFERENCE NUMBER
DLPR410YVA
DLPR410 Configuration PROM
2510442-0005
DLPR410AYVA
DLPR410A Configuration PROM (Added compatibility with DLP650LNIR)
DLPR410AYVA
DLPR410BYVA
DLPR410B Configuration PROM (Compatibile with DLP650LNIR)
DLPR410BYVA
11.1.3 Device Markings
Figure 11-2 shows the previous device marking for the DLPR410 device. For the DLPR410A and DLPR410B,
this device marking nomenclature has been updated to use the DLPR410A and DLPR410B device part numbers
instead of the previous 2510442 marking, as shown in Figure 11-3 and Figure 11-4.
2510442-0005
YY/WW
Pin 1
Figure 11-2. DLPR410 Device Markings
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DLPR410A
YVA YY/WW
Pin 1
Figure 11-3. DLPR410A Device Markings
DLPR410B
YVA YY/WW
Pin 1
Figure 11-4. DLPR410B Device Markings
Where YY/WW is the year/week the part was programmed.
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11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
Table 11-2. Related Documentation
DOCUMENT
TI LITERATURE NUMBER
DLP650LNIR 0.65 NIR WXGA S450 DMD data sheet
DLPS136
DLP7000 DLP 0.7 XGA 2xLVDS Type A DMD data sheet
DLPS026
DLP7000UV DLP 0.7 UV XGA 2xLVDS Type-A DMD data sheet
DLPS061
DLP9500 DLP 0.95 1080p 2xLVDS Type-A DMD data sheet
DLPS025
DLP9500UV DLP 0.95 UV 1080p 2xLVDS Type-A DMD data sheet
DLPS033
DLPA200 DMD Micromirror Driver data sheet
DLPS015
DLPC410 DMD Digital Controller data sheet
DLPS024
XCF16P data sheet
available at www.xilinx.com
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
Xilinx® is a registered trademark of Xilinx, Inc.
All trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this datasheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
(4/5)
(6)
DLPR410AYVA
ACTIVE
DSBGA
YVA
48
3
TBD
Call TI
Call TI
-40 to 85
DLPR410BYVA
ACTIVE
DSBGA
YVA
48
3
TBD
Call TI
Call TI
-40 to 85
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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