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DRV110
SLVSBA8G – MARCH 2012 – REVISED MARCH 2018
DRV110 120- and 230-V AC, 6- to 48-V DC Current Controller for
Solenoids, Relays, and Valves
1 Features
3 Description
•
The DRV110 device is a PWM current controller for
solenoids. The device is designed to regulate the
current with a well-controlled waveform to reduce
power dissipation. The solenoid current is ramped up
fast to ensure opening of the valve or relay. After
initial ramping, the solenoid current is kept at a peak
value to ensure correct operation, after which the
current is reduced to a lower hold level to avoid
thermal problems and reduce power dissipation.
1
•
•
•
•
•
•
•
•
Internal Zener Diode on Supply Pin for HighVoltage Operation
– 120- and 230-V AC Supply Through Rectifier
and RS Resistor
– 24-V, 48-V, and Higher DC Supply Through RS
Resistor
Drives an External MOSFET With PWM to Control
Solenoid Current
– External Sense Resistor for Regulating
Solenoid Current
Fast Ramp-Up of Solenoid Current to Ensure
Activation
Solenoid Current is Reduced in Hold Mode for
Lower Power and Thermal Dissipation
Ramp Peak Current, Keep Time at Peak Current,
Hold Current, and PWM Clock Frequency Can Be
Set Externally. They Can Also Be Operated at
Nominal Values Without External Components.
Protection
– Thermal Shutdown
– Undervoltage Lockout (UVLO)
Optional STATUS Output
Operating Temperature Range: –40ºC to +125ºC
8-Pin and 14-Pin TSSOP Package Options
2 Applications
•
•
Electromechanical Drivers: Solenoids, Valves,
Relays, Contactors, Switchgear, Pneumatics
White Goods, Solar, Transportation, Smart Grid,
Power Distribution
The peak current duration is set with an external
capacitor. The peak and hold levels of the current
ramp, as well as the PWM frequency, can
independently be set with external resistors. External
setting resistors can also be omitted if the default
values for the corresponding parameters are suitable
for the application.
The DRV110 device has an internal Zener diode that
limits the supply at VIN to VZENER for applications that
require a higher supply voltage. Using the internal
Zener, the DRV110 can be powered from 120-V and
230-V AC supplies through a rectifier and currentlimiting resistor. High DC voltages such as 48-V can
also be accommodated this way.
Device Information(1)
PART NUMBER
DRV110
PACKAGE
BODY SIZE (NOM)
TSSOP (14)
5.00 mm × 4.40 mm
TSSOP (8)
3.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
DRV110 Supplied by Power Line Voltage
RS
DRV110
M1
OUT
RSENSE
OSC
KEEP
HOLD
SENSE
ROSC
RPEAK
PEAK
EN
GND
C1
LS
D1
VIN
CKEEP
C2
RHOLD
120 and 230 V AC
Copyright © 2018, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRV110
SLVSBA8G – MARCH 2012 – REVISED MARCH 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
5
6.1
6.2
6.3
6.4
6.5
6.6
5
5
5
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 9
7.4 Device Functional Modes........................................ 13
8
Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical Application .................................................. 14
9 Power Supply Recommendations...................... 17
10 Layout................................................................... 17
10.1 Layout Guidelines ................................................. 17
10.2 Layout Example .................................................... 18
11 Device and Documentation Support ................. 19
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
19
19
19
19
19
19
12 Mechanical, Packaging, and Orderable
Information ........................................................... 19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (March 2017) to Revision G
Page
•
Changed the maximum supply limited by the Zener diode from 15 V to VZENER .................................................................... 1
•
Deleted virtual from the operating junction temperature and changed its maximum value from 125°C to 150°C in the
Absolute Maximum Ratings table ........................................................................................................................................... 5
•
Added the temperature range for the parameters in the Recommended Operating Conditions table, add the VS
parameter, and updated the VIN and IQ parameters ............................................................................................................... 5
•
Deleted the solenoid inductance parameter from the Recommended Operating Conditions table ....................................... 5
•
Deleted the IVIN test condition from the gate drive voltage parameter in the Electrical Characteristics table ........................ 6
•
Changed the parameter names for VPEAK and VHOLD in the Electrical Characteristics table .................................................. 6
•
Added the input pulldown resistance parameter in the Electrical Characteristics table......................................................... 6
•
Added the DRV110 Current Control with Varying OUT Duty Cycle image to the PWM Current Control section................ 10
•
Changed the RPEAK value for IPEAK = 450 mA from 50 kΩ to 55 kΩ in the Configuring Peak and Hold Currents section.... 10
•
Changed the Configuring Peak and Hold Currents section and PEAK and HOLD Mode VREF Settings image (which
is now named IPEAK and IHOLD settings for RSENSE = 1 Ω....................................................................................................... 11
•
Changed the Voltage Supply and Integrated Zener Diode section. Added the VZENER Value table and changed the
RS equation to specify calculations for RS,max and RS,min ...................................................................................................... 12
•
Deleted the Default Configuration schematic ....................................................................................................................... 14
•
Added the Current Limiting Resistor Selection and Passives Selection sections in the Detailed Design Procedure.......... 15
•
Changed the value of RPEAK from 303 kΩ to 400 kΩ in the Application Curve .................................................................... 17
Changes from Revision E (November 2016) to Revision F
Page
•
Changed the Functional Block Diagram ................................................................................................................................. 8
•
Changed the IHOLD equation ................................................................................................................................................ 11
•
Changed the Shutdown section to provide a description of the STATUS pin. .................................................................... 13
2
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SLVSBA8G – MARCH 2012 – REVISED MARCH 2018
Changes from Revision D (June 2016) to Revision E
Page
•
Changed the title of the document to include V AC and V DC values ................................................................................... 1
•
Revised Features and Applications lists ................................................................................................................................ 1
•
Changed first page graphic to schematic .............................................................................................................................. 1
•
Revised table notes for Recommended Operating Conditions table...................................................................................... 5
Changes from Revision C (April 2016) to Revision D
Page
•
Changed the title of the document ........................................................................................................................................ 1
•
Changed 160 kΩ in the fPWM equation to 66.67 kΩ .............................................................................................................. 11
•
Added the Receiving Notification of Documentation Updates section ................................................................................. 19
Changes from Revision B (July 2015) to Revision C
Page
•
Changed one test condition (ROSC = 50 kΩ to 160 kΩ) and the maximum value for the Externally set PWM clock
frequency (60 to 25) in the Electrical Characteristics table ................................................................................................... 6
•
Changed the PWM Clock Frequency Setting graph............................................................................................................. 11
Changes from Revision A (January 2013) to Revision B
•
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
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SLVSBA8G – MARCH 2012 – REVISED MARCH 2018
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5 Pin Configuration and Functions
PW Package
8-Pin TSSOP
Top View
PW Package
14-Pin TSSOP
Top View
NC
1
14
NC
OUT
KEEP
2
13
EN
6
SENSE
PEAK
3
12
STATUS
5
GND
HOLD
4
11
OUT
OSC
5
10
NC
NC
6
9
SENSE
VIN
7
8
GND
KEEP
1
8
EN
PEAK
2
7
OSC
3
VIN
4
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
8 PINS
14 PINS
8
13
I
Enable
GND
5
8
—
Ground
HOLD
—
4
I
Hold current set (1)
KEEP
1
2
I
Keep time set
NC
—
1
—
No connect
NC
—
6
—
No connect
NC
—
10
—
No connect
NC
—
14
—
No connect
OSC
3
5
I
PWM frequency set
OUT
7
11
O
Solenoid switch gate drive
PEAK
2
3
I
Peak current set
EN
SENSE
6
9
I
Solenoid current sense
STATUS
—
12
O
Open drain status indicator
VIN
4
7
I
6-V to 15-V supply
(1)
4
In the 8-pin package, the HOLD pin is not bonded out. For this package, the HOLD mode is configured to default (internal) settings.
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6 Specifications
6.1 Absolute Maximum Ratings
(1)
See
and
(2)
MIN
MAX
UNIT
Input voltage
–0.3
20
V
Voltage on EN, STATUS, PEAK, HOLD, OSC, SENSE, KEEP
–0.3
7
V
Voltage on OUT
–0.3
20
V
TJ
Operating junction temperature
–40
150
°C
Tstg
Storage temperature
–65
150
°C
VIN
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
–40°C ≤ TA ≤ 125°C (unless otherwise noted)
MIN
NOM
IQ
Supply current (the device sinks additional current when VIN > VZENER (1))
1
1.5
VIN
Voltage at the VIN pin (2) (3) (see Detailed Description)
6
VS
Voltage directly from the supply before clamped by the Zener diode
6
CIN
Input capacitor between VIN and GND
TA
Operating ambient temperature
(1)
(2)
(3)
(4)
(4)
MAX UNIT
3
mA
V
330
1
4.7
–40
V
µF
125
°C
The device regulates the supply with an internal Zener diode. The device sinks up to 3 mA with the added supply current. See
Equation 5 to find appropriate value for the RS resistor.
The maximum input voltage of the device depends on the clamping voltage of the internal Zener diode, which changes over
temperature. A current-limiting resistor is required to limit current to the Zener diode if the input voltage (VIN) is greater than VZENER. For
more information on resistor sizing see the Detailed Description section and Application and Implementation section.
For VS voltages less than VZENER, VIN = VS. For VS voltages greater than VZENER, VIN = VZENER.
4.7-µF input capacitor and full wave rectified 230-Vrms AC supply results in approximately 500-mV supply ripple.
6.4 Thermal Information
DRV110
THERMAL METRIC (1)
PW (TSSOP)
UNIT
8 PINS
14 PINS
RθJA
Junction-to-ambient thermal resistance
183.8
122.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
69.2
51.2
°C/W
RθJB
Junction-to-board thermal resistance
112.6
64.3
°C/W
ψJT
Junction-to-top characterization parameter
10.4
6.5
°C/W
ψJB
Junction-to-board characterization parameter
110.9
63.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
VIN = 14 V, –40°C ≤ TA ≤ 125°C, over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
IQ
Standby current
EN = 0, VIN = 14 V, bypass deactivated
200
250
Quiescent current
EN = 1, VIN = 14 V, bypass deactivated
360
570
Internally regulated supply
EN = 0, IVIN = 2 mA, bypass activated
10.5
15
19
EN = 1, IVIN = 2 mA, bypass activated
14.5
15
15.5
µA
V
GATE DRIVER
VDRV
Gate drive voltage
Supply voltage in regulation
IDRV_SINK
Gate drive sink current
VOUT = 15 V; VIN = 15 V
IDRV_SOURCE
Gate drive source current
VOUT = GND; VIN = 15 V
fPWM
PWM clock frequency
OSC = GND
DMAX
Maximum PWM duty cycle
DMIN
Minimum PWM duty cycle
tD
Start-up delay
8
15
VIN
V
15
mA
–15
–10
mA
20
27
kHz
50
µs
100%
7.5%
Delay between EN going high until gate driver
starts switching, fPWM = 20 kHz
CURRENT CONTROLLER, INTERNAL SETTINGS
IPEAK
Peak current
RSENSE = 1 Ω, PEAK = GND
270
300
330
mA
IHOLD
Hold current
RSENSE = 1 Ω, HOLD = GND
40
50
65
mA
CURRENT CONTROLLER, EXTERNAL SETTINGS
tKEEP
Externally set keep time at peak current
900
VPEAK
Voltage of internal reference to which the RPEAK = 50 kΩ
SENSE pin voltage is compared to for
RPEAK = 200 kΩ
IPEAK
CKEEP = 1 µF
100
VHOLD
Voltage of internal reference to which the RHOLD = 50 kΩ
SENSE pin voltage is compared for IHOLD RHOLD = 200 kΩ
150
fPWM
Externally set PWM clock frequency
ms
mV
300
mV
50
ROSC = 160 kΩ
25
ROSC = 200 kΩ
20
kHz
LOGIC INPUT LEVELS (EN)
VIL
Input low level
VIH
Input high level
1.65
Input pullup resistance
350
REN
1.3
Input pulldown resistance
V
V
500
kΩ
250
kΩ
LOGIC OUTPUT LEVELS (STATUS)
VOL
Output low level
Pulldown activated, ISTATUS = 2 mA
IIL
Output leakage current
Pulldown deactivated, V(STATUS) = 5 V
0.3
V
2
µA
UNDERVOLTAGE LOCKOUT
VUVLO
Undervoltage lockout threshold
4.6
V
THERMAL SHUTDOWN
TTSU
Junction temperature start-up threshold
140
°C
TTSD
Junction temperature shutdown
threshold
160
°C
6
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6.6 Typical Characteristics
Figure 1. Solenoid Current, EN, and PWM vs Time
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7 Detailed Description
7.1 Overview
The DRV110 device provides a PWM current controller for use with solenoids. The device provides a quick ramp
to a high peak current value in order to ensure opening of the valve or relay. The current is held for a
programmable time and then lowered to the hold current value to maintain the open state of the valve or relay
while reducing the total current consumption. Peak current duration, peak current amount, hold current amount
(in the 14-pin package), and PWM frequency can all be controlled by external components or used at default
levels by omitting these components (except peak current duration).
Enable and disable of the switch is controlled by the EN pin. The EN pin contains an internal resistor network to
set the pin to logic HIGH when the EN pin is floating. This feature can be used for situations where a control
signal is not required and the solenoid is only energized when a supply voltage is present. Such applications
could be valves or contactors.
The DRV110 also features a wide VIN range with an internal bypass regulator to maintain VIN at an acceptable
level. Finally, the 14-pin package features an open-drain pull-down path on the STATUS pin which is enabled as
long as undervoltage lockout or thermal shutdown has not triggered.
STATUS(1)
7.2 Functional Block Diagram
ROSC OSC
VS
VS
RS
VIN
UVLO
LDO
C1
Thermal
Shutdown
OSC
500 k
EN
LS
D1
1k
VIN
250 k
OUT
M1
1 µA
PWM
Control
SENSE
SW
+
100 mV
±
CKEEP
MUX
RPEAK
GND
HOLD(1)
PEAK
KEEP
REF
RHOLD
RSENSE
(1)
Copyright © 2017, Texas Instruments Incorporated
(1)
8
Available only in the 14-pin package.
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7.3 Feature Description
The DRV110 controls the current through the solenoid as shown in Figure 2. Activation starts when EN pin
voltage is pulled high either by an external driver or internal pullup. In the beginning of activation, DRV110 allows
the solenoid current to ramp up to the peak value IPEAK and it regulates it at the peak value for the time, tKEEP,
before reducing it to IHOLD. The solenoid current is regulated at the hold value as long as the EN pin is kept high.
The initial current ramp-up time depends on the inductance and resistance of the solenoid. Once EN pin is driven
to GND, DRV110 allows the solenoid current to decay to zero.
ISOLENOID
IPEAK
IHOLD
t
tKEEP
EN
t
Figure 2. Typical Current Waveform Through the Solenoid
7.3.1 Keep Time
The keep time, tKEEP, is set externally by connecting a capacitor to the KEEP pin. A constant current is sourced
from the KEEP pin that is driven into an external capacitor resulting in a linear voltage ramp. When the KEEP pin
voltage reaches 100 mV, the current regulation reference voltage, VREF, is switched from VPEAK to VHOLD. The
internal current source is switched off, and the capacitor is grounded for discharge. The dependency of tKEEP
from the external capacitor size can be calculated with Equation 1.
ésù
tKEEP éës ùû = CKEEP éëF ùû × 105 ê ú
ëF û
(1)
7.3.2 PWM Current Control
The current control loop regulates, cycle-by-cycle, the solenoid current by sensing voltage at the SENSE pin and
controlling the external switching device gate through the OUT pin. During the ON-cycle, the OUT pin voltage is
driven and kept high (equal to VIN voltage) allowing current to flow through the external switch as long as the
voltage at the SENSE pin is less than VREF. As soon as the voltage at the SENSE pin is above VREF, the OUT
pin voltage is immediately driven low and kept low until the next ON-cycle is triggered by the internal PWM clock
signal. In the beginning of each ON-cycle, the OUT pin voltage is driven high and kept high for at least the time
determined by the minimum PWM signal duty cycle, DMIN.
Because the current sense is done by comparing the voltage at the SENSE pin to a reference voltage, the
DRV110 device acts like a hysteresis controller. When the device acts like a hysteresis controller, it can make
the PWM frequency and duty cycle appear uneven for some solenoids (see Figure 3).
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Feature Description (continued)
VS
ICOIL
OSC
LS
D1
PWMCLK
PWMCLK
VIN
OUT
M1
VOUT
PWM
Control
VOUT
SENSE
VSENSE
VREF
VSENSE
VREF
92%
8%
100%
88%
70%
D
GND
10%
RSENSE
(1)
The DRV110 device measures the voltage at the SENSE node (VSENSE). This voltage is compared against the
reference voltage (VREF) each clock cycle. The voltage at the output node (VOUT) becomes low when VSENSE ≥ VREF.
The duty cycle (D) of the output voltage varies from 8% to 100%. In summary, the SENSE voltage is sampled after
each rising edge of the PWM CLK signal (PWMCLK) and goes low when VSENSE ≥ VREF at a minimum duty cycle of
8%.
Figure 3. DRV110 Current Control with Varying OUT Duty Cycle
7.3.3 Configuring Peak and Hold Currents
IPEAK and IHOLD depend on fixed resistance values RPEAK and RHOLD as shown in Figure 4. If the PEAK pin or
HOLD pin is connected to ground or RPEAK or RHOLD is less than 43.33 kΩ (typical), then IPEAK is at its default
value of 300 mA for IPEAK and 50 mA for IHOLD.
The IPEAK value can alternatively be set by connecting an external resistor to ground from the PEAK pin. For
example, if a 60-kΩ (= RPEAK) resistor is connected between PEAK and GND, and RSENSE = 1 Ω, then the
externally set IPEAK level will be 900 mA. If RPEAK = 200 kΩ and RSENSE = 1 Ω, then the externally set IPEAK level
will be 300 mA. TI does not recommend using a resistor from 30 kΩ and 55 kΩ to avoid the IPEAK or IHOLD current
slipping from the maximum current setting to the default setting.
In case RSENSE = 2 Ω instead of 1 Ω, then IPEAK = 450 mA (when RPEAK = 55 kΩ) and IPEAK = 150 mA (when
RPEAK = 200 kΩ). In the 8-pin package, the HOLD reference uses the internal VREF setting of 50 mV. In the 14pin package, external setting of the HOLD current, IHOLD, works in the same way as the external setting for IPEAK
but the current levels are 1/6 of the IPEAK levels for the same resistor setting.
External settings for IPEAK and IHOLD are independent of each other. If RPEAK or RHOLD is decreased below 33.33
kΩ (typical value), then the reference is clamped to the internal setting of 300 mV for PEAK and 50 mV for
HOLD. Use Equation 2 and Equation 3 to calculate the values for IPEAK and IHOLD respectively.
The currents and resistor values should be chosen such that the voltage across the sense resistor is more than
30 mV.
10
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Feature Description (continued)
IPEAK =
IHOLD
VREF
1 W ´ 900 mA ´ 66.67 kW
1
; 66.67 kW < RPEAK < 2 MW
=
´
RSENSE
RPEAK
RSENSE
(2)
VREF
RSENSE
(3)
1 : u 150 mA u 66.67 k:
1
u
;66.67 k: RHOLD
RHOLD
RSENSE
333 k:
1000
IHOLD
IPEAK
900
IHOLD/PEAK (mA)
800
700
600
500
400
300
200
100
0
0
50
100
150
RHOLD/PEAK (k )
200
250
D001
Figure 4. IPEAK and IHOLD settings for RSENSE = 1 Ω
7.3.4 Configuring the PWM Frequency
Frequency of the internal PWM clock signal, PWMCLK, that triggers each OUT pin ON-cycle can be adjusted by
external resistor, ROSC, connected between OSC and GND. Frequency as a function of resistor value is shown in
Figure 5. Default frequency is used when OSC is connected to GND directly. Use Equation 4 to calculate the
PWM frequency as a function of the external fixed adjustment resistor value (greater than 160 kΩ).
60 kHz
fPWM =
´ 66.67 kW ; 160 kW < ROSC < 2 MW
ROSC
(4)
40
35
30
fPWM (kHz)
160 k:, 25 kHz
25
20
15
(0 to 100 :, 20 kHz)
10
5
0
0
100
200
300
400
ROSC (k:)
500
600
700
D001
Figure 5. PWM Clock Frequency Setting
7.3.5 Voltage Supply and Integrated Zener Diode
Voltage at the OUT pin, that is the gate voltage of an external switching device, is equal to VIN voltage during
the ON-cycle. The voltage is driven to ground during the OFF-cycle. VIN voltages below VZENER can be supplied
directly from an external voltage source. Supply voltages of at least 6 V are supported.
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Feature Description (continued)
The DRV110 is able to regulate VIN voltage from a higher external supply voltage, VS, by an internal bypass
regulator that replicates the function of an ideal Zener diode. This requires that the supply current is sufficiently
limited by an external resistor between VS and the VIN pin. An external capacitor connected to the VIN pin is
used to store enough energy to charge the external switch gate capacitance at the OUT pin. A range of current
limiting resistor sizes (RS,min and RS,max) can be calculated with Equation 5 and Equation 6. This range keeps the
VIN current within the recommended operating conditions.
VS,minDC VZENER
RS,max
1 mA IGate,AVE
where
•
RS,min
IGate,AVE is the current flowing to the external switch. For a MOSFET, IGate,AVE is equal to the external FET gate
charge multiplied by fPWM.
(5)
VS,max DC
VZENER
3 mA IGate,AVE
(6)
Ideally, the DRV110 device clamps the input voltage to 15 V. For configurations that do not use the EN pin (force
the pin high or leave it floating), the DRV110 device clamps at 15 V (VZENER = 15 V) across the temperature
range of the device. If the EN pin is set to 0, then refer to the values in Table 1 to find the VZENER used when
calculating the value of RS, based on the temperature range of the application. Because the VZENER changes
when the EN state changes, select a value for RS that meets the current requirements at both VZENER voltages.
Table 1. VZENER Value
TEMPERATURE RANGE
ENABLE STATE
VZENER
–40°C ≤ TA ≤ 125°C
1
15 V
–40°C ≤ TA ≤ 35°C
0
15 V
–40°C ≤ TA ≤ 45°C
0
14.2 V
–40°C ≤ TA ≤ 55°C
0
13.9 V
–40°C ≤ TA ≤ 65°C
0
13.5 V
–40°C ≤ TA ≤ 75°C
0
13.1 V
–40°C ≤ TA ≤ 85°C
0
12.7 V
–40°C ≤ TA ≤ 95°C
0
12.3 V
–40°C ≤ TA ≤ 105°C
0
12 V
–40°C ≤ TA ≤ 115°C
0
11.4 V
–40°C ≤ TA ≤ 125°C
0
11 V
The open-drain pulldown path at the STATUS pin is deactivated if the undervoltage lockout or thermal shutdown
blocks have triggered or if the EN pin is low.
12
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7.4 Device Functional Modes
7.4.1 Normal Mode
The DRV110 transitions through three different states in normal mode:
OFF state
In the OFF state, the EN pin is low and the PWM output is off.
PEAK state The PEAK state begins when the EN pin is set high, and ends when the tKEEP time has been
reached. During this state, the PWM operates to reach the IPEAK current set by the RPEAK resistor.
HOLD state In the HOLD state, the tKEEP time has been reached, and the PWM continues to operate but at the
IHOLD level. This continues until the EN pin is set low again and the PWM turns off.
7.4.2 Shutdown
The DRV110 turns off the gate driver in undervoltage lockout (VIN < 4.6 V) or thermal shutdown (TJ > 160°C). If
temperature shutdown is activated, the DRV110 resumes operation when the junction temperature is below
140°C. The shutdown conditions are expressed by the STATUS pin going to the high-impedance state. A pullup
resistor can be connected to the STATUS pin so these conditions may be observed by a microcontroller. Table 2
provides an explanation of this operation.
Table 2. Shutdown Operation
CONDITIONS
OUTPUT PINS
EN
UVLO
TSD
STATUS
OUT
0
X
X
Hi-Z
LOW
1
0
0
Pulled down
HIGH or PWM
1
X
1
Hi-Z
LOW
1
1
X
Hi-Z
LOW
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DRV110 device is designed to operate a solenoid valve or relay. For detailed information on using the
DRV110 with 230 V AC solenoids, see Current Controlled Driver for 230V AC Solenoids Reference Design. A
typical DC input design will be outlined in Typical Application. Approximate resistor and capacitor values for the
peak current, hold current, sense, and keep time will be derived for a sample application.
8.2 Typical Application
120 and 230 V AC
D1
C2
RS
LS
DRV110
VIN
C1
M1
OUT
EN
RSENSE
OSC
ROSC
KEEP
HOLD
CKEEP
RHOLD
PEAK
RPEAK
GND
SENSE
Copyright © 2016, Texas Instruments Incorporated
Figure 6. DRV110 Powered by a Rectified AC Power Source
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Typical Application (continued)
16 V to 48 V
D1
RS
LS
DRV110
VIN
C1
M1
OUT
EN
RSENSE
OSC
ROSC
KEEP
HOLD
CKEEP
RHOLD
PEAK
RPEAK
GND
SENSE
Copyright © 2016, Texas Instruments Incorporated
Figure 7. DRV110 Powered by a DC Power Source Greater than 15 V
8.2.1 Design Requirements
The key elements to identify here are the system input voltage, peak current, hold current, and peak keep time
values required for the solenoid or relay being used. With these values, approximate RS, RPEAK, RHOLD (for 14-pin
package), CKEEP, and RSENSE values can be determined and the proper FET and diode can be identified. ROSC
can be varied in order to tune the circuit to the chosen solenoid or relay.
8.2.2 Detailed Design Procedure
8.2.2.1 Current Limiting Resistor Selection
The temperature range, input voltage, and enable state must be considered when selecting the current limiting
resistor. These values must be considered because the Zener clamping voltage of the DRV110 device starts
dropping from its ideal 15 V at temperatures greater than 45°C when the EN pin is pulled low. Applications that
leave the EN pin floating or pulled high at all times only require a current-limiting resistor when the input voltage
is greater than 15 V across all temperature.
While using a current-limiting resistor is not required when the supply voltage (VS) is less than the Zener
clamping voltage, VZENER, TI recommends populating a small resistor in case of possible input voltage transients
during operation. At the very least, TI recommends placing a resistor footprint jumped by a 0-Ω resistor. Table 3
lists recommended resistor values for voltages close to VZENER and common voltages greater than VZENER for
different enable states.
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Table 3. Recommended Resistor Values
–40°C ≤ TA ≤ 125°C
SUPPLY VOLTAGE
RECOMMENDED CURRENTLIMITING RESISTOR
EN Pulled High or Floating
< 15 V
500 Ω
24 V
9 kΩ
48 V
33 kΩ
110 V to 120 V
100 kΩ
220 V to 240 V
200 kΩ
EN Toggled Between 0 and 1
10 V
510 Ω
11 V
510 Ω
12 V
1 kΩ
13 V
2 kΩ
14 V
3 kΩ
15 V
3.9 kΩ
24 V
13 kΩ
48 V
36 kΩ
110 V to 120 V
100 kΩ
220 V to 240 V
200 kΩ
8.2.2.2 Passive Component Selection
With the selected peak current, hold current, and peak keep time values, the values of RPEAK, RHOLD (for 14-pin
package), CKEEP, and RSENSE can be determined. Table 4 lists the example values and results from calculation.
Table 4. Example Application Values When RSENSE = 1 Ω
VARIABLE
VALUE
14-PIN VALUES
8-PIN VALUES
CALCULATED FROM
Peak current
150 mA
RPEAK = 400 kΩ
RPEAK = 400 kΩ
Equation 2
Hold current
50 mA
RHOLD = 200 kΩ or
connect HOLD to ground
Default
Equation 3
Keep time
100 ms
CKEEP = 1 µF
CKEEP = 1 µF
Equation 1
PWM frequency
20 kHz
ROSC = Shorted to ground
ROSC = Shorted to ground
Equation 4
Use Equation 2 and Equation 3 to calculate the values of the RPEAK resistor and RHOLD (if applicable) resistor. For
the sample values, the RPEAK resistor is set to 400 kΩ and the RHOLD resistor is shorted to GND. TI recommends
using a 0-Ω resistor for prototyping in case changes to this value are desired.
Next, select the value of the CKEEP capacitor based on Equation 1. For the sample value, the CKEEP capacitor is
set to 1 µF. The ROSC resistor is initially be shorted to GND, but a 0-Ω resistor is also recommended for
prototyping. Additionally, a low-pass filter on the SENSE line can be added in a high-noise environment and is
recommended for prototyping. The typical value for the low pass filter resistor is 1 kΩ and the typical value for
the filter capacitor is 100 pF.
The value of sense resistor can be selected based on the preference of the designer. The only restriction is that
the voltage across the sense resistor (found by the RSENSE resistance times the IHOLD current) must be greater
than 30 mV for reliable operation.
The external FET and current recirculation diode must be selected based on the current values defined in
Table 4 and the supply voltage. The current recirculation diode should be a fast recovery diode.
16
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8.2.3 Application Curve
ROSC = 0 Ω
RPEAK = 400 kΩ
RHOLD = 0 Ω
RSENSE = 1 Ω
CKEEP = 1 μF
Lind = 1 H
Rind = 50 Ω
Measured on the EVM
Figure 8. ISOLENOID, EN, and VIN vs Time
9 Power Supply Recommendations
The input supply range must be at least 6 V, and needs a current-limiting resistor above VZENER. An input
capacitor of 4.7 µF (typical) is required as well. IQ max is 3 mA, but additional current will be required to operate
the solenoid or relay.
10 Layout
10.1 Layout Guidelines
Routing for the SENSE pin should be careful to avoid noise sources. Routing for the output node and sense
node should be minimized. The trace for the solenoid or relay current should be wide in order to prevent any
unexpected voltage drop.
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10.2 Layout Example
Figure 9. Layout Schematic
18
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Current Controlled Driver for 24-V DC Solenoid With Plunger Fault Detection reference
design
• Texas Instruments, Current Controlled Driver for 230V AC Solenoids Reference Design
• Texas Instruments, DRV110 and DRV120 Evaluation Modules (EVM) user's guide
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
DRV110APWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
110A
DRV110PWR
ACTIVE
TSSOP
PW
8
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
110
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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