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DRV401-Q1
SBOS814 – DECEMBER 2016
DRV401-Q1 Sensor Signal Conditioning Device
for Closed-Loop Magnetic Current Sensor
1 Features
3 Description
•
•
The DRV401-Q1 device is fully qualified for
automotive applications and is suitable for motor
control drive and battery monitoring systems.
1
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to
+125°C Ambient Operating Temperature
Range
– Device HBM ESD Classification Level 1C
– Device CDM ESD Classification Level C6
Single-Supply: 5-V
Power Output: H-Bridge
Designed for Driving Inductive Loads
Excellent DC Precision
Wide System Bandwidth
High-Resolution, Low-Temperature Drift
Built-In Degauss System
Extensive Fault Detection
External High-Power Driver Option
Compact Footprint
When used with a magnetic sensor, the DRV401-Q1
monitors ac and dc currents to high accuracy.
Provided functions include: probe excitation, signal
conditioning of the probe signal, signal loop amplifier,
an H-bridge driver for the compensation coil, and an
analog signal output stage that provides an output
voltage proportional to the primary current. It offers
overload and fault detection, as well as transient
noise suppression.
The DRV401-Q1 device directly drives the
compensation coil or connects to external power
drivers. Therefore, the DRV401-Q1 combines with
sensors to measure small to large currents.
To maintain the highest accuracy, the DRV401-Q1
demagnetizes (degausses) the sensor at power-up
and on demand.
Device Information(1)
2 Applications
•
•
•
•
•
•
•
•
PART NUMBER
Automotive
Motor Control in Automotive Applications
Flux Gate Current Sensing
Generator and Alternator Monitoring and Control
Frequency and Voltage Inverters
Motor Drive Controllers
System Power Consumption
Photovoltaic Systems
DRV401-Q1
PACKAGE
VQFN-20
BODY SIZE (NOM)
5.00 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Closed-Loop Magnetic Sensing
Patents Pending
Compensation
PWM
Compensation Winding
Primary Winding
RS
ICOMP1
PWM
ICOMP2
DRV401-Q1
Diff
Amp
Magnetic Core
Field Probe
IS2
IP
VOUT
REFIN
IS1
Probe
Interface
Integrator
Filter
Timing, Error Detection,
and Power Control
H-Bridge
Driver
Degauss
VREF
VREF
+5 V GND
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRV401-Q1
SBOS814 – DECEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
8
9 Power Supply Recommendations...................... 28
10 Layout................................................................... 29
10.1 Layout Guidelines ................................................. 29
10.2 Layout Example .................................................... 30
10.3 Power Dissipation ................................................. 30
11 Device and Documentation Support ................. 31
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Detailed Description ............................................ 14
7.1
7.2
7.3
7.4
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
8.1 Application Information............................................ 24
8.2 Typical Application ................................................. 26
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
14
14
15
23
Device Support......................................................
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
31
31
31
31
32
32
32
12 Mechanical, Packaging, and Orderable
Information ........................................................... 33
12.1 Thermal Pad.......................................................... 33
Application and Implementation ........................ 24
4 Revision History
2
DATE
REVISION
NOTES
December 2016
*
Initial release.
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5 Pin Configuration and Functions
5
PWM
PWM
IS1
GND1
IS2
19
18
17
16
VOUT
10
REFIN
9
4
GND2
REFOUT
ICOMP2
3
8
GAIN
Exposed
Thermal Pad
on Underside,
Connect
to GND1
7
2
IAIN2
DEMAG
6
1
IAIN1
ERROR
20
RGW Package
20-Pin VQFN With Exposed Thermal Pad
Top View
15
VDD1
14
OVER-RANGE
13
CCdiag
12
VDD2
11
ICOMP1
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
CCdiag
13
I
Control input for wire-break detection: high = enable
DEMAG
2
I
Control input; See the Demagnetization section.
ERROR
1
O
Error flag: open-drain output. See the Error Conditions section.
Control input for open-loop gain: low = normal, high = −8 dB
GAIN
3
I
GND1
17
—
Ground connection
GND2
9
—
Ground connection. Connect to GND1.
IAIN1
8
I
Inverting input of differential amplifier
IAIN2
7
I
Noninverting input of differential amplifier
ICOMP1
11
O
Output 1 of compensation coil driver
ICOMP2
10
O
Output 2 of compensation coil driver
IS1
18
I/O
Probe connection 1
IS2
16
I/O
Probe connection 2
OVERRANGE
14
O
Open-drain output for overrange indication: low = overrange
PWM
19
O
PWM output from probe circuit (inverted)
PWM
20
O
PWM output from probe circuit
REFOUT
4
O
Output for internal 2.5-V reference voltage
REFIN
5
I
Input for zero reference to differential amplifier
Thermal
pad
—
—
Exposed thermal pad. Connect to GND1.
VDD1
15
—
Supply voltage
VDD2
12
—
Supply voltage. Connect to VDD1.
VOUT
6
O
Output for differential amplifier
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SBOS814 – DECEMBER 2016
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted). (1)
MIN
Voltage
Differential amplifier
Current
Signal input pin
−0.5
VDD + 0.5
Signal input pin
–10
10
Signal input pin, IS1 and IS2
–75
75
Pins other than IS1 and IS2
–25
25
0
250
–50
150
Operating, TA
Temperature
UNIT
7
ICOMP short circuit
Junction, TJ
V
mA
150
Storage, Tstg
(1)
MAX
Supply voltage
–55
°C
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC Q100-002
(1)
Electrostatic
discharge
V(ESD)
Charged-device model (CDM), per AEC Q100-011
(1)
Pins IAIN1 and IAIN2
±1000
All other pins
±5000
All pins
±1000
Corner pins
±1000
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
Power supply voltage, VDD1, VDD2
4.5
5
5.5
UNIT
V
Specified temperature range
–40
25
+125
°C
6.4 Thermal Information
over operating free-air temperature range (unless otherwise noted)
DRV401-Q1
THERMAL METRIC
(1)
RGW
(VQFN)
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
34.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
22.8
°C/W
RθJB
Junction-to-board thermal resistance
12.1
°C/W
ψJT
Junction-to-top characterization parameter
0.3
°C/W
ψJB
Junction-to-board characterization parameter
12.0
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
3.5
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SBOS814 – DECEMBER 2016
6.5 Electrical Characteristics
at TA = 25°C and VDD1 = VDD2 = 5 V with external 100-kHz filter bandwidth (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
mV
DIFFERENTIAL AMPLIFIER
VOS
Offset voltage, RTO (1) (2)
RL = 10 kΩ to 2.5 V
VREFIN = 2.5 V
Gain = 4 V/V
±0.01
±0.1
dVOS/dT
Offset voltage drift, RTO (2)
RL = 10 kΩ to 2.5 V
VREFIN = 2.5 V
TA = –40°C to 125°C
ICOMP = 0 mA
±0.1
±1
µV/°C
CMRR
Offset voltage vs common-mode,
RTO
RL = 10 kΩ to 2.5 V
VREFIN = 2.5 V
−1 V to 6 V, VREF = 2.5 V
±50
±250
µV/V
PSRR
Offset voltage vs power supply,
RTO
RL = 10 kΩ to 2.5 V
VREFIN = 2.5 V
VREF not included
±4
±50
µV/V
SIGNAL INPUT
Common-mode voltage range
RL = 10 kΩ to 2.5 V
VREFIN = 2.5 V
–1
(VDD) + 1
V
SIGNAL OUTPUT
R = 10 kΩ to 2.5 V, VREFIN = 2.5 V,
Signal overrange indication (OVER- L
TA = –40°C to 125°C, ICOMP = 0 mA,
(2)
RANGE), delay
VIN = 1-V step. See (2)
2.5 to 3.5
Voltage output swing from negative RL = 10 kΩ to 2.5 V
rail (2),
VREFIN = 2.5 V
OVER-RANGE trip level
I = 2.5 mA, CMP trip level
Voltage output swing from positive
rail (2),
OVER-RANGE trip level
ISC
Short-circuit current
(2)
RL = 10 kΩ to 2.5 V
VREFIN = 2.5 V
I = −2.5 mA, CMP trip level
48
85
mV
VDD – 48
mV
RL = 10 kΩ to 2.5 V
VREFIN = 2.5 V
VOUT connected to GND
–18
mA
RL = 10 kΩ to 2.5 V
VREFIN = 2.5 V
VOUT connected to VDD
20
mA
4
V/V
Gain, VOUT/VIN_DIFF
RL = 10 kΩ to 2.5 V
VREFIN = 2.5 V
TA = –40°C to 125°C
Gain error
RL = 10 kΩ to 2.5 V
VREFIN = 2.5 V
Gain error drift
RL = 10 kΩ to 2.5 V
VREFIN = 2.5 V
TA = –40°C to 125°C
ICOMP = 0 mA
Linearity error
VREFIN = 2.5 V
RL = 1 kΩ
VDD – 85
µs
±0.02%
±0.1
±0.3%
ppm/°C
10
ppm
2
MHz
6.5
V/µs
FREQUENCY RESPONSE
BW–3
SR
(1)
(2)
dB
Bandwidth (2)
RL = 10 kΩ to 2.5 V
VREFIN = 2.5 V
Slew rate (2)
RL = 10 kΩ to 2.5 V
VREFIN = 2.5 V
CMVR = −1 V to 4 V
Parameter value referred-to-output (RTO).
θJP = junction-to-pad thermal resistance
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Electrical Characteristics (continued)
at TA = 25°C and VDD1 = VDD2 = 5 V with external 100-kHz filter bandwidth (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Settling time, large-signal (2)
RL = 10 kΩ to 2.5 V
VREFIN = 2.5 V
dV ±2 V to 1%, no external filter
0.9
µs
Settling time (2)
RL = 10 kΩ to 2.5 V
VREFIN = 2.5 V
dV ±0.4 V to 0.01%
14
µs
tS
INPUT RESISTANCE
Differential
RL = 10 kΩ to 2.5 V
VREFIN = 2.5 V
16.5
20
23.5
kΩ
Common-mode
RL = 10 kΩ to 2.5 V
VREFIN = 2.5 V
41
50
59
kΩ
External reference input
RL = 10 kΩ to 2.5 V
VREFIN = 2.5 V
41
50
59
kΩ
Output voltage noise density,
RTO (2)
RL = 10 kΩ to 2.5 V
VREFIN = 2.5 V
f = 1 kHz, compensation loop disabled
NOISE
en
170
nV/√Hz
COMPENSATION LOOP
DC STABILITY
Offset error
(3)
Offset error drift
Gain
PSRR
(2)
Probe f = 250 kHz, RLOAD = 20 Ω,
deviation from 50% PWM,
pin gain = L
0.03%
Probe f = 250 kHz, RLOAD = 20 Ω,
deviation from 50% PWM,
pin gain = L, TA = –40°C to 125°C
7.5
Probe f = 250 kHz, RLOAD = 20 Ω, pin gain
= L,
|VICOMP1| – |VICOMP2|
(2)
Power-supply rejection ratio
–200
Probe f = 250 kHz, RLOAD = 20 Ω
25
ppm/°C
200
500
ppm/V
ppm/V
FREQUENCY RESPONSE
Probe f = 250 kHz, RLOAD = 20 Ω, two
modes, 7.8 kHz
Open-loop gain
24/32
dB
PROBE COIL LOOP
–0.7 to
VDD + 0.7
V
Internal resistor, IS1 or IS2 to VDD1
(2)
47
59
71
Ω
Internal resistor, IS1 or IS2 to
GND1 (2)
60
75
90
Ω
Input voltage clamp range
RHIGH
RLOW
Field probe current < 50 mA
Resistance mismatch between IS1
and IS2 (2)
ppm of RHIGH + RLOW
300
1500
ppm
Total input resistance
TA = –40°C to 125°C
ICOMP = 0 mA
134
200
Ω
22
28
34
mA
250
280
310
Comparator threshold current
Minimum probe loop half-cycle
(2)
Probe loop minimum frequency
250
No oscillation detect (error)
suppression
ns
kHz
35
µs
250
mA
COMPENSATION COIL DRIVER, H-BRIDGE
Peak current
(2)
Voltage swing
(3)
6
VICOMP1 − VICOMP2 = 4 VPP
TA = –40°C to 125°C
ICOMP = 0 mA
20-Ω load
4.2
VPP
For VAC sensors, 0.2% of PWM offset approximately corresponds to 10-mA primary current per offset per winding.
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Electrical Characteristics (continued)
at TA = 25°C and VDD1 = VDD2 = 5 V with external 100-kHz filter bandwidth (unless otherwise noted)
PARAMETER
VOCM
TEST CONDITIONS
MIN
Output common-mode voltage
TYP
MAX
UNIT
VDD2 / 2
Wire break detect, threshold
current (4)
V
33
57
mA
2.5
2.505
±5
±50
ppm/°C
±15
±200
µV/V
VOLTAGE REFERENCE
Voltage
(2)
Voltage drift
PSRR
No load
Power-supply rejection ratio (2)
Load regulation
ISC
2.495
No load, TA = – 40°C to 125°C
ICOMP = 0 mA
(2)
(2)
Short-circuit current
Load to GND and VDD
dI = 0 mA to 5 mA
0.15
V
mV/mA
REFOUT connected to VDD
20
mA
REFOUT connected to GND
–18
mA
At TA = –40°C to 125°C
ICOMP = 0 mA; see the Demagnetization
section
106
DEMAGNETIZATION
Duration
130
ms
DIGITAL I/O
LOGIC INPUTS (DEMAG, GAIN, and CCdiag PINS)
Pull-up high current (CCdiag)
CMOS-type levels, 3.5 < VIN < VDD
Pull-up low current (CCdiag)
CMOS-type levels, 0 < VIN < 1.5
160
µA
5
Logic input leakage current
CMOS-type levels, 0 < VIN < VDD
µA
0.01
µA
Logic level, input: L/H
CMOS-type levels
2.1/2.8
Hysteresis
CMOS-type levels
0.7
4-mA sink
0.3
OUTPUTS (ERROR AND OVER-RANGE PINS)
Logic level, output: L
V
No
internal
pull-up
Logic level, input: H
OUTPUTS (PWM AND PWM PINS)
Logic level L
Push-pull type, 4-mA sink
Logic level H
Push-pull type, 4-mA source
0.2
V
VDD – 0.4
V
POWER SUPPLY
VDD
Specified voltage range
VRST
Power-on reset threshold
IQ
Quiescent current [I(VDD1) +
I(VDD2)]
TA = –40°C to 125°C
ICOMP = 0 mA
4.5
5
5.5
1.8
ICOMP = 0 mA, sensor not connected
V
6.8
Brownout voltage level
Brownout indication delay
V
mA
4
V
135
µs
TEMPERATURE RANGE
TJ
Specified range
–40
125
°C
TJ
Operating range
–50
150
°C
(4)
See the Compensation Driver subsection in the Detailed Description section.
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6.6 Typical Characteristics
at TA = 25°C and VDD1 = VDD2 = 5 V with external 100-kHz filter bandwidth, (unless otherwise noted)
100
0.04
60-Hz Line Frequency and Multiples
(measured in a 60-Hz environment)
0.03
M4645M4645-X211
0.01
VN (mV/ÖHz)
IPRIM (A)
0.02
0
M4645-X080
-0.01
Divided Field
Probe Frequency
10
-0.02
-0.03
0.1
-0.04
4.1
4.3
4.5
4.7
4.9
5.1
5.3
5.5
5.7
5.9
0.1
6.1
1
10
100
1k
10k
100k
Frequency (Hz)
VDD (V)
Sensor M4645−X080, RSHUNT = 10 Ω, Mode = Low
Figure 2. DRV401-Q1 Device and Sensor: Output Voltage
Noise Density
Figure 1. DRV401-Q1 Device and Sensor: Offset vs Supply
Voltage
1.20
0.3
T = -50°C
T = 25°C
T = 85°C
T = 125°C
0.1
DRV401-Q1 with M4645-X600 Sensor
DRV401-Q1 with M4645-X211 Sensor
DRV401-Q1 with M4645-X080 Sensor
1.15
1.10
Normalized Gain
Absolute Error (A)
0.2
0
-0.1
1.05
1.00
0.95
0.90
-0.2
0.85
TC (RSHUNT) ±25 ppm/°C
-0.3
-300
0.80
-200
0
-100
100
200
300
100
10
Primary Current (A)
1k
10 k
100 k
1M
Frequency (Hz)
Soldered DWP−20 with 1-in2 copper pad. Measurements by
Vacuumschmelze GmbH.
Figure 4. Gain Flatness vs Frequency
Figure 3. DRV401-Q1 Device and Sensor: Absolute Error
RTO
Over-Range
2000 A/div
2 V/div
VOUT
VOUT
ERROR
Population
Over-Range
ERROR
0
20
40
60
80
100 120
140 160 180 200
Time (ms)
Measurements by Vacuumschmelze GmbH.
Figure 5. 3-A ICOMP Overload Recovery
8
IPRIM
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
30
35
40
45
50
IPRIM
NOTE: IPRIM = 3000 A corresponds to ICOMP = 3 A
Voltage Offset (mV)
Measurements by Vacuumschmelze GmbH.
Figure 6. Differential Amplifier: Voltage Offset Production
Distribution
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Typical Characteristics (continued)
at TA = 25°C and VDD1 = VDD2 = 5 V with external 100-kHz filter bandwidth, (unless otherwise noted)
20
20
16
15
10
8
4
Gain (dB)
Input VOS (mV)
12
Sample Average
0
-4
5
0
-5
-8
-10
-12
-15
-16
-20
-20
-50
0
-25
25
75
50
100
125
10
150
100
1k
10 k
10 M
Figure 7. Differential Amplifier: Offset Voltage vs
Temperature, RTO
Figure 8. Differential Amplifier: Gain vs Frequency
5.0
-40°C
PSRR
25°C
4.9
Output Voltage (V)
100
CMRR
80
60
40
125°C
4.8
85°C
4.7
0.3
85°C
125°C
0.2
20
0.1
0
0
-40°C
25°C
10
100
1k
10 k
100 k
1M2M
0
1
2
4
3
5
6
7
8
9
10
Frequency (Hz)
Load Current (mA)
Figure 9. Differential Amplifier: PSRR and CMRR vs
Frequency
Figure 10. Differential Amplifier: Output Voltage vs Output
Current
25
1000
VOUT Shorted to 5 V
Short-Circuit Current (mA)
20
Noise Density (nV/ÖHz)
1M
Frequency (Hz)
120
PSRR and CMRR (dB)
100 k
Temperature (°C)
100
10
Autozero Frequency = 69 kHz
Sensor Not Running
en = 162 nV/ÖHz
(average over 250 Hz to 50 kHz)
100
1k
10 k
15
10
5
0
-5
-10
-15
-20
VOUT Shorted to 0 V
-25
100 k
1M
-50
-25
0
25
50
75
100
125
150
Temperature (°C)
Frequency (Hz)
Figure 11. Differential Amplifier: Output Noise Density
Figure 12. Differential Amplifier: Short-Circuit Current vs
Temperature
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Typical Characteristics (continued)
3.8
3.8
3.6
3.6
3.4
3.4
3.2
3.2
3.0
3.0
Voltage (V)
Voltage (V)
at TA = 25°C and VDD1 = VDD2 = 5 V with external 100-kHz filter bandwidth, (unless otherwise noted)
2.8
2.6
2.4
2.2
2.8
2.6
2.4
2.2
2.0
2.0
1.8
1.8
1.6
1.6
1.4
1.4
1 ms/div
1 ms/div
TA = −50°C
TA = 25°C
Figure 13. Differential Amplifier: Large-Signal Step
Response
3.5
3.6
3.4
3.4
3.3
Over-Range Delay (ms)
3.8
3.2
Voltage (V)
Figure 14. Differential Amplifier: Large-Signal Step
Response
3.0
2.8
2.6
2.4
2.2
2.0
3.2
Negative Over-Range
3.1
3.0
2.9
Positive Over-Range
2.8
2.7
1.8
2.6
1.6
2.5
1.4
At 5.0 V
VIN Step 0 V to ±1 V
-50
-25
0
25
1 ms/div
50
75
100
125
150
Temperature (°C)
TA = 150°C
Figure 15. Differential Amplifier: Large-Signal Step
Response
7.5
Figure 16. Differential Amplifier: Overrange Delay vs
Temperature
-6.5
At 5.0 V
At 5.0 V
-6.6
7.3
-6.7
7.2
-6.8
Slew Rate (V/ms)
Slew Rate (V/ms)
7.4
7.1
7.0
6.9
6.8
6.7
-6.9
-7.0
-7.1
-7.2
-7.3
6.6
-7.4
6.5
-7.5
-50
-25
0
25
50
75
100
125
150
-50
Temperature (°C)
0
25
50
75
100
125
150
Temperature (°C)
Figure 17. Differential Amplifier: Positive Slew Rate vs
Temperature
10
-25
Figure 18. Differential Amplifier: Negative Slew Rate vs
Temperature
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Typical Characteristics (continued)
50.250
RREFIN (kW)
50.125
50.000
49.875
49.750
49.625
-50
-25
0
25
50
75
100
125
150
Gain VPWMAVERAGE / (VICOMP1, VICOMP2) (dB)
at TA = 25°C and VDD1 = VDD2 = 5 V with external 100-kHz filter bandwidth, (unless otherwise noted)
70
60
50
Pin Gain = Low
40
Pin Gain = High
30
20
10
0
100
Temperature (°C)
10 k
100 k
Frequency (Hz)
Figure 19. Differential Amplifier: REFIN Resistance vs
Temperature
Figure 20. Compensation Loop: Small-Signal Gain
2000
VICOMP1 - VICOMP2 = 4.2 V
ILOAD = 210 mA
Gain Pin Low
1500
1000
Population
Duty Cycle Error (ppm)
1k
500
0
At 250 kHz, 5.0 V
-500
-1000
At 400 kHz, 5.0 V
-1500
-50
-25
0
25
50
75
100
125
-200
-180
-160
-140
-120
-100
-80
-60
-40
-20
0
20
40
60
80
100
120
140
160
180
200
-2000
150
Temperature (°C)
Gain (ppm/V)
Figure 21. Compensation Loop: Duty Cycle Error vs
Temperature
4.75
125°C
Output Swing (V)
4.50
-50°C
25°C
4.25
4.00
1.00
0.75
0.50
125°C
0.25
25°C
-50°C
0
0
50
100
150
200
250
300
Probe Comparator Threshold Current (mA)
5.00
Figure 22. Compensation Loop: DC Gain: Duty Cycle Error
Change
35.0
32.5
30.0
27.5
25.0
-50
-25
0
25
50
75
100
125
150
Temperature (°C)
Output Current (mA)
Figure 23. ICOMP Output Swing to Rail vs Output Current
Figure 24. Probe Comparator Threshold Current vs
Temperature
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Typical Characteristics (continued)
at TA = 25°C and VDD1 = VDD2 = 5 V with external 100-kHz filter bandwidth, (unless otherwise noted)
0.10
90
Output Impedance Mismatch (W)
85
80
Resistance (W)
Driver L
75
70
65
60
Driver H
55
50
0.08
0.06
0.04
0.02
0
45
-50
0
-25
25
75
50
100
125
150
-50
-25
0
25
50
75
100
125
150
Temperature (°C)
Temperature (°C)
Figure 25. Probe Driver: Internal Resistor vs Temperature
Figure 26. Output Impedance Mismatch of IS1 and IS2 vs
Temperature
2.5010
2.5008
2.5006
Population
VREF (V)
2.5004
2.5002
2.5000
2.4998
2.4996
2.4994
2.4992
-6
-4
-2
0
2
4
2.4950
2.4955
2.4960
2.4965
2.4970
2.4975
2.4980
2.4985
2.4990
2.4995
2.5000
2.5005
2.5010
2.5015
2.5020
2.5025
2.5030
2.5035
2.5040
2.5045
2.5050
2.4990
6
ILOAD (mA)
VREF (V)
Figure 28. Voltage Reference Production Distribution
Figure 27. Voltage Reference vs Load Current
2.525
2.520
2.515
VREF (V)
Population
2.510
2.505
2.500
2.495
2.490
2.485
0
2.5
5.0
7.5
10.0
12.5
15.0
17.5
20.0
22.5
25.0
27.5
30.0
32.5
35.0
37.5
40.0
42.5
45.0
47.5
50.0
2.480
2.475
-50
Figure 29. Voltage Reference Drift Production Distribution
12
-25
0
25
50
75
100
125
150
Temperature (°C)
Voltage Reference Drift (ppm/°C)
Figure 30. Voltage Reference vs Temperature
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Typical Characteristics (continued)
250
253
256
259
262
265
268
271
274
277
280
283
286
289
292
295
298
301
304
307
310
200
150
175
100
125
50
75
0
25
-50
-25
-75
-100
-150
-125
-175
-200
Population
Population
at TA = 25°C and VDD1 = VDD2 = 5 V with external 100-kHz filter bandwidth, (unless otherwise noted)
PSR (mV/V)
Minimum Probe Loop Half-Cycle (ns)
Figure 31. Voltage Reference Power-Supply Rejection
Production Distribution
Figure 32. Oscillator Production Distribution <
310
Minimum Probe Loop Half-Cycle (ns)
Minimum Probe Loop Half-Cycle (ns)
310
305
300
295
290
285
280
275
270
265
260
255
250
305
300
295
290
285
280
275
270
265
260
255
250
-50
-25
0
25
50
75
100
125
150
4.3
4.6
4.9
Temperature (°C)
5.2
5.5
5.8
6.0
VDD (V)
Figure 33. Oscillator vs Temperature
Figure 34. Oscillator vs Supply Voltage
4.20
Brown-Out Voltage (V)
4.15
4.10
4.05
4.00
3.95
3.90
3.85
3.80
-50
-25
0
25
50
75
100
125
150
Temperature (°C)
Figure 35. Brownout Voltage vs Temperature
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7 Detailed Description
7.1 Overview
Closed-loop current sensors measure current over wide frequency ranges, including dc. These types of devices
offer a contact-free method, as well as excellent galvanic isolation performance combined with high resolution,
accuracy, and reliability. The DRV401-Q1 is a complete sensor signal conditioning circuit that directly connects to
the current sensor, providing all necessary functions for the sensor operation.
7.2 Functional Block Diagram
Compensation
RS
ICOMP1
ICOMP2
Compensation Winding
Primary Winding
DRV401-Q1
Diff
Amp
Magnetic Core
Field Probe
IS2
IP
VOUT
REFIN
IS1
Probe
Interface
Integrator
Filter
Timing, Error Detection,
and Power Control
H-Bridge
Driver
Degauss
VREF
VREF
5 V GND
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7.3 Feature Description
The DRV401-Q1 operates from a single 5-V supply. The DRV401-Q1 is a complete sensor signal conditioning
circuit that directly connects to the current sensor, providing all necessary functions for the sensor operation. The
DRV401-Q1 device provides magnetic field probe excitation, signal conditioning, and compensation coil driver
amplification. In addition, the device detects error conditions and handles overload situations. A precise
differential amplifier allows translation of the compensation current into an output voltage using a small shunt
resistor. A buffered voltage reference is used for comparator, analog-to-digital converter (ADC), or bipolar zero
reference voltages.
Dynamic error correction ensures high dc precision over temperature and long-term accuracy. The DRV401-Q1
uses analog signal conditioning, and the internal loop filter and integrator are switched capacitor-based circuits.
Therefore, the DRV401-Q1 device allows combination with high-precision sensors for exceptional accuracy and
resolution.
A demagnetization cycle initiates on demand or on power-up. The cycle reduces offset and restores high
performance after a strong overload condition. An internal clock and counter logic generate the degauss function.
The same clock controls power-up, overload detection and recovery, error, and time-out conditions.
The DRV401-Q1 device is built on a highly reliable CMOS process. Unique protection cells at critical connections
enable the design to handle inductive energy.
7.3.1 Magnetic Probe (Sensor) Interface
The magnetic field probe consists of an inductor wound on a soft magnetic core. The probe is connected
between pins IS1 and IS2 of the probe driver that applies approximately 5 V (the supply voltage) through
resistors across the probe coil, as shown in Figure 36.
Typically, the probe core reaches saturation at a current of 28 mA, as shown in Figure 36. The comparator is
connected to VREF by approximately 0.5 V. A current comparator detects the saturation and inverts the excitation
voltage polarity, causing the probe circuit to oscillate in a frequency range of 250 kHz to 550 kHz. The oscillating
frequency is a function of the magnetic properties of the probe core and the coil.
VDD1
Probe
55 W
55 W
IS2
IS1
18 W
CMP
PWM
VREF = 0.5 V
NOTE: MOS components function as switches only.
Copyright © 2016, Texas Instruments Incorporated
The probe is connected between S1 and S2.
Figure 36. Magnetic Probe, Hysteresis, and Duty Cycle: Simplified Probe Circuit
The current rise rate is a function of the coil inductance: dI = L × V × dT. However, the inductance of the field
probe is low while the core material is in saturation (the horizontal part of the hysteresis curve) and is high at the
vertical part of the hysteresis curve. The resulting inductance and the series resistance determine the output
voltage and current versus time performance characteristic.
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Feature Description (continued)
Without external magnetic influence, the duty cycle is exactly 50% because of the inherent symmetry of the
magnetic hysteresis; the probe inductor is driven from −B saturation through the high inductance range to +B
saturation and back again in a time-symmetric manner, as shown in Figure 37.
B
2 V/div
V (IS1)
500 mV/div
H
V (PWM)/10
500 ns/div
Without an external magnetic field, the hysteresis curve is symmetrical and the probe loop generates 50% duty cycle.
Figure 37. Magnetic Probe, Hysteresis, and Duty Cycle: No External Magnetic Field
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Feature Description (continued)
If the core material is magnetized in one direction, a long and a short charge time result because the probe
current through the inductors generates a field that subtracts or adds to the flux in the probe core, driving the
probe core out of saturation or further into saturation, as shown in Figure 38. The current into the probe is limited
by the voltage drops across the probe driver resistors.
B
2 V/div
V (IS1)
500 mV/div
H
V (PWM)/10
500 ns/div
An external magnetic flux (H) generated from the primary current (IPRIM) shifts the hysteresis curve of the magnetic
field probe in the H-axis and the probe loop generates a nonsymmetrical duty cycle.
Figure 38. Magnetic Probe, Hysteresis, and Duty Cycle With External Magnetic Field
The DRV401-Q1 device continuously monitors the logic magnetic flux polarity state. In the case of distortion
noise and excessive overload that can fully saturate the probe, the overload control circuit recovers the probe
loop. During an overload condition, the probe oscillation frequency increases to approximately 1.6 MHz until
limited by the internal timing control.
In an overload condition, the compensation current (ICOMP) driver cannot deliver enough current into the sensor
secondary winding, so the magnetic flux in the sensor main core becomes uncompensated.
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Feature Description (continued)
The transition from normal operation to overload happens slowly because the inherent sensor transformer
characteristics induce the initial primary current step, as shown in Figure 39. As the transformer-induced
secondary current starts to decay, the compensation feedback driver increases the output voltage to maintain the
sensor core flux compensation at zero.
V(1 W ´ IPRIM/10)
1
ICOMP1
3
4
Sensor: 4 x 100
RSH = 10 W
Step Response
2 kHz In
V(Gain) = Low
ICOMP2
Channel 1: 2 V/div
Channels 2 through 4: 500 mV/div
2
VOUT
50 ms/div
A current pulse of 0 A to 18 A (channel 1) generates the two ICOMP signals (channel 3 and channel 4). Channel 2
shows the resulting output signal (VOUT). This test uses the M4645-X030 sensor with no bandwidth limitation, and a
20-sample average.
Figure 39. Primary Current Step Response
When the system compensation loop reaches the driving limit, the rising magnetic flux causes one of the probe
pulse-width modulator (PWM) half-periods to become shorter. The minimum half-period of the probe oscillation is
limited by the internal timing to 280 ns, based on the properties of the VAC magnetic sensors. After three
consecutive cycles of the same half-period being shorter than 280 ns, the DRV401-Q1 device enters overloadlatch mode. The device stores the ICOMP driver output signal polarity and continues producing the skewed-duty
cycle PWM signal. This action prevents the loss of compensation signal polarity information during strong
overloads. In this case, both PWM half-periods are short and approximately equal, because the field probe stays
completely in one of the saturated regions.
The overload-latch condition is removed after the primary current goes low enough for the ICOMP driver to
compensate, and both half-periods of the probe driver oscillation become longer than 280 ns (the field probe
comes out of the saturated region).
Peak voltages and currents generate during normal operations and overload conditions. Both probe connection
pins are internally protected against coupled energy from the magnetic core. Wiring between probe and device
inputs must be short and guarded against interference, as shown in the Layout Guidelines section.
For reliable operation, error detection circuits monitor the probe operation:
1. If the probe driver comparator (CMP) output stays low longer than 32 μs, the ERROR flag asserts active, and
the compensation current (ICOMP) is set to zero.
2. If the probe driver period is less than 275 ns on three consecutive pulses, the ERROR flag asserts active.
See the Error Conditions section for more details.
7.3.2 PWM Processing
The PWM and PWM outputs represent the probe output signal as a differential PWM signal. The signal drives
external circuitry and is used for synchronous ripple reduction. The PWM signal from the probe excitation and
sense stage is internally connected to a high-performance, switched-capacitor integrator followed by an
integrating-differentiating filter. The filter converts the PWM signal into a filtered delta signal and prepares the
PWM signal to drive the analog compensation coil driver. The gain roll-off frequency of the filter stage provides
high dc gain and loop stability. If additional gain is added from external circuitry, the internal gain is reduced by 8
dB, which asserts the GAIN pin high, as shown in the External Compensation Coil Driver section.
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Feature Description (continued)
7.3.3 Compensation Driver
The compensation coil driver provides the driving current for the compensation coil. A fully-differential driver
stage offers high signal voltages to overcome the wire resistance of the coil with a 5-V supply. The compensation
coil is connected between ICOMP1 and ICOMP2, generating an analog voltage across the coil (shown in Figure 39)
that turns into current from the wire resistance (and eventually from the inductance). The compensation current
represents the primary current transformed by the turns ratio. A shunt resistor is connected in this loop and the
high-precision difference amplifier translates the voltage from the shunt to an output voltage.
Both compensation driver outputs provide low impedance over a wide frequency range to ensure smooth
transitions between the closed-loop compensation frequency range and the high-frequency range, where the
primary winding directly couples the primary current into the compensation coil at a rate set by the winding ratio.
The two compensation driver outputs are designed with protection circuitry to handle inductive energy. However,
additional external protection diodes may be necessary for high-current sensors.
For reliable operation, a wire break in the compensation circuit can be detected. If the feedback loop is broken,
the integrating filter drives the ICOMP1 and ICOMP2 outputs to the opposite rails. With one of these pins coming
within 300 mV to ground, a comparator tests for a minimum current flowing between ICOMP1 and ICOMP2. If the
current stays below the threshold current level for a minimum of 100 μs, the ERROR pin is asserted active (low).
The threshold current level for the test is less than 57 mA at 25°C and 65 mA at −40°C if the ICOMP pins are fully
railed, as shown in the Typical Characteristics section.
For sensors with high winding resistance (compensation coil resistance + RSHUNT) or that are connected to an
external compensation driver, this function must be disabled by pulling the CCdiag pin low, as shown in
Equation 1:
VOUT
RMAX =
65 mA
where:
•
•
VOUT equals the peak voltage between ICOMP1 and ICOMP2 at a 65-mA drive current; and
RMAX equals the sum of the coil and the shunt resistance
(1)
7.3.4 External Compensation Coil Driver
An external driver for the compensation coil connects to the ICOMP1 and ICOMP2 outputs. To prevent a wire break
indication, CCdiag must be asserted low.
An external driver provides a higher drive voltage and more drive current. The driver moves the power dissipation
to the external transistors, thereby allowing a higher winding resistance in the compensation coil and more
current. Figure 40 shows a block diagram of an external compensation coil driver. To drive the buffer, one or
both of the ICOMP outputs may be used. Note, however, that the additional voltage gain can cause instability of
the loop. Therefore, the internal gain may be reduced by approximately 8 dB by asserting the GAIN pin high.
RSHUNT is connected to GND to allow for a single-ended external compensation driver. The differential amplifier
continues to sense the voltage, and is used for the gain and over-range comparator or ERROR flag.
V+
DRV401-Q1
ICOMP1
External
Buffer
Compensation
Coil
ICOMP2
V-
RSHUNT
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Figure 40. DRV401-Q1 with External Compensation Coil Driver and RSHUNT Connected to GND
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Feature Description (continued)
7.3.5 Shunt Sense Amplifier
The differential (H-bridge) driver arrangement for the compensation coil requires a differential sense amplifier for
the shunt voltage. This differential amplifier offers wide bandwidth and a high slew rate for fast current sensors.
Excellent dc stability and accuracy result from an auto-zero technique. The voltage gain is 4 V/V, set by precisely
matched and stable internal SiCr resistors.
7.3.6 Over-Range Comparator
High peak current can overload the differential amplifier connected to the shunt. The OVER-RANGE pin, an
open-drain output, indicates an over-voltage condition for the differential amplifier by pulling low. The output of
this flag is suppressed for 3 μs, preventing unwanted triggering from transients and noise. This pin returns to high
when the overload condition is removed (an external pull-up is required to return the pin high).
This ERROR flag provides a warning about a signal clipping condition, but is also a window comparator output
for actively shutting off circuits in the system. The value of the shunt resistor defines the operating window for the
current. The value of the shunt resistor sets the ratio between the nominal signal and the trip level of the overrange flag. The trip current of this window comparator is calculated using the following example:
With a 5-V supply, the output voltage swing is approximately ±2.45 V (load and supply voltage-dependent).
The gain of 4 V/V allows an input swing of ±0.6125 V.
Thus, the clipping current is IMAX = 0.6125 V / RSHUNT.
See Figure 10.
The over-range condition is internally detected when the amplifier exceeds the linear operating range, not merely
as a set voltage level. Therefore, the error or the over-range comparator level is reliably indicated in fault
conditions such as output shorts, low load or low supply conditions. The flag is activated when the output cannot
drive the voltage higher. The configuration is a safety improvement over a voltage level comparator.
NOTE
The internal resistance of the compensation coil may prevent high compensation current
from flowing because of ICOMP driver overload. Therefore, the differential amplifier may not
overload with this current. However, a fast rate of change of the primary current would be
transmitted through transformer action and safely trigger the overload flag.
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7.3.7 Voltage Reference
The precision 2.5-V reference circuit offers low drift (typically 10 ppm/K), used for internal biasing, and connects
to the REFOUT pin. The circuit is intended as the reference point of the output signal to allow a bipolar signal
around it. The output is buffered for low impedance and tolerates sink and source currents of ±5 mA. Capacitive
loads may be directly connected, but generate ringing on fast load transients. A small series resistor of a few
ohms improves the response, especially for a capacitive load in the range of 1 μF. Figure 41 illustrates this circuit
configuration and the transient load regulation with 1-nF direct load.
The reference source is part of the integrated circuit and referenced to GND2. Large current pulses driving the
compensation coil generates a voltage drop in the GND connection that may add on to the reference voltage.
Therefore, a low impedance GND layout is critical to handle the currents and the high bandwidth of the device.
Test Circuit:
1 nF
±5 V
10 mV/div
10 kW
REFOUT
+2.5 V
2.5 ms/div
Figure 41. Pulse Response: Test Circuit and Scope Shot of Reference
7.3.8 Demagnetization
Iron cores are not immune to residual (remanence) magnetism. The residual remanence produces a signal offset
error, especially after strong current overload, which goes along with high magnetic field density. Therefore, the
DRV401-Q1 device includes a signal generator for a demagnetization cycle. The digital control pin, DEMAG,
starts the cycle on demand after the pin is held high for at least 25.6 μs. Shorter pulses are ignored. The cycle
lasts for approximately 110 ms. During this time, the ERROR flag is asserted low to indicate that the output is not
valid. When DEMAG is high during power-on, a demagnetization cycle immediately initiates (12 μs) after poweron (VDD > 4 V). Holding DEMAG low avoids this cycle at power-up. See the Power-On and Brownout section for
more information.
The probe circuit is in normal operation and oscillates during the demagnetization cycle. The PWM and PWM
outputs are active accordingly.
A demagnetization cycle can be aborted by pulling DEMAG low, filtered by 25 μs to ignore glitches, as shown in
Figure 46. In a typical circuit, the DEMAG pin may be connected to the positive supply, which enables a degauss
cycle every time the unit is powered on.
The degauss cycle is based on an internal clock and counter logic. The maximum current is limited by the
resistance of the connected coil in series with the shunt resistor. The DEMAG logic input requires a 5-V, CMOScompatible signal.
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Power-On and Brownout
Power-on is detected with the supply voltage going higher than 4 V at VDD1. When DEMAG is high, a degauss
cycle is started, as shown in Figure 46 through Figure 49. During this time the ERROR flag remains low,
indicating the not ready condition. Maintaining DEMAG low prevents this cycle, and the DRV401-Q1 device starts
operation approximately 32 μs after power-up. If no probe error conditions are detected within four full cycles
(that is, the probe half-periods are shorter than 32 μs and longer than 280 ns), the compensation driver starts
and the ERROR pin indicates the ready condition by going high, typically about 42 μs after power-up.
NOTE
An external pull-up resistor is required to pull the ERROR pin high.
Both supply pins (VDD1 and VDD2) must not differ by more than 100 mV for proper device operation. They are
normally connected together or separately filtered as shown in Layout.
The DRV401-Q1 device tests for low supply voltage with a brownout voltage level of 4 V; proper power
conditions must be supplied. Good power-supply and low equivalent series resistance (ESR) bypass capacitors
are required to maintain the supply voltage during the large current pulses that the DRV401-Q1 device drives.
A critical voltage level is derived from the proper operation of the probe driver. The probe interface relies on a
peak current flowing through the probe to trip the comparator. The probe resistance plus the internal resistance
of the driver (see Probe Coil Loop, Internal Resistor parameters in the Electrical Characteristics table) sets the
lower limit for the acceptable supply voltage. Voltage drops lasting less than 31 μs are ignored. The probe error
detection activates the ERROR pin when proper oscillation fails for more than 32 μs.
A low supply voltage condition, or brownout, is detected at 4 V. Short and light voltage drops of less than 100 μs
are ignored, provided the probe circuit continues to operate. If the probe no longer operates, the ERROR pin
goes active. Signal overload recovery is only provided if the probe loop was not discontinued.
A supply drop lasting longer than 100 μs generates power-on reset. A voltage dip down to 1.8 V (for VDD1)
initiates a power-on reset.
7.3.10 Error Conditions
In addition to the overrange flag that indicates signal clipping in the output amplifier (differential amplifier), a
system error flag is provided. The ERROR flag indicates conditions when the output voltage does not represent
the primary current. The ERROR flag is active during a demagnetization cycle, power-fail, or brownout. The
ERROR flag becomes active with an open or short-circuit in the probe loop. When the error condition is no longer
present and the circuit returns to normal operation, the flag resets.
The ERROR and overrange flags are open-drain logic outputs. The flags connect together for a wired-OR and
require an external pull-up resistor for proper operation.
The following conditions result in ERROR flag activation (ERROR asserts low):
1. The probe comparator stays low for more than 32 μs. This condition occurs if the probe coil connection is
open or if the supply voltage dips to the level where the required saturation current cannot be reached.
During the 32-μs timeout, the ICOMP driver remains active but goes inactive thereafter. In case of recovery,
ERROR is low and the ICOMP driver remains in reset for another 3.3 ms.
2. The probe driver pulse-width is less than 280 ns for three consecutive periods. This condition indicates a
shorted field probe coil or a fully-saturated sensor at start-up. If this condition persists longer than 25 μs and
then recovers, the ERROR flag remains low and ICOMP is in reset for another 3.3 ms. If the condition lasts
less than 25 μs, the ERROR flag recovers immediately and the ICOMP driver is not interrupted.
3. During demagnetization, if the cycle is aborted early by pulling DEMAG low, the ERROR flag stays low for
another 3.3 ms (ICOMP is disabled during this time).
4. An open compensation coil is detected (longer than 100 μs). This condition indicates that not enough current
is flowing in the ICOMP driver output; this condition may be the result of a high-resistance compensation coil or
the connection of an external driver. Detection of this condition can be disabled by setting the CCdiag pin
low.
22
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NOTE
The probe driver, the PWM signal filter, and the ICOMP driver continue to function in normal
mode. Only the ERROR flag is asserted in the case when an open compensation coil is
detected.
5. At power-on after VDD1 crosses the 4-V threshold, the ERROR flag is low for approximately 42 μs.
6. A supply voltage low (brownout) condition lasts longer than 100 μs. Recovery is the same as power-up, with
or without a demagnetization cycle.
7.3.11 Protection Recommendations
The IAIN1 and IAIN2 inputs require external protection to limit the voltage swing beyond 10 V of the supply voltage.
The driver outputs ICOMP1 and ICOMP2 handles high current pulses protected by internal clamp circuits to the
supply voltage. If repeated overcurrents of large magnitudes are expected, connect external Schottky diodes to
the supply rails. This external protection prevents current flowing into the die.
The IS1 and IS2 probe connections are protected with diode clamps to the supply rails. In normal applications,
no external protection is required. The maximum current must be limited to ±75 mA.
All other pins offer standard protection. See the Absolute Maximum Ratings table for more information.
7.4 Device Functional Modes
The DRV401-Q1 has a single functional mode and is operational when the power supply voltages, VDD1 and
VDD2, are between 4.5 V and 5.5 V. For unusual operating conditions where a brownout condition may occur the
DRV401-Q1 may perform a power-on reset. See the Power-On and Brownout section for a complete description
of operation during a brownout.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Functional Principle of Closed-Loop Current Sensors with Magnetic Probe Using the DRV401-Q1
Device
Closed-loop current sensors measure current over wide frequency ranges, including dc. These types of devices
offer a contact-free method and an excellent galvanic isolation performance combined with high resolution,
accuracy, and reliability.
At dc and in low-frequency ranges, the magnetic field induced from the current in the primary winding is
compensated by a current flowing through a compensation winding. A magnetic field probe, located in the
magnetic core loop, detects the magnetic flux. This probe delivers the signal to the amplifier that drives the
current through the compensation coil, bringing the magnetic flux back to zero. This compensation current is
proportional to the primary current, relative to the winding ratio.
In higher-frequency ranges, the compensation winding acts as the secondary winding in the current transformer,
while the H-bridge compensation driver is rolled off and provides low output impedance.
A difference amplifier senses the voltage across a small shunt resistor that is connected to the compensation
loop. This difference amplifier generates the output voltage that is referenced to REFIN and is proportional to the
primary current. The Functional Block Diagram shows the DRV401-Q1 device used as a compensation current
sensor.
24
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Application Information (continued)
8.1.2 Basic Connection
The circuit shown in Figure 42 offers an example of a fully-connected current sensor system.
IP
Primary Winding
Current Sensor Module
Probe
Core
Main Core
Probe Coil
S1
Compensation Coil
S2
K1
K2
+5 V
IS2
ICOMP
R3
R4
C4
D1
C3
R2
D2
R1
+5 V
IS1
IS2
PWM
GAIN
PWM
ICOMP1
CCdiag
ICOMP2
(PWM is in
phase with IS1)
+5 V
VDD1
C2
IAIN2
IAIN1
Amp
V=4
+5 V
R6
Integrator
Probe Coil
Driver and
Comparator
OVER-RANGE
H-Bridge
Driver
VSW
R5
GND1
VOUT
REFIN
VSW
2.5 V
Bandgap
Reference
REFOUT
10 MHz
DEMAG
Logic: Timing, Error Detection, and Demagnetize
Oscillator Reset
Power Valid
DRV401-Q1
R7
VDD2
ERROR
GND2
C4
+5 V
+5 V
Copyright © 2016, Texas Instruments Incorporated
Figure 42. Basic Connection Circuit
The connection example in Figure 42 illustrates the few external components required for optimal performance.
Each component is described in the following list:
• IP is the primary current to be measured; K1 and K2 connect to the compensation coil. S1 and S2 connect to
the magnetic field probe. The dots indicate the winding direction on the sensor main core.
• R1 and R2 form the shunt resistor RSHUNT. This resistance is split into two to allow for adjustments to the
required RSHUNT value. The accuracy and temperature stability of these resistors are part of the final system
performance.
• R3 and R4, together with C3 and C4, form a network that reduces the remaining probe oscillator ripple in the
output signal. The component values depend on the sensor type and are tailored for best results. This
network is not required for normal operation.
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Application Information (continued)
•
•
•
•
R5 is the dummy shunt (RD) resistor used to restore the symmetry of both differential amplifier inputs. R5 = 4
× RSHUNT, but the accuracy is less important.
R6 and R7 are pull-up resistors connected to the logic outputs.
C1 and C2 are decoupling capacitors. Use low ESR-type capacitors connected close to the pins. Use lowimpedance printed circuit board (PCB) traces, either avoiding vias (plated-through holes) or using multiple
vias. A combination of a large (> 1-μF) and a small (< 4.7-nF) capacitor are suggested. When selecting
capacitors, make sure to consider the large pulse currents handled from the DRV401-Q1 device.
D1 and D2 are protection diodes for the differential amplifier input. They are only needed if the voltage drop at
RSHUNT exceeds 10 V at the maximum possible peak current.
8.2 Typical Application
The differential (H-bridge) driver arrangement for the compensation coil requires a differential sense amplifier for
the shunt voltage. This differential amplifier offers wide bandwidth and a high slew rate for fast current sensors.
Excellent dc stability and accuracy result from an auto-zero technique. The voltage gain is 4 V/V, set by precisely
matched and stable internal SiCr resistors.
Both inputs of the differential amplifier are normally connected to the current shunt resistor. The resistor adds to
the internal (10-kΩ) resistor, slightly reducing the gain in this leg. For best common-mode rejection (CMR), a
dummy shunt resistor (R5) is placed in series with the REFIN pin to restore matching of both resistor dividers, as
shown in Figure 43.
DRV401-Q1
Differential Amplifier Section
ICOMP2
R1
10 kW
R2
40 kW
Decoupling, Low-Pass Filter
VOUT
RSHUNT
Differential
Amplifier
R3
10 kW
R4
40 kW
REFIN
RF
50 W
ADC
R5
Dummy
Shunt
CF
10 nF
Compensated
REFIN
K2
Copyright © 2016, Texas Instruments Incorporated
R5 is a dummy shunt resistor equal to 4 × RSHUNT to compensate for RSHUNT and provide optimal CMR.
Figure 43. Internal Difference Amplifier with an Example of a Decoupling Filter
8.2.1 Design Requirements
•
•
•
•
26
Operate from a single 5-V power supply.
Measure the compensation coil current with a gain = 4 V/V.
Maximize the gain accuracy.
Minimize the common-mode error.
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Typical Application (continued)
8.2.2 Detailed Design Procedure
For gains of 4 V/V, Equation 2 shows the calculation:
R2
R 4 + R5
4=
=
R1 RSHUNT + R3
(2)
With R2 / R1 = R4 / R3 = 4; R5 = RSHUNT × 4.
Typically, the gain error resulting from the resistance of RSHUNT is negligible; for 70 dB of common-mode
rejection, however, the match of both divider ratios must be better than 1/3000.
The amplifier output may drive close to the supply rails, and is designed to drive the input of a successiveapproximation resistance (SAR)-type ADC; adding an RC low-pass filter stage between the DRV401-Q1 device
and the ADC is recommended. This filter limits the signal bandwidth and decouples the high-frequency
component of the converter input sampling noise from the amplifier output. For RF and CF values, see the
specific converter recommendations in the specific product data sheet. Empirical evaluation may be necessary to
obtain optimum results.
The output drives 100 pF directly and shows 50% overshoot with approximately 1-nF capacitance. Adding RF
allows much larger capacitive loads, as shown in Figure 44 and Figure 45.
NOTE
Note that with an RF value of only 20 Ω, the load capacitor must be smaller than 1 nF or
larger than 33 nF to avoid overshoot; with an RF value of 50 Ω, this transient area is
avoided.
The reference input (REFIN) is the reference node for the exact output signal (VOUT). Connecting REFIN to the
reference output (REFOUT) results in a live zero reference voltage of 2.5 V. Using the same reference for REFIN
and the ADC avoids mismatch errors that exist between two reference sources.
20 mV/div
20 mV/div
8.2.3 Application Curves
10 ms/div
10 ms/div
R5 = 20 Ω, CD =
100 nF
R5 = 50 Ω, CD = 10
nF
Figure 44. Figure 44 Performance (VOUT)
Figure 45. Figure 45 Performance (VOUT)
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9 Power Supply Recommendations
The DRV401-Q operates from a single power supply, nominally 5 V, and must remain between 4.5 V and 5.5 V
for normal operation. See Figure 46, Figure 47, Figure 48, and Figure 49 for device power-on behavior.
VDD1
5 V/div
V(ERROR)
106 ms
1
4
V(ICOMP2)
RSH = 10 W
2 V/div
2
VOUT
3
20 ms/div
With power-up, the VOUT across the compensation coil centers around half the supply and then starts the cycle after
the 4-V threshold is exceeded. The ERROR flag resets to H after the cycle is completed.
Figure 46. Demagnetization and Power-On Timing: Demagnetization Cycle on Power-Up
VDD1
42 ms
5 V/div
1
V(ERROR)
4
V(IS1)
2 V/div
2
V(ICOMP2)
Initial setting upon
closing of feedback loop.
3
20 ms/div
The probe oscillation V(IS1) starts just before ERROR resets—15 μs after the supply voltage crosses the 4-V
threshold.
Figure 47. Demagnetization and Power-On Timing: Power-Up Without Demagnetization
V(DEMAG)
5 V/div
1
4
106 ms
V(ERROR)
V(ICOMP2)
2
2 V/div
RSH = 10 W
VOUT
3
20 ms/div
Figure 48. Demagnetization and Power-On Timing: Demagnetization Cycle On Command
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5 V/div
V(DEMAG)
1
V(ERROR)
4
V(ICOMP2)
RSH = 10 W
2
2 V/div
3.4 ms
VOUT
3
500 ms/div
The ERROR flag resets to H (as shown) and the output settles back to normal operation.
Figure 49. Demagnetization and Power-On Timing: Abort of Demagnetization Cycle
10 Layout
10.1 Layout Guidelines
The typical device configuration is shown in Figure 42. The DRV401-Q1 operates with relatively large currents
and fast current pulses, and offers wide-bandwidth performance. The device is often exposed to large distortion
energy from the primary signal and the operating environment. Therefore, the wiring layout must provide
shielding and low-impedance connections between critical points.
Use low-ESR capacitors for power-supply decoupling. Use a combination of a small capacitor and a large
capacitor with a 1-μF or larger value. Use low-impedance tracks to connect the capacitors to the pins.
Both grounds must be connected to a local ground plane. Both supplies can be connected together; however,
best results are achieved with separate decoupling (to the local GND plane) and ferrite beads in series with the
main supply. The ferrite beads decouple the DRV401-Q1 device, reducing interaction with other circuits powered
from the same supply voltage source.
The reference output is referred to GND2. A low-impedance, star-type connection is required to avoid the driver
current and the probe current modulating the voltage drop on the ground track.
The connection wires of the difference amplifier to the shunt must be low resistance and of equal length. For best
accuracy, avoid current in this connection. Consider using a Kelvin Contact-type connection. The required
resistance value may be set using two resistors.
Wires and PCB traces for S1 and S2 must be close or twisted. ICOMP1 and ICOMP2 must be wired close together.
To avoid capacitive coupling, run a ground shield between the S1/S2 and ICOMP wire pair or keep them distant
from each other.
The compensation driver outputs (ICOMP) are low frequency only. However, the primary signal (with highfrequency content present) is coupled into the compensation winding, the shunt, and the difference amplifier. TI
recommends a careful layout.
The REFOUT and VOUT output drives some capacitive loads, but avoid large direct capacitive loads; these loads
increase internal pulse currents. Given the wide bandwidth of the differential amplifier, isolate any large
capacitive load with a small series resistor. A small capacitor (in the pF range) improves the transient response
on a high resistive load.
The exposed thermal pad on the bottom of the package must be soldered to GND because the thermal pad is
internally connected to the substrate, which must be connected to the most negative potential. Solder the
exposed pad to the PCB to provide structural integrity and long-term reliability.
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10.2 Layout Example
Probe coil
20 19 18 17
+5V
16
1
15
2
14
Exposed
thermal pad,
connect to
GND1
3
4
13
+5V
12
5
11
6
7
8
9
10
VOUT
Compensation
coil
+5V
Copyright © 2016, Texas
Instruments Incorporated
Figure 50. DRV401-Q1 Layout Example (RGW Package)
10.3 Power Dissipation
Using the thermally-enhanced VQFN package dramatically reduces the thermal impedance from junction to case.
This package is constructed using a down-set lead frame that the die is mounted on. This arrangement results in
the lead frame exposed as a thermal pad on the underside of the package. Because this thermal pad has direct
thermal contact with the die, excellent thermal performance can be achieved by providing a good thermal path
away from the thermal pad.
The two outputs (ICOMP1 and ICOMP2) are linear outputs. Therefore, the power dissipation on each output is
proportional to the current multiplied by the internal voltage drop on the active transistor. For ICOMP1 and ICOMP2,
this internal voltage drop is the voltage drop to VDD2 or GND, according to the current-conducting side of the
output.
Output short-circuits are particularly critical for the driver because the full supply voltage can be seen across the
conducting transistor, and the current is not limited by anything other than the current density limitation of the
FET. Permanent damage to the device may occur.
The DRV401-Q1 does not include temperature protection or thermal shutdown.
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a
free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range
of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain
analysis of SPICE, as well as additional design capabilities.
Available as a free download from the WEBENCH® Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI software
be installed. Download the free TINA-TI software from the TINA-TI folder.
11.1.1.2 TI Precision Designs
TI Precision Designs are analog solutions created by TI’s precision analog applications experts and offer the
theory of operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and
measured performance of many useful circuits. TI Precision Designs are available online at
http://www.ti.com/ww/en/analog/precision-designs/.
11.1.1.3 WEBENCH® Filter Designer
WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The WEBENCH
Filter Designer allows the user to create optimized filter designs using a selection of TI operational amplifiers and
passive components from TI's vendor partners.
Available as a web-based tool from the WEBENCH® Design Center, WEBENCH® Filter Designer allows the
user to design, optimize, and simulate complete multistage active filter solutions within minutes.
11.2 Documentation Support
11.2.1 Related Documentation
The following documents are relevant to using the DRV401-Q1 device, and recommended for reference. All are
available for download at www.ti.com unless otherwise noted.
• PowerPAD Thermally-Enhanced Package (SLMA002)
• Quad Flatpack No-Lead Logic Packages (SCBA017)
• QFN/SON PCB Attachment (SLUA271)
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
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Community Resources (continued)
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
TINA-TI is a trademark of Texas Instruments, Inc and DesignSoft, Inc.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
32
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
12.1 Thermal Pad
Packages with an exposed thermal pad are specifically designed to provide excellent power dissipation, but
board layout greatly influences overall heat dissipation. Table 1 shows the thermal resistance (θJA) for the
package with the exposed thermal pad soldered to a normal PCB, as described in PowerPAD ThermallyEnhanced Package (SLMA002). Refer to EIA/JEDEC Specifications JESD51-0 to 7, QFN/SON PCB Attachment
(SLUA271) and Quad Flatpack No-Lead Logic Packages (SCBA017). These documents are available for
download at www.ti.com.
Table 1. θJA and θJP Estimations According to EIA/JED51-7 (1)
PARAMETER
VQFN
θJP
9
θJA with still air
40
θJA with forced airflow (150 lfm)
38
(1)
θJA = junction-to-ambient thermal resistance.
TI recommends measuring the temperature as close as possible to the thermal pad. The relatively low thermal
impedance, θJP, of less than 10°C/W (with some additional °C/W to the temperature test point on the PCB)
allows good estimation of the junction temperature in the application.
The thermal pad on the PCB must contain nine or more vias for the VQFN package.
Component population, layout of traces, layers, and air flow strongly influence heat dissipation. Worst-case load
conditions must be tested in the actual operating environment to ensure proper thermal conditions. Minimize
thermal stress for proper long-term operation with a junction temperature well below 125°C.
NOTE
All thermal models have an accuracy ≈ 20%.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
DRV401AQRGWRQ1
ACTIVE
VQFN
RGW
20
3000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
DRV
401Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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