DRV411
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SBOS693B – AUGUST 2013 – REVISED DECEMBER 2013
Sensor Signal Conditioning IC for Closed-Loop Magnetic Current Sensors
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FEATURES
DESCRIPTION
•
The DRV411 is designed to condition InSb Hall
elements for use in closed-loop current-sensor
modules. The DRV411 provides precision excitation
circuitry for the Hall-element effectively eliminating
the offset and offset-drift of the Hall element. This
device also provides a 250-mA H-bridge for driving
the sensor compensation coil as well a precision
differential amplifier to generate the output signal.
The 250-mA drive capability of the H-bridge roughly
doubles the current measurement range compared to
conventional single-ended drive methods.
1
23
•
•
•
•
•
•
•
•
Optimized for Symmetric Hall-Elements
(for example, AKM HW-322, HW-302, or similar)
Spinning Current Hall Sensor Excitation
– Elimination of Hall Sensor Offset and Drift
– Elimination of 1/f Noise
Extended Current Measurement Range
– H-Bridge Drive Capability: 250 mA
Precision Difference Amplifier:
– Offset and Drift: 100 µV (max), 2 µV/°C
(max)
– System Bandwidth: 200 kHz
Precision Reference:
– Accuracy: 0.2% (max)
– Drift: 50 ppm/°C (max)
– Pin-Selectable for 2.5 V, 1.65 V, and
Ratiometric Mode
Overrange and Error Flags
Supply: 2.7 V to 5.5 V
Packages: 4-mm × 4-mm QFN and TSSOP-20
PowerPAD™
Temperature Range: –40°C to +125°C
The Hall sensor front-end circuit and the differential
amplifier employ proprietary offset cancelling
techniques. These techniques, along with a highaccuracy voltage reference, significantly improve the
accuracy of the overall current-sensor module. The
output voltage is pin-selectable to support a 2.5-V
output for use with a 5-V power supply, as well as
1.65-V for 3.3-V sensors.
For optimum heat dissipation, the DRV411 is
available in thermally enhanced 4-mm × 4-mm QFN
and TSSOP-20 with PowerPAD packages. The
DRV411 is specified for operation over the full
extended industrial temperature range of –40°C to
+125°C.
APPLICATIONS
•
•
Closed-Loop Current-Sensor Modules
DC and AC Current Measurement
BLOCK DIAGRAM
RSHUNT
VDD ICOMP1
IAIN1
IAIN2
DRV411
Primary Winding
Magnetic Core
Sensor
Excitation
Differential
Amplifier
Hall
Sensor
HALL1
Rotation
Switches
HALL4
Demod
and
Filtering
Class AB
Pre-Driver
Linear
H-Bridge
Driver
VOUT
REFIN
IPRIM
Compensation
Winding
Gain, Compensation,
Excitation Control
GSEL1 GSEL2
ERROR
GND ICOMP2
Overrange
Voltage Reference
2.5V, 1.65V,
Ratiometric
OR
RSEL1 RSEL2
REFOUT
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
DRV411
SBOS693B – AUGUST 2013 – REVISED DECEMBER 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE INFORMATION (1)
(1)
For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or visit
the device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range (unless otherwise noted).
VALUE
MIN
MAX
Supply voltage (VDD to GND)
Input voltage
(2)
Differential amplifier inputs
Input current to input terminals (3)
UNIT
+7
V
GND – 0.5
VDD + 0.5
V
GND – 6
VDD + 6
–25
+25
mA
300
mA
ICOMP short circuit (4)
V
Junction temperature, TJ max
–50
+150
°C
Storage temperature range, Tstg
–65
+150
°C
Human body model (HBM)
JEDEC standard 22, test method A114-C.01
–2000
+2000
V
Charged device model (CDM)
JEDEC standard 22, test method C101
–1000
+1000
V
Machine model (MM)
JEDEC standard 22, test method A115
–150
+150
V
Electrostatic
discharge (ESD)
ratings
(1)
(2)
(3)
(4)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolutemaximum rated conditions for extended periods may affect device reliability.
Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails must
be current limited, except for the differential amplifier input pins.
These inputs are not internally protected against overvoltage. The differential amplifier input pins must be limited to 5 mA (max) or ±1.5
V (max).
Power-limited; observe maximum junction temperature.
THERMAL INFORMATION
DRV411
THERMAL METRIC (1)
PWP (TSSOP)
RGP (QFN)
20 PINS
20 PINS
θJA
Junction-to-ambient thermal resistance
37.2
33.8
θJCtop
Junction-to-case (top) thermal resistance
24.3
34.6
θJB
Junction-to-board thermal resistance
19.8
11.1
ψJT
Junction-to-top characterization parameter
0.7
0.4
ψJB
Junction-to-board characterization parameter
19.6
11.2
θJCbot
Junction-to-case (bottom) thermal resistance
2.0
2.4
(1)
2
UNITS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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SBOS693B – AUGUST 2013 – REVISED DECEMBER 2013
ELECTRICAL CHARACTERISTICS
At TA = +25°C, VDD = +2.7 V to +5.5 V, and zero output current ICOMP, unless otherwise noted.
DRV411
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
HALL ELEMENT EXCITATION / AMPLIFICATION
VEX
Hall sensor excitation voltage
IEX
Hall sensor excitation current
fspin
Excitation switching frequency
AOLFB
TA= –40°C to +125°C, GSEL [00,01,10]
0.7
0.8
0.95
TA= –40°C to +125°C, GSEL [1,1]
0.6
0.74
0.95
TA= –40°C to +125°C
Front-end open-loop flatband gain
V
10
mA
1
MHz
GSEL [0,0] (1), fZero = 3.8 kHz
250
V/V
GSEL [0,1], fZero = 7.2 kHz
250
V/V
GSEL [1,0], fZero = 3.8 kHz
1000
V/V
120
dB
TA= –40°C to +125°C,
GSEL [00,01,10,11]
AOL
Front-end open-loop gain
94
VOS_FE
Front-end voltage offset
dVOS_FE/dT
Front-end voltage offset drift
GBWP
Gain-bandwidth product
GSEL [1,1]
CMRR
Common-mode-rejection ratio
GSEL [1,1], VCM = 0 V to VDD – 1.8 V
No Hall sensor, GSEL [00, 01, 10]
GSEL [1,1]
TA= –40°C to +125°C, no Hall sensor,
GSEL [00,01,10]
TA= –40°C to +125°C, GSEL [1,1]
Error comparator threshold
20
100
µV
5
12
mV
0.2
µV/°C
5
µV/°C
14
MHz
300
µV/V
75
mV
DIFFERENTIAL AMPLIFIER
VOS
Input offset voltage, RTO (2)
(3)
±0.01
±0.1
dVOS/dT
Input offset voltage drift, RTO
TA= –40°C to +125°C
±0.4
±2
µV/°C
CMRR
vs common-mode voltage, RTO
VCM = −1 V to VDD + 1 V, VREF = VDD / 2
±50
±250
µV/V
PSRR
vs power-supply, RTO
VDD = +2.7 V to +5.5 V, VCM = VREFIN
±4
±50
µV/V
VCM
Common-mode input range
VIN1 = VIN2 = VREFIN
–1
Differential impedance
23.5
kΩ
Common-mode impedance
40
50
60
kΩ
External reference input impedance
40
50
60
GERR
Gain error
TA= –40°C to +125°C
±0.02%
±0.3%
±1
±5
Linearity error
RL = 1 kΩ
12
I = +2.5 mA, VDD = 5 V, comparator trip
level
48
Voltage output swing from positive rail
(OR pin trip level)
Short-circuit current (3)
Signal overrange indication delay
(OR pin) (3)
BW–3dB
Bandwidth
SR
Slew rate
(2)
(3)
V/V
TA= –40°C to +125°C
(3)
(3)
kΩ
4
Gain error drift
Voltage output swing from negative rail
(OR pin trip level)
(1)
V
20
Gain, VOUT/VIN_DIFF
en
VDD + 1
16.5
G
ISC
mV
I = –2.5 mA, VDD = 5 V, comparator trip
level
ppm
85
mV
VDD – 48
mV
VOUT connected to GND
–18
mA
VOUT connected to VDD
20
mA
2.5 to 3.5
µs
VIN = 1-V step, see note
(3)
(3)
Settling time large-signal (3)
ΔV = ± 2 V to 1%, no external filter
Settling time (3)
ΔV = ± 0.4 V to 0.01%
Output voltage noise density, RTO (3)
f = 1 kHz, compensation loop disabled
VDD – 85
ppm/°C
2
MHz
6.5
V/µs
0.9
µs
8
170
µs
nV/√Hz
Note that the numbers in the brackets correspond to the GSEL number and its value. For example, in this case, GSEL [0,0] means that
GSEL1 = 0 and GSEL2 = 0.
Parameter value referred to output (RTO).
See Typical Characteristic curves.
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ELECTRICAL CHARACTERISTICS (continued)
At TA = +25°C, VDD = +2.7 V to +5.5 V, and zero output current ICOMP, unless otherwise noted.
DRV411
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TA= –40°C to +125°C,
VICOMP1 – VICOMP2 = 4.2 VPP, VDD = 5 V
210
250
mA
TA= –40°C to +125°C,
VICOMP1 – VICOMP2 = 2.5 VPP, VDD = 3.3 V
125
150
mA
20-Ω load, VDD = 5 V
4.2
20-Ω load, VDD = 3.3 V
2.5
COMPENSATION COIL DRIVER, H-BRIDGE
Peak current
Voltage swing
Output common-mode
VPP
VPP
VDD / 2
V
VOLTAGE REFERENCE
Reference voltage (4)
VREF
PSRR
2.495
2.5
2.505
V
REFSEL [1,0], no load
1.647
1.65
1.653
V
REFSEL [1,1], no load
49.6
50
50.4
% of VDD
Reference voltage drift (4)
TA= –40°C to +125°C, REFSEL [00,10]
±5
±50
ppm/°C
Voltage divider gain error drift
TA= –40°C to +125°C, REFSEL [1,1]
±5
±50
ppm/°C
REFSEL [00,10], RGP package
±15
±200
µV/V
REFSEL [00,10], PWP package
±15
±300
µV/V
Load to GND or VDD,
ΔILOAD = 0 mA to 5 mA
0.15
0.35
mV/mA
Power-supply rejection ratio
(4)
Load regulation
ISC
REFSEL [0,0] (5), no load
Short-circuit current
REFOUT connected to VDD
20
mA
REFOUT connected to GND
–18
mA
DIGITAL INPUT/OUTPUT
Logic Inputs (GSEL, REFSEL pins)
CMOS-type levels
Input leakage current
0.01
µA
VIH
High-level input voltage
0.7 × VDD
VDD + 0.3
V
VIL
Low-level input voltage
–0.3
0.3 × VDD
V
Logic Outputs (ERROR, OR pins)
VOL
Low-level output voltage
VOH
High-level output voltage
4-mA sink
0.3
V
(6)
V
See
POWER SUPPLY
VDD
Specified voltage
2.7
IQ
Quiescent current
TA= –40°C to +125°C, ICOMP = 0 mA, no
excitation
VRST
Power-on reset threshold
TA= –40°C to +125°C
5.5
6
2.4
V
mA
V
TEMPERATURE
(4)
(5)
(6)
4
Specified range
–40
+125
°C
Operating range
–50
+150
°C
See Typical Characteristic curves.
Note that the numbers in the brackets correspond to the REFSEL number and its value. For example, in this case, REFSEL [0,0] means
that REFSEL1 = 0 and REFSEL2 = 0.
OR and ERROR are open-drain outputs. No internal pull-up resistor. Output voltage depends on the external pull up resistor that is
used.
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PIN CONFIGURATION
16
HALL3
REFSEL2
2
15
HALL4
REFSEL1
3
14
ERROR
REFOUT
4
REFIN
5
IAIN2
5
IAIN1
6
GND
7
GND
8
13
GSEL1
ICOMP2
9
12
GSEL2
ICOMP1
10
11
VDD
ERROR
1
16
OR
Exposed
Thermal Pad
on Bottom Side,
Connect to GND
10
HALL2
GND
17
Exposed
Thermal Pad
on Bottom Side,
Connect to GND
HALL4
4
HALL3
VOUT
17
HALL1
18
18
9
3
8
REFIN
GND
OR
IAIN1
19
HALL2
2
19
REFOUT
7
REFSEL2
IAIN2
20
HALL1
1
6
REFSEL1
20
RGP PACKAGE
QFN-20
(TOP VIEW)
VOUT
PWP PACKAGE
TSSOP-20
(TOP VIEW)
15
GSEL1
14
GSEL2
13
VDD
12
ICOMP1
11
ICOMP2
PIN ASSIGNMENTS
PIN
NAME
PWP
(TSSOP)
RGP
(QFN)
ERROR
14
16
Open-drain output for error indication. See the Error Conditions section.
GND
7
9
Ground connection
GND
8
10
Ground connection
GSEL1
13
15
Input. Selects the gain of the Hall amplifier. See Gain Selection and Compensation Frequency section.
GSEL2
12
14
Input. Selects the gain of the Hall amplifier. See Gain Selection and Compensation Frequency section.
HALL1
18
20
Pin 1 of AKM HW322 / HW302 or similar
HALL2
17
19
Pin 2 of AKM HW322 / HW302 or similar
HALL3
16
18
Pin 3 of AKM HW322 / HW302 or similar
HALL4
15
17
Pin 4 of AKM HW322 / HW302 or similar
IAIN1
6
8
Inverting input of differential amplifier
IAIN2
5
7
Noninverting input of differential amplifier
ICOMP1
10
12
Output 1 of compensation coil driver
ICOMP2
9
11
Output 2 of compensation coil driver
OR
19
1
Open-drain output for overrange indication. See the Error Conditions section.
REFIN
3
5
Input for zero reference to differential amplifier
REFOUT
2
4
Output terminal for selected reference voltage
REFSEL1
1
3
Input. Sets reference mode. See the Voltage Reference section.
REFSEL2
20
2
Input. Sets reference mode. See the Voltage Reference section.
VDD
11
13
Supply voltage
VOUT
4
6
Output of differential amplifier
Thermal Pad
DESCRIPTION
Connect to GND
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TYPICAL CHARACTERISTICS
At VDD = 5 V and TA = +25 °C, unless otherwise noted.
5.0
Normalized Gain (ISEC/IPRIM)
1.10
4.0
Voltage (V)
VDD
V(ICOMP1)
3.0
2.0
V(ICOMP2)
1.0
VEX
1.05
1.00
0.95
Core Impedance 50 mH
0.0
0.90
Time (50 µs/div)
10
100
1k
10k
100k
Frequency (Hz)
C036
Figure 1. START-UP BEHAVIOR
C037
Figure 2. FRONT-END GAIN FLATNESS vs FREQUENCY
900
600
500
860
GSEL [00,01,10]
840
Occurrence
Excitation Voltage (mV)
880
820
800
780
400
300
200
760
GSEL [1,1]
740
100
720
700
-30
-10
10
30
50
70
90
0
110 130 150
Temperature (ºC)
750
760
770
780
790
800
810
820
830
840
850
860
870
880
890
900
910
920
-50
C00
Excitation Voltage VEX (mV)
C002
Figure 3. HALL SENSOR EXCITATION VOLTAGE vs
TEMPERATURE
Figure 4. HALL SENSOR EXCITATION VOLTAGE
HISTOGRAM
600
120
550
GSEL [1,0]
500
100
GSEL [0,1]
400
80
350
Gain (dB)
Occurrence
450
300
250
200
60
40
GSEL [0,0]
150
100
20
Excitation Switching Frequency (MHz)
Figure 5. EXCITATION SWITCHING FREQUENCY
HISTOGRAM
6
0
1.035
1.030
1.025
1.020
1.015
1.010
1.005
1.000
0.995
0.990
0.985
0.980
0.975
0
0.970
50
1
10
100
1k
Frequency (Hz)
10k
100k
C007
C00
Figure 6. FRONT-END OPEN-LOOP GAIN vs FREQUENCY
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TYPICAL CHARACTERISTICS (continued)
At VDD = 5 V and TA = +25 °C, unless otherwise noted.
150
500
VDD = 5 V
125
400
350
100
Occurrence
Open-Loop Gain (dB)
VDD = 5.5 V
GSEL [0,0]
450
VDD = 3.3 V
75
300
250
200
150
50
100
Temperature (ºC)
C008
5
30
C04
Figure 8. FRONT-END OFFSET VOLTAGE HISTOGRAM
8
140
VDD = 2.7 V
GSEL [00, 01, 10]
GSEL [0,0]
6
Offset Voltage (µV)
120
100
Occurrence
0
Offset Voltage (µV)
Figure 7. FRONT-END OPEN-LOOP GAIN vs
TEMPERATURE
80
60
40
4
2
GSEL [0,1]
0
-2
-4
0
-6
±0.50
±0.45
±0.40
±0.35
±0.30
±0.25
±0.20
±0.15
±0.10
±0.05
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
20
Offset Voltage Drift (µV/ºC)
GSEL [1,0]
2.5
3.0
3.5
4.0
4.5
5.0
Supply Voltage VDD (V)
5.5
C009
C00
Figure 9. FRONT-END OFFSET VOLTAGE DRIFT
HISTOGRAM
Figure 10. FRONT-END OFFSET VOLTAGE vs POWER
SUPPLY
20
6.0
5.8
15
GSEL [0,0]
5.6
10
Offset Voltage (mV)
Offset Voltage (µV)
25
110 130 150
20
90
15
70
10
50
±5
30
±10
10
±15
-10
±20
-30
±30
0
-50
±25
50
25
GSEL [0,1]
5
0
GSEL [1,0]
-5
5.4
VDD = 5 V
5.2
5.0
4.8
VDD = 3.3 V
4.6
4.4
-10
VDD = 5.5 V
Op-amp Mode
GSEL [1,1]
4.2
-15
4.0
-50
-30
-10
10
30
50
70
90
110 130 150
Temperature (ºC)
-50
Figure 11. FRONT-END OFFSET VOLTAGE vs
TEMPERATURE
-30
-10
10
30
50
70
90
110 130 150
Temperature (ºC)
C011
C010
Figure 12. FRONT-END OFFSET VOLTAGE vs
TEMPERATURE (OP-AMP MODE)
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TYPICAL CHARACTERISTICS (continued)
At VDD = 5 V and TA = +25 °C, unless otherwise noted.
5.5
±2.5
25ºC
VDD = 5 V
±3.0
±3.5
-40ºC
VDD = 3.3 V
±4.0
V(ICOMP1 - ICOMP2) (V)
150ºC
±4.5
±5.0
±5.5
0.00
0.05
-40ºC
25ºC
VDD = 5 V
0.10
0.15
0.20
0.25
150ºC
4.0
VDD = 3.3 V
3.5
-40ºC
3.0
2.5
0.00
0.30
25ºC
4.5
25ºC
150ºC
- ICOMP (A)
0.05
0.10
0.15
0.20
0.25
0.30
ICOMP (A)
C02
Figure 13. OUTPUT VOLTAGE SWING vs NEGATIVE
OUTPUT CURRENT
C025
Figure 14. OUTPUT VOLTAGE SWING vs POSITIVE
OUTPUT CURRENT
600
1200
TA = 85ºC
VDD = 5.5 V
500
RTO
GSEL [00, 01, 10]
1000
400
800
Occurrence
300
200
600
25
20
15
10
5
0
0
-5
0
-10
200
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
105
110
115
120
125
100
-15
400
-20
Occurrence
-40ºC
5.0
-25
V(ICOMP1 - ICOMP2) (V)
150ºC
Offset Voltage (µV)
Error Comparator Threshold (mV)
C04
Figure 15. ERROR COMPARATOR THRESHOLD
HISTOGRAM
C00
Figure 16. DIFFERENTIAL AMPLIFIER, OFFSET VOLTAGE
HISTOGRAM
100
700
90
600
500
70
Occurrence
60
50
40
CMRR
30
400
300
200
PSRR
20
100
10
0
0
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
-200
-180
-160
-140
-120
-100
-80
-60
-40
-20
0
20
40
60
80
100
120
140
Rejection Ratio (dB)
80
C012
Common-Mode Rejection Ratio (µV/V)
C002
Figure 17. DIFFERENTIAL AMPLIFIER CMRR AND PSRR vs
FREQUENCY
8
Figure 18. DIFFERENTIAL AMPLIFIER COMMON-MODE
REJECTION RATIO HISTOGRAM
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TYPICAL CHARACTERISTICS (continued)
At VDD = 5 V and TA = +25 °C, unless otherwise noted.
50
500
RTO
450
40
30
Offset Voltage (µV)
400
Occurrence
350
300
250
200
150
20
10
0
-10
-20
-30
50
-40
0
-50
±10
±9
±8
±7
±6
±5
±4
±3
±2
±1
0
1
2
3
4
5
6
7
8
9
10
100
2.5
3.0
3.5
4.0
4.5
5.0
Supply Voltage VDD (V)
Power-Supply Rejection Ratio PSRR (µV/V)
5.5
C014
C03
Figure 19. DIFFERENTIAL AMPLIFIER POWER-SUPPLY
REJECTION RATIO HISTOGRAM
Figure 20. DIFFERENTIAL AMPLIFIER OFFSET VOLTAGE vs
POWER SUPPLY
20
52.00
15
10
Gain (dB)
Input Resistance, RIN (k
)
51.75
51.50
5
0
51.25
-5
51.00
-10
-50
-25
0
25
50
75
100
125
150
Temperature (ºC)
10
-0.01
600
-0.02
Gain Error (%)
700
500
400
300
500
400
300
200
-0.08
100
0
0
-0.07
-100
10M
C015
-0.05
100
-200
1M
-0.04
-0.06
-300
100k
-0.03
200
-400
10k
Figure 22. DIFFERENTIAL AMPLIFIER GAIN vs FREQUENCY
0
-500
1k
Frequency (Hz)
800
Gain Error (ppm)
100
C04
Figure 21. DIFFERENTIAL AMPLIFIER REFERENCE INPUT
IMPEDANCE vs TEMPERATURE
Occurrence
CLOAD = 200 pF
-50
-25
0
25
50
75
100
125
Temperature (ºC)
150
C039
C003
Figure 23. DIFFERENTIAL AMPLIFIER GAIN ERROR
HISTOGRAM
Figure 24. DIFFERENTIAL AMPLIFIER GAIN ERROR vs
TEMPERATURE
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TYPICAL CHARACTERISTICS (continued)
At VDD = 5 V and TA = +25 °C, unless otherwise noted.
5.00
0.30
-40ºC
4.95
0.25
Output Voltage (V)
Output Voltage (V)
150ºC
25ºC
4.90
4.85
4.80
0.10
0.05
150ºC
4.70
1
2
3
4
5
6
7
Load Current (mA)
8
9
10
0
1
2
3
4
5
6
7
8
9
Load Current (mA)
C016
Figure 25. DIFFERENTIAL AMPLIFIER OUTPUT VOLTAGE
vs OUTPUT CURRENT (POSITIVE RAIL)
10
C017
Figure 26. DIFFERENTIAL AMPLIFIER OUTPUT VOLTAGE
vs OUTPUT CURRENT (NEGATIVE RAIL)
22.0
22
18.0
18
VDD = 5.5 V
VDD = 2.7 V
10
6
2
-2
-6
VDD = 2.7 V
-10
to GND
VDD = 5.5 V
-14
to VDD
14.0
to VDD
Current ISC (mA)
14
Current ISC (mA)
-40ºC
0.00
0
10.0
6.0
2.0
±2.0
±6.0
±10.0
±14.0
-18
to GND
±18.0
-22
-50
-25
0
25
50
75
100
125
Temperature (ºC)
±22.0
150
2.5
0.08
0.06
Overrange Threshold (V)
0.06
Positive Threshold
0.02
0.00
±0.02
Negative Threshold
±0.06
±0.08
0.04
±0.10
4.5
5.0
5.5
C05
Positive Threshold
0.02
0.00
±0.02
Negative Threshold
±0.04
±0.06
RLOAD = 1k
4.0
Figure 28. DIFFERENTIAL AMPLIFIER SHORT-CIRCUIT
CURRENT vs POWER SUPPLY
0.08
±0.04
3.5
Supply Voltage VDD (V)
0.10
0.04
3.0
C04
Figure 27. DIFFERENTIAL AMPLIFIER SHORT-CIRCUIT
CURRENT vs TEMPERATURE
Overrange Threshold (V)
0.15
25ºC
4.75
RLOAD = 1 k
±0.08
-50
-30
-10
10
30
50
70
Temperature (ºC)
90
110 130 150
2.5
C018
Figure 29. OVERRANGE TRIP LEVEL vs TEMPERATURE
10
0.20
3.0
3.5
4.0
4.5
Supply Voltage VDD (V)
5.0
5.5
C019
Figure 30. OVERRANGE TRIP LEVEL vs POWER SUPPLY
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TYPICAL CHARACTERISTICS (continued)
At VDD = 5 V and TA = +25 °C, unless otherwise noted.
3.0
3.75
2.5
2.0
Overrange Delay (µs)
3.5
1.5
Negative Overrange
1.0
0.5
Voltage (V)
3.25
3
0.0
±0.5
±1.0
Positive Overrange
±1.5
2.75
VIN
VOUT
±2.0
±2.5
2.5
±3.0
-50
-30
-10
10
30
50
70
90
0.0
110 130 150
Temperature (ºC)
1.3
5.0
1.0
4.5
0.8
4.0
0.5
Voltage (V)
Voltage (V)
1.5
5.5
3.5
3.0
VIN
3.0
4.0
5.0
6.0
Time (µs)
7.0
8.0
0.9
1.0
C021
VIN
VOUT
±1.5
±2.0
0.0
±1.0
1.0
2.0
Time (µs)
C022
3.0
C00
Figure 34. DIFFERENTIAL AMPLIFIER SETTLING TIME
(RISING EDGE)
1.5
100-6
Output Voltage Noise Density (V/¥+])
Figure 33. DIFFERENTIAL AMPLIFIER STEP RESPONSE
1.3
1.0
0.8
Voltage (V)
0.8
±0.8
±1.3
2.0
0.7
0.0
±1.0
1.0
0.6
±0.3
0.5
0.0
0.5
0.3
1.0
0.0
±1.0
0.4
±0.5
VOUT
1.5
0.3
Figure 32. DIFFERENTIAL AMPLIFIER OVERLOAD
RECOVERY
6.0
2.0
0.2
Time (ms)
Figure 31. OVERRANGE DELAY vs TEMPERATURE
2.5
0.1
C020
0.5
VIN
0.3
0.0
±0.3
±0.5
±0.8
VOUT
±1.0
±1.3
±1.5
±2.0
±1.0
0.0
1.0
Time (µs)
2.0
3.0
100-7
Auto-Zero Frequency = 62.5 kHz
Sensor Not Running
en = 162nV/¥+] DYHUDJHRYHU+]WRN+]
100-8
10
Figure 35. DIFFERENTIAL AMPLIFIER SETTLING TIME
(FALLING EDGE)
100
1k
10k
Frequency (Hz)
C04
100k
C023
Figure 36. DIFFERENTIAL AMPLIFIER OUTPUT VOLTAGE
NOISE DENSITY
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TYPICAL CHARACTERISTICS (continued)
At VDD = 5 V and TA = +25 °C, unless otherwise noted.
1400
2.5020
REFSEL [0,0]
REFSEL [0,0]
1200
2.5010
1000
2.5005
Occurrence
2.5000
2.4995
800
600
400
2.4990
ILOAD (mA)
5
C026
2.5030
4
2.5025
3
2.5020
2
2.5015
1
2.5010
0
2.5005
-1
2.5000
-2
2.4995
-3
2.4990
-4
2.4985
0
-5
2.4980
2.4980
2.4975
200
2.4985
2.4970
Reference Voltage, VREF (V)
2.5015
Reference Voltage VREF (V)
Figure 37. 2.5-V REFERENCE OUTPUT VOLTAGE vs LOAD
CURRENT
2.5002
2.5055
2.5050
REFSEL [0,0]
VDD = 2.7 V
Reference Voltage, VREF (V)
2.5045
2.5040
VDD = 5.5 V
2.5035
2.5030
2.5025
2.5020
2.5001
2.5000
2.4999
2.4998
REFSEL [0,0]
2.5015
2.4997
-50
-30
-10
10
30
50
70
90
110 130 150
Temperature (ºC)
2.5
3.0
C028
Figure 39. 2.5-V REFERENCE OUTPUT VOLTAGE vs
TEMPERATURE
3.5
4.0
4.5
Supply Voltage VDD (V)
5.0
C031
1200
1.6522
REFSEL [1,0]
REFSEL [1,0]
1.6517
1000
1.6512
800
Occurrence
1.6507
1.6502
600
400
1.6497
4
5
C027
1.6530
3
1.6525
2
1.6515
ILOAD (mA)
1
1.6510
0
1.6505
±1
1.6500
±2
1.6495
±3
1.6490
±4
1.6485
0
±5
1.6480
1.6492
1.6475
200
1.6470
Reference Voltage, VREF (V)
5.5
Figure 40. 2.5-V REFERENCE OUTPUT VOLTAGE vs
POWER SUPPLY
1.6520
Reference Voltage, VREF (V)
C039
Figure 38. 2.5-V REFERENCE OUTPUT VOLTAGE
HISTOGRAM
Reference Voltage VREF (V)
Figure 41. 1.65-V REFERENCE OUTPUT VOLTAGE vs LOAD
CURRENT
12
C05
Figure 42. 1.65-V REFERENCE OUTPUT VOLTAGE
HISTOGRAM
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TYPICAL CHARACTERISTICS (continued)
At VDD = 5 V and TA = +25 °C, unless otherwise noted.
2.5050
2.5045
VDD = 2.7 V
1.6545
Reference Voltage, VREF (V)
Reference Voltage, VREF (V)
1.6550
1.6540
1.6535
VDD = 5.5 V
1.6530
1.6525
REFSEL [1,0]
1.6520
2.5040
2.5035
2.5030
2.5025
2.5020
Ratiometric Mode
REFSE L [ 1,1]
2.5015
2.5010
-50
-30
-10
10
30
50
70
90
110 130 150
Temperature (ºC)
-50
-30
-10
10
Figure 43. 1.65-V REFERENCE OUTPUT VOLTAGE vs
TEMPERATURE
30
50
70
90
110 130 150
Temperature (ºC)
C028
C028
Figure 44. RATIOMETRIC REFERENCE OUTPUT VOLTAGE
vs TEMPERATURE
5.0
2.6
2.5
4.0
POR Threshold (V)
Supply Current, IDD (mA)
4.5
3.5
3.0
VDD = 5.5 V
2.5
VDD = 5 V
2.0
1.5
VDD = 2.7 V
1.0
Ramp-up
2.4
2.3
Ramp-down
2.2
2.1
0.5
2.0
0.0
-50
-25
0
25
50
75
100
125
150
Temperature (ºC)
-50
Figure 45. SUPPLY CURRENT vs TEMPERATURE
-30
-10
10
30
50
70
90
110 130 150
Temperature (ºC)
C04
C028
Figure 46. POWER-ON-RESET vs TEMPERATURE
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FUNCTIONAL DESCRIPTION
OVERVIEW
The DRV411 is a complete sensor signal conditioning circuit that directly connects to the current sensor,
providing all necessary functions for the sensor operation. The DRV411 operates from a single +2.7-V to +5.5-V
supply, and provides magnetic field probe (Hall sensor) excitation, signal conditioning, and compensation-coil
driver amplification. In addition, this device detects error conditions and handles overload situations. A precise
differential amplifier allows translation of the compensation current into an output voltage using a small shunt
resistor. A buffered voltage reference can be used for comparator, analog-to-digital converter (ADC), or bipolar
zero reference voltages. Dynamic error correction ensures high dc precision over temperature and long-term
accuracy.
The DRV411 uses analog signal conditioning circuitry; the internal loop filter and integrator are switched
capacitor-based circuits. The DRV411 can be combined with high-precision sensors for exceptional accuracy and
resolution. An internal clock and counter logic control power-up, overload detection and recovery, error, and timeout conditions. The DRV411 is built using a highly reliable CMOS process. Unique protection cells at critical
connections enable the design to handle inductive energy.
HALL SENSOR INTERFACE
The DRV411 works best with symmetrical InSb Hall elements, such as the HW322 and HW302 from AKM or
other vendors. Symmetrical Hall elements are Hall elements where input impedance and output impedance are
closely matched. However, hall elements suffer from offset and offset drift across temperature that affects the
accuracy and linearity of the current sensor. The DRV411 contains patented excitation and conditioning circuitry
that significantly reduces offset and offset drift. The excitation circuit regulates the voltage across the hall
element to a maximum voltage of 0.95 V. This voltage is very stable across the full temperature range. The
excitation current varies with temperature in order to keep the hall sensitivity constant. A special current limiting
circuit limits the current delivered to the hall element to a maximum current of 10 mA regardless of the
temperature or the impedance of the hall element.
DYNAMIC OFFSET AND NOISE CANCELLATION USING SPINNING CURRENT METHOD
The DRV411 incorporates dynamic offset cancellation circuitry that helps eliminate offset drift and 1/f noise of the
hall sensor. The excitation current is spun through the hall sensor in orthogonal directions at a fixed clock
frequency using rotation multiplexer switches, as shown in Figure 47 (a) to (d). The excitation source ensures a
constant current during each spin cycle but keeps the sensitivity of the hall sensor independent by varying the
current across temperature for impedance variations from 100 Ω to 2 kΩ. The corresponding Hall output is
averaged across the four orthogonal directions to effectively cancel the Hall offset and the 1/f noise. The DRV411
continuously monitors the offset of the Hall element and triggers an error flag if the offset remains > 50 mV as a
result of any damage to the Hall sensor. Refer to the Error Conditions section for more details.
IEXCIT
VHALL ¤
R2
R1
VHALL +
R2
R1
R2
R1
R2
R1
IEXCIT
IEXCIT
VHALL +
VHALL ¤
VHALL ¤
R4
R4
R3
Hall Sensor
R4
R3
VHALL +
VHALL ¤
IEXCIT
(b)
R4
R3
Hall Sensor
Hall Sensor
Hall Sensor
(a)
B
B
B
B
R3
VHALL +
(d)
(c)
Figure 47. Hall Sensor Current Spinning Method
14
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Low-frequency noise can be a concern for Hall sensors with constant voltage and current excitation. The
dynamic offset cancellation technique eliminates 1/f noise from the Hall sensor. Figure 48 shows the effect of
current spinning on the Hall sensor, referred to primary current noise.
100-2
Primary Current Noise (A/¥+])
Hall Sensor only
100-3
100-4
100-5
100-6
DRV411 + Hall Sensor
100-7
0.1
0
1
10
100
1k
Frequency (Hz)
10k
100k
C04
Figure 48. Effect of Noise Cancellation with Current Spinning
COMPENSATION COIL DRIVER
The compensation coil driver provides the driving current for the compensation coil. A fully differential driver
stage offers the high-signal voltage to overcome the wire resistance of the coil with only a 5-V supply. The
compensation coil is connected between ICOMP1 and ICOMP2, both generating an analog voltage across the
coil (see Figure 51) that turns into current from the wire resistance (and eventually from the inductance). The
compensation current represents the primary current transformed by the turns ratio. A shunt resistor is connected
in this loop and the high precision differential amplifier translates the voltage from this shunt to an output voltage
(see the Functional Principle of Closed-Loop Current Sensors with a Hall Sensor section).
Both compensation driver outputs provide low impedance over a wide frequency range that insures smooth
transition between the closed-loop compensation frequency range and the high-frequency range, where the
primary winding directly couples the primary current into the compensation coil according to the winding ratio
(transformer effect).
The two compensation driver outputs are specially protected to handle inductive energy. However, it might be
necessary to use high-current sensors to add external protection diodes (see the Protection Recommendations
section).
GAIN SELECTION AND COMPENSATION FREQUENCY
Proper selection of the GSEL mode enables the sensor designer to create a sensor with stable gain over a wide
frequency range and excellent loop stability. Modes Gain_1 to Gain_3 allow for different fixed gain and zerofrequency options to be selected according to the requirements of the individual sensor. See Table 1 for more
information. Evaluate Gain_3 mode (GSEL [1,0]) first because it works with most common sensors.
Mode Selection
Gain_1 Mode For use with sensors with compensation coil inductance < 50 mH.
Gain_2 Mode For use with sensors with very small form factor (small core diameter), where the transformer
effect starts to dominate the transfer function at frequencies significantly above 3.8 kHz. Typically the
inductance of the compensation coil would be very small.
Gain_3 Mode Works well with a wide selection of sensors with compensation coil inductance typically ≥ 50 mH.
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Table 1. Gain Setting and Compensation Frequency
MODE
GSEL1
GSEL2
Gain_1
0
0
G = 250 V/V. Compensation frequency set to 3.8 kHz.
DESCRIPTION
Gain_2
0
1
G = 250 V/V. Compensation frequency set to 7.2 kHz.
Gain_3
1
0
G = 1000 V/V. Compensation frequency set to 3.8 kHz.
External gain and compensation
(op-amp mode)
1
1
Current spinning and front-end chopping are turned off. Constant voltage
excitation is enabled. Gain and compensation set by using external
resistors and capacitors, such as in discrete designs.
3.0
3.0
GSEL [0,0]
Step û IPRIM = 10 A
Core Inductance 50 mH
2.9
2.8
2.8
ICOMP1
2.6
2.5
2.4
2.3
2.6
2.5
2.4
ICOMP2
2.3
2.2
2.1
ICOMP1
2.7
VICOMP (V)
VICOMP (V)
2.7
GSEL [0,1]
Step û IPRIM = 10 A
Core Inductance 50 mH
2.9
ICOMP2
2.2
2.1
Time (100 µs/div)
Time (100 µs/div)
C033
Figure 49. Settling of ICOMP1 and ICOMP2
(Mode Gain_1)
C033
Figure 50. Settling of ICOMP1 and ICOMP2
(Mode Gain_2)
3.0
2.9
2.8
ICOMP1
GSEL [1,0]
Step û IPRIM = 10 A
Core Inductance 50 mH
VICOMP (V)
2.7
2.6
2.5
2.4
2.3
ICOMP2
2.2
2.1
Time (100 µs/div)
C033
Figure 51. Settling of ICOMP1 and ICOMP2
(Mode Gain_3)
Along with symmetrical InSb Hall elements, the DRV411 can also be connected to symmetrical GaAs Hall
elements. The advantage of GaAs Hall elements is that they provide an extended temperature range to +125°C.
See the following section, External Gain and Compensation (Op-amp Mode) for more details. This type of Hall
element has a lower sensitivity than InSb-type sensors. In order to compensate for this difference, TI
recommends using gain setting mode Gain_3 with GaAs sensors. If the sensitivity is too low and the loop gain is
insufficient, the loop can become unstable. In op-amp mode, gain can be set with external components.
16
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EXTERNAL GAIN AND COMPENSATION (OP-AMP MODE)
Op-amp mode allows several degrees of freedom for the sensor designer. In op-amp mode, the DRV411
functions like a conventional operation amplifier with high open loop gain (> 100 dB). The internal compensation
is disconnected, so that the sensor gain and compensation can be set externally. The DRV411 still provides a
stable excitation voltage of 0.74 V between terminals HALL1 and HALL3. The outputs of the Hall sensor must be
connected to terminal HALL2 and HALL4. The maximum current is limited to 10 mA to protect the Hall element.
The following list shows some ways to use op-amp mode:
• Op-amp mode can be used in cases where modes Gain_1 to Gain_3 do not lead to an acceptable frequency
response from the sensor module. In this mode, external compensation must be designed in to suit the
sensor requirements (see Figure 57).
• DRV411 can be used with symmetrical GaAs Hall sensors. However, because of the inherently low sensitivity
of GaAs sensors, the internal gain (compensation) may not be sufficient. In such cases, use op-amp mode to
make the system stable with external compensation. In op-amp mode, the excitation circuit provides a
constant 0.74 V across the HALL1 and HALL3 outputs, with HALL3 referred to GND. Connect the Hall
outputs to the HALL2 and HALL4 pins (see Figure 57). For Hall sensors with large input impedances, do not
exceed the common-mode input range of the op-amp inputs (see the Electrical Characteristics section).
• Op-amp mode can also be used for interfacing to nonsymmetrical Hall elements, which are Hall elements
where the input impedance and output impedance are not equal. Different Hall sensor input and output
impedances lead to very large sensor offsets that might be outside the correction range of the DRV411
excitation circuit. In this mode, the ERROR pin is disabled (see the Error Conditions for more details). For
Hall sensors with large input impedances, do not exceed the common-mode input range of the op amp inputs.
• If an external excitation circuit is required for the Hall sensor in op-amp mode, bypass the internal sensor by
ignoring the HALL1 and HALL3 terminals. Connect the Hall sensor outputs to the HALL2 and HALL4
terminals. For Hall sensors with large input impedances, do not exceed the common-mode input range of the
op amp inputs.
SHUNT SENSE AMPLIFIER
The differential (H-bridge) driver arrangement for the compensation coil requires a differential sense amplifier for
the shunt voltage. This differential amplifier offers wide bandwidth and a high slew rate for fast current sensors.
Excellent dc stability and accuracy result from an auto-zero technique. The voltage gain is 4 V/V, set by precisely
matched and stable internal resistors.
For gains of 4 V/V:
R 4 + R5
R
4= 2 =
R1
RSHUNT + R3
where:
•
•
R2 / R1 = R4 / R3 = 4
R5 = RSHUNT × 4
(1)
Both inputs of the differential amplifier are normally connected to the current shunt resistor. This resistor adds to
the internal 10-kΩ resistor, slightly reducing the gain in this signal path. For best common-mode rejection (CMR),
a dummy shunt resistor (R5 = 4 x RSHUNT) is placed in series with the REFIN pin to restore matching of both
resistor dividers; see Figure 52.
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Compensation
Coil
R1
10 k
IAN1
R2
40 k
_
RSHUNT
Differential
Amplifier
R3
10 k
IAIN2
DRV411
+
R4
40 k
RF
500
VOUT
optional
ADC
CF
10 nF
REFIN
REFIN (compensated)
R5
(Dummy Shunt)
ICOMP
Figure 52. Internal Difference Amplifier with Example of a Decoupling Filter
Typically, the gain error resulting from the resistance of RSHUNT is negligible; for 70 dB of common-mode
rejection, however, the match of both divider ratios must be higher than 1/3000.
The amplifier output can drive close to the supply rails, and is designed to drive the input of a SAR-type ADC;
adding an RC low-pass filter stage between the DRV411 and the ADC is recommended. This filter not only limits
the signal bandwidth but also decouples the high-frequency component of the converter input sampling noise
from the amplifier output. For RF and CF values, refer to the specific converter recommendations in the
respective product data sheet. Empirical evaluation may be necessary to obtain optimum results.
The output drives 100 pF directly and shows 50% overshoot with approximately 1-nF capacitance. Adding RF
allows for much larger capacitive loads. Note that with an RF of only 20 Ω, the load capacitor must be either less
than 1 nF or more than 33 nF to avoid overshoot; with an RF of 50 Ω, this transient area is avoided.
The reference input (REFIN) is the reference node for the exact output signal (VOUT). Connecting REFIN to the
reference output (REFOUT) results in a live zero reference voltage that is user-selectable. Use the same
reference for REFIN and the ADC to avoid mismatch errors that exist between the two reference sources.
OVERRANGE COMPARATOR
High peak current can overload the differential amplifier connected to the shunt. The OR pin, an open-drain
output, indicates an overvoltage condition for the differential amplifier by pulling low. The output of this flag is
suppressed for 3 μs, preventing unwanted triggering from transients and noise. This pin returns to high as soon
as the overload condition is removed (an external pull-up is required to return the pin high).
This error flag not only provides a warning about a signal-clipping condition, but is also a window comparator
output for actively shutting off circuits in the system. The value of the shunt resistor defines the operating window
for the current and sets the ratio between the nominal signal and the trip level of the overrange flag. The trip
current of this window comparator is calculated using the following example:
With a 5-V supply, the output voltage swing is approximately ±2.45 V (load and supply voltage-dependent).
The gain of 4 V/V enables an input swing of ±0.6125 V.
Thus, the clipping current is IMAX = 0.6125 V / RSHUNT.
See Figure 13 and Figure 14 in the Typical Characteristics section for details.
The overrange condition is internally detected as soon as the amplifier exceeds its linear operating range, not
just a preset voltage level. Therefore, the error of the overrange comparator level is reliably indicated in fault
conditions such as output shorts, low load, or low-supply conditions. As soon as the output cannot drive the
voltage higher, the flag is activated. This configuration is a safety improvement over a voltage-level comparator.
Note that the internal resistance of the compensation coil may prevent high compensation current from flowing
because of ICOMP driver overload. Therefore, the differential amplifier may not overload with this current.
However, a fast rate of change of the primary current is transmitted through transformer action and safely
triggers the overload flag.
18
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VOLTAGE REFERENCE
The precision reference circuit offers low drift (typically 5 ppm/K) and is used for internal biasing; it is also
connected to the REFOUT pin. The circuit is intended as the reference point of the output signal to allow a
bipolar signal around it. This output is buffered for low impedance and tolerates sink and source currents of ±5
mA. Capacitive loads can be directly connected, but generate ringing on fast load transients. A small series
resistor of a few ohms improves the response, especially for a capacitive load in the range of 1 μF.
Reference Output Voltage Selection
As shown in Table 2, the most common use-cases for the DRV411 are with 5-V and 3.3-V power supplies, where
the sensor output must be centered at 2.5 V and 1.65 V, respectively. The internal reference provides very good
accuracy and drift performance. See the Electrical Characteristics for detailed information.
Table 2. Reference Output Voltage Selection
MODE
REFSEL1
REFSEL2
REF = 2.5 V
0
0
Used with sensor module supply of 5 V
DESCRIPTION
REF = 1.65 V
1
0
Used with sensor module supply of 3.3 V
Ratiometric output
1
1
Provides output centered on VS / 2
In the ratiometric output mode, the reference is bypassed and the power supply is divided by two. The internal
resistor divider offers very tight tolerances and a temperature coefficient of less than 10 ppm/°C. In this case, the
sensor module output is centered on VS / 2.
For sensor modules with a reference pin, the DRV411 also allows overwriting the internal reference with an
external reference voltage, as shown in Figure 53. When an external reference that has a significant voltage
difference compared to the internal reference is connected, resistor R5 limits the current flowing from the internal
reference. In this case, the internal reference sources the current shown in Equation 2:
Vint_ref Vext_ref
Iint_ref =
600 :
(2)
Compensation
Coil
IAIN1
Current Sense Module
VDD
R1
10 k
R2
40 k
DRV411
_
RSHUNT
Differential
Amplifier
IAIN2
R3
10 k
+
VOUT
R4
40 k
R5
REFIN
REFIN
(external)
Dummy Shunt
(optional)
Internal
Voltage
Reference
ICOMP
External
Voltage
Reference
REFOUT
R6
600
GND
Figure 53. DRV411 with External Reference
The example of 600 Ω for R6 was chosen for illustration purposes; different values are possible. Note that if no
external reference is connected, R6 has little impact on the common-mode rejection of the differential amplifier,
and therefore, should be as small as possible.
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POWER-ON STARTUP AND BROWNOUT
Power-on is detected when the supply voltage exceeds 2.4 V at VDD. At this point, digital logic starts up and
waits for 100 µs for the excitation source to settle to its final value. During this period, ICOMP1 and ICOMP2
outputs are pulled low, so that there is no undesired signal drive on the compensation coil. Also, the error
conditions are suppressed and the ERROR pin is asserted low for 100 µs. This ensures that the excitation
voltage has reached the final level and there is no false error triggered on the output. The output on the VOUT
terminal is only valid 100 µs after power-on reset.
The DRV411 tests for low supply voltages with a brownout voltage level of +2.4 V. Good power-supply and low
ESR bypass capacitors are required to maintain the supply voltage during the large current pulses driven by the
DRV411. Supply voltage drops below the brown-out level lasting less than 25 μs are ignored. A supply drop
lasting longer than 25 μs generates power-on reset. A voltage dip on VDD down to +1.8 V also initiates a poweron reset. After the power supply returns to 2.4 V (see the power-on reset threshold parameter in the Electrical
Characteristics), the device initiates a startup cycle as previously described.
ERROR CONDITIONS
In addition to the overrange flag that indicates signal clipping in the output amplifier (differential amplifier), a
system error flag is provided. The error flag indicates conditions when the output voltage does not represent the
primary current. The error flag is active during a power fail or brown-out, or when the Hall sensor offset becomes
greater than 50 mV, which usually means that the Hall sensor is not functioning within its normal operating
range. The error flag also goes active with an open circuit in the Hall sensor connection. As soon as the error
condition is no longer present and the circuit has returned to normal operation, the flag resets.
Both the error and overrange flags are open-drain logic outputs. They can be connected together for a wired-OR,
and require an external pull-up resistor for proper operation.
The following conditions result in error flag activation (ERROR asserts low):
1. For 100 µs from power-up, or if a supply-voltage low (brown-out) condition lasts for more than 25 μs.
Recovery is the same as power-up.
2. If the Hall sensor offset becomes greater than 50 mV.
3. If one or more of the Hall sensor terminals is disconnected.
PROTECTION RECOMMENDATIONS
The inputs IAIN1 and IAIN2 require external protection to limit the voltage swing below 6 V of the supply voltage.
Driver outputs ICOMP1 and ICOMP2 can handle high-current pulses protected by internal clamp circuits to the
supply voltage. If large magnitude overcurrents are expected, it is highly recommended to connect external
Schottky diodes to the supply rails. This external protection prevents current flowing into the die and destroying
the circuitry.
All other pins offer standard protection; see the Absolute Maximum Ratings table.
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APPLICATION INFORMATION
FUNCTIONAL PRINCIPLE OF CLOSED-LOOP CURRENT SENSORS WITH A HALL SENSOR
Closed-loop current sensors measure currents over wide frequency ranges, including dc currents. These types of
devices offer a contact-free method, as well as excellent galvanic isolation performance combined with high
resolution, accuracy, and reliability. At dc and in low-frequency ranges, the magnetic field induced from the
current in the primary winding is compensated by a current driven through a compensation coil. A magnetic field
probe (Hall sensor) located in the magnetic core loop detects the magnetic flux. This probe delivers the signal to
the signal conditioning circuitry that drives the current through the compensation coil, bringing the magnetic flux
back to zero. This compensation current is proportional to the primary current, relative to the winding ratio.
In higher frequency ranges, the compensation winding acts as the secondary winding in the current transformer,
while the H-bridge compensation driver is rolled off and provides low output impedance.
A difference amplifier senses the voltage across a small shunt resistor that is connected to the compensation
loop. This difference amplifier generates the output voltage that is proportional to the primary current. Figure
Figure 54 shows the principle of a closed-loop current sensor.
IComp
Primary Winding
RSense
Magnetic Core
Sense
Amplifier
Signal
Conditioning
Compensation
Coil Windings
Coil
Driver
VOUT
Field Probe
IPRIM
Figure 54. Principle of a Closed-Loop Current Sensor
USING DRV411 IN ±15-V SENSOR APPLICATIONS
To take advantage of the current spinning architecture for ±15-V sensor modules, the application circuit shown in
Figure 55 can be used. The DRV411 max supply voltage is 5.5 V; therefore, the ±15V supplies must be
externally regulated to less than 5.5 V across the power supply pins of the DRV411. In addition, an external
power driver stage must be implemented that then drives the compensation coil. These techniques allow the
design of exceptionally precise and stable ±15-V current-sense modules.
+15 V
LDO
5V
VDD
ICOMP1
HALL1
HALL1
HALL3
HALL4
Signal
Conditioning
H-Bridge
Driver
ICOMP2
External
Driver
Compensation
Coil
DRV411
GND
-15 V
RSHUNT
Figure 55. DRV411 Application Example: ±15-V Sensor Modules
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ADDITIONAL APPLICATION EXAMPLES
VDD
Primary Winding
Ip
R1
REFSEL2
OR
OVERRANGE
Hall Sensor
REFSEL1
REFOUT
IN+
HALL1
REFIN
OUT+
HALL2
VOUT
IN
HALL3
IAIN2
OUT
Magnetic Core
ERROR
DRV411
HALL4
IAIN1
ERROR
GND
GSEL1
GND
GSEL2
ICOMP2
VDD
ICOMP1
R2
Compensation Coil
VDD
VDD
VREF
VOUT
D1
D3
Protection Diodes
D2
D4
RSHUNT
GND
K1
VDD
K2
Place decoupling
close to VDD pin
C1
ICOMP
Figure 56. Typical Application Example with Gain_1 Setting (see Table 1)
VDD
Hall Sensor
Primary Winding
Ip
R1
REFSEL2
REFSEL1
OR
OVERRANGE
REFOUT
IN+
HALL1
REFIN
OUT+
HALL2
VOUT
IN
HALL3
IAIN2
OUT
Magnetic Core
ERROR
RF1
RF2
R2
Compensation Coil
CF1
CF2
VDD
DRV411
VDD
VREF
VOUT
D1
D3
Protection Diodes
HALL4
IAIN1
ERROR
GND
GSEL1
GND
GSEL2
ICOMP2
VDD
ICOMP1
D2
D4
RSHUNT
GND
VDD
K1
C1
K2
Place decoupling
close to VDD pin
ICOMP
Figure 57. Application Example with External Gain and Compensation Setting
(GSEL1 and GSEL2 set High), No Current Spinning
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LAYOUT CONSIDERATIONS
The DRV411 operates with relatively large currents and offers wide bandwidth. It is often exposed to large
distortion energy from the primary signal and from the environment. Therefore, the wiring layout must provide
shielding and low impedance connections between critical points. Power-supply decoupling requires low-ESR
capacitors, and eventually a combination of a 4.7-nF NP0-type capacitor and a second capacitor of 1 µF or
larger. Use low-impedance tracks to connect the capacitors to the pins. Avoid plated through-hole connectors;
use multiple plated through-holes instead. The ground (GND) should be connected to a local ground plane. Best
supply decoupling is achieved with ferrite beads in series to the main supply. The ferrite beads decouple the
DRV411, and thus reduce interaction with other circuits powered from the same supply voltage source.
The reference output (REFOUT) is referred to GND. A low-impedance and star-type connection is required to
avoid the driver current and the probe current modulating the voltage drop on the ground track. The REFOUT
and VOUT outputs can drive some capacitive load, but avoid large direct capacitive loading because it increases
internal pulse currents. Given the wide bandwidth of the differential amplifier, isolate large capacitive loads with a
small series resistor. Using a small capacitor of some pF improves the transient response on high resistive loads.
The exposed thermal pad, or PowerPAD, on the bottom of the package must be soldered to GND because it is
internally connected to the substrate that must be connected to the most negative potential.
POWER DISSIPATION
The use of the thermally-enhanced PowerPAD SOIC and QFN packages dramatically reduces the thermal
impedance from junction to case. These packages are constructed using a down-set lead frame that the die is
mounted on. This arrangement results in the lead frame being exposed as a thermal pad on the underside of the
package. The PowerPAD has direct thermal contact with the die; therefore, excellent thermal performance can
be achieved as a result of providing a good thermal path away from the thermal pad.
The two outputs, ICOMP1 and ICOMP2, are linear outputs, and therefore the power dissipation on each output is
proportional to the current multiplied by the internal voltage drop on the active transistor. For ICOMP1 and
ICOMP2, it is the voltage drop to VDD or GND according to the current-conducting side of the output.
CAUTION
Output short-circuit conditions are particularly critical for the ICOMP driver because the
full supply voltage can be seen across the conducting transistor and the current is not
limited other than by the current density limitation of the FET; permanent damage can
occur. The DRV411 does not feature temperature protection or thermal shut-down.
Thermal Pad
Packages with an exposed thermal pad are specifically designed to provide excellent power dissipation, but
board layout greatly influences the overall heat dissipation. Technical details are described in Application Report
SLMA002, PowerPad Thermally Enhanced Package, available for download at www.ti.com.
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SBOS693B – AUGUST 2013 – REVISED DECEMBER 2013
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REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in this version.
Changes from Revision A (August 2013) to Revision B
Page
•
Changed ESD parameter in Absolute Maximum Ratings table: deleted first human body model row, added machine
model row ............................................................................................................................................................................. 2
•
Changed Hall Element Excitation, Error comparator threshold parameter typical specification in Electrical
Characteristics table ............................................................................................................................................................. 3
•
Changed Voltage Reference, PSRR parameter: added second row to PSRR parameter, added RGP package to
test conditions of first row ..................................................................................................................................................... 4
•
Changed Digital Input/Output, VOL and VOH parameters: swapped symbols and parameter names ................................... 4
•
Changed Figure 15 ............................................................................................................................................................... 8
•
Changed Figure 36: changed units in y-axis ...................................................................................................................... 11
•
Changed last paragraph of Gain Selection and Compensation Frequency section ........................................................... 16
Changes from Original (August 2013) to Revision A
Page
•
Changed Figure 14 to show correct image ........................................................................................................................... 8
•
Changed Figure 25 to show correct image ......................................................................................................................... 10
•
Changed Figure 34 to show correct image ......................................................................................................................... 11
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
DRV411AIPWP
ACTIVE
HTSSOP
PWP
20
70
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
DRV411
DRV411AIPWPR
ACTIVE
HTSSOP
PWP
20
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
DRV411
DRV411AIRGPR
ACTIVE
QFN
RGP
20
3000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
DRV411
DRV411AIRGPT
ACTIVE
QFN
RGP
20
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
DRV411
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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