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DRV8343-Q1
SLVSE12A – MARCH 2018 – REVISED APRIL 2019
DRV8343-Q1 12-V / 24-V Automotive Gate Driver Unit (GDU) with Independent Half Bridge
Control and Three Integrated Current Sense Amplifiers
1 Features
3 Description
•
The DRV8343-Q1 device is an integrated gate driver
for three-phase applications. The device provides
three half-bridge gate drivers, each capable of driving
high-side and low-side N-channel power MOSFETs.
The dedicated Source and Drain pins enable the
independent
MOSFET
control
for
solenoid
application. The DRV8343-Q1 generates the correct
gate drive voltages using an integrated charge pump
sufficient for the high-side MOSFETs and a linear
regulator for the low-side MOSFETs. The Smart Gate
Drive architecture supports peak gate drive currents
up to 1-A source and 2-A. The DRV8343-Q1 can
operate from a single power supply and supports a
wide input supply range of 5.5 to 60 V for the gate
driver.
•
•
•
•
•
•
•
•
•
•
AEC-Q100 qualified for automotive applications
– Temperature grade 1: –40°C ≤ TA ≤ 125°C
Three independent half-bridge gate driver
– Dedicated source (SHx) and drain (DLx) pins
to support independent MOSFET control
– Drives 3 high-side and 3 low-side N-channel
MOSFETs (NMOS)
Smart gate drive architecture
– Adjustable slew rate control
– 1.5-mA to 1-A peak source current
– 3-mA to 2-A peak sink current
Charge-pump of gate driver for 100% Duty Cycle
3 Integrated current sense amplifiers (CSAs)
– Adjustable gain (5, 10, 20, 40 V/V)
– Bidirectional or unidirectional support
SPI (S) and hardware (H) interface available
6x, 3x, 1x, and independent PWM modes
Supports 3.3-V, and 5-V logic inputs
Charge pump output can be used to drive the
reverse supply protection MOSFET
Linear voltage regulator, 3.3 V, 30 mA
Integrated protection features
– VM undervoltage lockout (UVLO)
– Charge pump undervoltage (CPUV)
– Short to battery (SHT_BAT)
– Short to ground (SHT_GND)
– MOSFET overcurrent protection (OCP)
– Gate driver fault (GDF)
– Thermal warning and shutdown (OTW/OTSD)
– Fault condition indicator (nFAULT)
The 6x, 3x, 1x, and independent input PWM modes
allow for simple interfacing to controller circuits. The
configuration settings for the gate driver and device
are highly configurable through the SPI or hardware
(H/W) interface. The DRV8343-Q1 device integrates
three low-side current sense amplifiers that allow
bidirectional current sensing on all three phases of
the drive stage.
A low-power sleep mode is provided to achieve low
quiescent current. Internal protection functions are
provided for undervoltage lockout, charge pump fault,
MOSFET overcurrent, MOSFET short circuit, phasenode short to supply and ground, gate driver fault,
and overtemperature. Fault conditions are indicated
on the nFAULT pin with details through the device
registers for the SPI device variant.
Device Information(1)
PART NUMBER
DRV8343-Q1
Simplified Schematic
5.5 to 60 V
PWM
Controller
12-V and 24-V Automotive Motor-Control
Applications
– BLDC and BDC motor modules
– Fans and blowers
– Fuel and water pumps
– Solenoid drive
BODY SIZE (NOM)
7.00 mm × 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
PACKAGE
HTQFP (48)
SPI or H/W
nFAULT
Sense output
3.3 V
30 mA
DRV8343-Q1
Three-Phase
Smart Gate Driver
Protection
Gate Drive
N-Channel
MOSFETs
1
Current
Sense
3x Sense Amplifiers
3.3-V LDO
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRV8343-Q1
SLVSE12A – MARCH 2018 – REVISED APRIL 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
8
1
1
1
2
3
3
7
Absolute Maximum Ratings ...................................... 7
ESD Ratings.............................................................. 7
Recommended Operating Conditions....................... 8
Thermal Information .................................................. 8
Electrical Characteristics........................................... 9
SPI Timing Requirements ....................................... 15
Typical Characteristics ............................................ 16
Detailed Description ............................................ 17
8.1
8.2
8.3
8.4
8.5
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
17
18
20
51
52
8.6 Register Maps ......................................................... 54
9
Application and Implementation ........................ 69
9.1 Application Information............................................ 69
9.2 Typical Application ................................................. 69
10 Power Supply Recommendations ..................... 78
10.1 Power Supply Consideration in Generator Mode . 78
10.2 Bulk Capacitance Sizing ....................................... 78
11 Layout................................................................... 80
11.1 Layout Guidelines ................................................. 80
11.2 Layout Example .................................................... 81
12 Device and Documentation Support ................. 82
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
82
82
82
82
82
83
83
13 Mechanical, Packaging, and Orderable
Information ........................................................... 83
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (March 2018) to Revision A
•
Page
Changed device status to Production Data ........................................................................................................................... 1
PP
2
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Product Folder Links: DRV8343-Q1
DRV8343-Q1
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SLVSE12A – MARCH 2018 – REVISED APRIL 2019
5 Device Comparison Table
DEVICE
VARIANT (1)
INTERFACE (1)
DRV8343H
Hardware
DRV8343S
SPI
DRV8343-Q1
(1)
For more information on the device name and device options, see the Device Nomenclature section.
6 Pin Configuration and Functions
NC
PGND
INLC
INHC
INLB
INHB
INLA
INHA
nDIAG
DVDD
AGND
CAL
48
47
46
45
44
43
42
41
40
39
38
37
DRV8343H PHP PowerPAD™ Package
48-Pin HTQFP With Exposed Thermal Pad
Top View
CPL
1
36
ENABLE
CPH
2
35
GAIN
VCP
3
34
VDS
VM
4
33
IDRIVE
VDRAIN
5
32
MODE
GHA
6
31
nFAULT
SHA
7
30
VREF
Thermal
Pad
SNC
SNA
12
25
SPC
Not to scale
SLC
GLC
DLC
SHC
GHC
GHB
DLB
SHB
GLB
SLB
SPB
SNB
24
26
23
11
22
SPA
21
SOC
20
27
19
10
18
SLA
17
SOB
16
SOA
28
15
29
9
14
8
13
DLA
GLA
Pin Functions—DRV8343H
PIN
NO.
NAME
TYPE (1)
DESCRIPTION
1
CPL
PWR
Charge pump switching node. Connect a flying capacitor between the CPH and CPL pins
2
CPH
PWR
Charge pump switching node. Connect a flying capacitor between the CPH and CPL pins
3
VCP
PWR
Charge pump output. Connect a bypass capacitor between the VCP and VM pins
4
VM
PWR
Gate driver power supply input. Connect to the bridge power supply. Connect bypass capacitors VM and PGND pins
5
VDRAIN
I
High-side MOSFET drain sense input. Connect to the common point of the MOSFET drains
6
GHA
O
High-side gate driver output. Connect to the gate of the high-side power MOSFET
7
SHA
I
High-side source sense input. Connect to the high-side power MOSFET source. If high-side power MOSFET is not used,
connect to GND
8
DLA
I
Low-side MOSFET drain sense input. Connect to the low-side MOSFET drain
(1)
PWR = power, I = input, O = output, NC = no connection, OD = open-drain output
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SLVSE12A – MARCH 2018 – REVISED APRIL 2019
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Pin Functions—DRV8343H (continued)
PIN
NO.
NAME
TYPE (1)
DESCRIPTION
9
GLA
O
Low-side gate driver output. Connect to the gate of the low-side power MOSFET
10
SLA
I
Low-side source sense input. Connect to the low-side power MOSFET source
11
SPA
I
Low-side current shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt
resistor
12
SNA
I
Current sense amplifier input. Connect to the low-side of the current shunt resistor
13
SNB
I
Low-side source sense input. Connect to the low-side power MOSFET source
14
SPB
I
Low-side current shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt
resistor
15
SLB
I
Low-side source sense input. Connect to the low-side power MOSFET source
16
GLB
O
Low-side gate driver output. Connect to the gate of the low-side power MOSFET
17
DLB
I
Low-side MOSFET drain sense input. Connect to the low-side MOSFET drain
18
SHB
I
High-side source sense input. Connect to the high-side power MOSFET source. If high-side power MOSFET is not used,
connect to GND
19
GHB
O
High-side gate driver output. Connect to the gate of the high-side power MOSFET
20
GHC
O
High-side gate driver output. Connect to the gate of the high-side power MOSFET
21
SHC
I
High-side source sense input. Connect to the high-side power MOSFET source. If high-side power MOSFET is not used,
connect to GND
22
DLC
I
Low-side MOSFET drain sense input. Connect to the low-side MOSFET drain
23
GLC
O
Low-side gate driver output. Connect to the gate of the low-side power MOSFET
24
SLC
I
Low-side source sense input. Connect to the low-side power MOSFET source
25
SPC
I
Low-side current shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt
resistor
26
SNC
I
Current sense amplifier input. Connect to the low-side of the current shunt resistor
27
SOC
O
Current sense amplifier output
28
SOB
O
Current sense amplifier output
29
SOA
O
Current sense amplifier output
30
VREF
PWR
31
nFAULT
OD
32
MODE
I
PWM input mode setting. This pin is a 7-level input pin set by an external resistor
33
IDRIVE
I
Gate drive output current setting. This pin is a 7-level input pin set by an external resistor
34
VDS
I
VDS monitor trip point setting. This pin is a 7-level input pin set by an external resistor
35
GAIN
I
Amplifier gain setting. The pin is a 4-level input pin set by an external resistor
36
ENABLE
I
Gate driver enable. When this pin is logic low the device goes to a low-power sleep mode. An 20-μs (typ) low pulse can be
used to reset fault conditions
Amplifier calibration input. Set logic high to internally short amplifier inputs
Current sense amplifier power supply input and reference. Connect a bypass capacitor between VREF and AGND
Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor
37
CAL
I
38
AGND
PWR
Device analog ground. Connect to system ground
39
DVDD
PWR
3.3-V internal regulator output. Connect a bypass capacitor between the DVDD and AGND pins. This regulator can externally
source up to 30 mA.
40
nDIAG
I
Control pin for open load diagnostic and offline short-to-battery and short-to-ground diagnostic. To enable the diagnostics at
device power-up, do not connect this pin (or tie it to ground). To disable the diagnostics, connect this pin to the DVDD pin.
41
INHA
I
High-side gate driver control input. This pin controls the output of the high-side gate driver
42
INLA
I
Low-side gate driver control input. This pin controls the output of the low-side gate driver
43
INHB
I
High-side gate driver control input. This pin controls the output of the high-side gate driver
44
INLB
I
Low-side gate driver control input. This pin controls the output of the low-side gate driver
45
INHC
I
High-side gate driver control input. This pin controls the output of the high-side gate driver
46
INLC
I
Low-side gate driver control input. This pin controls the output of the low-side gate driver
47
PGND
PWR
48
NC
NC
—
Thermal
Pad
PWR
4
Device power ground. Connect to system ground
No connect. Do not connect anything to this pin
Must be connected to ground
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SLVSE12A – MARCH 2018 – REVISED APRIL 2019
NC
PGND
INLC
INHC
INLB
INHB
INLA
INHA
VSDO
DVDD
AGND
CAL
48
47
46
45
44
43
42
41
40
39
38
37
DRV8343S PHP PowerPAD™ Package
48-Pin HTQFP With Exposed Thermal Pad
Top View
CPL
1
36
ENABLE
CPH
2
35
nSCS
VCP
3
34
SCLK
VM
4
33
SDI
VDRAIN
5
32
SDO
GHA
6
31
nFAULT
SHA
7
30
VREF
DLA
8
29
SOA
GLA
9
28
SOB
SLA
10
27
SOC
SPA
11
26
SNC
SNA
12
25
SPC
Thermal
24
Not to scale
SLC
23
GLC
22
DLC
20
21
SHC
GHC
19
GHB
18
SHB
17
DLB
16
GLB
14
15
SLB
SPB
SNB
13
Pad
Pin Functions—DRV8343S
PIN
NO.
NAME
TYPE (1)
DESCRIPTION
1
CPL
PWR
Charge pump switching node. Connect a flying capacitor between the CPH and CPL pins
2
CPH
PWR
Charge pump switching node. Connect a flying capacitor between the CPH and CPL pins
3
VCP
PWR
Charge pump output. Connect a bypass capacitor between the VCP and VM pins
4
VM
PWR
Gate driver power supply input. Connect to the bridge power supply. Connect bypass capacitors between the VM and PGND
pins
5
VDRAIN
I
High-side MOSFET drain sense input. Connect to the common point of the MOSFET drains
6
GHA
O
High-side gate driver output. Connect to the gate of the high-side power MOSFET
7
SHA
I
High-side source sense input. Connect to the high-side power MOSFET source. If high-side power MOSFET is not used,
connect to GND
8
DLA
I
Low-side MOSFET drain sense input. Connect to the low-side MOSFET drain
9
GLA
O
Low-side gate driver output. Connect to the gate of the low-side power MOSFET
10
SLA
I
Low-side source sense input. Connect to the low-side power MOSFET source
11
SPA
I
Low-side current shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt
resistor
12
SNA
I
Current sense amplifier input. Connect to the low-side of the current shunt resistor
13
SNB
I
Low-side source sense input. Connect to the low-side power MOSFET source
14
SPB
I
Low-side current shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt
resistor
15
SLB
I
Low-side source sense input. Connect to the low-side power MOSFET source
16
GLB
O
Low-side gate driver output. Connect to the gate of the low-side power MOSFET
17
DLB
I
Low-side MOSFET drain sense input. Connect to the low-side MOSFET drain
(1)
PWR = power, I = input, O = output, NC = no connection, OD = open-drain output, PP = push-pull
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Pin Functions—DRV8343S (continued)
PIN
NO.
NAME
TYPE (1)
DESCRIPTION
SHB
I
High-side source sense input. Connect to the high-side power MOSFET source. If high-side power MOSFET is not used,
connect to GND
19
GHB
O
High-side gate driver output. Connect to the gate of the high-side power MOSFET
20
GHC
O
High-side gate driver output. Connect to the gate of the high-side power MOSFET
21
SHC
I
High-side source sense input. Connect to the high-side power MOSFET source. If high-side power MOSFET is not used,
connect to GND
18
22
DLC
I
Low-side MOSFET drain sense input. Connect to the low-side MOSFET drain
23
GLC
O
Low-side gate driver output. Connect to the gate of the low-side power MOSFET
24
SLC
I
Low-side source sense input. Connect to the low-side power MOSFET source
25
SPC
I
Low-side current shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt
resistor
26
SNC
I
Current sense amplifier input. Connect to the low-side of the current shunt resistor
27
SOC
O
Current sense amplifier output
28
SOB
O
Current sense amplifier output
29
SOA
O
Current sense amplifier output
30
VREF
PWR
31
nFAULT
OD
Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor
32
SDO
PP
Serial data output. Data is shifted out on the rising edge of the SCLK pin. VSDO determines logic level on the output
33
SDI
I
Serial data input. Data is captured on the falling edge of the SCLK pin
34
SCLK
I
Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin
35
nSCS
I
Serial chip select. A logic low on this pin enables serial interface communication
36
ENABLE
I
Gate driver enable. When this pin is logic low the device goes to a low-power sleep mode. An 20-μs (typ) low pulse can be
used to reset fault conditions
Amplifier calibration input. Set logic high to internally short amplifier inputs
Current sense amplifier power supply input and reference. Connect a bypass capacitors between VREF and AGND
37
CAL
I
38
AGND
PWR
Device analog ground. Connect to system ground
39
DVDD
PWR
3.3-V internal regulator output. Connect a bypass capacitor between the DVDD and AGND pins. This regulator can externally
source up to 30 mA.
40
VSDO
PWR
Supply pin for SDO output. Connect to 5-V or 3.3-V depending on the desired logic level. Connect a bypass capacitors
between VSDO and AGND
41
INHA
I
High-side gate driver control input. This pin controls the output of the high-side gate driver
42
INLA
I
Low-side gate driver control input. This pin controls the output of the low-side gate driver
43
INHB
I
High-side gate driver control input. This pin controls the output of the high-side gate driver
44
INLB
I
Low-side gate driver control input. This pin controls the output of the low-side gate driver
45
INHC
I
High-side gate driver control input. This pin controls the output of the high-side gate driver
46
INLC
I
Low-side gate driver control input. This pin controls the output of the low-side gate driver
47
PGND
PWR
48
NC
NC
—
Thermal
Pad
PWR
6
Device power ground. Connect to system ground
No connect. Do not connect anything to this pin
Must be connected to ground
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SLVSE12A – MARCH 2018 – REVISED APRIL 2019
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
GATE DRIVER
Power supply pin voltage (VM)
–0.3
65
V
Voltage differential between ground pins (AGND, BGND, DGND, PGND)
–0.3
0.3
V
MOSFET drain sense pin voltage (VDRAIN)
–0.3
65
V
Charge pump pin voltage (CPH, VCP)
–0.3
VVM + 13.5
V
Charge-pump negative-switching pin voltage (CPL)
–0.3
VVM
V
Internal logic regulator pin voltage (DVDD)
–0.3
3.8
V
Voltage difference between VM and VDRAIN
–10
10
V
Digital pin voltage (CAL, ENABLE, GAIN, IDRIVE, INHx, INLx, MODE, nFAULT, nSCS, SCLK, SDI,
SDO, VDS, nDIAG)
–0.3
5.75
V
Continuous high-side gate drive pin voltage (GHx)
–5 (2)
VVCP + 0.5
V
–7
VVCP + 0.5
V
Transient 200-ns high-side gate drive pin voltage (GHx)
High-side gate drive pin voltage with respect to SHx (GHx)
–0.3
13.5
V
Continuous high-side source sense pin voltage (SHx, DLx)
–5 (2)
VVM + 5
V
–7
VVM + 7
V
–5 (2)
VDRAIN + 5
V
–7
VDRAIN + 7
V
–0.5
15
V
Transient 200-ns high-side source sense pin voltage (SHx, DLx)
Continuous high-side source sense pin voltage (SHx, DLx)
Transient 200-ns high-side source sense pin voltage (SHx, DLx)
Continuous low-side gate drive pin voltage (GLx)
Gate drive pin source current (GHx, GLx)
Internally limited
Gate drive pin sink current (GHx, GLx)
Internally limited
A
A
Continuous low-side source sense pin voltage (SLx)
–1
1
V
Transient 200-ns low-side source sense pin voltage (SLx)
–3
3
V
Continuous shunt amplifier input pin voltage (SNx, SPx)
–1
1
V
Transient 200-ns shunt amplifier input pin voltage (SNx, SPx)
–3
3
V
Reference input pin voltage (VREF)
–0.3
5.75
V
Shunt amplifier output pin voltage (SOx)
–0.3
VVREF + 0.3
0
8
–0.3
5.75
0
10
Open drain pullup voltage (nFAULT)
–0.3
5.75
Open drain output current (nFAULT)
0
10
mA
Operating junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–65
150
°C
Shunt amplifier output current (SOx)
Push-pull output buffer reference voltage (VSDO)
Push-pull output current (SDO)
(1)
(2)
V
mA
V
mA
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Continuous high-side gate pin (GHx) and phase node pin voltage (SHx) should be limited to –2 V minimum for an absolute maximum of
65 V on VM. At 60 V and below, the full specification of –5 V continuous on GHx and SHx is allowable.
7.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC Q100-002
V(ESD)
(1)
Electrostatic
discharge
Charged-device model (CDM), per AEC Q100011
(1)
±2000
All pins
±500
Corner pins (1, 10, 11, 20, 21, 30, 31, and 40)
±750
UNIT
V
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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7.3 Recommended Operating Conditions
MIN
MAX
UNIT
5.5
50
V
5.5
60
V
0
5.5
V
(3)
kHz
GATE DRIVER
Power supply voltage (VM) Continuous
VVM
(1)
Power supply voltage (VM) Transient over voltage
(2)
Input voltage (CAL, ENABLE, GAIN, IDRIVE, INHx, INLx, MODE, nSCS, SCLK, SDI,
VDS, VSDO, nDIAG)
VI
fPWM
Applied PWM signal (INHx, INLx)
0
IGATE_HS
High-side average gate-drive current (GHx)
0
25 (3)
mA
IGATE_LS
Low-side average gate-drive current (GLx)
0
25 (3)
mA
IDVDD
External load current (DVDD)
0
30 (3)
mA
VVREF
Reference voltage input (VREF)
3
5.5
V
VSDO
Push-pull voltage (SDO)
3
5.5
V
VOD
Open drain pullup voltage (nFAULT)
0
5.5
V
TA
Operating ambient temperature
–40
125
°C
(1)
(2)
(3)
200
Operation at VM = 5.5V only when coming from higher VM. The minimum VM voltage for startup is greater than VUVLO (rising) voltage.
VM recommended operating condition for electrical characteristic table. Product life time depends on VM voltage. The device is intended
for 12–V and 24–V battery automotive system with life-time nominal voltage of 5.5 V - 50 V. The device can be operated during
additional overvoltage events as specified in ISO16750-2:2012
Power dissipation and thermal limits must be observed
7.4 Thermal Information
DRV8343-Q1
THERMAL METRIC (1)
PHP (HTQFP)
UNIT
48 PINS
RθJA
Junction-to-ambient thermal resistance
26.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
16.3
°C/W
RθJB
Junction-to-board thermal resistance
6.7
°C/W
ψJT
Junction-to-top characterization parameter
0.2
°C/W
ψJB
Junction-to-board characterization parameter
6.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.0
°C/W
(1)
8
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
Over recommended operating conditions 5.5 ≤ VVM ≤ 60 V (unless otherwise noted). Typical limits apply for VVM = 24 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VVM = 24 V, ENABLE = 3.3 V, INHx/INLx = 0 V, SHx = 0
V
12
16
ENABLE = 0 V, VVM = 24 V, TA = 25°C
12
20
UNIT
POWER SUPPLIES (DVDD, VCP, VM)
IVM
VM operating supply current
IVMQ
VM sleep mode supply current
tRST
Reset pulse time
ENABLE = 0 V period to reset faults
tWAKE (1)
Turnon time
ENABLE = 3.3 V to outputs ready, VVM > VUVLO
tSLEEP
Turnoff time
ENABLE = 0 V to device sleep mode
VDVDD
DVDD regulator voltage
VCP operating voltage
with respect to VM
VVCP
ENABLE = 0 V, VVM = 24 V, TA = 125°C
50
4.4
mA
µA
43
µs
1
ms
1
ms
VVM > 6 V, IDVDD = 0 to 30 mA
3
3.3
3.6
V
VVM = 5.5 to 6 V, IDVDD = 0 to 20 mA
3
3.3
3.6
V
VVM = 13 V, IVCP = 0 to 25 mA
8.4
11
12.5
VVM = 10 V, IVCP = 0 to 20 mA
6.3
9
10
VVM = 8 V, IVCP = 0 to 15 mA
5.4
7
8
VVM = 5.5 V, IVCP = 0 to 5 mA
4
5
6
V
LOGIC-LEVEL INPUTS (CAL, ENABLE, INHx, INLx, SCLK, SDI)
VIL
Input logic low voltage
VIH
Input logic high voltage
VHYS
Input logic hysteresis
IIL
Input logic low current
VVIN = 0 V; INHx, INLx, SDI(IDRIVE), SCLK(VDS),
ENABLE
IIH
Input logic high current
VVIN = 5 V; INHx, INLx, SDI(IDRIVE), SCLK(VDS)
IIH
Input logic high current
VVIN = 5 V; ENABLE
RPD
Pulldown resistance
To AGND; INHx, INLx, SDI(IDRIVE), SCLK(VDS)
RPD
Pulldown resistance
To AGND; ENABLE
Propagation delay
INHx/INLx input buffer and digital core propagation
delay. Dead time is excluded.
tPD
0
0.7
1.6
5.5
182
–5
V
V
mV
5
µA
50
90
µA
80
110
µA
50
100
200
kΩ
30
60
110
kΩ
105
ns
LOGIC LEVEL INPUT (nSCS)
VIL,nSCS
Input logic low voltage
VIH,nSCS
Input logic high voltage
RPU,nSCS
Pullup resistance
To DVDD
0
0.7
1.6
5.5
V
90
kΩ
25
50
V
FOUR-LEVEL H/W INPUT (GAIN)
VI1
Input mode 1 voltage
Tied to AGND
VI2
Input mode 2 voltage
47 kΩ ± 5% to tied AGND
0
V
1.2
V
VI3
Input mode 3 voltage
Hi-Z ( > 500 kΩ to AGND)
VI4
Input mode 4 voltage
Tied to DVDD
2
V
RPU
Pullup resistance
Internal pullup to DVDD
25
50
80
kΩ
RPD
Pulldown resistance
Internal pulldown to AGND
40
84
130
kΩ
3.3
V
SEVEN-LEVEL H/W INPUTS (MODE, IDRIVE, VDS)
VI1
Input mode 1 voltage
Tied to AGND
0
V
VI2
Input mode 2 voltage
18 kΩ ± 5% tied to AGND
0.5
V
VI3
Input mode 3 voltage
75 kΩ ± 5% tied to AGND
1.1
V
VI4
Input mode 4 voltage
Hi-Z ( > 1.5 MΩ )
1.65
V
VI5
Input mode 5 voltage
75 kΩ ± 5% tied to DVDD
2.2
V
VI6
Input mode 6 voltage
18 kΩ ± 5% tied to DVDD
2.8
V
VI7
Input mode 7 voltage
MODE : 0.47 kΩ ± 5% tied to DVDD
VDS, IDRIVE : Tied to DVDD
3.3
V
RPU
Pullup resistance
Internal pullup to DVDD
35
73
125
kΩ
RPD
Pulldown resistance
Internal pulldown to AGND
35
73
125
kΩ
PUSH-PULL OUTPUT (SDO)
(1)
Does not include OLP/Shorts diagnostic delay time in the H/W device
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Electrical Characteristics (continued)
Over recommended operating conditions 5.5 ≤ VVM ≤ 60 V (unless otherwise noted). Typical limits apply for VVM = 24 V
PARAMETER
RPU,SDO
Internal pullup
RPD,SDO
Internal pulldown
TYP
MAX
To VSDO = 5 V
TEST CONDITIONS
MIN
40
90
To VSDO = 3.3 V
60
120
To GND
30
50
UNIT
Ω
Ω
OPEN DRAIN OUTPUT (nFAULT)
VOL
Output logic low voltage
IO = 5 mA
IOZ
Output high impedance leakage
VO = 5 V
–1
0.15
V
9
µA
VVM = 13 V, IVCP = 0 to 25 mA, GHx no output load
8.4
11
12.5
VVM = 10 , IVCP = 0 to 20 mA, GHx no output load
6.3
9
10
VVM = 8 V, IVCP = 0 to 15 mA, GHx no output load
5.4
7
8
VVM = 5.5 V, IVCP = 0 to 5 mA, GHx no output load
4
5
6
VVM = 12 V, IVCP = 0 to 25 mA, GLx no output load
9
11
12
VVM = 10 V, IVCP = 0 to 20 mA, GLx no output load
9.9
10.0
10.1
VVM = 8 V, IVCP = 0 to 15 mA, GLx no output load
7.9
8.0
8.1
VVM = 5.5 V, IVCP = 0 to 5 mA, GLx no output load
5.4
5.5
5.6
GATE DRIVERS (GHx, GLx)
High-side gate drive voltage
with respect to SHx
VGSH
Low-side gate drive voltage
with respect to PGND
VGSL
Gate drive
dead time
tDEAD
SPI Device
DEAD_TIME = 00b
500
DEAD_TIME = 01b
1000
DEAD_TIME = 10b
2000
DEAD_TIME = 11b
4000
H/W Device
Peak current
gate drive time
tDRIVE
SPI Device
10
Peak current gate drive max time
V
ns
1000
TDRIVE = 00b
500
TDRIVE = 01b
1000
TDRIVE = 10b
2000
TDRIVE = 11b
3000
H/W Device
tDRIVE_MAX
V
ns
3000
IDRIVEP_Hx = 0000b, 0001b, 0010b, 0011b
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20
µs
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Electrical Characteristics (continued)
Over recommended operating conditions 5.5 ≤ VVM ≤ 60 V (unless otherwise noted). Typical limits apply for VVM = 24 V
PARAMETER
TEST CONDITIONS
SPI Device
IDRIVEP
Peak source
gate current
H/W Device
MIN
TYP
MAX
IDRIVEP_Hx = 0000b (GHx), VVM = 24 V
0.45
1.5
3.0
IDRIVEP_Lx = 0000b (GLx), VVM = 24 V
0.81
2.7
5.4
IDRIVEP_Hx = 0001b (GHx), VVM = 24 V
1.05
3.5
7
IDRIVEP_Lx = 0001b (GLx), VVM = 24 V
1.17
3.9
7.8
IDRIVEP_Hx = 0010b (GHx), VVM = 24 V
1.5
5
10
IDRIVEP_Lx = 0010b (GLx), VVM = 24 V
1.95
6.5
13
IDRIVEP_Hx or IDRIVEP_Lx = 0011b (GHx/GLx), VVM =
24 V
3
10
20
IDRIVEP_Hx or IDRIVEP_Lx = 0100b (GHx/GLx), VVM =
24 V
4.5
15
30
IDRIVEP_Hx or IDRIVEP_Lx = 0101b (GHx/GLx), VVM =
24 V
15
50
100
IDRIVEP_Hx or IDRIVEP_Lx = 0110b (GHx/GLx), VVM =
24 V
18
60
120
IDRIVEP_Hx or IDRIVEP_Lx = 0111b (GHx/GLx), VVM =
24 V
19.5
65
130
IDRIVEP_Hx or IDRIVEP_Lx = 1000b (GHx/GLx), VVM =
24 V
76
200
400
IDRIVEP_Hx or IDRIVEP_Lx = 1001b (GHx/GLx), VVM =
24 V
79.8
210
420
IDRIVEP_Hx or IDRIVEP_Lx = 1010b (GHx/GLx), VVM =
24 V
98.8
260
520
IDRIVEP_Hx or IDRIVEP_Lx = 1011b (GHx/GLx), VVM =
24 V
100.7
265
530
IDRIVEP_Hx or IDRIVEP_Lx = 1100b (GHx/GLx), VVM =
24 V
279.3
735
1470
IDRIVEP_Hx or IDRIVEP_Lx = 1101b (GHx/GLx), VVM =
24 V
304
800
1600
IDRIVEP_Hx or IDRIVEP_Lx = 1110b (GHx/GLx), VVM =
24 V
355.3
935
1870
IDRIVEP_Hx or IDRIVEP_Lx = 1111b (GHx/GLx), VVM =
24 V
380
1000
2000
IDRIVE = Tied to AGND (GHx), VVM = 24 V
0.45
1.5
3.0
IDRIVE = Tied to AGND (GLx), VVM = 24 V
0.81
2.7
5.4
IDRIVE = 18 kΩ ± 5% tied to AGND (GHx), VVM = 24 V
1.5
5
10
IDRIVE = 18 kΩ ± 5% tied to AGND (GLx), VVM = 24 V
1.95
6.5
13
3
10
20
IDRIVE = Hi-Z (GHx/GLx), VVM = 24 V
18
60
120
IDRIVE = 75 kΩ ± 5% tied to DVDD (GHx/GLx), VVM = 24
V
76
200
400
IDRIVE = 18 kΩ ± 5% tied to DVDD (GHx/GLx), VVM = 24
V
98.8
260
520
IDRIVE = Tied to DVDD (GHx/GLx), VVM = 24 V
380
1000
2000
IDRIVE = 75 kΩ ± 5% tied to AGND (GHx/GLx), VVM = 24
V
mA
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UNIT
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Electrical Characteristics (continued)
Over recommended operating conditions 5.5 ≤ VVM ≤ 60 V (unless otherwise noted). Typical limits apply for VVM = 24 V
PARAMETER
TEST CONDITIONS
SPI Device
IDRIVEN
Peak sink
gate current
H/W Device
SPI Device
MIN
TYP
MAX
IDRIVEN_Hx or IDRIVEN_Lx = 0000b, VVM = 24 V
0.9
3
5.4
IDRIVEN_Hx or IDRIVEN_Lx = 0001b, VVM = 24 V
2.09
7
12.6
IDRIVEN_Hx or IDRIVEN_Lx = 0010b, VVM = 24 V
3
10
18
IDRIVEN_Hx or IDRIVEN_Lx = 0011b, VVM = 24 V
6
20
36
IDRIVEN_Hx or IDRIVEN_Lx= 0100b, VVM = 24 V
9
30
54
IDRIVEN_Hx or IDRIVEN_Lx = 0101b, VVM = 24 V
30
100
180
IDRIVEN_Hx or IDRIVEN_Lx = 0110b, VVM = 24 V
36
120
216
IDRIVEN_Hx or IDRIVEN_Lx = 0111b, VVM = 24 V
39
130
234
IDRIVEN_Hx or IDRIVEN_Lx = 1000b, VVM = 24 V
120
400
720
IDRIVEN_Hx or IDRIVEN_Lx = 1001b, VVM = 24 V
126
420
756
IDRIVEN_Hx or IDRIVEN_Lx = 1010b, VVM = 24 V
156
520
936
IDRIVEN_Hx or IDRIVEN_Lx = 1011b, VVM = 24 V
159
530
954
IDRIVEN_Hx or IDRIVEN_Lx = 1100b, VVM = 24 V
441
1470
2646
IDRIVEN_Hx or IDRIVEN_Lx = 1101b, VVM = 24 V
480
1600
2880
IDRIVEN_Hx or IDRIVEN_Lx = 1110b, VVM = 24 V
561
1870
3366
IDRIVEN_Hx or IDRIVEN_Lx = 1111b, VVM = 24 V
600
2000
3600
IDRIVE = Tied to AGND, VVM = 24 V
0.9
3
5.4
IDRIVE = 18 kΩ ± 5% tied to AGND, VVM = 24 V
3
10
18
IDRIVE = 75 kΩ ± 5% tied to AGND, VVM = 24 V
6
20
36
36
120
216
IDRIVE = 75 kΩ ± 5% tied to DVDD, VVM = 24 V
120
400
720
IDRIVE = 18 kΩ ± 5% tied to DVDD, VVM = 24 V
156
520
936
IDRIVE = Tied to DVDD, VVM = 24 V
600
2000
3600
IDRIVEP_Hx = 0000b, VVM = 24 V
0.45
1.5
3.8
IDRIVEP_Hx = 0001b, VVM = 24 V
1.05
3.5
7
IDRIVEP_Hx = 0010b, VVM = 24 V
1.5
5
10
IDRIVE = Hi-Z, VVM = 24 V
IDRIVEP_Hx = 0011b, VVM = 24 V
IHOLDP
Gate holding source
current after tDRIVE
All other IDRIVE settings, VVM = 24 V
IDRIVE tied to AGND, VVM = 24 V
H/W Device
SPI Device
IHOLDN
Gate holding sink
current after tDRIVE
10
20
15
30
mA
mA
0.45
1.5
3.8
IDRIVE = 18 kΩ ± 5% tied to AGND, VVM = 24 V
1.5
5
10
IDRIVE = 75 kΩ ± 5% tied to AGND, VVM = 24 V
3
10
20
All other IDRIVE settings, VVM = 24 V
4.5
15
30
IDRIVEP_Hx = 0000b, VVM = 24 V
0.9
3
5.4
IDRIVEP_Hx = 0001b, VVM = 24 V
2
7
12.6
IDRIVEP_Hx = 0010b, VVM = 24 V
3
10
18
IDRIVEP_Hx = 0011b, VVM = 24 V
6
20
36
All other IDRIVE settings, VVM = 24 V
9
30
54
0.9
3
5.4
IDRIVE = 18 kΩ ± 5% tied to AGND, VVM = 24 V
3
10
18
IDRIVE = 75 kΩ ± 5% tied to AGND, VVM = 24 V
6
20
36
All other IDRIVE settings, VVM = 24 V
9
30
54
9
30
54
0.6
2
3.6
A
IDRIVE tied to AGND, VVM = 24 V
H/W Device
3
4.5
UNIT
mA
ISTRONG
Gate strong pulldown current
(GHx to SHx and GLx to PGND)
IDRIVEP_Hx = 0000b, 0001b, 0010b, 0011b, VVM = 24 V
ROFF
Gate hold off resistor
GHx to SHx
150
280
kΩ
ROFF
Gate hold off resistor
GLx to PGND
150
280
kΩ
All other IDRIVE settings, VVM = 24 V
mA
CURRENT SHUNT AMPLIFIER (SNx, SOx, SPx, VREF)
12
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Electrical Characteristics (continued)
Over recommended operating conditions 5.5 ≤ VVM ≤ 60 V (unless otherwise noted). Typical limits apply for VVM = 24 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
4.9
5
5.1
CSA_GAIN = 01b, CSA_FET = 0b
9.8
10
10.2
CSA_GAIN = 10b, CSA_FET = 0b
19.6
20
20.4
CSA_GAIN = 11b, CSA_FET = 0b
39.2
40
40.8
CSA_GAIN = 00b, CSA_FET = 1b
4.85
5
5.15
CSA_GAIN = 01b, CSA_FET = 1b
9.7
10
10.3
CSA_GAIN = 10b, CSA_FET = 1b
19.4
20
20.6
CSA_GAIN = 11b, CSA_FET = 1b
38.8
40
41.2
CSA_GAIN = 00b, CSA_FET = 0b
SPI Device
GCSA
Amplifier gain
SPI Device
H/W Device
GAIN = Tied to AGND
4.9
5
5.1
GAIN = 47 kΩ ± 5% tied to AGND
9.8
10
10.2
GAIN = Hi-Z
19.6
20
20.4
GAIN = Tied to DVDD
39.2
40
40.8
VO_STEP = 0.5 V, GCSA = 5 V/V
150
VO_STEP = 0.5 V, GCSA = 10 V/V
300
VO_STEP = 0.5 V, GVSA = 20 V/V
600
tSET
Settling time to ±1%
VCOM
Common mode input range
VDIFF
Differential mode input range
VOFF
Input offset error
VSP = VSN = 0 V, VREF = 3.3 V, GCSA = 10, 20, 40 V/V
VOFF
Input offset error
VSP = VSN = 0 V, VREF = 3.3 V, GCSA = 5 V/V
VDRIFT
Drift offset
VSP = VSN = 0 V
VLINEAR
SOx output voltage linear range
VO_STEP = 0.5 V, GCSA = 40 V/V
VBIAS
SOx output voltage
bias
V/V
ns
1200
–0.15
0.15
–0.3
0.3
–4
4
–5
-45
10
VSP = VSN = 0 V, CAL = 3.3 V, VREF_DIV = 0b
VVREF –
0.3
VSP = VSN = 0 V, CAL = 3.3 V, VREF_DIV = 1b
VVREF /
2
VSP = VSN = 0 V, CAL = 3.3 V
VVREF /
2
IBIAS
SPx/SNx input bias current
VSLEW
SOx output slew rate
60-pF load
10
IVREF
VREF input current
VVREF = 5 V
2
UGB
Unity gain bandwidth
60-pF load
8
V
V
mV
5
mV
45
µV/°C
VVREF –
0.25
0.25
SPI Device
H/W Device
UNIT
V
V
100
µA
V/µs
3
mA
MHz
PROTECTION CIRCUITS
VM falling, UVLO report
5.2
5.4
VM rising, UVLO recovery
5.4
5.9
VM undervoltage hysteresis
Rising to falling threshold
200
VM undervoltage deglitch time
VM falling, UVLO report
VUVLO
VM undervoltage lockout
VUVLO,DVDD
DVDD undervoltage lockout
VUVLO_HYS
tUVLO_DEG
VCPUV
Charge pump undervoltage lockout
VGS_CLAMP
High-side gate clamp
VOLA
Open load active mode detection
threshold
IOL
Open load current
tOLP
Open load passive
diagnostic delay
2.9
11.5
µs
VCP falling, CPUV report
VVM +
2.5
VVM +
3.1
Positive clamping voltage
15
16.5
19
–0.7
DLx – VDRAIN
150
300
430
SLx – SHx, –1 < SLx < 0
150
300
500
2.5
SPI Device
H/W Device
OLP_SHRT_DLY = 00b
0.25
OLP_SHRT_DLY = 01b
1.25
OLP_SHRT_DLY = 10b
5
OLP_SHRT_DLY = 11b
11.5
After tWAKE and tSHORTS elapse
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V
V
mV
mA
ms
5
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V
mV
VVM +
1.4
Negative clamping voltage
V
13
DRV8343-Q1
SLVSE12A – MARCH 2018 – REVISED APRIL 2019
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Electrical Characteristics (continued)
Over recommended operating conditions 5.5 ≤ VVM ≤ 60 V (unless otherwise noted). Typical limits apply for VVM = 24 V
PARAMETER
Offline short-tobattery and short-toGND diagnostic delay
tSHORTS
TEST CONDITIONS
SPI Device
H/W Device
SPI Device
VVDS_OCP
VDS overcurrent
trip voltage
H/W Device
MIN
0.1
OLP_SHRT_DLY = 01b
0.5
OLP_SHRT_DLY = 10b
2
OLP_SHRT_DLY = 11b
4.4
After tWAKE elapses
VDS and VSENSE
overcurrent deglitch
time
SPI Device
2
0.06
0.11
VDS_LVL = 0001b
0.08
0.13
0.18
VDS_LVL = 0010b
0.15
0.2
0.25
VDS_LVL = 0011b
0.2
0.26
0.32
VDS_LVL = 0100b
0.24
0.31
0.38
VDS_LVL = 0101b
0.38
0.45
0.52
VDS_LVL = 0110b
0.45
0.53
0.61
VDS_LVL = 0111b
0.51
0.6
0.69
VDS_LVL = 1000b
0.59
0.68
0.77
VDS_LVL = 1001b
0.64
0.75
0.86
VDS_LVL = 1010b
0.81
0.94
1.07
VDS_LVL = 1011b
0.97
1.13
1.29
VDS_LVL = 1100b
1.14
1.3
1.46
VDS_LVL = 1101b
1.34
1.5
1.66
VDS_LVL = 1110b
1.52
1.7
1.88
VDS_LVL = 1111b
1.69
1.88
2.07
VDS = Tied to AGND
0.01
0.06
0.11
VDS = 18 kΩ ± 5% tied to AGND
0.08
0.13
0.18
VDS = 75 kΩ ± 5% tied to AGND
0.2
0.26
0.32
VDS = Hi-Z
0.51
0.6
0.69
VDS = 75 kΩ ± 5% tied to DVDD
0.97
1.13
1.29
VDS = 18 kΩ ± 5% tied to DVDD
1.69
1.88
2.07
SPI Device
V
Disabled
OCP_DEG=000b
2.5
OCP_DEG = 001b
4.75
OCP_DEG = 010b
6.75
OCP_DEG = 011b
8.75
OCP_DEG = 100b
10.25
OCP_DEG = 101b
11.5
OCP_DEG = 110b
16.5
OCP_DEG = 111b
20.5
µs
4.75
SEN_LVL = 00b
VSENSE overcurrent
trip voltage
UNIT
ms
0.01
H/W Device
VSEN_OCP
MAX
VDS_LVL = 0000b
VDS = Tied to DVDD
tOCP_DEG
TYP
OLP_SHRT_DLY = 00b
0.25
SEN_LVL = 01b
0.5
SEN_LVL = 10b
0.75
SEN_LVL = 11b
1
H/W Device
V
1
TRETRY = 00b
2
TRERTY = 01b
4
TRETRY = 10b
6
tRETRY
Overcurrent fault retry
time
THYS
Thermal hysteresis
Die temperature, TJ
TOTSD
Thermal shutdown temperature
Die temperature, TJ
150
170
188
°C
TOTW
Thermal warning temperature
Die temperature, TJ
130
150
169
°C
SPI Device
TRETRY = 11b
14
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ms
8
20
°C
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7.6 SPI Timing Requirements
Over recommended operating conditions unless otherwise noted. Typical limits apply for VVM = 24 V
MIN
tREADY
SPI ready after enable
tCLK
SCLK minimum period
tCLKH
NOM
MAX
VM > UVLO, ENABLE = 3.3 V
1
UNIT
ms
100
ns
SCLK minimum high time
50
ns
tCLKL
SCLK minimum low time
50
ns
tSU_SDI
SDI input data setup time
20
ns
tH_SDI
SDI input data hold time
30
tD_SDO
SDO output data delay time
tSU_nSCS
nSCS input setup time
50
ns
tH_nSCS
nSCS input hold time
50
ns
tHI_nSCS
nSCS minimum high time before active low
500
ns
tDIS_nSCS
nSCS disable time
tHI_nSCS
ns
SCLK high to SDO valid, CL = 20 pF
30
nSCS high to SDO high impedance
ns
10
tSU_nSCS
ns
tH_nSCS
nSCS
tCLK
SCLK
tCLKH
SDI
X
tCLKL
MSB
LSB
X
tSU_SDI tH_SDI
SDO
Z
MSB
LSB
tD_SDO
Z
tDIS_nSCS
Figure 1. SPI Slave Mode Timing Diagram
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7.7 Typical Characteristics
30
VM sleep mode supply current I VMQ (µA)
VM Operating supply current IVM (mA)
13.5
13.25
13
12.75
12.5
12.25
12
11.75
11.5
11.25
TA = -40°C
TA = 25°C
TA = 125°C
11
10.75
10.5
25
20
Ta -40
Ta 125
15
10
5
0
5
10
15
20
25
30 35
VM (V)
40
45
50
55
60
5
No PWM Switching
12
9
6
3
IVCP = 0mA
IVCP = 12.5mA
IVCP = 25mA
29
37
VM (V)
45
53
45
55
60
D002
10
Ta = -40
Ta = 25
Ta = 125
8
6
4
2
0
0
60
3
6
9
12
IVCP (mA)
D003
TA = 25°C
15
D004
VM = 8V
Figure 4. VCP w.r.t VM over VM voltage > 13V
16
35
VM (V)
Figure 3. VM Sleep Mode Supply Current
VCP operating voltage with respect to VM (V)
VCP operating voltage with respect to VM (V)
Figure 2. VM Operating Supply Current
21
25
ENABLE = 0V
15
0
13
15
D001
Figure 5. VCP w.r.t VM over output load IVCP
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8 Detailed Description
8.1 Overview
The DRV8343-Q1 device is an integrated gate driver for three-phase motor driver automotive applications. These
devices decrease system complexity by integrating three independent half-bridge gate drivers, charge pump, and
linear regulator for the supply voltages of the high-side and low-side gate drivers.The device also integrates three
current shunt (or current sense) amplifiers. A standard serial peripheral interface (SPI) provides a simple method
for configuring the various device settings and reading fault diagnostic information through an external controller.
Alternatively, a hardware interface (H/W) option allows for configuring the most common settings through fixed
external resistors.
The gate drivers support external N-channel high-side and low-side power MOSFETs and can drive up to 1-A
source, 2-A sink peak currents. A doubler charge pump generates the supply voltage of the high-side gate drive.
This charge pump architecture regulates the VCP output voltage for driving high-side power MOSFET. The
supply voltage of the low-side gate driver is generated using a linear regulator from the VM power supply that
regulates for driving low-side power MOSFET. A Smart Gate Drive architecture provides the ability to
dynamically adjust the strength of the gate drive output current which lets the gate driver control the VDS
switching speed of the power MOSFET. This feature lets the user remove the external gate drive resistors and
diodes, reducing the component count in the bill of materials (BOM), cost, and area of the printed circuit board
(PCB). The architecture also uses an internal state machine to protect against short-circuit events in the gate
driver, control the half-bridge dead time, and protect against dV/dt parasitic turnon of the external power
MOSFET.
The DRV8343-Q1 device integrates three bidirectional current sense amplifiers for monitoring the current level
through each of the external half-bridges using a low-side shunt resistor. The gain setting of the current sense
amplifiers can be adjusted through the SPI or hardware interface. The SPI method providing additional flexibility
to adjust the output bias point.
In addition to the high level of device integration, the DRV8343-Q1 device provides a wide range of integrated
protection features. These features include power supply undervoltage lockout (UVLO), charge pump
undervoltage lockout (CPUV), short to supply (SHT_BAT), short-to-ground (SHT_GND), open-load detection
(OLD), VDS overcurrent monitoring (OCP), gate driver short-circuit detection (GDF), and overtemperature
shutdown (OTW and OTSD). Fault events are indicated by the nFAULT pin with detailed information available in
the SPI registers on the SPI device version.
The DRV8343-Q1 device is available in a 0.5-mm pin pitch, 7 × 7 mm, HTQFP surface-mount package.
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8.2 Functional Block Diagram
VM
VM
VDRAIN
VM
VCP
VCP
>10 …F 4.7 …F 1 …F
47 nF
GHA
HS
SHA
VCP
Charge
Pump
CPH
DLA
VGLS
CPL
GLA
LS
VGLS
30 mA
1 …F
VGLS
Linear
Regulator
SLA
Gate Driver
VM
DVDD
AGND
PGND
VCP
DVDD
Linear
Regulator
GHB
HS
SHB
Power
DLB
VGLS
Digital
Core
ENABLE
GLB
LS
INHA
SLB
Gate Driver
INLA
VM
Smart Gate
Drive
INHB
VCP
GHC
HS
Protection
INLB
SHC
Control
Inputs
DLC
VGLS
INHC
GLC
LS
INLC
VCC
Gate Driver
RnFAULT
MODE
IDRIVE
nFAULT
Fault Output
VDS
SLC
GAIN
VCC
SPC
VREF
0.1 …F
AV
SNC
RSEN
SOC
SPB
SOB
SOA
Output
Offset
Bias
AV
SNB
RSEN
SPA
CAL
AV
SNA
RSEN
Figure 6. Block Diagram for DRV8343H
18
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Functional Block Diagram (continued)
VM
VM
VDRAIN
VM
VCP
VCP
>10 …F 4.7 …F 1 …F
47 nF
GHA
HS
SHA
VCP
Charge
Pump
CPH
DLA
VGLS
CPL
GLA
LS
VGLS
30 mA
1 …F
SLA
VGLS
Linear
Regulator
Gate Driver
VM
DVDD
VCP
DVDD
Linear
Regulator
AGND
GHB
HS
Power
PGND
SHB
VCC
DLB
Digital
Core
VSDO
0.1 …F
VGLS
GLB
LS
ENABLE
SLB
Gate Driver
INHA
Smart Gate
Drive
INLA
Protection
Control
Inputs
INHB
VM
VCP
GHC
HS
SHC
DLC
INLB
VGLS
GLC
LS
INHC
VCC
INLC
Gate Driver
RPU
VSDO
SDI
SPI
Fault Output
SDO
nFAULT
SLC
SCLK
DVDD
VCC
nSCS
SPC
VREF
0.1 …F
AV
SNC
RSEN
SOC
SOB
SOA
Output
Offset
Bias
SPB
AV
SNB
RSEN
SPA
CAL
AV
SNA
RSEN
Figure 7. Block Diagram for DRV8343S
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8.3 Feature Description
8.3.1 Three Phase Smart Gate Drivers
The DRV8343-Q1 device integrates three, half-bridge gate drivers, each capable of driving high-side and lowside N-channel power MOSFETs. A doubler charge pump provides the correct gate bias voltage to the high-side
MOSFET across a wide operating voltage range in addition to providing 100% support of the duty cycle. An
internal linear regulator provides the gate bias voltage for the low-side MOSFETs. The half-bridge gate drivers
can be used in combination to drive a three-phase motor or separately to drive other types of loads.
The DRV8343-Q1 device implements a Smart Gate Drive architecture which allows the user to dynamically
adjust the gate drive current without requiring external resistors to limit the gate current. Additionally, this
architecture provides a variety of protection features for the external MOSFETs including automatic dead time
insertion, prevent of parasitic dV/dt gate turnon, and gate fault detection.
8.3.1.1 PWM Control Modes
The DRV8343-Q1 device provides eight different PWM control modes in the SPI device and seven different
modes in the H/W device to support various commutation and control methods. Texas Instruments does not
recommend changing the MODE pin or PWM_MODE register during operation of the power MOSFETs. Set all
INHx and INLx pins to logic low before making a MODE pin or PWM_MODE register change. Table 1 shows the
different mode settings for the SPI device. The MODE bit setting of 100b is not available in the H/W device.
Table 1. 6x PWM Mode Truth Table
H/W DEVICE
SPI DEVICE
MODE SETTINGS
Tied to AGND
000b
6x PWM
18 kΩ to AGND
001b
3x PWM
75 kΩ to AGND
010b
1x PWM
Hi-Z
011b
Independent half-bridge (for all three half-bridges)
Not Available
100b
Phases A and B are independent half-bridges, Phase C is independent FET
75 kΩ to DVDD
101b
Phases B and C are independent half-bridges, Phase A is independent FET
18 kΩ to DVDD
110b
Phases A is independent half-bridge, Phase B and C are independent FET
0.47 kΩ to DVDD
111b
Independent MOSFET (for all three half-bridges)
8.3.1.1.1 6x PWM Mode (PWM_MODE = 000b or MODE Pin Tied to AGND)
In 6x PWM mode, each half-bridge supports three output states: low, high, or high-impedance (Hi-Z). The
corresponding INHx and INLx signals control the output state as listed in Table 2.
Table 2. 6x PWM Mode Truth Table
20
INLx
INHx
GLx
GHx
SHx + DLx
0
0
0
1
L
L
Hi-Z
L
H
1
H
0
H
L
L
1
1
L
L
Hi-Z
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6-PWM
INHA
MCU PWM
INLA
MCU PWM
INHB
MCU PWM
INLB
MCU PWM
INHC
MCU PWM
INLC
MCU PWM
Figure 8. 6-PWM Mode
8.3.1.1.2 3x PWM Mode (PWM_MODE = 001b or MODE Pin = 18 kΩ to AGND)
In 3x PWM mode, the INHx pin controls each half-bridge and supports two output states: low or high. The INLx
pin is used to put the half bridge in the Hi-Z state. If the Hi-Z state is not required, tie all INLx pins to logic high.
The corresponding INHx and INLx signals control the output state as listed in Table 3.
Table 3. 3x PWM Mode Truth Table
INLx
INHx
GLx
GHx
SHx + DLx
0
1
X
L
L
Hi-Z
0
H
L
1
L
1
L
H
H
3-PWM
INHA
MCU PWM
INLA
INHB
MCU PWM
INLB
INHC
MCU PWM
INLC
Figure 9. 3-PWM Mode
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8.3.1.1.3 1x PWM Mode (PWM_MODE = 010b or MODE Pin = 75 kΩ to AGND)
In 1x PWM mode, the DRV8343-Q1 device uses 6-step block commutation tables that are stored internally. This
feature allows for a three-phase BLDC motor to be controlled using one PWM sourced from a simple controller.
The PWM is applied on the INHA pin and determines the output frequency and duty cycle of the half-bridges.
The half-bridge output states are managed by the INLA, INHB, and INLB pins which are used as state logic
inputs. The state inputs can be controlled by an external controller or connected directly to the digital outputs of
the Hall effect sensor from the motor (INLA = HALL_A, INHB = HALL_B, INLB = HALL_C). The 1x PWM mode
usually operates with synchronous rectification (low-side MOSFET recirculation); however, the mode can be
configured to use asynchronous rectification (MOSFET body diode freewheeling) on SPI devices. This
configuration is set using the 1PWM_COM bit in the SPI registers.
The INHC input controls the direction through the 6-step commutation table which is used to change the direction
of the motor when Hall effect sensors are directly controlling the state of the INLA, INHB, and INLB inputs. Tie
the INHC pin low if this feature is not required.
The INLC input brakes the motor by turning off all high-side MOSFETs and turning on all low-side MOSFETs
when the INLC pin is pulled low. This brake is independent of the state of the other input pins. Tie the INLC pin
high if this feature is not required. In the SPI device, the brake and coast mode can also be selected by the
1PWM_BRAKE register (see Table 21).
Table 4. Synchronous 1x PWM Mode
GATE DRIVE OUTPUTS (1)
LOGIC AND HALL INPUTS
STATE
INHC = 0
INHC = 1
PHASE A
INLA
INHB
INLB
INLA
INHB
INLB
GHA
PHASE B
GLA
GHB
PHASE C
GLB
GHC
GLC
DESCRIPTION
Stop
0
0
0
0
0
0
L
L
L
L
L
L
Stop
Align
1
1
1
1
1
1
PWM
!PWM
L
H
L
H
Align
1
1
1
0
0
0
1
L
L
PWM
!PWM
L
H
B→C
2
1
0
0
0
1
1
PWM
!PWM
L
L
L
H
A→C
3
1
0
1
0
1
0
PWM
!PWM
L
H
L
L
A→B
4
0
0
1
1
1
0
L
L
L
H
PWM
!PWM
C→B
5
0
1
1
1
0
0
L
H
L
L
PWM
!PWM
C→A
6
0
1
0
1
0
1
L
H
PWM
!PWM
L
L
B→A
(1)
!PWM is the inverse of the PWM signal.
Table 5. Asynchronous 1x PWM Mode 1PWM_COM = 1 (SPI Only)
LOGIC AND HALL INPUTS
STATE
INHC = 0
GATE DRIVE OUTPUTS
INHC = 1
PHASE A
INLA
INHB
INLB
INLA
INHB
INLB
PHASE B
GHA
GLA
GHB
PHASE C
GLB
GHC
GLC
DESCRIPTION
Stop
0
0
0
0
0
0
L
L
L
L
L
L
Stop
Align
1
1
1
1
1
1
PWM
L
L
H
L
H
Align
1
1
1
0
0
0
1
L
L
PWM
L
L
H
B→C
2
1
0
0
0
1
1
PWM
L
L
L
L
H
A→C
3
1
0
1
0
1
0
PWM
L
L
H
L
L
A→B
4
0
0
1
1
1
0
L
L
L
H
PWM
L
C→B
5
0
1
1
1
0
0
L
H
L
L
PWM
L
C→A
6
0
1
0
1
0
1
L
H
PWM
L
L
L
B→A
Figure 10 and Figure 11 show the different possible configurations in 1x PWM mode.
22
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MCU_GPIO
MCU_GPIO
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INHA
INLA
INHB
INLB
MCU_GPIO
MCU_GPIO
MCU_GPIO
INHC
INLC
INHA
MCU_PWM
PWM
INLA
STATE0
INHB
STATE1
INLB
BLDC Motor
STATE2
INHC
MCU_GPIO
DIR
INLC
MCU_GPIO
PWM
H
STATE0
STATE1
H
BLDC Motor
STATE2
H
DIR
nBRAKE
nBRAKE
Figure 10. 1x PWM—Simple Controller
Figure 11. 1x PWM—Hall Effect Sensor
8.3.1.1.4 Independent Half-Bridge PWM Mode (PWM_MODE = 011b or MODE Pin is > 1.5 MΩ to AGND or Hi-Z)
In independent half-bridge PWM mode, the INHx pin controls each half-bridge independently and supports two
output states: low or high. The corresponding INHx and INLx signals control the output state as listed in Table 6.
The INLx pin is used to change the half-bridge to high impedance. If the high-impedance (Hi-Z) state is not
required, tie all INLx pins logic high.
Table 6. Independent Half-Bridge Mode Truth Table
INLx
INHx
GLx
GHx
0
X
L
L
1
0
H
L
1
1
L
H
8.3.1.1.5 Phases A and B are Independent Half-Bridges, Phase C is Independent FET (MODE = 100b)
In this mode, phases A and B are independent half-bridge control, with independent fault handling and dead time
enforcement by the device. Phase C is independent FET mode where the dead time inserted by the device is
bypassed and both MOSFETs can be turned-on at the same time. This mode is not available in the H/W version.
8.3.1.1.6 Phases B and C are Independent Half-Bridges, Phase A is Independent FET (MODE = 101b or MODE Pin is
75 kΩ to DVDD)
In this mode, phases B and C are independent half-bridge control, with independent fault handling and dead time
enforcement by the device. Phase A is independent FET mode where the dead time inserted by the device is
bypassed and both MOSFETs can be turned-on at the same time.
8.3.1.1.7 Phases A is Independent Half-Bridge, Phases B and C are Independent FET (MODE = 110b or MODE Pin is
18 kΩ to DVDD)
In this mode, phase A is independent half-bridge control, with dead time enforcement by the device. Phases B
and C are independent FET mode where the dead time is bypassed and both MOSFETs in a given phase can
be turned-on at the same time. Fault handling is also done independently for each FET in phases B and C.
8.3.1.1.8 Independent MOSFET Drive Mode (PWM_MODE = 111b or MODE Pin = 0.47 kΩ to DVDD)
In independent MOSFET drive mode, the INHx and INLx pins control the outputs, GHx and GLx, respectively.
This control mode lets the DRV8343-Q1 device drive separate high-side and low-side loads with each halfbridge. These types of loads include unidirectional brushed DC motors, solenoids, and low-side and high-side
switches. In this mode, turning on both the high-side and low-side MOSFETs at the same time in a given halfbridge gate driver is possible to use the device as a high-side or low-side driver. The dead time (tDEAD) is
bypassed in the mode and must be inserted by the external MCU.
Table 7. Independent PWM Mode Truth Table
INLx
INHx
GLx
0
0
L
GHx
L
0
1
L
H
1
0
H
L
1
1
H
H
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Figure 12 shows how the DRV8343-Q1 device can be used to connect a high-side load and a low-side load at
the same time with one half-bridge and drive the loads independently. In this mode, the VDS monitors are active
for both the MOSFETs to protect from an overcurrent condition.
VDS
+
±
VM
VDRAIN
VCP
GHx
HS
INHx
Load
SHx
INLx
DLx
VGLS
GLx
LS
Load
SLx/SPx
Gate Driver
VDS
+
±
Figure 12. Independent PWM High-Side and Low-Side Drivers
If the half-bridge is used to implement only a high-side or low-side driver, using the VDS monitors to help protect
from an overcurrent condition is possible as shown in Figure 13 or Figure 14. The unused gate driver can stay
disconnected.
VDS
+
±
VDS
VM
+
±
VCP
VCP
INHx
GHx
HS
GHx
HS
INHx
DLx
VGLS
DLx
INLx
VGLS
GLx
LS
Load
SHx
SHx
INLx
VM
VDRAIN
VDRAIN
GLx
Load
LS
SLx/SPx
Gate Driver
+
VDS ±
+
VDS ±
Figure 13. One High-Side Driver
24
SLx/SPx
Gate Driver
Figure 14. One Low-Side Driver
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Figure 15 shows how the DRV8343-Q1 device can be used to connect a solenoid load where both the high-side
and low-side MOSFETs can be turned on at the same time to drive the load without causing shoot-through. TI
recommends having the external diodes for current recirculation. If a half-bridge is not used, the gate pins (GHx
and GLx) can stay unconnected and the sense pins (SHx and DLx) can be tied directly or with a resistor to GND.
VDRAIN
VDRAIN
HS_VSD
HS_VSD
+
±
GHx
HS_VSD
+
±
GHx
+
±
SHx
SHx
GHx
SHx
PH_B
PH_A
PH_C
DLx
DLx
LS_VSD
VDRAIN
GLx
LS_VSD
+
DLx
GLx
LS_VSD
+
±
±
SLx
GLx
+
±
SLx
SLx
Figure 15. Solenoid Drive Configuration
8.3.1.2 Device Interface Modes
The DRV8343-Q1 device supports two different interface modes (SPI and hardware) to let the end application
design for either flexibility or simplicity. The two interface modes share the same four pins, allowing the different
versions to be pin-to-pin compatible. This compatibility lets application designers evaluate with one interface
version and potentially switch to another with minimal modifications to their circuit design and layout.
8.3.1.2.1 Serial Peripheral Interface (SPI)
The SPI devices support a serial communication bus that lets an external controller send and receive data with
the DRV8343-Q1 device. This support lets the external controller configure device settings and read detailed
fault information. The interface is a four wire interface using the SCLK, SDI, SDO, and nSCS pins which are
described as follows:
• The SCLK pin is an input that accepts a clock signal to determine when data is captured and propagated on
the SDI and SDO pins.
• The SDI pin is the data input.
• The SDO pin is the data output. The SDO pin has a push-pull output structure.
• The nSCS pin is the chip select input. A logic low signal on this pin enables SPI communication with the
DRV8343-Q1 device.
For more information on the SPI, see the SPI Communication section.
8.3.1.2.2 Hardware Interface
Hardware interface devices convert the four SPI pins into four
IDRIVE, MODE, and VDS. This conversion lets the application
settings by tying the pin logic high or logic low, or with a simple
requirement for an SPI bus from the external controller. General
the nFAULT pin.
•
•
•
•
The
The
The
The
resistor-configurable inputs which are GAIN,
designer configure the most common device
pullup or pulldown resistor. This removes the
fault information can still be obtained through
GAIN pin configures the gain of the current sense amplifier.
IDRIVE pin configures the gate drive current strength.
MODE pin configures the PWM control mode.
VDS pin configures the voltage threshold of the VDS overcurrent monitors.
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For more information on the hardware interface, see the Pin Diagrams section.
DVDD
RGAIN
SCLK
DVDD
GAIN
SPI
DVDD
Hardware
Interface
DVDD
SDI
IDRIVE
VSDO
DVDD
MODE
SDO
DVDD
DVDD
VDS
nSCS
RVDS
Figure 17. Hardware Interface
Figure 16. SPI
8.3.1.3 Gate Driver Voltage Supplies
The voltage supply for the high-side gate driver is created using a doubler charge pump that operates from the
VM voltage supply input. The charge pump lets the gate driver correctly bias the high-side MOSFET gate with
respect to the source across a wide input supply voltage range. The charge pump is regulated to keep a fixed
output voltage VVCP and supports an average output current IGATE_HS. The charge pump is continuously
monitored for undervoltage events to prevent under-driven MOSFET conditions. The charge pump requires a
ceramic capacitor between the VM and VCP pins to act as the storage capacitor. Additionally, a flying capacitor
is required between the CPH and CPL pins.
VM
VM
CVCP
VCP
CPH
VM
Charge
Pump
Control
CFLY
CPL
Figure 18. Charge Pump Architecture
The voltage supply of the low-side gate driver is created using a linear regulator that operates from the VM
voltage supply input. The linear regulator lets the gate driver correctly bias the low-side MOSFET gate with
respect to ground. The linear regulator output is VGSL and supports an output current IGATE_LS.
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8.3.1.4 Smart Gate Drive Architecture
The DRV8343-Q1 gate drivers use an adjustable, complimentary, push-pull topology for both the high-side and
low-side drivers. This topology allows for both a strong pullup and pulldown of the external MOSFET gates.
Gate Drive (Internal)
VGATE
VGATE
MOSFET (External)
VGATE
VGATE
OFF
1A
OFF
ISOURCE
OFF
2A
OFF
210 mA
OFF
420 mA
60 mA
ON
120 mA
OFF
20 mA
OFF
10 mA
VDRAIN
Figure 19. Charge Pump Architecture
Additionally, the gate drivers use a Smart Gate Drive architecture to provide additional control of the external
power MOSFETs, additional steps to protect the MOSFETs, and optimal tradeoffs between efficiency and
robustness. This architecture is implemented through two components called IDRIVE and TDRIVE which are
described in the IDRIVE: MOSFET Slew-Rate Control section and TDRIVE: MOSFET Gate Drive Control
section. Figure 20 shows the high-level functional block diagram of the gate driver.
The IDRIVE gate drive current and TDRIVE gate drive time should be initially selected based on the parameters
of the external power MOSFET used in the system and the desired rise and fall times (see the Application and
Implementation section).
The high-side gate driver also implements a Zener clamp diode to help protect the external MOSFET gate from
overvoltage conditions in the case of external short-circuit events on the MOSFET.
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VCP
INHx
INLx
VM
Control
Inputs
GHx
Level
Shifters
150 k
SHx
VGS
+
±
VGLS
DLx
Digital
Core
GLx
Level
Shifters
150 k
SLx/SPx
VGS
+
±
PGND
Figure 20. Gate Driver Block Diagram
8.3.1.4.1 IDRIVE: MOSFET Slew-Rate Control
The IDRIVE component implements adjustable gate drive current to control the MOSFET VDS slew rates. The
MOSFET VDS slew rates are a critical factor for optimizing radiated emissions, energy, and duration of diode
recovery spikes, dV/dt gate turnon resulting in shoot-through, and switching voltage transients related to
parasitics in the external half-bridge. The IDRIVE component operates on the principal that the MOSFET VDS
slew rates are predominately determined by the rate of gate charge (or gate current) delivered during the
MOSFET QGD or Miller charging region. By letting the gate driver adjust the gate current, the gate driver can
effectively control the slew rate of the external power MOSFETs.
The IDRIVE component lets the DRV8343-Q1 device dynamically switch between gate drive currents either
through a register setting on SPI devices or the IDRIVE pin on hardware interface devices. The SPI devices
provide 16 IDRIVE settings ranging from 1.5-mA to 1-A source and 3-mA to 2-A sink. Hardware interface devices
provide 7 IDRIVE settings within the same ranges. The setting of the gate drive current is delivered to the gate
during the turnon and turnoff of the external power MOSFET for the tDRIVE duration. After the MOSFET turnon or
turnoff, the gate driver switches to a smaller hold current (IHOLD) to improve the gate driver efficiency. In the event
of an overcurrent condition, the IDRIVE component is automatically decreased to help prevent device damage.
For additional details on the IDRIVE settings, see the Register Maps section for the SPI devices and the Pin
Diagrams section for the hardware interface devices.
8.3.1.4.2 TDRIVE: MOSFET Gate Drive Control
The TDRIVE component is an integrated gate drive state machine that provides automatic dead time insertion
through handshaking between the high-side and low-side gate drivers, parasitic dV/dt gate turnon prevention,
and MOSFET gate fault detection.
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The first component of the TDRIVE state machine is automatic dead time insertion. Dead time is period of time
between the switching of the external high-side and low-side MOSFETs to make sure that they do not cross
conduct and cause shoot-through. The DRV8343-Q1 device uses VGS voltage monitors to measure the MOSFET
gate-to-source voltage and determine the correct time to switch instead of relying on a fixed time value. This
feature lets the dead time of the gate driver adjust for variation in the system such as temperature drift and
variation in the MOSFET parameters. An additional digital dead time (tDEAD) can be inserted and is adjustable
through the registers on SPI devices.
The second component of the TDRIVE state machine is parasitic dV/dt gate turnon prevention. To implement this
component, the TDRIVE state machine enables a strong pulldown current (ISTRONG) on the opposite MOSFET
gate whenever a MOSFET is switching. The strong pulldown occurs for the TDRIVE duration. This feature helps
remove parasitic charge that couples into the MOSFET gate when the voltage half-bridge switch node slews
rapidly.
The third component implements a gate-fault detection scheme to detect pin-to-pin solder defects, a MOSFET
gate failure, or a MOSFET gate stuck-high or stuck-low voltage condition. This implementation is done with a pair
of VGS gate-to-source voltage monitors for each half-bridge gate driver. When the gate driver receives a
command to change the state of the half-bridge it starts to monitor the gate voltage of the external MOSFET. If,
at the end of the tDRIVE period, the VGS voltage has not increased the correct threshold, the gate driver reports a
fault. To make sure that a false gate drive fault (GDF) is not detected, a tDRIVE time should be selected that is
longer than the time required to charge or discharge the MOSFET gate. The tDRIVE time does not increase the
PWM time and will terminate if another PWM command is received while active. In the SPI device, for IDRIVE bit
settings of 0000b, 0001b, 0010b, and 0011b, a longer tDRIVE time of 20-µs is automatically selected by the
TDRIVE_MAX bit. If the 20-µs tDRVIE time is not required, write a 0 to the TDRIVE_MAX bit to disable it and set
the tDRIVE time by the TDRIVE bits. For all other IDRIVE settings, writing to the TDRIVE_MAX bit is disabled. This
option is not available in the H/W device.
For additional details on the TDRIVE settings, see the Register Maps section for SPI devices and the Pin
Diagrams section for hardware interface devices. Figure 21 shows an example of the TDRIVE state machine in
operation.
VINHx
VINLx
VGHx
tDEAD
IHOLD
IDRIVE
tDEAD
IHOLD
IHOLD
ISTRONG
IGHx
IDRIVE
tDRIVE
IHOLD
tDRIVE
VGLx
tDEAD
tDEAD
IHOLD
IDRIVE
IHOLD
ISTRONG
IHOLD
IGLx
IDRIVE
IHOLD
tDRIVE
tDRIVE
Figure 21. TDRIVE State Machine
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8.3.1.4.3 Propagation Delay
The propagation delay time (tpd) is measured as the time between an input logic edge to a detected output
change. This time has three parts consisting of the digital input deglitcher delay, the digital propagation delay,
and the delay through the analog gate drivers.
The input deglitcher prevents high-frequency noise on the input pins from affecting the output state of the gate
drivers. To support multiple control modes and dead time insertion, a small digital delay is added as the input
command propagates through the device. Lastly, the analog gate drivers have a small delay that contributes to
the overall propagation delay of the device.
8.3.1.4.4 MOSFET VDS Monitors
The gate drivers implement adjustable VDS voltage monitors to detect overcurrent or short-circuit conditions on
the external power MOSFETs. When the monitored voltage is greater than the VDS trip point (VVDS_OCP) for
longer than the deglitch time (tOCP), an overcurrent condition is detected and action is taken according to the
device VDS fault mode.
The high-side VDS monitors measure the voltage between the VDRAIN and SHx pins.The low-side VDS monitors
measure the voltage between the DLx and SLx pins. If the current sense amplifier is unused, tie the SP pins to
the common ground point of the external half-bridges.
For the SPI devices, the reference point of the low-side VDS monitor can be changed between the SPx and SNx
pins if desired with the LS_REF register setting.
The VVDS_OCP threshold is programmable from 0.06 V to 1.88 V. For additional information on the VDS monitor
levels, see the Register Maps section for SPI devices and in the Pin Diagrams section hardware interface device.
VM
VDS
+
±
VDS
VVDS_OCP
VDRAIN
+
±
GHx
SHx
VDS
+
±
VDS
VVDS_OCP
DLx
+
±
GLx
SLx
0
1
LS_REF
(SPI Only)
SNx
RSENSE
PGND
Figure 22. DRV8343-Q1 VDS Monitors
8.3.1.4.5 VDRAIN Sense Pin
The DRV8343-Q1 device provides a separate sense pin for the common point of the high-side MOSFET drain.
This pin is called VDRAIN. This pin lets the sense line for the overcurrent monitors (VDRAIN) and the power
supply (VM) stay separate and prevent noise on the VDRAIN sense line. This separation also lets
implementation of a small filter on the gate driver supply (VM) or insertion of a boost converter to support lower
voltage operation if desired. Care must still be used when designing the filter or separate supply because VM is
still the reference point for the VCP charge pump that supplies the high-side gate drive voltage (VGSH). The VM
supply must not drift too far from the VDRAIN supply to avoid violating the VGS voltage specification of the
external power MOSFETs.
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8.3.1.4.6 nFAULT Pin
The nFAULT pin has an open-drain output and should be pulled up to a 5 V or 3.3 V supply. When a fault is
detected, the nFAULT line is logic low. For a 3.3-V pullup the nFAULT pin can be tied to the DVDD pin with a
resistor (refer to the Application and Implementation section). For a 5-V pullup an external 5-V supply must be
used.
Output
nFAULT
Figure 23. nFAULT Pin
During the power-up sequence, or when going from sleep mode, the digital core of the device is enabled to a VM
voltage of approximately 3.3 V and the device is fully operational after VM exceeds 5.5 V. After the digital core is
alive if the VM does not exceed 5.5 V within 100-µs the device will flag a UVLO fault. In the H/W device, the
nFAULT pin is driven low. In the SPI device, the FAULT and ULVO bits will be latched high
8.3.2 DVDD Linear Voltage Regulator
A 3.3-V, 30-mA linear regulator is integrated into the DRV8343-Q1 device and is available for use by external
circuitry. This regulator can provide the supply voltage for a low-power MCU or other circuitry supporting low
current. The output of the DVDD regulator should be bypassed near the DVDD pin with a X5R or X7R, 1-µF, 6.3V ceramic capacitor routed directly back to the adjacent AGND ground pin.
The DVDD nominal, no-load output voltage is 3.3 V. When the DVDD load current exceeds 30 mA, the regulator
functions like a constant-current source. The output voltage drops significantly with a current load greater than 30
mA.
VM
REF
+
±
DVDD
3.3 V, 30 mA
0.1 …F
AGND
Figure 24. DVDD Linear Regulator Block Diagram
Use Equation 1 to calculate the power dissipated in the device by the DVDD linear regulator.
P
VVM VDVDD u IDVDD
(1)
For example, at a VVM of 24 V, drawing 20 mA out of DVDD results in a power dissipation as shown in
Equation 2.
P 24 V 3.3 V u 20 mA 414 mW
(2)
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8.3.3 Pin Diagrams
Figure 25 shows the input structure for the logic level pins, INHx, INLx, CAL, ENABLE, nSCS, SCLK, and SDI.
The input can be driven with a voltage or external resistor.
DVDD
STATE
RESISTANCE
INPUT
VIH
Tied to DVDD
Logic High
VIL
Tied to AGND
Logic Low
100 k
Figure 25. Logic-Level Input Pin Structure
Figure 26 shows the structure of the four level input pin, GAIN, on hardware interface devices. The input can be
set with an external resistor.
GAIN
DVDD
STATE
RESISTANCE
DVDD
40 V/V
+
VI4
Tied to DVDD
VI3
Hi-Z (>500 kŸ WR
AGND)
VI2
47 NŸ “5%
to AGND
VI1
Tied to AGND
50 k
±
20V/V
84 k
+
±
10 V/V
+
±
5 V/V
Figure 26. Four Level Input Pin Structure
Figure 27 shows the structure of the seven level input pins, MODE, IDRIVE and VDS, on hardware interface
devices. The input can be set with an external resistor.
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IDRIVE
VDS
MODE
1/2 A
Disabled
Independent MOSFET
260 / 520 mA
1.88 V
Ph A as Ind. Half bridge
Ph B & Ph C as Ind. FET
200 / 400 mA
1.13 V
Ph B & Ph C as Ind. Half
bridge, Ph A as Ind. FET
60 / 120 mA
0.60 V
Independent
Half-Bridge
10 / 20 mA
0.26 V
1x PWM
5 / 10 mA
0.13 V
3x PWM
1.5 / 3 mA
0.06 V
6x PWM
+
STATE
RESISTANCE
VI7
0.47 NŸ “ 5%
to DVDD (1)
VI6
18 k ± 5%
to DVDD
VI5
75 k ± 5%
to DVDD
VI4
Hi-Z (>1.5 MŸ
to AGND)
VI3
75 k ± 5%
to AGND
VI2
18 NŸ “5%
to AGND
VI1
±
DVDD
DVDD
+
±
73 k
+
±
73 k
+
±
+
Tied to AGND
±
+
±
Figure 27. Seven Level Input Pin Structure
(1)
Figure 28 shows the structure of the open-drain output pin, nFAULT. The open-drain output requires an external
pullup resistor to function correctly.
DVDD
RPU
STATE
STATUS
No Fault
Inactive
OUTPUT
Fault
Active
Active
Inactive
Figure 28. Open-Drain Output Pin Structure
8.3.4 Low-Side Current Sense Amplifiers
The DRV8343-Q1 integrates three, high-performance low-side current sense amplifiers for current
measurements using low-side shunt resistors in the external half-bridges. Low-side current measurements are
commonly used to implement overcurrent protection, external torque control, or brushless DC commutation with
the external controller. All three amplifiers can be used to sense the current in each of the half-bridge legs or one
amplifier can be used to sense the sum of the half-bridge legs. The current sense amplifiers include features
such as programmable gain, offset calibration, unidirectional and bidirectional support, and a voltage reference
pin (VREF).
(1)
VI7 requires a 0.47 kΩ resistor to DVDD for MODE input pin. VDS and IDRIVE pins can be directly tied to DVDD.
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8.3.4.1 Bidirectional Current Sense Operation
The SOx pin on the DRV8343 outputs an analog voltage equal to the voltage across the SPx and SNx pins
multiplied by the gain setting (GCSA). The gain setting is adjustable between four different levels: 5 V/V, 10 V/V,
20 V/V, and 40 V/V. Use Equation 3 to calculate the current through the shunt resistor.
VVREF
VSOx
2
I
GCSA u RSENSE
(3)
R2
R3
R4
R5
R6
SOx
I
R1
VCC
±
VREF
+
0.1 …F
R2
SPx
R1
RSENSE
SNx
½
+
R3
±
R4
R5
Figure 29. Bidirectional Current Sense Configuration
SO (V)
VREF
VVREF / 2
VLINEAR
SP ± SN (V)
Figure 30. Bidirectional Current Sense Output
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I
SP
SO
R
AV
SN
SO
VREF
SP ± SN
±0.3 V
VVREF ± 0.25 V
±I × R
VSO(range±)
VSO(off)max
VVREF / 2
VOFF,
VDRIFT
0V
VSO(off)min
VSO(range+)
0.25 V
I×R
0.3 V
0V
Figure 31. Bidirectional Current Sense Regions
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8.3.4.2 Unidirectional Current Sense Operation (SPI only)
On the DRV8343-Q1 SPI device, use the VREF_DIV bit to remove the VREF divider. In this case the curren
sense amplifier operates unidirectionally and the SOx pin outputs an analog voltage equal to the voltage across
the SPx and SNx pins multiplied by the gain setting (GCSA). Use Equation 4 to calculate the current through the
shunt resistor.
VVREF VSOx
I
GCSA u RSENSE
(4)
R2
R3
R4
R5
R6
SOx
I
R1
±
+
SPx
R1
RSENSE
SNx
VCC
R2
VREF
+
0.1 …F
R3
±
R4
R5
Figure 32. Unidirectional Current-Sense Configuration
SO (V)
VREF
VVREF ± 0.3 V
VLINEAR
SP ± SN (V)
Figure 33. Unidirectional Current-Sense Output
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I
SP
SO
R
AV
SN
SO
VREF
VVREF ± 0.25 V
VSO(off)max
SP ± SN
VOFF,
VVREF ± 0.3 V
0V
VDRIFT
VSO(off)min
VSO(range)
I×R
0.3 V
0.25 V
0V
Figure 34. Unidirectional Current-Sense Regions
8.3.4.3 Amplifier Calibration Modes
To minimize DC offset and drift over temperature, a DC calibration mode is provided and enabled through the
SPI register (CSA_CAL_X). This option is not available on the H/W interface device. When the calibration setting
is enabled, the inputs to the amplifier are shorted and the shunt resistor is disconnected. DC calibration can be
done at any time, even when the half-bridges are operating. For the best results, perform manual calibration
during the switching OFF period to decrease the potential noise impact to the amplifier. Figure 35 shows a
diagram of the calibration mode. When a CSA_CAL_X bit is enabled, the corresponding amplifier goes to the
calibration mode.
In both the SPI and H/W device options, the CAL pin can be used to perform DC calibration to all the three
amplifiers at the same time. When the CAL pin is pulled high, the inputs of all the three amplifiers are shorted
and the shunt resistors are disconnected which lets the host microcontroller perform manual calibration.
RF
SOx
ROUT
RSP
!CAL
SP
RSN
!CAL
SN
VREF
+
CAL
RSENSE
CAL
RG
+
-
Figure 35. Amplifier Manual Calibration
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In addition to the manual calibration, the DRV8343-Q1 device provides an auto calibration feature on both the
SPI and H/W device versions to minimize the amplifier input offset after power up and during run time to account
for temperature and device variation. Auto calibration is automatically performed on device power up for both the
H/W and SPI device options. The power up auto calibration starts immediately after the VREF pin crosses the
minimum operational VREF voltage. Wait 50 µs for the power up auto calibration routine to complete after the
VREF pin voltage crosses the minimum VREF operational voltage. The auto calibration functions by performing a
trim routine of the amplifier to minimize the amplifier input offset, after which the trim codes are stored in the
device and the amplifiers are ready for normal operation. For the SPI device option, auto calibration can also be
performed again during run time by enabling the CAL_MODE register setting.
NOTE
Auto calibration happens only in the bidirectional mode. If unidirectional mode is selected
and auto calibration is commanded, the amplifier will switch to bidirectional mode to
perform the auto calibration routine. After auto calibration routine is complete, the amplifier
will revert to unidirectional mode.
For the SPI device option, auto calibration can also be performed again during run time by enabling the
AUTO_CAL register setting. Auto calibration can then be commanded with the corresponding CSA_CAL_X
register setting to rerun the auto calibration routine. During auto calibration all of the amplifiers will be configured
for the maximum gain setting in order to improve the accuracy of the calibration routine.
For manual calibration, after writing a 1 to the CAL_CSA_X bits or taking the CAL pin high, the micro-controller
needs to wait for 50 µs before performing manual calibration. This 50 µs wait time is for the auto calibration
routine to complete. TI recommends that after the 50 µs expires, the micro-controller reads the outputs of the
amplifiers to determine the offset and then perform the manual calibration routine.
Table 8. CAL and CAL_CSA_X table
SPI device option
H/W device option
CAL_MODE = 0b
CAL_MODE = 1b
CSA_CAL_X = 1b
Manual calibration
Auto calibration
N/A
CAL pin = High
Manual calibration
Auto calibration
Manual Calibration
8.3.4.4 MOSFET VDS Sense Mode (SPI Only)
The current sense amplifiers on the DRV8343-Q1 SPI device can be configured to amplify the voltage across the
external low-side MOSFET VDS. This configuration lets the external controller measure the voltage drop across
the MOSFET RDS(on) without the shunt resistor and then calculate the half-bridge current level. This setting is not
available in the H/W device.
To enable this mode set the CSA_FET bit to 1. The positive input of the amplifier is then internally connected to
the DLx pin with an internal clamp to prevent high voltage on the DLx pin from damaging the sense amplifier
inputs. During this mode of operation, the SPx pins should stay disconnected. When the CSA_FET bit is set to 1,
the negative reference for the low-side VDS monitor is automatically set to the SNx pin, regardless of the state of
the state of the LS_REF bit. This setting is implemented to prevent disabling of the low-side VDS monitor.
If the system operates in MOSFET VDS current sense mode, route the DLx and SNx pins with Kelvin connections
across the drain and source of the external low-side MOSFETs.
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VM
VM
VDRAIN
High-Side
High-Side
VDS Monitor
VDS
VDRAIN
VDS Monitor
+
±
VDS
GHx
(SPI only)
GHx
SHx
CSA_FET = 0
+
±
(SPI only)
DLx
SHx
CSA_FET = 1
DLx
LS_REF = 0
LS_REF = X
Low-Side
VDS Monitor
Low-Side
+
VDS
±
VDS Monitor
GLx
VDS
0
+
±
1
GLx
0
1
10 k
10 k
SPx
10 k
SOx
SLx
10 k
RSENSE
AV
10 k
SNx
SOx
SLx
AV
10 k
AGND
SPx
SNx
AGND
Figure 36. Resistor Sense Configuration
Figure 37. VDS Current Sense Mode
When operating in MOSFET VDS current sense mode, the amplifier is enabled at the end of the tDRIVE time. At
this time, the amplifier input is connected to the DLx pin, and the SOx output is valid. When the low-side
MOSFET receives a signal to turn off, the amplifier inputs, SPx and SNx, are shorted together internally.
8.3.5 Gate Driver Protective Circuits
The DRV8343-Q1 device is protected against VM undervoltage, charge pump undervoltage, MOSFET VDS
overcurrent, gate driver shorts, and overtemperature events. The DRV8343-Q1 device also provides a detection
mechanism for open-load, offline short-to-supply, and offline short-to-ground conditions. When a fault occurs, the
individual fault bit is set high along with the global FAULT bit in the FAULT status register for the SPI device. The
FAULT bit is OR’ed with all the other individual status bits. In the H/W device, only the nFAULT pin is driven low
during a fault condition. Some of the protection and detection features can be disabled through SPI in the SPI
device, or the nDIAG pin in the H/W device
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Table 9. Fault Action and Response
FAULT
CONDITION
CONFIGURATION
REPORT
GATE DRIVER
LOGIC
RECOVERY
VM undervoltage
(UVLO)
VVM < VUVLO
—
nFAULT
Hi-Z
Disabled
Automatic:
VVM > VUVLO
Charge pump
undervoltage
(CPUV)
DIS_CPUV = 0b
nFAULT
Hi-Z
Active
VVCP < VCPUV
DIS_CPUV = 1b
None
Active
Active
OCP_MODE = 00b
nFAULT
Hi-Z
Active
Latched:
CLR_FLT, ENABLE Pulse
OCP_MODE = 01b
nFAULT
Hi-Z
Active
Retry:
tRETRY
OCP_MODE = 10b
nFAULT
Active
Active
Report only
OCP_MODE = 11b
None
Active
Active
No action
OCP_MODE = 00b
nFAULT
Hi-Z
Active
Latched:
CLR_FLT, ENABLE Pulse
OCP_MODE = 01b
nFAULT
Hi-Z
Active
Retry:
tRETRY
OCP_MODE = 10b
nFAULT
Active
Active
Report only
OCP_MODE = 11b
None
Active
Active
No action
DIS_GDF = 0b
nFAULT
Hi-Z
Active
Latched:
CLR_FLT, ENABLE Pulse
DIS_GDF = 1b
None
Active
Active
No action
OTW_REP = 0b
None
Active
Active
No action
VDS overcurrent
(VDS_OCP)
VSENSE overcurrent
(SEN_OCP)
Gate driver fault
(GDF)
Thermal warning
(OTW)
Thermal shutdown
(OTSD)
VDS > VVDS_OCP
VSP > VSEN_OCP
Gate voltage stuck > tDRIVE
TJ > TOTW
No load detected
Open load active
(OLA)
No load detected
Offline short-to-supply
(SHT_BAT)
Phase node short-to-supply
Offline short-to-ground
(SHT_GND)
Phase node short-to-ground
Device internal
memory (1)data fault
Memory checksum fault detected
(1)
40
OTW_REP = 1b
nFAULT
Active
Active
Automatic:
TJ < TOTW – THYS
OTSD_MODE = 0b
nFAULT
Hi-Z
Active
Latched:
CLR_FLT, ENABLE Pulse
OTSD_MODE = 1b
nFAULT
Hi-Z
Active
Automatic:
TJ < TOTSD – THYS
EN_OLP = 0b
None
Hi-Z
Active
No action
EN_OLP = 1b
nFAULT
Hi-Z
Active
Report only
EN_OLA_X = 0b
None
Active
Active
No action
EN_OLA_X = 1b
nFAULT
Active
Active
Report only
EN_SHT_TST = 0b
None
Hi-Z
Active
No action
EN_SHT_TST = 1b
nFAULT
Hi-Z
Active
Report only
EN_SHT_TST = 0b
None
Hi-Z
Active
No action
EN_SHT_TST = 1b
nFAULT
Hi-Z
Active
Report only
—
nFAULT
Active
Active
No action
TJ > TOTSD
Open load passive
(OLP)
Automatic:
VVCP > VCPUV
The DRV8343-Q1 has a OTP (one time program) memory which stores TI internal data used for analog functional blocks. The memory has a check-sum feature, and nFAULT is pulled
low if a fault is detected at power up.
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8.3.5.1 VM Supply Undervoltage Lockout (UVLO)
If at any time the input supply voltage on the VM pin falls lower than the VUVLO threshold, all of the external
MOSFETs are disabled, the charge pump is disabled, and the nFAULT pin is driven low. The FAULT and
VM_UVLO bits are also latched high in the registers on SPI devices. Normal operation starts again (gate driver
operation and the nFAULT pin is released) when the VM undervoltage condition clears. The VM_UVLO bit stays
set until cleared through the CLR_FLT bit or an ENABLE pin reset pulse (tRST).
8.3.5.2 VCP Charge Pump Undervoltage Lockout (CPUV)
If at any time the voltage on the VCP pin (charge pump) falls lower than the CPUV threshold voltage of the
charge pump, all of the external MOSFETs are disabled and the nFAULT pin is driven low. The FAULT and
CPUV bits are also latched high in the registers in the SPI device. Normal operation starts again (gate driver
operation and the nFAULT pin is released) when the VCP undervoltage condition is removed. The FAULT and
CPUV bits stay set until cleared through the CLR_FLT bit or an ENABLE pin reset pulse (tRST). Setting the
DIS_CPUV bit high on the SPI devices disables this protection feature. If the DIS_CPUV bit is set high and a
charge pump undervoltage condition occurs, the device keeps operating but the CPUV fault bit is set high in the
SPI register until cleared through the CLR_FLT bit or an ENABLE pin reset pulse (tRST). CPUV protection cannot
be disabled in the H/W device.
8.3.5.3 MOSFET VDS Overcurrent Protection (VDS_OCP)
A MOSFET overcurrent event is sensed by monitoring the VDS voltage drop across the external MOSFET
RDS(on). If the voltage across an enabled MOSFET exceeds the VVDS_OCP threshold for longer than the tOCP_DEG
deglitch time, a VDS_OCP event is recognized and action is done according to the OCP_MODE. On hardware
interface devices, the VVDS_OCP threshold is set with the VDS pin, the tOCP_DEG is fixed at 4 μs, and the
OCP_MODE is configured for latched shutdown but can be disabled by tying the VDS pin to DVDD. In the SPI
device, the VVDS_OCP threshold is set through the VDS_LVL SPI register, the tOCP_DEG is set through the
OCP_DEG bits in the SPI register, and the OCP_MODE bit can operate in four different modes: VDS latched
shutdown, VDS automatic retry, VDS report only, and VDS disabled.
8.3.5.3.1 VDS Latched Shutdown (OCP_MODE = 00b)
After a VDS_OCP event in this mode, all external MOSFETs are disabled and the nFAULT pin is driven low. The
FAULT, VDS_OCP, and corresponding MOSFET OCP bits are latched high in the SPI registers. Normal
operation starts again (gate driver operation and the nFAULT pin is released) when the VDS_OCP condition
clears and a clear faults command is issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST).
This is the default mode in both the H/W and SPI device options.
8.3.5.3.2 VDS Automatic Retry (OCP_MODE = 01b)
After a VDS_OCP event in this mode, all the external MOSFETs are disabled and the nFAULT pin is driven low.
The FAULT, VDS_OCP, and corresponding MOSFET OCP bits are latched high in the SPI registers. Normal
operation starts again automatically (gate driver operation and the nFAULT pin is released) after the tRETRY time
elapses. The FAULT, VDS_OCP, and MOSFET OCP bits stay latched until the tRETRY period expires.
8.3.5.3.3 VDS Report Only (OCP_MODE = 10b)
No protective action occurs after a VDS_OCP event in this mode. The overcurrent event is reported by driving
the nFAULT pin low and latching the FAULT, VDS_OCP, and corresponding MOSFET OCP bits high in the SPI
registers. The gate drivers continue to operate as usual. The external controller manages the overcurrent
condition by acting appropriately. The reporting clears (nFAULT pin is released) when the VDS_OCP condition
clears and a clear faults command is issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST).
8.3.5.3.4 VDS Disabled (OCP_MODE = 11b)
No action occurs after a VDS_OCP event in this mode. The VDS overcurrent monitor is disabled for all three
half-bridges at the same time and the DIS_VDS_x bits are locked. In the H/W device, VDS_OCP is disabled for
all three half-bridges at the same time through the VDS pin.
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8.3.5.4 VSENSE Overcurrent Protection (SEN_OCP)
Half-bridge overcurrent is also monitored by sensing the voltage drop across the external current-sense resistor
with the SP pin. If at any time, the voltage on the SP input of the current-sense amplifier exceeds the VSEN_OCP
threshold for longer than the tOCP_DEG deglitch time, a SEN_OCP event is recognized and action is done
according to the OCP_MODE. On hardware interface devices, the VSENSE threshold is fixed at 1 V, tOCP_DEG is
fixed at 4 μs, and the OCP_MODE for VSENSE is fixed for latched shutdown. In the SPI device, the VSENSE
threshold is set through the SEN_LVL SPI register, the tOCP_DEG is set through the OCP_DEG SPI register, and
the OCP_MODE bit can operate in four different modes: VSENSE latched shutdown, VSENSE automatic retry,
VSENSE report only, and VSENSE disabled.
8.3.5.4.1 VSENSE Latched Shutdown (OCP_MODE = 00b)
After a SEN_OCP event in this mode, all the external MOSFETs are disabled and the nFAULT pin is driven low.
The FAULT and SEN_OCP bits are latched high in the SPI registers. Normal operation starts again (gate driver
operation and the nFAULT pin is released) when the SEN_OCP condition clears and a clear faults command is
issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST). This is the default mode in both the H/W
and SPI device options.
8.3.5.4.2 VSENSE Automatic Retry (OCP_MODE = 01b)
After a SEN_OCP event in this mode, all the external MOSFETs are disabled and the nFAULT pin is driven low.
The FAULT, SEN_OCP, and corresponding sense OCP bits are latched high in the SPI registers. Normal
operation starts again automatically (gate driver operation and the nFAULT pin is released) after the tRETRY time
elapses. The FAULT, SEN_OCP, and sense OCP bits stay latched until the tRETRY period expires.
8.3.5.4.3 VSENSE Report Only (OCP_MODE = 10b)
No protective action occurs after a SEN_OCP event in this mode. The overcurrent event is reported by driving
the nFAULT pin low and latching the FAULT and SEN_OCP bits high in the SPI registers. The gate drivers
continue to operate. The external controller manages the overcurrent condition by acting appropriately. The
reporting clears (nFAULT released) when the SEN_OCP condition clears and a clear faults command is issued
either through the CLR_FLT bit or an ENABLE reset pulse (tRST).
8.3.5.4.4 VSENSE Disabled (OCP_MODE = 11b)
No action occurs after a SEN_OCP event in this mode. The SEN_OCP overcurrent monitor is disabled for all
three half-bridges at the same time and the DIS_SEN_x bits are locked. In the H/W device, SEN_OCP is
disabled for all three half-bridges at the same time through the VDS pin.
8.3.5.5 Gate Driver Fault (GDF)
The GHx and GLx pins are monitored such that if the voltage on the external MOSFET gate does not increase or
decrease after the tDRIVE time, a gate driver fault is detected. This fault may be encountered if the GHx or GLx
pins are shorted to the PGND, SHx, SLx, or VM pins. Additionally, a gate driver fault may be encountered if the
selected IDRIVE setting is not sufficient to turn on the external MOSFET within the tDRIVE period. After a gate
drive fault is detected, all external MOSFETs are disabled and the nFAULT pin driven low. In addition, the
FAULT, GDF, and corresponding VGS bits are latched high in the SPI registers. Normal operation starts again
(gate driver operation and the nFAULT pin is released) when the gate driver fault condition is removed and a
clear faults command is issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST). In the SPI
device, setting the DIS_GDF bit high disables this protection feature. If DIS_GDF bit is set high and a gate drive
fault occurs, the device keeps operating but the appropriate VGS fault bit is set high in the SPI register until
cleared through the CLR_FLT bit or an ENABLE pin reset pulse (tRST). GDF cannot be disabled in the H/W
device option.
Gate driver faults can indicate that the selected IDRIVE or tDRIVE settings are too low to slew the external
MOSFET in the desired time. Increasing either the IDRIVE or tDRIVE setting can resolve gate driver faults in these
cases. Alternatively, if a gate-to-source short occurs on the external MOSFET, a gate driver fault is reported
because of the MOSFET gate not turning on. The tDRIVE time also refers to the GDF fault blanking time.
Fault handling is done as follows based on the MODE setting:
• In 6x, 3x, and 1x PWM modes a GDF fault in one of the external MOSFETs turns off all the MOSFETs.
• In independent half-bridge mode (MODE = 011b or MODE pin is Hi-Z) a GDF fault in one half-bridge only
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•
•
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disables both the MOSFETs in that half-bridge. The MOSFETs in the other half-bridges operate as
commanded.
In independent MOSFET mode (MODE = 111b or MODE pin tied to DVDD) a GDF fault in a MOSFET only
disables that particular MOSFET. All the other MOSFETs operate as commanded. The same fault handling
scheme applies for MODE = 100b, 101b, and 110b.
A GDF fault in phases set as Independent half-bridge disables both MOSFETs in that particular phase.
A GDF fault in phases set as Independent FET mode disables the MOSFET where the fault occurred.
8.3.5.6 Thermal Warning (OTW)
If the die temperature exceeds the trip point of the thermal warning (TOTW), the OTW bit is set in the registers of
SPI devices. The device performs no additional action and continues to function. When the die temperature falls
lower than the hysteresis point of the thermal warning, the OTW bit clears automatically. The OTW bit can also
be configured to report on the nFAULT pin by setting the OTW_REP bit to 1 through the SPI registers. OTW is
not available in the H/W device.
8.3.5.7 Thermal Shutdown (OTSD)
If the die temperature exceeds the trip point of the thermal shutdown limit (TOTSD), all the external MOSFETs are
disabled, the charge pump is shut down, and the nFAULT pin is driven low. In addition, the FAULT and OTSD
bits are latched high. This protection feature cannot be disabled. The overtemperature protection can operate in
two different modes.
8.3.5.7.1 Latched Shutdown (OTSD_MODE = 0b)
In latched shutdown mode, after a OTSD event, normal operation starts again (motor driver operation and the
nFAULT line released) when the OTSD condition is removed and a clear faults command has been issued either
through the CLR_FLT bit or an nSLEEP reset pulse. This is the default mode for a OTSD event in the SPI
device.
When the DRV8343-Q1 device hits thermal shutdown, the OTSD and FAULT bits are latched in the SPI register.
Clearing the fault through the CLR_FLT bit or an nSLEEP reset pulse will clear the OSTD and FAULT bits. When
the DRV8343-Q1 device hits thermal shutdown, the device will disable the charge pump without triggering
CPUV. The charge pump will be enabled again when the OTSD and FAULT bits are cleared through the
CLR_FLT bit or an nSleep reset Pulse.
8.3.5.7.2 Automatic Recovery (OTSD_MODE = 1b)
In automatic recovery mode, after a OTSD event, normal operation starts again (motor driver operation and the
nFAULT line released) when the junction temperature falls to less than the overtemperature threshold limit minus
the hysteresis (TOTSD – THYS). The OTSD bit stays latched high indicating that a thermal event occurred until a
clear faults command is issued either through the CLR_FLT bit or an nSLEEP reset pulse. This is the default
mode for a OTSD event in the H/W device.
8.3.5.8 Open Load Detection (OLD)
If the load is disconnected from the device, an open load is detected and the nFAULT pin is latched low. In the
DRV8343-Q1 device, The FAULT, OL_SHT, and the corresponding open load (OL_PH_x) bits in the SPI register
are latched high. When the open-load condition is removed, and the MCU clears the fault through either the
CLR_FLT bit or an ENABLE-pin reset pulse (tRST), the device is ready to drive the motor based on the input
commands.
8.3.5.8.1 Open Load Detection in Passive Mode (OLP)
In open load detection in passive mode, open load diagnosis is performed without the motor in motion. If the
motor is disconnected from the device an open load is detected and the nFAULT pin will latch low until a clear
faults command is issued by the MCU either through the CLR_FLT bit or an ENABLE reset pulse. The fault also
clears when the device is power cycled or comes out of sleep mode. OLP is designed for applications having
capacitance less than the values listed in Table 10 between motor phase pins to ground.
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Table 10. Open Load Passive Diagnostic Run-Time
Capacitance (nF)
OLP_SHTS_DLY (ms)
5
0.25
26
1.25
110
5
270
11.5
When the open load test is running, all external MOSFETs are disabled. For the H/W device option, at power-up
or after going from sleep mode, the offline short-to-supply (SHT_BAT) and short-to-ground (SHT_GND)
diagnostics run first followed by the OLP diagnostic if the nDIAG pin is left as no connect or tied to GND. If the
nDIAG pin is tied to DVDD (or an external 3.3 V) the open load test is not performed. If a short condition is
detected, the OLP diagnostic is not run (see Offline Shorts Diagnostics). If a short condition and open load
occurs on a given phase at device power-up, for example, only the short condition is reported on the nFAULT pin
and through the SPI fault register. In the SPI device option the OLP test is performed when commanded through
SPI. If both short and OLP diagnostics are enabled simultaneously and a short condition is detection, only the
short condition is reported on the nFAULT pin and through the SPI fault register.
The sequence to perform open load diagnostics in passive mode is as follows:
1. Device powered up (ENABLE = 1).
2. Mode is selected by SPI.
3. Hi-Z all three half-bridges by turning-off all the external MOSFETs.
4. Write a 1 to the EN_OLP bit in the SPI register and OLP is performed.
– If an open load is detected, the nFAULT pin is driven low, and the FAULT bit, the OLD bit, and the
respective OL_PH_x bit are latched high. When the open load condition is removed, a clear faults
command must be issued by the MCU either through the CLR_FLT bit or an ENABLE reset pulse which
resets the OL_PH_x register bit and causes the nFAULT pin to go high.
– If open load is not detected, the EN_OLP bits return to default setting (0b) after tOL expires.
The EN_OLP register keeps the written command until the diagnostic is complete. The half bridges must stay in
Hi-Z state for the entire duration of the test. While open load diagnostic is running, if an input change occurs or
the EN_OLP bit is set low, the open load test is aborted to start normal operation again, and no fault is reported.
OLP should not be performed if the motor is energized.
The open load detection checks for a high impedance connection on the motor phase pins (SHx or DLx). The
diagnostic has two major steps as listed in the OLP Steps section. The sequencing of the pullup and pulldown
current varies depending on the load connections. Figure 38 a simplified H-bridge configuration as an example
for open load detection.
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VM
VM
VREF
+
OL1_PU
output
±
OLx_PU
SHx / DLx
VM
VREF
SHx / DLx
+
OL1_PU
output
±
SLx
OLx_PD
Figure 38. Circuit for Open Load Detection in Passive Mode
8.3.5.8.1.1 OLP Steps
The OLP algorithm list is as follows:
• The pullup current source is enabled. If a load is connected, current passes through the pullup resistor and
the OLx_PU comparator output stays low. If an open load condition occurs, the current through the pullup
resistor goes 0 and the OLx_PU comparator trips high.
• The pulldown current source is enabled. In the same way, the OLx_PD comparator output either stays low to
indicate load-connected, or trips high to indicate an open load condition.
• If both the OLx_PU and OLx_PD comparators report an open load, the OL_PH_x bit in the SPI register
latches high, and the nFAULT line goes low, to indicate an OL fault.
When the OL condition is removed, a clear faults command must be issued by the micro-controller either through
the CLR_FLT bit or an ENABLE reset pulse which resets open load register bits. The charge pump stays active
during this fault condition. The load connections shown in Figure 39 are not supported OLP.
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VDRAIN
HS_VSD
VDRAIN
VDRAIN
+
GHx
±
VM
DLx
IPD
IPU
SHx
LS_VSD
GLx
+
±
SLx
Figure 39. Load Configurations Not Supported
8.3.5.8.2 Open Load Detection in Active Mode (OLA)
An open load in active mode is disabled by default in the SPI device and can be enabled independently per halfbridge by writing a 1 to the EN_OLA_x bit. In the H/W device, OLA runs if the nDIAG pin is left as unconnected
or tied to GND. OLA is detected when the motor gets disconnected from the driver when it is commutating.
Figure 40 shows a simplified H-bridge configuration for OLA implementation during high-side current
recirculation. When the voltage drop across the body diode of the MOSFET does not exhibit overshoot greater
than the VOLA over VM between the time the low-side FET is switched off and the high side FET is switched on
during an output PWM cycle. An open load is not detected if the energy stored in the inductor is high enough to
cause an overshoot greater than the VOLA over VM caused by the fly-back current flowing through the body diode
of the high-side FET.
VM
SH1
DL1
SH2
DL2
±
SH2
DL2
VM
+
SH1
DL1
VM
SH1
DL1
SH2
DL2
±
+
Detects OLD if the No OLD detected if the
diode VF drop < VOLA diode VF drop > VOLA
Figure 40. Circuit for Open Load Detection in Active Mode
NOTE
Depending on the operating conditions and on external circuitry, such as the output
capacitors, an open load could be reported even though the load is present. This case
might occur during a direction change or for small load currents respectively small PWM
duty cycles. Therefore, TI recommends evaluating the open load diagnosis only in known
suitable operating conditions and to ignore it otherwise.
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The device has a failure counter to avoid inadvertent triggering of the open load active diagnosis. Three
consecutive occurrences of the internal open load signal must occur, essentially three consecutive PWM pulses
without freewheeling detected, before an open load is reported through the nFAULT pin and in the respective
SPI register.
In the SPI device, depending on the load configuration and the PWM sequence, OLA on one phase can latch all
three OL_PH_x bits high. In that case, the OLP diagnostic can be initiated to determine which phase has the
open load condition. The load connections shown in Figure 39 are not supported by OLA.
For OLA to function correctly, place capacitors between the motor phase node and GND. This capacitor is
required for BLDC, bi-directional BDC and unidirectional BDC motors at the phase node. If a solenoid load is
connected, as shown in Figure 15, the capacitor is not required. Size the capacitors according Equation 5. Make
sure that the capacitor (Cphase) is placed on the PCB.
Cphase t
VTH u Crss
VOLA(min)
Cos s
where
•
•
VTH is the threshold voltage of the MOSFET.
VOLA(min) is 150 mV.
(5)
The values of Crss and Coss of the MOSFETs should be used for 0-V VDS. Derating of Cphase must be considered
when selecting the capacitance.
8.3.5.9 Offline Shorts Diagnostics
The device detects short-to-battery and short-to-ground conditions when the motor is not commutating. These
offline diagnostics can be activated in the SPI device by setting the EN_SHT_TST bit high. Both the short-tobattery and short-to-ground diagnostics run when the EN_SHT_TST bit is set high. In the H/W device, these
diagnostics run at power-up or when going from the sleep mode if the nDIAG pin is left unconnected or tied to
GND. To disable the diagnostics in the H/W device, connect the nDIAG pin to the DVDD supply (or an external
3.3 V or 5 V rail). The short-to-supply diagnostic runs first (see Offline Short-to-Supply Diagnostic (SHT_BAT))
followed by the short-to-ground diagnostic (see Offline Short-to-Ground Diagnostic (SHT_GND)). In the SPI
device, the duration for this diagnostics is selected through the OLP_SHTS_DLY register. In the H/W device, the
duration is fixed to 2 ms.
8.3.5.9.1 Offline Short-to-Supply Diagnostic (SHT_BAT)
When the EN_SHT_TST bit is set high, all the pulldown current sources on the DLx pins are enabled. The
voltage across each pulldown source is individually measured and compared to an internal threshold (VTH). If the
voltage across any of the current sources exceeds VTH, the DRV8343-Q1 device flags that as a fault condition.
The nFAULT pin is driven low, and in the SPI device the FAULT, OL_SHT, and the corresponding SHT_BAT_x
bit is set. Figure 41 shows the internal circuit for the short to battery detection.
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VM
GHA
GHB
SHA
GHC
Short to Ground
(SHT_GND)
Diagnostic Circuit
SHB
SHC
DLC
DLB
GLC
DLA
GLB
VTH
VTH
VTH
GLC
Figure 41. Offline Short-to-Supply Detection Circuit
In the SPI device, depending on the load configuration, SHT_BAT on one phase can latch all three SHT_BAT_x
bits high. To determine which phase has a short-to-supply fault condition, the external MOSFETs can be enabled
and the appropriate VDS_Lx fault bit is latched indicating the faulty phase node. SHT_BAT is not supported for
load configurations shown in Figure 39.
8.3.5.9.2 Offline Short-to-Ground Diagnostic (SHT_GND)
When the EN_SHT_TST bit is set high, all the pullup current sources on the SHx pins are enabled. The voltage
across each pullup source is individually measured and compared to an internal threshold (VTH). If the voltage
across any of the current sources exceeds VTH, the DRV8343-Q1 device flags that as a fault condition. The
nFAULT pin is driven low, and in the SPI device the FAULT, OL_SHT, and the corresponding SHT_GND_x bit is
set. Figure 42 shows the internal circuit for the short-to-ground detection.
48
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VM
VM
GHA
GHB
SHA
VTH
VTH
VTH
GHC
SHB
SHC
DLC
DLB
Short to Supply
(SHT_BAT)
Diagnostic Circuit
GLC
DLA
GLB
GLC
Figure 42. Offline Short-to-Ground Detection Circuit
In the SPI device, depending on the load configuration, SHT_GND on one phase can latch all three SHT_GND_x
bits high. To determine which phase has a short-to-ground fault condition, the external MOSFETs can be
enabled and the appropriate VDS_Hx fault bit is latched indicating the faulty phase node. SHT_GND is not
supported for load configurations shown in Figure 39.
8.3.5.10 Reverse Supply Protection
The circuit in Figure 43 can be implemented to help protect the system from reverse supply conditions. This
circuit requires the following additional components:
• N-channel MOSFET
• NPN BJT
• Diode
• 10-kΩ and 43-kΩ resistors
The VCP voltage with respect to VM supplies the gate-source voltage of N-channel MOSFET, and the voltage
VVCP depends on VM voltage. The characteristics of N-Channel MOSFET (e.g. gate threshold voltage) and the
VM voltage range of the system need to be reviewed by the system integrator.
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VBAT
43 k
10 k
1 µF
47 nF
0.1 µF
CPL
CPH
VCP
+ Bulk
10 µF (min)
VM
VDRAIN
GHA
SHA
DLA
GLA
SLA
VM
GHB
SHB
DLB
GLB
SLB
VM
GHC
SHC
DLC
GLC
SPC
RSEN
SNC
Figure 43. Reverse Supply Protection
50
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8.4 Device Functional Modes
8.4.1 Gate Driver Functional Modes
8.4.1.1 Sleep Mode
The ENABLE pin manages the state of the DRV8343-Q1 device. When the ENABLE pin is low, the device goes
to a low-power sleep mode. In sleep mode, all gate drivers are disabled, all external MOSFETs are disabled, the
charge pump is disabled, the DVDD regulator is disabled, and the SPI bus is disabled. The tSLEEP time must
elapse after a falling edge on the ENABLE pin before the device goes to sleep mode. The device comes out of
sleep mode automatically if the ENABLE pin is pulled high. The tWAKE time must elapse before the device is
ready for inputs.
In sleep mode and when VVM < VUVLO, all external MOSFETs are disabled. The high-side gate pins, GHx, are
pulled to the SHx pin by an internal resistor and the low-side gate pins, GLx, are pulled to the PGND pin by an
internal resistor.
8.4.1.2 Operating Mode
When the ENABLE pin is high and the VVM voltage is greater than the VUVLO voltage, the device goes to
operating mode. The tWAKE time must elapse before the device is ready for inputs. In this mode the charge pump,
low-side gate regulator, DVDD regulator, and SPI bus are active.
8.4.1.3 Fault Reset (CLR_FLT or ENABLE Reset Pulse)
In the case of device latched faults, the DRV8343-Q1 device goes to a partial shutdown state to help protect the
external power MOSFETs and system.
When the fault condition clears, the device can go to the operating state again by either setting the CLR_FLT SPI
bit on SPI devices or issuing a result pulse to the ENABLE pin on either interface variant. The ENABLE reset
pulse (tRST) consists of a high-to-low-to-high transition on the ENABLE pin. The low period of the sequence
should fall with the tRST time window or else the device will start the complete shutdown sequence. The reset
pulse has no effect on any of the regulators, device settings, or other functional blocks
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8.5 Programming
This section applies only to the DRV8343-Q1 SPI devices.
8.5.1 SPI Communication
8.5.1.1 SPI
On DRV8343-Q1 SPI devices, an SPI bus is used to set device configurations, operating parameters, and read
out diagnostic information. The SPI operates in slave mode and connects to a master controller. The SPI input
data (SDI) word consists of a 16-bit word, with an 8-bit command and 8 bits of data. The SPI output data (SDO)
word consists of 8-bit register data. The first 8 bits are don’t care bits.
A
•
•
•
valid frame must meet the following conditions:
The SCLK pin should be low when the nSCS pin transitions from high to low and from low to high.
The nSCS pin should be pulled high for at least 400 ns between words.
When the nSCS pin is pulled high, any signals at the SCLK and SDI pins are ignored and the SDO pin is
placed in the Hi-Z state.
Data is captured on the falling edge of the SCLK pin and data is propagated on the rising edge of the SCLK
pin.
The most significant bit (MSB) is shifted in and out first.
A full 16 SCLK cycles must occur for transaction to be valid.
If the data word sent to the SDI pin is less than or more than 16 bits, a frame error occurs and the data word
is ignored.
For a write command, the existing data in the register being written to is shifted out on the SDO pin following
the 8-bit command data.
•
•
•
•
•
8.5.1.1.1 SPI Format
The SDI input data word is 16 bits long and consists of the following format:
• 1 read or write bit, W (bit B15)
• 7 address bits, A (bits B14 through B8)
• 8 data bits, D (bits B7 through B0)
The SDO output data word is 16 bits long and the first 5 bits are don't care bits. The data word is the content of
the register being accessed.
For a write command (W0 = 0), the response word on the SDO pin is the data currently in the register being
written to.
For a read command (W0 = 1), the response word is the data currently in the register being read.
Table 11. SDI Input Data Word Format
R/W
ADDRESS
DATA
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
W0
0
0
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Table 12. SDO Output Data Word Format
R/W
DON'T CARE
DATA
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
W0
X
X
X
X
X
X
X
D7
D6
D5
D4
D3
D2
D1
D0
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nSCS
SCLK
SDI
X
MSB
LSB
X
SDO
Z
MSB
LSB
Z
Capture
Point
Propagate
Point
Figure 44. SPI Slave Timing Diagram
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8.6 Register Maps
This section applies only to the DRV8343-Q1 SPI devices.
NOTE
Do not modify reserved registers or addresses not listed in the register map (Table 13).
Writing to these registers may have unintended effects. For all reserved bits, the default
value is 0. To help prevent erroneous SPI writes from the master controller, set the LOCK
bits to lock the SPI registers.
Table 13. DRV8343-Q1 Register Map
Register
Name
7
6
5
4
3
2
1
0
Access
Type
Address
FAULT Status
FAULT
GDF
CPUV
UVLO
OCP
OTW
OTSD
OL_SHT
R
0x00
DIAG Status A
SA_OC
SHT_GND_A
SHT_BAT_A
OL_PH_A
VGS_LA
VGS_HA
VDS_LA
VDS_HA
R
0x01
DIAG Status B
SB_OC
SHT_GND_B
SHT_BAT_B
OL_PH_B
VGS_LB
VGS_HB
VDS_LB
VDS_HB
R
0x02
DIAG Status C
SC_OC
SHT_GND_C
SHT_BAT_C
OL_PH_C
VGS_LC
VGS_HC
VDS_LC
VDS_HC
R
0x03
IC1 Control
CLR_FLT
1PWM_COM
1PWM_DIR
RW
0x04
IC2 Control
OTSD_MODE
EN_OLP
EN_OLA_C
RW
0x05
PWM_MODE
OLP_SHTS_DLY
EN_SHT_TST
1PWM_BRAKE
EN_OLA_B
EN_OLA_A
IC3 Control
IDRIVEP_LA
IDRIVEP_HA
RW
0x06
IC4 Control
IDRIVEP_LB
IDRIVEP_HB
RW
0x07
IC5 Control
IDRIVEP_LC
IDRIVEP_HC
RW
0x08
IC6 Control
VDS_LVL_LA
VDS_LVL_HA
RW
0x09
IC7 Control
VDS_LVL_LB
VDS_LVL_HB
RW
0x0A
IC8 Control
IC9 Control
VDS_LVL_LC
COAST
VDS_LVL_HC
TRETRY
IC10 Control
DEAD_TIME
LOCK
DIS_CPUV
DIS_GDF
DIS_VDS_C
DIS_VDS_B
IC11 Control
RSVD
OTW_REP
IC12 Control
LS_REF
CSA_FET
CSA_GAIN_C
IC13 Control
CAL_MODE
VREF_DIV
SEN_LVL_C
IC14 Control
RSVD
CBC
DIS_SEN_C
TDRIVE_MAX
DIS_SEN_B
TDRIVE
0x0B
RW
0x0C
RW
0x0D
OCP_MODE
RW
0x0E
CSA_GAIN_B
CSA_GAIN_A
RW
0x0F
SEV_LVL_B
SEN_LVL_A
RW
0x10
RW
0x11
DIS_SEN_A
OCP_DEG
RW
DIS_VDS_A
CSA_CAL_C
CSA_CAL_B
CSA_CAL_A
Complex bit access types are encoded to fit into small table cells. Table 14 shows the codes that are used for
access types in this section.
Table 14. Status Registers Access Type Codes
Access Type
Code
Description
R
Read
Read Type
R
Reset or Default Value
-n
Value after reset or the default value
8.6.1 Status Registers
Table 15 lists the memory-mapped registers for the status registers. All register offset addresses not listed in
Table 15 should be considered as reserved locations and the register contents should not be modified.
The status registers are used to reporting warning and fault conditions. Status registers are read-only registers.
Table 15. Status Registers Summary Table
Address
54
Register Name
Section
0x00
FAULT Status
Go
0x01
DIAG Status A
Go
0x02
DIAG Status B
Go
0x03
DIAG Status C
Go
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8.6.1.1 FAULT Status Register (Address = 0x00) [reset = 0x00]
FAULT Status is shown in Figure 45 and described in Table 16.
Figure 45. FAULT Status Register
7
FAULT
R-0b
6
GDF
R-0b
5
CPUV
R-0b
4
UVLO
R-0b
3
OCP
R-0b
2
OTW
R-0b
1
OTSD
R-0b
0
OL_SHT
R-0b
Table 16. FAULT Status Register Field Descriptions
Bit
Field
Type
Default
Description
7
FAULT
R
0b
Logic OR of FAULT status registers
6
GDF
R
0b
Indicates gate drive fault condition
5
CPUV
R
0b
Indicates charge pump undervoltage fault condition
4
UVLO
R
0b
Indicates undervoltage lockout fault condition
3
OCP
R
0b
Indicated overcurrent fault condition either by VDS or SEN_OCP
2
OTW
R
0b
Indicates overtemperature warning
1
OTSD
R
0b
Indicates overtemperature shutdown
0
OL_SHT
R
0b
Indicates open load detection, or offline short-to-supply or GND
detection
8.6.1.2 DIAG Status A Register (Address = 0x01) [reset = 0x00]
DIAG Status A is shown in Figure 46 and described in Table 17.
Figure 46. DIAG Status A Register
7
SA_OC
R-0b
6
SHT_GND_A
R-0b
5
SHT_BAT_A
R-0b
4
OL_PH_A
R-0b
3
VGS_LA
R-0b
2
VGS_HA
R-0b
1
VDS_LA
R-0b
0
VDS_HA
R-0b
Table 17. DIAG Status A Register Field Descriptions
Bit
Field
Type
Default
Description
7
SA_OC
R
0b
Indicates overcurrent on Phase A sense amplifier
6
SHT_GND_A
R
0b
Indicates offline short-to-ground fault in Phase A
5
SHT_BAT_A
R
0b
Indicates offline short to battery fault in Phase A
4
OL_PH_A
R
0b
Indicates open load fault in Phase A
3
VGS_LA
R
0b
Indicates gate drive fault on the A low-side MOSFET
2
VGS_HA
R
0b
Indicates gate drive fault on the A high-side MOSFET
1
VDS_LA
R
0b
Indicates VDS overcurrent fault on the A low-side MOSFET
0
VDS_HA
R
0b
Indicates VDS overcurrent fault on the A high-side MOSFET
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8.6.1.3 DIAG Status B Register (Address = 0x02) [reset = 0x00]
DIAG Status B is shown in Figure 47 and described in Table 18.
Figure 47. DIAG Status B Register
7
SB_OC
R-0b
6
SHT_GND_B
R-0b
5
SHT_BAT_B
R-0b
4
OL_PH_B
R-0b
3
VGS_LB
R-0b
2
VGS_HB
R-0b
1
VDS_LB
R-0b
0
VDS_HB
R-0b
Table 18. DIAG Status B Register Field Descriptions
Bit
Field
Type
Default
Description
7
SB_OC
R
0b
Indicates overcurrent on Phase B sense amplifier
6
SHT_GND_B
R
0b
Indicates offline short-to-ground fault in Phase B
5
SHT_BAT_B
R
0b
Indicates offline short to battery fault in Phase B
4
OL_PH_B
R
0b
Indicates open load fault in Phase B
3
VGS_LB
R
0b
Indicates gate drive fault on the B low-side MOSFET
2
VGS_HB
R
0b
Indicates gate drive fault on the B high-side MOSFET
1
VDS_LB
R
0b
Indicates VDS overcurrent fault on the B low-side MOSFET
0
VDS_HB
R
0b
Indicates VDS overcurrent fault on the B high-side MOSFET
8.6.1.4 DIAG Status C Register (address = 0x03) [reset = 0x00]
DIAG Status C iss shown in Figure 48 and described in Table 19.
Figure 48. DIAG Status C Register
7
SC_OC
R-0b
6
SHT_GND_C
R-0b
5
SHT_BAT_C
R-0b
4
OL_PH_C
R-0b
3
VGS_LC
R-0b
2
VGS_HC
R-0b
1
VDS_LC
R-0b
0
VDS_HC
R-0b
Table 19. DIAG Status C Register Field Descriptions
Bit
56
Field
Type
Default
Description
7
SC_OC
R
0b
Indicates overcurrent on Phase C sense amplifier
6
SHT_GND_C
R
0b
Indicates offline short-to-ground fault in Phase C
5
SHT_BAT_C
R
0b
Indicates offline short to battery fault in Phase C
4
OL_PH_C
R
0b
Indicates open load fault in Phase C
3
VGS_LC
R
0b
Indicates gate drive fault on the C low-side MOSFET
2
VGS_HC
R
0b
Indicates gate drive fault on the C high-side MOSFET
1
VDS_LC
R
0b
Indicates VDS overcurrent fault on the C low-side MOSFET
0
VDS_HC
R
0b
Indicates VDS overcurrent fault on the C high-side MOSFET
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8.6.2 Control Registers
Table 20 lists the memory-mapped registers for the control registers. All register offset addresses not listed in
Table 20 should be considered as reserved locations and the register contents should not be modified.
The IC control registers are used to configure the device. Control registers are read and write capable.
Table 20. Control Registers Summary Table
Address
Register Name
Section
0x04
IC1 Control
Go
0x05
IC2 Control
Go
0x06
IC3 Control
Go
0x07
IC4 Control
Go
0x08
IC5 Control
Go
0x09
IC6 Control
Go
0x0A
IC7 Control
Go
0x0B
IC8 Control
Go
0x0C
IC9 Control
Go
0x0D
IC10 Control
Go
0x0E
IC11 Control
Go
0x0F
IC12 Control
Go
0x10
IC13 Control
Go
0x11
IC14 Control
Go
8.6.2.1 IC1 Control Register (Address = 0x04) [reset = 0x00]
IC1 Control is shown in Figure 49 and described in Table 21.
Figure 49. IC1 Control Register
7
CLR_FLT
R/W-0b
6
5
PWM_MODE
R/W-000b
4
3
1PWM_COM
R/W-0b
2
1PWM_DIR
R/W-0b
1
0
1PWM_BRAKE
R/W-00b
Table 21. IC1 Control Field Descriptions
Bit
7
6-4
Field
Type
Default
Description
CLR_FLT
R/W
0b
Write a 1 to this bit to clear all latched fault bits. This bit
automatically resets after being written
PWN_MODE
R/W
000b
000b = 6x PWM mode
001b = 3x PWM mode
010b = 1x PWM mode
011b = Independent half-bridge (for all phases)
100b = Phases A and B are independent half-bridges, Phase C
is independent FET
101b = Phases B and C are independent half-bridges, Phase A
is independent FET
110b = Phase A is independent half-bridge, Phases B and C are
independent FET
111b =Independent FET (for all phases)
3
1PWM_COM
R/W
0b
0b = 1x PWM mode uses synchronous rectification
1b = 1x PWM mode uses asynchronous rectification (diode
freewheeling)
2
1PWM_DIR
R/W
0b
In 1x PWM mode this bit is OR’ed with the INHC (DIR) input
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Table 21. IC1 Control Field Descriptions (continued)
Bit
Field
Type
Default
Description
1-0
1PWM_BRAKE
R/W
00b
00b = Outputs follow commanded inputs
01b = Turn on all three low-side MOSFETs
10b = Turn on all three high-side MOSFETs
11b = Turn off all six MOSFETs (coast)
8.6.2.2 IC2 Control Register (address = 0x05) [reset = 0x40]
IC2 Control is shown in Figure 50 and described in Table 22.
Figure 50. IC2 Control Register
7
OTSD_MODE
R/W-0b
6
5
OLP_SHTS_DLY
R/W-10b
4
EN_SHT_TST
R/W-0b
3
EN_OLP
R/W-0b
2
EN_OLA_C
R/W-0b
1
EN_OLA_B
R/W-0b
0
EN_OLA_A
R/W-0b
Table 22. IC2 Control Field Descriptions
Bit
7
Field
Type
Default
Description
OTSD_MODE
R/W
0b
0b = Overtemperature condition will cause a latched fault
1b = Overtemperature condition will cause an automatic
recovery when the fault condition is removed
6-5
OLP_SHTS_DLY
R/W
10b
00b = OLP delay is 0.25 ms and Shorts test delay is 0.1 ms
01b = OLP delay is 1.25 ms and Shorts test delay is 0.5 ms
10b = OLP delay is 5 ms and Shorts test delay is 2 ms
11b = OLP delay is 11.5 ms and Shorts test delay is 4.4 ms
58
4
EN_SHT_TST
R/W
0b
Write a 1 to enable offline short to battery and ground diagnoses
3
EN_OLP
R/W
0b
Write a 1 to enable open load diagnostic in standby mode.
When open load test is complete EN_OLP returns to the default
setting
2
EN_OLA_C
R/W
0b
Write a 1 to enable open load active diagnostic on Phase C
1
EN_OLA_B
R/W
0b
Write a 1 to enable open load active diagnostic on Phase B
0
EN_OLA_A
R/W
0b
Write a 1 to enable open load active diagnostic on Phase A
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8.6.2.3 IC3 Control Register (Address = 0x06) [reset = 0xFF]
IC3 Control is shown in Figure 51 and described in Table 23.
Figure 51. IC3 Control Register
7
6
5
4
3
2
IDRIVEP_LA
R/W-1111b
1
0
IDRIVEP_HA
R/W-1111b
Table 23. IC3 Control Field Descriptions
Bit
Field
Type
Default
Description
7-4
IDRIVEP_LA
R/W
1111b
0000b = 1.5 mA
0001b = 3.5 mA
0010b = 5 mA
0011b = 10 mA
0100b = 15 mA
0101b = 50 mA
0110b = 60 mA
0111b = 65 mA
1000b = 200 mA
1001b = 210 mA
1010b = 260 mA
1011b = 265 mA
1100b = 735 mA
1101b = 800 mA
1110b = 935 mA
1111b = 1000 mA
3-0
IDRIVEP_HA
R/W
1111b
0000b = 1.5 mA
0001b = 3.5 mA
0010b = 5 mA
0011b = 10 mA
0100b = 15 mA
0101b = 50 mA
0110b = 60 mA
0111b = 65 mA
1000b = 200 mA
1001b = 210 mA
1010b = 260 mA
1011b = 265 mA
1100b = 735 mA
1101b = 800 mA
1110b = 935 mA
1111b = 1000 mA
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8.6.2.4 IC4 Control Register (Address = 0x07) [reset = 0xFF]
IC4 Control is shown in Figure 52 and described in Table 24.
Figure 52. IC4 Control Register
7
6
5
4
3
2
IDRIVEP_LB
R/W-1111b
1
0
IDRIVEP_HB
R/W-1111b
Table 24. IC4 Control Field Descriptions
Bit
Field
Type
Default
Description
7-4
IDRIVEP_LB
R/W
1111b
0000b = 1.5 mA
0001b = 3.5 mA
0010b = 5 mA
0011b = 10 mA
0100b = 15 mA
0101b = 50 mA
0110b = 60 mA
0111b = 65 mA
1000b = 200 mA
1001b = 210 mA
1010b = 260 mA
1011b = 265 mA
1100b = 735 mA
1101b = 800 mA
1110b = 935 mA
1111b = 1000 mA
3-0
IDRIVEP_HB
R/W
1111b
0000b = 1.5 mA
0001b = 3.5 mA
0010b = 5 mA
0011b = 10 mA
0100b = 15 mA
0101b = 50 mA
0110b = 60 mA
0111b = 65 mA
1000b = 200 mA
1001b = 210 mA
1010b = 260 mA
1011b = 265 mA
1100b = 735 mA
1101b = 800 mA
1110b = 935 mA
1111b = 1000 mA
60
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8.6.2.5 IC5 Control Register (Address = 0x08) [reset = 0xFF]
IC5 Control is shown in Figure 53 and described in Table 25.
Figure 53. IC5 Control Register
7
6
5
4
3
2
IDRIVEP_LC
R/W-1111b
1
0
IDRIVEP_HC
R/W-1111b
Table 25. IC5 Control Field Descriptions
Bit
Field
Type
Default
Description
7-4
IDRIVEP_LC
R/W
1111b
0000b = 1.5 mA
0001b = 3.5 mA
0010b = 5 mA
0011b = 10 mA
0100b = 15 mA
0101b = 50 mA
0110b = 60 mA
0111b = 65 mA
1000b = 200 mA
1001b = 210 mA
1010b = 260 mA
1011b = 265 mA
1100b = 735 mA
1101b = 800 mA
1110b = 935 mA
1111b = 1000 mA
3-0
IDRIVEP_HC
R/W
1111b
0000b = 1.5 mA
0001b = 3.5 mA
0010b = 5 mA
0011b = 10 mA
0100b = 15 mA
0101b = 50 mA
0110b = 60 mA
0111b = 65 mA
1000b = 200 mA
1001b = 210 mA
1010b = 260 mA
1011b = 265 mA
1100b = 735 mA
1101b = 800 mA
1110b = 935 mA
1111b = 1000 mA
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8.6.2.6 IC6 Control Register (Address = 0x09) [reset = 0x99]
IC6 Control is shown in Figure 54 and described in Table 26.
Figure 54. IC6 Control Register
7
6
5
4
3
2
VDS_LVL_LA
R/W-1001b
1
0
VDS_LVL_HA
R/W-1001b
Table 26. IC6 Control Field Descriptions
Bit
Field
Type
Default
Description
7-4
VDS_LVL_LA
R/W
1001b
0000b = 0.06 V
0001b = 0.13 V
0010b = 0.2 V
0011b = 0.26 V
0100b = 0.31 V
0101b = 0.45 V
0110b = 0.53 V
0111b = 0.6 V
1000b = 0.68 V
1001b = 0.75 V
1010b = 0.94 V
1011b = 1.13 V
1100b = 1.3 V
1101b = 1.5 V
1110b = 1.7 V
1111b = 1.88 V
3-0
VDS_LVL_HA
R/W
1001b
0000b = 0.06 V
0001b = 0.13 V
0010b = 0.2 V
0011b = 0.26 V
0100b = 0.31 V
0101b = 0.45 V
0110b = 0.53 V
0111b = 0.6 V
1000b = 0.68 V
1001b = 0.75 V
1010b = 0.94 V
1011b = 1.13 V
1100b = 1.3 V
1101b = 1.5 V
1110b = 1.7 V
1111b = 1.88 V
62
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8.6.2.7 IC7 Control Register (Address = 0x0A) [reset = 0x99]
IC7 Control is shown in Figure 55 and described in Table 27.
Figure 55. IC7 Control Register
7
6
5
4
3
2
VDS_LVL_LB
R/W-1001b
1
0
VDS_LVL_HB
R/W-1001b
Table 27. IC7 Control Field Descriptions
Bit
Field
Type
Default
Description
7-4
VDS_LVL_LB
R/W
1001b
0000b = 0.06 V
0001b = 0.13 V
0010b = 0.2 V
0011b = 0.26 V
0100b = 0.31 V
0101b = 0.45 V
0110b = 0.53 V
0111b = 0.6 V
1000b = 0.68 V
1001b = 0.75 V
1010b = 0.94 V
1011b = 1.13 V
1100b = 1.3 V
1101b = 1.5 V
1110b = 1.7 V
1111b = 1.88 V
3-0
VDS_LVL_HB
R/W
1001b
0000b = 0.06 V
0001b = 0.13 V
0010b = 0.2 V
0011b = 0.26 V
0100b = 0.31 V
0101b = 0.45 V
0110b = 0.53 V
0111b = 0.6 V
1000b = 0.68 V
1001b = 0.75 V
1010b = 0.94 V
1011b = 1.13 V
1100b = 1.3 V
1101b = 1.5 V
1110b = 1.7 V
1111b = 1.88 V
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8.6.2.8 IC8 Control Register (Address = 0x0B) [reset = 0x99]
IC8 control is shown in Figure 56 and described in Table 28.
Figure 56. IC8 Control Register
7
6
5
4
3
2
VDS_LVL_LC
R/W-1001b
1
0
VDS_LVL_HC
R/W-1001b
Table 28. IC8 Control Field Descriptions
Bit
Field
Type
Default
Description
7-4
VDS_LVL_LC
R/W
1001b
0000b = 0.06 V
0001b = 0.13 V
0010b = 0.2 V
0011b = 0.26 V
0100b = 0.31 V
0101b = 0.45 V
0110b = 0.53 V
0111b = 0.6 V
1000b = 0.68 V
1001b = 0.75 V
1010b = 0.94 V
1011b = 1.13 V
1100b = 1.3 V
1101b = 1.5 V
1110b = 1.7 V
1111b = 1.88 V
3-0
VDS_LVL_HC
R/W
1001b
0000b = 0.06 V
0001b = 0.13 V
0010b = 0.2 V
0011b = 0.26 V
0100b = 0.31 V
0101b = 0.45 V
0110b = 0.53 V
0111b = 0.6 V
1000b = 0.68 V
1001b = 0.75 V
1010b = 0.94 V
1011b = 1.13 V
1100b = 1.3 V
1101b = 1.5 V
1110b = 1.7 V
1111b = 1.88 V
64
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8.6.2.9 IC9 Control Register (Address = 0x0C) [reset = 0x2F]
IC9 Control is shown in Figure 57 and described in Table 29.
Figure 57. IC9 Control Register
7
COAST
R/W-0b
6
5
4
TRETRY
R/W-01b
3
DEAD_TIME
R/W-01b
2
TDRIVE_MAX
R/W-1b
1
0
TDRIVE
R/W-11b
Table 29. IC9 Control Field Descriptions
Bit
Field
Type
Default
Description
7
COAST
R/W
0b
Write a 1 to this bit to put all the MOSFETs in the Hi-Z state
6-5
TRETRY
R/W
01b
00b = 2 ms
01b = 4 ms
10b = 6 ms
11b = 8 ms
4-3
DEAD_TIME
R/W
01b
00b = 500 ns
01b = 1000 ns
10b = 2000 ns
11b = 4000 ns
2
1-0
TDRIVE_MAX
R/W
1b
Write a 0 to this bit to disable the maximum tDRIVE time of 20 µs.
This bit is automatically enabled when IDRIVE = 0000b, 0001b,
0010b, or 0011b is selected
TDRIVE
R/W
11b
00b = 500 ns peak gate-current drive time
01b = 1000 ns peak gate-current drive time
10b = 2000 ns peak gate-current drive time
11b = 3000 ns peak gate-current drive time
8.6.2.10 IC10 Control Register (Address = 0x0D) [reset = 0x61]
IC10 Control is shown in Figure 58 and described in Table 30.
Figure 58. IC10 Control Register
7
6
LOCK
R/W-011b
5
4
DIS_CPUV
R/W-0b
3
DIS_GDF
R/W-0b
2
1
OCP_DEG
R/W-001b
0
Table 30. IC10 Control Field Descriptions
Bit
Field
Type
Default
Description
7-5
LOCK
R/W
011b
Write 110b to lock the settings by ignoring further register writes
except to these bits and address 0x04h bit 7 (CLR_FLT). Writing
any sequence other than 110b has no effect when unlocked.
Write 011b to this register to unlock all registers. Writing any
sequence other than 011b has no effect when locked.
4
DIS_CPUV
R/W
0b
3
DIS_GDF
R/W
0b
0b = Charge-pump undervoltage lockout fault is enabled
1b = Charge-pump undervoltage lockout fault is disabled
0b = Gate drive fault is enabled
1b = Gate drive fault is disabled
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Table 30. IC10 Control Field Descriptions (continued)
Bit
Field
Type
Default
Description
2-0
OCP_DEG
R/W
001b
000b = 2.5 µs
001b = 4.75 µs
010b = 6.75 µs
011b = 8.75 µs
100b = 10.25 µs
101b = 11.5 µs
110b = 16.5 µs
111b = 20.5 µs
8.6.2.11 IC11 Control Register (Address = 0x0E) [reset = 0x00]
IC11 Control is shown in Figure 59 and described in Table 31.
Figure 59. IC11 Control Register
7
RSVD
R/W-0b
6
OTW_REP
R/W-0b
5
CBC
R/W-0b
4
DIS_VDS_C
R/W-0b
3
DIS_VDS_B
R/W-0b
2
DIS_VDS_A
R/W-0b
1
0
OCP_MODE
R/W-00b
Table 31. IC11 Control Field Descriptions
Bit
Field
Type
Default
Description
7
RSVD
R/W
0b
Reserved
6
OTW_REP
R/W
0b
0b = Overtemperature warning is not reported on nFAULT
5
CBC
R/W
0b
In retry OCP_MODE, for both VDS_OCP and SEN_OCP, the
fault is automatically cleared when a PWM input is given
4
DIS_VDS_C
R/W
0b
Write a 1 to this bit to disable VDS_OCP for MOSFETs in Phase
C
3
DIS_VDS_B
R/W
0b
Write a 1 to this bit to disable VDS_OCP for MOSFETs in Phase
B
2
DIS_VDS_A
R/W
0b
Write a 1 to this bit to disable VDS_OCP for MOSFETs in Phase
A
1-0
OCP_MODE
R/W
00b
00b = Overcurrent causes a latched fault
1b = Overtemperature warning is reported on nFAULT
01b = Overcurrent causes an automatic retrying fault
10b = Overcurrent is report only but no action is taken
11b = Overcurrent is not reported and no action is taken
8.6.2.12 IC12 Control Register (Address = 0x0F) [reset = 0x2A]
IC12 Control is shown in Figure 60 and described in Table 32.
Figure 60. IC12 Control Register
7
LS_REF
R/W-0b
66
6
CSA_FET
R/W-0b
5
4
CSA_GAIN_C
R/W-10b
3
2
CSA_GAIN_B
R/W-10b
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1
0
CSA_GAIN_A
R/W-10b
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Table 32. IC12 Control Field Descriptions
Bit
7
Field
Type
Default
Description
LS_REF
R/W
0b
0b = VDS_OCP for the low-side MOSFET is measured
across DLx to SLx
1b = VDS_OCP for the low-side MOSFET is measured across
DLx to AGND (see Figure 37)
6
CSA_FET
R/W
0b
0b = Current sense amplifier positive input is SPx
1b = Current sense amplifier positive input is DLx (also
automatically sets the LS_REF bit to 1b
5-4
CSA_GAIN_C
R/W
10b
00b = 5 V/V current sense amplifier gain
01b = 10 V/V current sense amplifier gain
10b = 20 V/V current sense amplifier gain
11b = 40 V/V current sense amplifier gain
3-2
CSA_GAIN_B
R/W
10b
00b = 5 V/V current sense amplifier gain
01b = 10 V/V current sense amplifier gain
10b = 20 V/V current sense amplifier gain
11b = 40 V/V current sense amplifier gain
1-0
CSA_GAIN_A
R/W
10b
00b = 5 V/V current sense amplifier gain
01b = 10 V/V current sense amplifier gain
10b = 20 V/V current sense amplifier gain
11b = 40 V/V current sense amplifier gain
8.6.2.13 IC13 Control Register (Address = 0x10) [reset = 0x7F]
IC13 Control is shown in Figure 61 and described in Table 33.
Figure 61. IC13 Control Register
7
CAL_MODE
R/W-0b
6
VREF_DIV
R/W-1b
5
4
3
SEN_LVL_C
R/W-11b
2
1
SEN_LVL_B
R/W-11b
0
SEN_LVL_B
R/W-11b
Table 33. IC13 Control Field Descriptions
Bit
Field
Type
Default
Description
7
CAL_MODE
R/W
0b
0b = Amplifier calibration operates in manual mode
6
VREF_DIV
R/W
1b
SEN_LVL_C
R/W
11b
1b = Amplifier calibration uses internal auto calibration routine
0b = Sense amplifier reference voltage is VREF (unidirectional
mode)
1b = Sense amplifier reference voltage is VREF divided by 2
5-4
00b = Sense OCP 0.25 V
01b = Sense OCP 0.5 V
10b = Sense OCP 0.75 V
11b = Sense OCP 1 V
3-2
SEN_LVL_B
R/W
11b
00b = Sense OCP 0.25 V
01b = Sense OCP 0.5 V
10b = Sense OCP 0.75 V
11b = Sense OCP 1 V
1-0
SEN_LVL_A
R/W
11b
00b = Sense OCP 0.25 V
01b = Sense OCP 0.5 V
10b = Sense OCP 0.75 V
11b = Sense OCP 1 V
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8.6.2.14 IC14 Control Register (Address = 0x10) [reset = 0x00]
IC14 Control is shown in Figure 62 and described in Table 34.
Figure 62. IC14 Control Register
7
6
RSVD
R/W-00b
5
DIS_SEN_C
R/W-0b
4
DIS_SEN_B
R/W-0b
3
DIS_SEN_A
R/W-0b
2
CSA_CAL_C
R/W-0b
1
CSA_CAL_B
R/W-0b
0
CSA_CAL_A
R/W-0b
Table 34. IC14 Control Field Descriptions
Bit
Field
Type
Default
Description
7-6
RSVD
R/W
00b
Reserved
5
DIS_SEN_C
R/W
0b
0b = Sense overcurrent fault is enabled for Phase C
4
DIS_SEN_B
R/W
0b
3
DIS_SEN_A
R/W
0b
2
CSA_CAL_C
R/W
0b
1b = Sense overcurrent fault is disabled for Phase C
0b = Sense overcurrent fault is enabled for Phase B
1b = Sense overcurrent fault is disabled for Phase B
0b = Sense overcurrent fault is enabled for Phase A
1b = Sense overcurrent fault is disabled for Phase A
0b = Normal current sense amplifier C operation
1b = Short inputs to current sense amplifier C for offset
calibration (manual calibration mode) if CAL_MODE = 0b. Auto
calibration mode if CAL_MODE = 1b.
1
CSA_CAL_B
R/W
0b
0b = Normal current sense amplifier B operation
1b = Short inputs to current sense amplifier B for offset
calibration (manual calibration mode) if CAL_MODE = 0b. Auto
calibration mode if CAL_MODE = 1b.
0
CSA_CAL_A
R/W
0b
0b = Normal current sense amplifier A operation
1b = Short inputs to current sense amplifier A for offset
calibration (manual calibration mode) if CAL_MODE = 0b. Auto
calibration mode if CAL_MODE = 1b.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The DRV8343-Q1 device is primarily used in applications for three-phase brushless DC motor control. The
design procedures in the Typical Application section highlight how to use and configure the DRV8343-Q1 device.
9.2 Typical Application
9.2.1 Primary Application
The DRV8343-Q1 SPI device is used in this application example.
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Typical Application (continued)
VCC
CVSDO
3.3 V, 30 mA
37
AGND
DVDD
INHA
CAL
38
39
40
41
42
INLA
43
INHB
45
44
INLB
VSDO
CPL
INHC
46
INLC
1
PGND
NC
48
47
CDVDD
36
ENABLE
35
2
CFLY
CPH
nSCS
VCP
SCLK
3
VM
33
CVM2
CVM1
5
32
SDO
VDRAIN
VDRAIN
6
SHA
30
VREF
8
DLA
29
DLA
SOA
GLA
SOB
SLA
SOC
SPA
SNC
9
GLA
27
26
11
SPA
12
SNA
SPC
SLC
24
SLC
GLC
23
GLC
DLC
SHC
22
DLC
SHC
GHC
21
GHC
20
GHB
GHB
19
SHB
SHB
18
DLB
17
DLB
GLB
SLB
16
15
SLB
SPB
14
SPB
13
SNB
GLB
SPC
VM
VM
VM
SNC
25
SNB
SNA
CVREF
28
10
SLA
+
VM
VM
+
VDRAIN
GHA
GHB
GHC
SHA
SHB
SHC
DLA
DLB
DLC
C
B
A
GLB
GLA
GLC
SLA
SLB
SLC
SPA
SPB
SPC
RSENSE
SNA
VCC
nFAULT
GND
(PAD)
7
SHA
RnFAULT
31
GHA
GHA
VCC
SDI
VM
+
CVM3
34
4
CVCP
RSENSE
SNB
RSENSE
SNC
Figure 63. Primary Application Schematic
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Typical Application (continued)
9.2.1.1 Design Requirements
Table 35 lists the example input parameters for the system design.
Table 35. Design Parameters
EXAMPLE DESIGN PARAMETER
REFERENCE
Nominal supply voltage
VVM
Supply voltage range
MOSFET part number
EXAMPLE VALUE
24 V
8 V to 45 V
CSD18536KCS
MOSFET total gate charge
Qg
83 nC (typical) at VVGS = 10 V
MOSFET gate to drain charge
Qgd
14 nC (typical)
tr
1000 ns
ƒPWM
10 kHz
Maximum motor current
Imax
100 A
ADC reference voltage
VVREF
3.3 V
Winding sense current range
ISENSE
–40 A to +40 A
IRMS
28.3 A
Target output rise time
PWM Frequency
Motor RMS current
Sense resistor power rating
System ambient temperature
PSENSE
2W
TA
–40°C to 125°C
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 External MOSFET Support
The DRV8343-Q1 MOSFET support is based on the capacity of the charge pump and PWM switching frequency
of the output. For a quick calculation of MOSFET driving capacity, use Equation 6 and Equation 7 for three
phase BLDC motor applications.
Trapezoidal 120° Commutation: IVCP > Qg × ƒPWM
where
• ƒPWM is the maximum desired PWM switching frequency.
• IVCP is the charge pump capacity, which depends on the VM pin voltage.
• The multiplier based on the commutation control method, may vary based on implementation.
Sinusoidal 180° Commutation: IVCP > 3 × Qg × ƒPWM
(6)
(7)
9.2.1.2.1.1 Example
If a system with a VVM voltage of 8 V (IVCP = 15 mA) uses a maximum PWM switching frequency of 10 kHz, then
the charge pump can support MOSFETs using trapezoidal commutation with a Qg less than 750 nC, and
MOSFETs using sinusoidal commutation with a Qg less than 250 nC.
9.2.1.2.2 IDRIVE Configuration
The strength of the gate drive current, IDRIVE, is selected based on the gate-to-drain charge of the external
MOSFETs and the target rise and fall times at the outputs. If IDRIVE is selected to be too low for a given
MOSFET, then the MOSFET may not turn on completely within the tDRIVE time and a gate drive fault may be
asserted. Additionally, slow rise and fall times result in higher switching power losses. TI recommends adjusting
these values in the system with the required external MOSFETs and motor to determine the best possible setting
for any application.
The IDRIVEP and IDRIVEN current for both the low-side and high-side MOSFETs are independently adjustable on
SPI devices through the SPI registers. On hardware interface devices, both source and sink settings are selected
at the same time on the IDRIVE pin.
For MOSFETs with a known gate-to-drain charge Qgd, desired rise time (tr), and a desired fall time (tf), use
Equation 8 and Equation 9 to calculate the value of IDRIVEP and IDRIVEN (respectively).
IDRIVEP ! Qgd u tr
(8)
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2 u IDRIVEP
(9)
9.2.1.2.2.1 Example
Use Equation 10 to calculate the value of IDRIVEP for a gate-to-drain charge of 14 nC and a rise time from 100 to
300 ns.
IDRIVEP
12 nC
14 mA
1000 ns
(10)
Select an IDRIVEP value that is close to 14 mA which will set the IDRIVEN value close to 28 mA. For this example,
the value of IDRIVEP was selected as 15 mA.
9.2.1.2.3 VDS Overcurrent Monitor Configuration
The VDS monitors are configured based on the worst-case motor current and the RDS(on) of the external
MOSFETs as shown in Equation 11.
VDS _ OCP ! Imax u RDS(on)max
(11)
9.2.1.2.3.1 Example
The goal of this example is to set the VDS monitor to trip at a current greater than 100 A. According to the
CSD18536KCS 60 V N-Channel NexFET™ Power MOSFET data sheet, the RDS(on) value is 1.8 times higher at
175°C, and the maximum RDS(on) value at a VGS of 10 V is 1.6 mΩ. From these values, the approximate worstcase value of RDS(on) is 1.8 × 1.6 mΩ = 2.88 mΩ.
Using Equation 11 with a value of 2.88 mΩ for RDS(on) and a worst-case motor current of 100 A, Equation 12
shows the calculated the value of the VDS monitors.
VDS _ OCP ! 100 A u 2.88 m:
VDS _ OCP ! 0.288 V
(12)
For this example, the value of VDS_OCP was selected as 0.31 V.
The SPI devices allow for adjustment of the deglitch time for the VDS overcurrent monitor. The deglitch time can
be set to 2 µs, 4 µs, 6 µs, 8 µs, 10 µs, 12 µs, 16 µs, or 20 µs.
9.2.1.2.4 Sense Amplifier Bidirectional Configuration
The sense amplifier gain on the DRV8343-Q1 device and sense resistor value are selected based on the target
current range, VREF voltage supply, power rating of the sense resistor, and operating temperature range. In
bidirectional operation of the sense amplifier, the dynamic range at the output is approximately calculated as
shown in Equation 13.
VVREF
VO
VVREF 0.25 V
2
(13)
Use Equation 14 to calculate the approximate value of the selected sense resistor with VO calculated using
Equation 13.
VO
R
PSENSE ! IRMS2 u R
AV u I
(14)
From Equation 13 and Equation 14, select a target gain setting based on the power rating of the target sense
resistor.
9.2.1.2.4.1 Example
In this system example, the value of the VREF voltage is 3.3 V with a sense current from –40 to +40 A. The
linear range of the SOx output is 0.25 V to VVREF – 0.25 V (from the VLINEAR specification). The differential range
of the sense amplifier input is –0.3 to +0.3 V (VDIFF).
3.3 V
VO
3.3 V 0.25 V
1.4 V
(15)
2
72
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1.4 V
A V u 40 A
2.5 m: !
2 W ! 28.32 u R o R
2.5 m:
(16)
1.4 V
o A V ! 14
A V u 40 A
(17)
Therefore, the gain setting must be selected as 20 V/V or 40 V/V and the value of the sense resistor must be
less than 2.5 mΩ to meet the power rating for the sense resistor. For this example, the gain setting was selected
as 20 V/V. The value of the resistor and worst case current can be verified that R < 2.5 mΩ and Imax = 40 A does
not violate the differential range specification of the sense amplifier input (VSPxD).
9.2.1.2.5 External Components
Table 36lists the recommended external components.
Table 36. External Components
(1)
(2)
COMPONENT
PIN 1
PIN 2
RECOMMENDED
CFLY
CPH
CPL
47-nF ceramic capacitor X5R or X7R rated for VM (1)
CVCP
VCP
VM
1-µF ceramic capacitor X5R or X7R rated for VCP – VM
(1)
(1)
CVM1
VM
PGND
0.1-µF ceramic capacitor X5R or X7R rated for VM
CVM2
VM
PGND
4.7-µF ceramic capacitor X5R or X7R rated for VM (1)
CVM3
VM
PGND
> 10-µF electrolytic capacitor rated for VM (1)
CVREF
VREF
AGND
0.1-µF ceramic capacitor X5R or X7R rated for VREF (1)
CDVDD
DVDD
AGND
1-µF ceramic capacitor X5R or X7R rated for DVDD (1)
CVSDO
VSDO
AGND
0.1-µF ceramic capacitor X5R or X7R rated for VSDO (1). DRV8343S
only
RnFAULT
nFAULT
VCC (2)
2.5 – 10 kΩ pulled up the MCU I/O (VCC) power supply
RSENSE
SPx
SNx
2.5 mΩ shunt resistor for current sense amplifier
The effective capacitance of ceramic capacitors varies with DC operating voltage and temperature. As a rule of thumb, expect the
effective capacitance to decrease by as much as 50% at the extremes of the operating voltage. The system designer must review the
capacitor characteristics and select the component accordingly.
The VCC pin is not a pin on the DRV8343-Q1 device, but a VCC supply voltage pullup is required for the open-drain output, nFAULT.
These pins can also be pulled up to DVDD.
9.2.1.3 Application Curves
Figure 64. Device Power Up Sequence Waveform
Figure 65. BLDC Motor Commutation and Current Sense
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9.2.2 Application With One Sense Amplifier
In this application, one sense amplifier is used in unidirectional mode for a summing current sense scheme often
used in trapezoidal or hall-based BLDC commutation control.
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VCC
3.3 V, 30 mA
CVSDO
CFLY
37
CAL
AGND
DVDD
38
39
40
41
INLA
INHA
42
43
INHB
45
46
44
INLB
VSDO
CPL
INHC
1
INLC
NC
PGND
47
48
CDVDD
36
ENABLE
2
35
CPH
nSCS
VCP
SCLK
3
VM
CVCP
4
33
CVM2
CVM1
5
32
SDO
VDRAIN
VDRAIN
GHA
SHA
30
VREF
29
8
DLA
DLA
SOA
GLA
SOB
SLA
SOC
SPA
SNC
SNA
SPC
9
GLA
27
26
11
SPA
12
SLC
24
SLC
GLC
GLC
23
DLC
22
DLC
SHC
21
SHC
GHC
GHC
20
GHB
GHB
19
SHB
SHB
18
DLB
17
VM
VM
VM
DLB
GLB
SLB
16
15
SLB
SPB
14
13
GLB
25
SNB
SNA
CVREF
28
10
SLA
VCC
nFAULT
GND
(PAD)
7
SHA
RnFAULT
31
6
GHA
VCC
SDI
VM
+
CVM3
34
+
VM
VM
+
VDRAIN
GHA
GHB
GHC
SHA
SHB
SHC
DLA
DLB
DLC
C
B
A
GLA
GLB
GLC
SLA
SLB
SLC
SPA
RSENSE
SNA
Figure 66. Alternative Application Schematic
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9.2.2.1 Design Requirements
Table 37 lists the example design input parameters for system design.
Table 37. Design Parameters
EXAMPLE DESIGN PARAMETER
REFERENCE
EXAMPLE VALUE
ADC reference voltage
VVREF
3.3 V
Sensed current
ISENSE
0 to 40 A
IRMS
28.3 A
Motor RMS current
Sense-resistor power rating
System ambient temperature
PSENSE
3W
TA
–40°C to 125°C
9.2.2.2 Detailed Design Procedure
9.2.2.2.1 Sense Amplifier Unidirectional Configuration
The sense amplifiers are configured to be unidirectional through the registers on SPI devices by writing a 0 to the
VREF_DIV bit.
The sense amplifier gain and sense resistor values are selected based on the target current range, VREF, power
rating of the sense resistor, and operating temperature range. In unidirectional operation of the sense amplifier,
use Equation 18 to calculate the approximate value of the dynamic range at the output.
VO
VVREF 0.25 V 0.25 V VVREF 0.5 V
(18)
Use Equation 19 to calculate the approximate value of the selected sense resistor.
VO
R
PSENSE ! IRMS2 u R
AV u I
where
•
VO
VVREF
0.5 V
(19)
From Equation 18 and Equation 19, select a target gain setting based on the power rating of a target sense
resistor.
9.2.2.2.1.1 Example
In this system example, the value of the VREF voltage is 3.3 V with a sense current from 0 to 40 A. The linear
range of the SOx output for the device is 0.25 V to VVREF – 0.25 V (from the VLINEAR specification). The
differential range of the sense-amplifier input is –0.3 to +0.3 V (VDIFF).
VO 3.3 V 0.5 V 2.8 V
(20)
R
2.8 V
A V u 40 A
3 W ! 28.32 u R o R
3.75 m:
(21)
2.8 V
3.75 m: !
o A V ! 18.7
A V u 40 A
(22)
Therefore, the gain setting must be selected as 20 V/V or 40 V/V and the value of the sense resistor must be
less than 3.75 mΩ to meet the power rating for the sense resistor. For this example, the gain setting was
selected as 20 V/V. The value of the resistor and worst-case current can be verified that R < 3.75 mΩ and Imax =
40 A does not violate the differential range specification of the sense amplifier input (VSPxD).
9.2.2.2.1.2 Unused pins
One sense amplifier, channel A, is used in the figure Figure 66, and channel B and C are not used. The
connections of the channel B and C sense amplifier signals are recommended as below;
• Connect SPB, SNB, SPC and SNC pins to AGND
• Leave SOB and SOC pins open
76
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9.2.2.2.2 External Components
Refer to Table 36 for the recommended external components.
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10 Power Supply Recommendations
The DRV8343-Q1 device is designed to operate from an input voltage supply (VM) range from 6 V to 60 V.
10.1 Power Supply Consideration in Generator Mode
When the motor shaft of BLDC or PMSM motor is turned by an external force, the motor windings will generate a
voltage on the motor inputs. This condition is known as generator mode or motor back-drive. In the generator
mode, a positive voltage can be observed on SHx pins of the device. If there is a switch between VDRAIN and
VM (SWVDRAIN in Figure 67 ) and the following conditions exist in the system, the absolute max voltage of VCP
with respect to VM needs to be reviewed;
• Generator mode
• SWVDRAIN is off
• VM and VCP are low voltage (e.g. VM = 0V)
If SHx voltage (VSHx) exceeds VCP voltage, the VCP voltage starts following VSHx because of the device internal
diodes D1 and D2 (or D3). If VCP - VM voltage exceeds the absolute max voltage of DRV8343-Q1, the ESD
diode D4 starts conducting and results in a big current from SHx to VM through the diodes D2, D1 and D4. To
avoid this condition, it is recommended to add an external diode DVDRAIN_VM between VDRAIN and VM.
SWVDRAIN
12-V or 24-V
Battery
Optional
VM
VCP
DVDRAN_VM
DRV8343-Q1
ESD
VDRAIN
D4
D1
GHx
Level
shifter
INHx
D2
external
force
D3
SHx
M
VSHx
VGLS
GLx
Level
shifter
INLx
SLx
GND
Figure 67. Power Supply Consideration in Generator mode
10.2 Bulk Capacitance Sizing
Having appropriate local bulk capacitance is an important factor in motor drive system design. It is generally
beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size. The
amount of local capacitance depends on a variety of factors including:
• The highest current required by the motor system
• The power supply's type, capacitance, and ability to source current
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Bulk Capacitance Sizing (continued)
•
•
•
•
The amount of parasitic inductance between the power supply and motor system
The acceptable supply voltage ripple
Type of motor (brushed DC, brushless DC, stepper)
The motor startup and braking methods
The inductance between the power supply and motor drive system will limit the rate current can change from the
power supply. If the local bulk capacitance is too small, the system will respond to excessive current demands or
dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage
stays stable and high current can be quickly supplied.
The data sheet provides a recommended minimum value, but system level testing is required to determine the
appropriate sized bulk capacitor.
Parasitic Wire
Inductance
Motor Drive System
Power Supply
VM
+
+
Motor Driver
±
GND
Local
Bulk Capacitor
IC Bypass
Capacitor
Figure 68. Motor Drive Supply Parasitics Example
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11 Layout
11.1 Layout Guidelines
Bypass the VM pin to the PGND pin using a low-ESR ceramic bypass capacitor CVM1. Place this capacitor as
close to the VM pin as possible with a thick trace or ground plane connected to the PGND pin. Additionally,
bypass the VM pin using a bulk capacitor rated for VM. This component can be electrolytic. This capacitance
must be at least 10 µF.
Additional bulk capacitance is required to bypass the high current path on the external MOSFETs. This bulk
capacitance should be placed such that it minimizes the length of any high current paths through the external
MOSFETs. The connecting metal traces should be as wide as possible, with numerous vias connecting PCB
layers. These practices minimize inductance and let the bulk capacitor deliver high current.
Place a low-ESR ceramic capacitor CFLY between the CPL and CPH pins. Additionally, place a low-ESR ceramic
capacitor CVCP between the VCP and VM pins.
Bypass the DVDD pin to the AGND pin with CDVDD. Place this capacitor as close to the pin as possible and
minimize the path from the capacitor to the AGND pin.
The VDRAIN pin can be shorted directly to the VM pin. However, if a significant distance is between the device
and the external MOSFETs, use a dedicated trace to connect to the common point of the drains of the high-side
external MOSFETs. Do not connect the SLx pins directly to PGND. Instead, use dedicated traces to connect
these pins to the sources of the low-side external MOSFETs. These recommendations offer more accurate VDS
sensing of the external MOSFETs for overcurrent detection.
Minimize the loop length for the high-side and low-side gate drivers. The high-side loop is from the GHx pin of
the device to the high-side power MOSFET gate, then follows the high-side MOSFET source back to the SHx
pin. The low-side loop is from the GLx pin of the device to the low-side power MOSFET gate, then follows the
low-side MOSFET source back to the PGND pin.
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D
S
D
S
D
G
D
D
G
D
S
D
S
D
S
D
G
D
S
D
S
D
S
S
D
S
D
S
D
G
D
S
D
S
D
S
D
G
D
D
G
D
S
D
S
D
S
SLC
OUTC
VREF
SOA
SOB
SOC
VCC
ENABLE
nSCS
SCLK
SDI
SO
nFAULT
S
37
38
39
40
41
42
43
44
45
46
47
48
Thermal Pad
24
23
22
21
20
19
18
17
16
15
14
13
GLC
DLC
SHC
GHC
GHB
SHB
DLB
GLB
SLB
SPB
SNB
OUTA
CPL
CPH
VCP
VM
VDRAIN
GHA
SHA
DLA
GLA
SLA
SPA
SNA
1
2
3
4
5
6
7
8
9
10
11
12
CAL
AGND
DVDD
VSDO
INHA
INLA
INHB
INLB
INHC
INLC
PGND
NC
OUTB
36
35
34
33
32
31
30
29
28
27
26
25
ENABLE
nSCS
SCLK
SDI
SDO
nFAULT
VREF
SOA
SOB
SOC
SNC
SPC
CAL
INLC
INHC
INLB
INHB
INLA
INHA
VCC
11.2 Layout Example
Figure 69. Layout Example
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Device Nomenclature
The following figure shows a legend for interpreting the complete device name:
DRV83
(4)
(3)
(S)
(Q) (PHP) (R) (Q1)
Prefix
DRV83 ± Three Phase Brushless DC
Qualified to use in
automotive environment
Tape and Reel
R ± Tape and Reel
T ± Small Tape and Reel
Series
4 ± 60 V device
Package
PHP ± 7 × 7 × 1 mm QFP
Operating Temperature
Q ± N40C to 125C
Sense amplifiers
0 ± No sense amplifiers
3 ± Three current sense amplifiers
Interface
S ± SPI
H ± Hardware
12.2 Documentation Support
12.2.1 Related Documentation
• Texas Instruments, AN-1149 Layout Guidelines for Switching Power Supplies application report
• Texas Instruments, Enhanced Fault Diagnostics in DRV834x-Q1 TI TechNote
• Texas Instruments, Hardware Design Considerations for an Electric Bicycle using BLDC Motor
• Texas Instruments, Layout Guidelines for Switching Power Supplies
• Texas Instruments, Sensored 3-Phase BLDC Motor Control Using MSP430™ application report
• Texas Instruments, Understanding IDRIVE and TDRIVE In TI Motor Gate Drivers application report
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
PowerPAD, NexFET, MSP430, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
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12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
DRV8343HPHPRQ1
ACTIVE
HTQFP
PHP
48
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
DRV8343H
DRV8343SPHPRQ1
ACTIVE
HTQFP
PHP
48
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
DRV8343S
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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