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DRV8848
SLLSEL7A – OCTOBER 2014 – REVISED NOVEMBER 2015
DRV8848 Dual H-Bridge Motor Driver
1 Features
3 Description
•
The DRV8848 provides a dual H-bridge motor driver
for home appliances and other mechatronic
applications. The device can be used to drive one or
two DC motors, a bipolar stepper motor, or other
loads. A simple PWM interface allows easy
interfacing to controller circuits.
1
•
•
•
•
•
•
•
Dual H-Bridge Motor Driver
– Single/Dual Brushed DC
– Stepper
PWM Control Interface
Optional Current Regulation With 20-μs Fixed OffTime
High Output Current per H-Bridge
– 2-A Maximum Driver Current at 12 V and
TA = 25°C
– Parallel Mode Available Capable of 4-A
Maximum Driver Current at 12 V and
TA = 25°C
4- to 18-V Operating Supply Voltage Range
Low-Current 3-µA Sleep Mode
Thermally-Enhanced Surface Mount Package
Protection Features
– VM Undervoltage Lockout (UVLO)
– Overcurrent Protection (OCP)
– Thermal Shutdown (TSD)
– Fault Condition Indication Pin (nFAULT)
A low-power sleep mode is provided, which shuts
down internal circuitry to achieve very-low quiescent
current draw. This sleep mode can be set using a
dedicated nSLEEP pin.
Internal protection functions are provided for UVLO,
OCP, short-circuit protection, and overtemperature.
Fault conditions are indicated by a nFAULT pin.
Device Information(1)
PART NUMBER
2 Applications
•
•
•
The output block of each H-bridge driver consists of
N-channel and P-channel power MOSFETs
configured as full H-bridges to drive the motor
windings. Each H-bridge includes circuitry to regulate
the winding current using a fixed off-time chopping
scheme. The DRV8848 is capable of driving up to 2
A of current from each output or 4 A of current in
parallel mode (with proper heat sinking, at 12 V and
TA = 25°C).
DRV8848
Appliances
General Brushed and Stepper Motors
Printers
PACKAGE
HTSSOP (16)
BODY SIZE (NOM)
5.00 mm × 6.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
4 to 18 V
Controller
PWM
PWM
VREF
nFAULT
DRV8848
Dual
H-Bridge
Motor
Driver
1A
1A
DC
M
DC
M
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRV8848
SLLSEL7A – OCTOBER 2014 – REVISED NOVEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 9
7.3 Feature Description................................................... 9
7.4 Device Functional Modes........................................ 14
8
Application and Implementation ........................ 15
8.1 Application Information............................................ 15
8.2 Typical Application ................................................. 15
9
Power Supply Recommendations...................... 17
9.1 Bulk Capacitance Sizing ......................................... 17
10 Layout................................................................... 18
10.1 Layout Guidelines ................................................. 18
10.2 Layout Example .................................................... 18
11 Device and Documentation Support ................. 19
11.1
11.2
11.3
11.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
19
19
19
19
12 Mechanical, Packaging, and Orderable
Information ........................................................... 19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (October 2014) to Revision A
Page
•
Updated unit for RDS(ON) .......................................................................................................................................................... 5
•
Corrected lines for Figure 6 ................................................................................................................................................. 10
•
Added Community Resources ............................................................................................................................................. 19
2
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SLLSEL7A – OCTOBER 2014 – REVISED NOVEMBER 2015
5 Pin Configuration and Functions
PWP Package
16-Pin HTSSOP
Top View
nSLEEP
AOUT1
AISEN
AOUT2
BOUT2
BISEN
BOUT1
nFAULT
1
16
2
15
3
14
4
13
GND
(PPAD)
5
12
6
11
7
10
8
9
AIN1
AIN2
VINT
GND
VM
VREF
BIN2
BIN1
Pin Functions
PIN
NAME
NO.
TYPE
DESCRIPTION
AIN1
16
I
Bridge A input 1
Controls AOUT1; tri-level input
AIN2
15
I
Bridge A input 2
Controls AOUT2; tri-level input
AISEN
3
O
Winding A sense
Connect to current sense resistor for bridge A, or GND if current regulation is not required
AOUT1
2
AOUT2
4
O
Winding A output
BIN1
9
I
Bridge B input 1
Controls BOUT1; internal pulldown
BIN2
10
I
Bridge B input 2
Controls BOUT2; internal pulldown
BISEN
6
O
Winding B sense
Connect to current sense resistor for bridge A, or GND if current regulation is not required
BOUT1
7
BOUT2
5
O
Winding B output
13
GND
PPAD
PWR
Device ground
Both the GND pin and device PowerPAD must be connected to ground
nFAULT
8
OD
Fault indication pin
Pulled logic low with fault condition; open-drain output requires external pullup
nSLEEP
1
I
Sleep mode input
Logic high to enable device; logic low to enter low-power sleep mode; internal pulldown
VINT
14
—
Internal regulator
Internal supply voltage; bypass to GND with 2.2-μF, 6.3-V capacitor
VM
12
PWR
Power supply
Connect to motor power supply; bypass to GND with a 0.1- and 10-μF (minimum) ceramic
capacitor rated for VM
VREF
11
I
Full-scale current
reference input
Voltage on this pin sets the full scale chopping current; short to VINT if not supplying an
external reference voltage
External Components
(1)
COMPONENT
PIN 1
PIN 2
CVM
VM
GND
10-µF (minimum) ceramic capacitor rated for VM
RECOMMENDED
CVM
VM
GND
0.1-µF ceramic capacitor rated for VM
CVINT
VINT
GND
6.3-V, 2.2-µF ceramic capacitor
RnFAULT
VCC (1)
nFAULT
RAISEN
AISEN
GND
Sense resistor, see Typical Application for sizing
RBISEN
BISEN
GND
Sense resistor, see Typical Application for sizing
>1 kΩ
VCC is not a pin on the DRV8848, but a VCC supply voltage pullup is required for open-drain output nFAULT; nFAULT may be pulled
up to VINT
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SLLSEL7A – OCTOBER 2014 – REVISED NOVEMBER 2015
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range referenced with respect to GND (unless otherwise noted)
Power supply voltage (VM)
Power supply voltage ramp rate (VM)
(1)
MIN
MAX
UNIT
–0.3
20
V
0
2
V/µs
Internal regulator voltage (VINT)
–0.3
3.6
V
Analog input pin voltage (VREF)
–0.3
3.6
V
Control pin voltage (AIN1, AIN2, BIN1, BIN2, nSLEEP, nFAULT)
–0.3
7
V
Continuous phase node pin voltage (AOUT1, AOUT2, BOUT1, BOUT2)
–0.3
VVM + 0.6
V
Continuous shunt amplifier input pin voltage (AISEN, BISEN) (2)
–0.6
0.6
V
Peak drive current (AOUT1, AOUT2, BOUT1, BOUT2, AISEN, BISEN)
Internally limited
A
TJ
Operating junction temperature
–40
150
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Transients of ±1 V for less than 25 ns are acceptable.
6.2 ESD Ratings
VALUE
Electrostatic
discharge
V(ESD)
(1)
(2)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±4000
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Power supply voltage range (1)
VVM
VVREF
Reference rms voltage range
ƒPWM
Applied STEP signal
IVINT
VINT external load current
(2)
(3)
Irms
Motor rms current per H-bridge
TA
Operating ambient temperature
(1)
(2)
(3)
MIN
MAX
4
18
UNIT
V
1
3.3
V
0
250
kHz
1
mA
0
1
A
–40
85
°C
Note that RDS(ON) increases and maximum output current is reduced at VM supply voltages below 5 V.
Operational at VREF between 0 and 1 V, but accuracy is degraded.
Power dissipation and thermal limits must be observed.
6.4 Thermal Information
DRV8848
THERMAL METRIC (1)
PWP (HTSSOP)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
40.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
32.7
°C/W
RθJB
Junction-to-board thermal resistance
28.7
°C/W
ψJT
Junction-to-top characterization parameter
0.6
°C/W
ψJB
Junction-to-board characterization parameter
11.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
4.7
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
TA = 25°C, over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLIES (VM, VINT)
VVM
VM operating voltage
4
18
V
3.8
5.5
mA
1.2
IVM
VM operating supply current
VVM = 12 V, excluding winding current,
nSLEEP = 1
IVMQ
VM sleep mode supply current
VVM = 12 V, nSLEEP = 0
3
μA
tSLEEP
Sleep time
nSLEEP = 0 to sleep mode
1
ms
tWAKE
Wake time
nSLEEP = 1 to output transition
1
ms
tON
Power-on time
VVM > VUVLO rising to output transition
1
ms
VINT
VINT voltage
VVM > 4 V, IOUT = 0 A to 1 mA
2.5
0.5
3.13
3.3
3.47
V
0
0.7
V
5.5
LOGIC-LEVEL INPUTS (BIN1, BIN2, NSLEEP)
VIL
Input logic low voltage
VIH
Input logic high voltage
1.6
VHYS
Input logic hysteresis
100
IIL
Input logic low current
VIN = 0 V
–1
IIH
Input logic high current
VIN = 5 V
1
RPD
Pulldown resistance
tDEG
Input deglitch time
tPROP
Propagation delay
V
mV
1
μA
30
μA
BIN1, BIN2
200
nSLEEP
500
AIN1 or AIN2
400
ns
BIN1 or BIN2
200
ns
AIN1 or AIN2 edge to output change
800
ns
BIN1 or BIN2 edge to output change
400
ns
kΩ
TRI-LEVEL INPUTS (AIN1, AIN2)
VIL
Tri-level input logic low voltage
VIZ
Tri-level input Hi-Z voltage
0
0.7
VIH
Tri-level input logic high voltage
1.6
VHYS
Tri-level input hysteresis
100
IIL
Tri-level input logic low current
VIN = 0 V
–30
IIH
Tri-level input logic high current
VIN = 5 V
1
RPD
Tri-level pulldown resistance
To GND
170
kΩ
RPU
Tri-level pullup resistance
To VINT
340
kΩ
1.1
V
V
5.5
V
mV
–1
30
μA
μA
CONTROL OUTPUTS (NFAULT)
VOL
Output logic low voltage
IO = 5 mA
IOH
Output logic high leakage
VO = 3.3 V
–1
0.5
V
1
μA
MOTOR DRIVER OUTPUTS (AOUT1, AOUT2, BOUT1, BOUT2)
VVM = 12 V, I = 0.5 A, TJ = 25°C
550
VVM = 12 V, I = 0.5 A, TJ = 85°C (1)
660
VVM = 12 V, I = 0.5 A, TJ = 25°C
350
RDS(ON)
High-side FET on-resistance
RDS(ON)
Low-side FET on-resistance
IOFF
Off-state leakage current
tRISE
Output rise time
60
ns
tFALL
Output fall time
60
ns
tDEAD
Output dead time
200
ns
VVM = 12 V, I = 0.5 A, TJ = 85°C
(1)
VVM = 5 V, TJ = 25°C
Internal dead time
mΩ
mΩ
420
–1
1
μA
PWM CURRENT CONTROL (VREF, AISEN, BISEN)
IREF
Externally applied VREF input
current
VVREF = 1 to 3.3 V
VTRIP
xISEN trip voltage
For 100% current step with VVREF = 3.3 V
(1)
1
500
μA
mV
Not tested in production; limits are based on characterization data
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Electrical Characteristics (continued)
TA = 25°C, over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
tBLANK
Current sense blanking time
AISENSE
Current sense amplifier gain
tOFF
Current control constant off time
MIN
Reference only
TYP
MAX
UNIT
1.8
μs
6.6
V/V
20
μs
PROTECTION CIRCUITS
VVM falling; UVLO report
2.9
VUVLO
VM undervoltage lockout
IOCP
Overcurrent protection trip level
tDEG
Overcurrent deglitch time
2.8
μs
tOCP
Overcurrent protection period
1.6
ms
VVM rising; UVLO recovery
V
3
2
TTSD
(1)
Thermal shutdown temperature
Die temperature TJ
THYS
(1)
Thermal shutdown hysteresis
Die temperature TJ
150
A
160
180
°C
50
°C
6.6 Timing Requirements
TA = 25°C, over recommended operating conditions unless otherwise noted
NO.
MIN
MAX
UNIT
1
t1
Delay time, xIN1 to xOUT1
100
600
ns
2
t2
Delay time, xIN2 to xOUT1
100
600
ns
3
t3
Delay time, xIN1 to xOUT2
100
600
ns
4
t4
Delay time, xIN2 to xOUT2
100
600
ns
5
tF
Output rise time
50
150
ns
6
tR
Output fall time
50
150
ns
xIN1
xIN2
80%
1
xOUT1
2
80%
4
xOUTx
z
z
20%
20%
3
5
xOUT2
z
6
z
Figure 1. Timing Diagram
6
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6.7 Typical Characteristics
4.5
4
± ƒ&
25°C
85°C
125°C
± ƒ&
25°C
85°C
125°C
3.5
4
3
IVM (mA)
IVM (mA)
2.5
3.5
3
2
1.5
1
0.5
2.5
0
2
-0.5
0
5
10
VVM (V)
15
20
0
5
D001
Figure 2. IVM vs VVM
15
20
D002
Figure 3. IVMQ vs VVM
1.8
1.8
± ƒ&
25°C
1.6
85°C
125°C
1.6
RDSON HS + LS (:)
1.4
RDSON HS + LS (:)
10
VVM (V)
1.2
1
0.8
0.6
4V
12 V
18 V
1.4
1.2
1
0.4
0.8
0.2
0
0
5
10
VVM (V)
15
20
0.6
-50
D003
Figure 4. RDSON vs VVM
0
50
TA (°C)
100
150
D004
Figure 5. RDSON vs Temperature
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7 Detailed Description
7.1 Overview
The DRV8848 is an integrated motor driver solution for two DC motors or a bipolar stepper motor. The device
integrates two H-bridges that use NMOS low-side drivers and PMOS high-side drivers and current sense
regulation circuitry. The DRV8848 can be powered with a supply range between 4 to 18 V and is capable of
providing an output current to 1-A rms.
A simple PWM interface allows easy interfacing to the controller circuit.
The current regulation uses a fixed off-time (tOFF) PWM scheme. The current regulation trip point is controlled by
the value of the sense resistor and the voltage applied to VREF.
A low-power sleep mode is included, which allows the system to save power when not driving the motor.
8
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7.2 Functional Block Diagram
VM
VM
VM
0.1 µF
VINT
Internal Ref and
Regs
2.2 µF
10 µF
VREF
VM
VINT
AOUT1
AIN1
Gate
Drive
and
OCP
VINT
AIN2
DCM
VM
Step
Motor
AOUT2
BIN1
AISEN
ISEN
BIN2
VINT
Logic
optional
VREF
VM
nSLEEP
BOUT1
nFAULT
Gate
Drive
and
OCP
DCM
VM
OverTemp
BOUT2
ISEN
BISEN
optional
VREF
PPAD
GND
7.3 Feature Description
7.3.1 PWM Motor Drivers
DRV8848 contains two identical H-bridge motor drivers with current-control PWM circuitry. Figure 6 shows a
block diagram of the circuitry.
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Feature Description (continued)
VM
OCP
VM
xOUT1
xIN1
Predrive
xIN2
Step
Motor
xOUT2
PWM
OCP
-
xISEN
A=6.6
+
Optional
VREF
Internal
reference
Figure 6. PWM Motor Driver Circuitry
7.3.2 Bridge Control
Table 1 shows the logic for the inputs xIN1 and xIN2.
Table 1. Bridge Control
xIN1
xIN2
xOUT1
xOUT2
0
0
Z
Z
Coast (fast decay)
Function (DC Motor)
0
1
L
H
Reverse
1
0
H
L
Forward
1
1
L
L
Brake (slow decay)
SPACE
NOTE
Pins AIN1 and AIN2 are tri-level, so when they are left Hi-Z, they are not internally pulled
to logic low. When AIN1 or AIN2 are set to Hi-Z and not in parallel mode, the output driver
maintains the previous state.
10
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7.3.3 Parallel Operation
The two drivers can be used in parallel to deliver twice the current to a single motor. To enter parallel mode,
AIN1 and AIN2 must be left Hi-Z during power-up or when exiting sleep mode (nSLEEP toggling from 0 to 1).
BIN1 and BIN2 are used to control the drivers. Tie AISEN and BISEN to a single sense resistor if current control
is desired. To exit parallel mode, AIN1 and AIN2 must be driven high or low and the device must be powered-up
or exit sleep mode. Figure 7 shows a block diagram of the device using parallel mode.
VM
AOUT1
AIN1
Gate
Drive
and
OCP
AIN2
VM
AOUT2
BIN1
Controller
AISEN
ISEN
BIN2
Logic
VM
nSLEEP
BOUT1
Gate
Drive
and
OCP
DCM
VM
BOUT2
ISEN
BISEN
optional
VREF
Figure 7. Parallel Mode Operation
7.3.4 Current Regulation
The current through the motor windings is regulated by a fixed-off-time PWM current regulation circuit. With DC
brushed motors, current regulation can be used to limit the stall current (which is also the startup current) of the
motor.
Current regulation works as follows:
When an H-bridge is enabled, current rises through the winding at a rate dependent on the supply voltage and
inductance of the winding. If the current reaches the current chopping threshold, the bridge disables the current
for a time tOFF before starting the next PWM cycle. Note that immediately after the current is enabled, the voltage
on the xISEN pin is ignored for a period of time (tBLANK) before enabling the current sense circuitry. This blanking
time also sets the minimum on-time of the PWM cycle.
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The PWM chopping current is set by a comparator which compares the voltage across a current sense resistor,
connected to the xISEN pin, with a reference voltage. The reference voltage is derived from the voltage applied
to the VREF pin and it is VVREF / 6.6. The VREF pin can be tied, on board, to the 3.3 V – VINT pin, or it can be
externally forced to a desired VREF voltage.
The full scale chopping current in a winding is calculated as follows:
VVREF
IFS
6.6 u RISENSE
where
•
•
•
IFS is the regulated current.
VVREF is the voltage on the VREF pin.
RISENSE is the resistance of the sense resistor.
(1)
Example: If VVREF is 3.3 V and a 500-mΩ sense resistor is used, the full-scale chopping current is 3.3 V / (6.6 ×
500 mΩ) = 1 A.
Note that if the current control is not needed, the xISEN pins may be connected directly to ground. In this case,
VREF should be connected to VINT.
7.3.5 Current Recirculation and Decay Modes
During PWM current chopping, the H-bridge is enabled to drive current through the motor winding until the PWM
current chopping threshold is reached (see case 1 in Figure 8).
After the chopping current threshold is reached, the drive current is interrupted, but due to the inductive nature of
the motor, current must continue to flow for some period of time. This is called recirculation current. To handle
this recirculation current, the DRV8848 H-bridge operates in mixed decay mode.
Mixed decay is a combination of fast and slow decay modes. In fast decay mode, the opposite drivers are turned
on to allow the current to decay (see case 2 in Figure 8). If the winding current approaches zero, while in fast
decay, the bridge is disabled to prevent any reverse current flow. In slow decay mode, winding current is
recirculated by enabling both of the low-side FETs in the bridge (see case 3 in Figure 8). Mixed decay starts with
fast decay, then goes to slow decay. In DRV8848, the mixed decay ratio is 25% fast decay and 75% slow decay
(as shown in Figure 9).
12
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xVM
1 Drive Current
1
2 Fast decay
xOUT2
xOUT1
3 Slow decay
2
3
Figure 8. Decay Modes
PWM
ON
PWM OFF (tOFF)
Mixed Decay
25%
Itrip
25% of tOFF
PWM CYCLE
Figure 9. Mixed Decay
7.3.6 Protection Circuits
The DRV8848 is fully protected against undervoltage, overcurrent, and overtemperature events.
7.3.6.1 OCP
An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive. If this
analog current limit persists for longer than the OCP deglitch time tOCP, all FETs in the H-bridge are disabled and
the nFAULT pin is driven low. The device remains disabled until the retry time tRETRY occurs. The OCP is
independent for each H-bridge.
Overcurrent conditions are detected independently on both high-side and low-side devices; that is, a short to
ground, supply, or across the motor winding all result in an OCP event. Note that OCP does not use the current
sense circuitry used for PWM current control, so OCP functions even without presence of the xISEN resistors.
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7.3.6.2 TSD
If the die temperature exceeds safe limits TTSD, all FETs in the H-bridge are disabled and the nFAULT pin is
driven low. After the die temperature has fallen to a safe level, operation automatically resumes. The nFAULT pin
is released after operation has resumed.
7.3.6.3 UVLO
If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage, VUVLO, all circuitry in the
device is disabled, and all internal logic is reset. Operation resumes when VVM rises above the UVLO rising
threshold. The nFAULT pin is driven low during an undervoltage condition and is released after operation has
resumed.
Table 2. Fault Handling
FAULT
ERROR REPORT
H-BRIDGE
INTERNAL
CIRCUITS
VM undervoltage (UVLO)
nFAULT unlatched
Disabled
Shut down
System and fault clears on recovery
Overcurrent (OCP)
nFAULT unlatched
Disabled
Operating
System and fault clears on recovery and
motor is driven after time, tRETRY
Thermal shutdown (TSD)
nFAULT unlatched
Disabled
Operating
System and fault clears on recovery
RECOVERY
7.4 Device Functional Modes
The DRV8848 is active unless the nSLEEP pin is brought logic low. In sleep mode, the VINT regulator is
disabled and the H-bridge FETs are disabled Hi-Z. Note that tSLEEP must elapse after a falling edge on the
nSLEEP pin before the device is in sleep mode. The DRV8848 is brought out of sleep mode automatically if
nSLEEP is brought logic high. Note that tWAKE must elapse before the output change state after wake-up.
When VVM falls below the VM UVLO threshold (VUVLO), the output driver, internal logic, and VINT regulator are
reset.
Table 3. Functional Modes
14
MODE
CONDITION
H-BRIDGE
VINT
Operating
4 V < VVM < 18 V
nSLEEP pin = 1
Operating
Operating
Sleep
4 V < VVM < 18 V
nSLEEP pin = 0
Disabled
Disabled
Fault
Any fault condition met
Disabled
Depends on fault
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DRV8848 is used in stepper or brushed DC motor control.
8.2 Typical Application
The user can configure the DRV8848 with the following design procedure.
1
2
500 PŸ
DCM
3
4
nSLEEP
AIN1
AOUT1
AIN2
AISEN
VINT
DRV8848
AOUT2
GND
16
15
14
13
2.2 µF
10 µF
5
500 PŸ
DCM
6
7
8
VCC
VM
BOUT2
GND
(PPAD)
BISEN
VREF
BOUT1
BIN2
nFAULT
BIN1
0.1 µF
12
VM
11
10
9
10 NŸ
logic supply
Figure 10. Typical Application Schematic
8.2.1 Design Requirements
Table 4 gives design input parameters for system design.
Table 4. Design Parameters
DESIGN PARAMETER
Nominal supply voltage
Supply voltage range
Motor winding resistance
Motor winding inductance
REFERENCE
VVM
EXAMPLE VALUE
12 V
4 to 18 V
RL
3 Ω/phase
LL
330 µH/phase
Target chopping current
ICHOP
500 mA
Chopping current reference voltage
VVREF
3.3 V
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8.2.2 Detailed Design Procedure
8.2.2.1 Current Regulation
The chopping current (ICHOP) is the maximum current driven through either winding. This quantity depends on the
sense resistor value (RXISEN).
VVREF
ICHOP
6.6 u R XISEN
(2)
ICHOP is set by a comparator which compares the voltage across RXISEN to a reference voltage. Note that ICHOP
must follow Equation 3 to avoid saturating the motor.
VVM (V)
ICHOP (A)
RL (:) 2 u RDS(ON) (:) R XISEN (:)
where
•
•
VVM is the motor supply voltage.
RL is the motor winding resistance.
(3)
8.2.3 Application Curves
AIN1
Fast decay
Current trip point
Slow decay
AIN2
I Motor
Figure 11. Current Regulation
16
Figure 12. Stepper Mode Operation
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9 Power Supply Recommendations
The DRV8848 is designed to operate from an input voltage supply (VVM) range between 4 and 18 V. Place a 0.1µF ceramic capacitor rated for VM as close to the DRV8848 as possible. In addition, the user must include a bulk
capacitor of at least 10 µF on VM.
9.1 Bulk Capacitance Sizing
Bulk capacitance sizing is an important factor in motor drive system design. It depends on a variety of factors
including:
• Type of power supply
• Acceptable supply voltage ripple
• Parasitic inductance in the power supply wiring
• Type of motor (brushed DC, brushless DC, stepper)
• Motor startup current
• Motor braking method
The inductance between the power supply and motor drive system limits the rate that current can change from
the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands
or dumps from the motor with a change in voltage. Size the bulk capacitance to meet acceptable voltage ripple
levels.
The data sheet provides a recommended minimum value, but system-level testing is required to determine the
appropriate-sized bulk capacitor.
Power Supply
Parasitic Wire
Inductance
Motor Drive System
VM
+
±
+
Motor
Driver
GND
Local
Bulk Capacitor
IC Bypass
Capacitor
Figure 13. Setup of Motor Drive System With External Power Supply
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10 Layout
10.1 Layout Guidelines
Bypass the VM terminal to GND using a low-ESR ceramic bypass capacitor with a recommended value of 10 μF
rated for VM. Place this capacitor as close to the VM pin as possible with a thick trace or ground plane
connection to the device GND pin.
Bypass VINT to ground with a ceramic capacitor rated 6.3 V. Place this bypassing capacitor as close to the pin
as possible.
10.2 Layout Example
nSLEEP
AIN1
AOUT1
AIN2
2.2 µF
RAISEN
RBISEN
AISEN
VINT
AOUT2
GND
BOUT2
VM
BISEN
VREF
BOUT1
BIN2
nFAULT
BIN1
10 µF
Figure 14. Layout Recommendation
18
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11 Device and Documentation Support
11.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
DRV8848PWP
ACTIVE
HTSSOP
PWP
16
90
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
DRV8848
DRV8848PWPR
ACTIVE
HTSSOP
PWP
16
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
DRV8848
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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