DRV8876N
DRV8876N
SLVSFE6A – AUGUST 2019 – REVISED
APRIL 2021
SLVSFE6A – AUGUST 2019 – REVISED APRIL 2021
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DRV8876N H-Bridge Motor Driver
1 Features
3 Description
•
The DRV8876N is an integrated motor driver with
N-channel H-bridge, charge pump, and protection
circuitry. The charge pump improves efficiency by
supporting N-channel MOSFET half bridges and
100% duty cycle driving. The family of devices come
in pin-to-pin RDS(on) variants to support different loads
with minimal design changes.
•
•
•
•
•
•
•
N-channel H-bridge motor driver
– Drives one bidirectional brushed DC motor
– Two unidirectional brushed DC motors
– Other resistive and inductive loads
4.5-V to 37-V operating supply voltage range
High output current capability: 3.5-A Peak
Selectable input control modes (PMODE)
– PH/EN and PWM H-bridge control modes
– Independent half-bridge control mode
Supports 1.8-V, 3.3-V, and 5-V logic inputs
Ultra low-power sleep mode
– VUVLO, nSLEEP = 5 V to active
1
ms
tSLEEP
Turnoff time
nSLEEP = 0 V to sleep mode
1
ms
VVCP
Charge pump regulator voltage
VCP with respect to VM, VVM = 24 V
fVCP
Charge pump switching frequency
5
V
400
kHz
LOGIC-LEVEL INPUTS (EN/IN1, PH/IN2, nSLEEP)
VIL
Input logic low voltage
VIH
Input logic high voltage
VHYS
Input hysteresis
VVM < 5 V
0
0.7
VVM ≥ 5 V
0
0.8
1.5
5.5
nSLEEP
V
V
200
mV
50
mV
IIL
Input logic low current
VI = 0 V
IIH
Input logic high current
VI = 5 V
–5
50
RPD
Input pulldown resistance
To GND
100
5
µA
75
µA
kΩ
TRI-LEVEL INPUTS (PMODE)
VTIL
Tri-level input logic low voltage
0
0.65
4.5 V < VVM < 5.5 V
0.9
1.0
1.1
5.5 V ≤ VVM ≤ 37 V
0.9
1.1
1.2
V
VTIZ
Tri-level input Hi-Z voltage
VTIH
Tri-level input logic high voltage
ITIL
Tri-level input logic low current
VI = 0 V
–50
ITIZ
Tri-level input Hi-Z current
VI = 1.1 V
–10
ITIH
Tri-level input logic high current
VI = 5 V
113
RTPD
Tri-level pulldown resistance
To GND
44
kΩ
RTPU
Tri-level pullup resistance
To internal 5 V
156
kΩ
1.5
5.5
–32
V
V
µA
10
150
µA
µA
QUAD-LEVEL INPUTS (IMODE)
VQI2
Quad-level input level 1
Voltage to set quad-level 1
RQI2
Quad-level input level 2
Resistance to GND to set quad-level 2
0
18.6
20
0.45
V
21.4
kΩ
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4.5 V ≤ VVM ≤ 37 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
RQI3
Quad-level input level 3
Resistance to GND to set quad-level 3
VQI4
Quad-level input level 4
Voltage to set quad-level 4
RQPD
Quad-level pulldown resistance
To GND
RQPU
Quad-level pullup resistance
To internal 5 V
MIN
TYP
MAX
UNIT
57.6
62
66.4
kΩ
2.5
5.5
V
136
kΩ
68
kΩ
OPEN-DRAIN OUTPUTS (nFAULT)
VOL
Output logic low voltage
IOD = 5 mA
IOZ
Output logic high current
VOD = 5 V
–2
0.35
V
2
µA
DRIVER OUTPUTS (OUT1, OUT2)
RDS(on)_HS
High-side MOSFET on resistance
VVM = 24 V, IO = 1 A, TJ = 25°C
350
420
mΩ
RDS(on)_LS
Low-side MOSFET on resistance
VVM = 24 V, IO = –1 A, TJ = 25°C
350
420
mΩ
VSD
Body diode forward voltage
ISD = 1 A
0.9
V
tRISE
Output rise time
VVM = 24 V, OUTx rising 10% to 90%
150
ns
tFALL
Output fall time
VVM = 24 V, OUTx falling 90% to 10%
150
ns
tPD
Input to output propagation delay
EN/IN1, PH/IN2 to OUTx, 200 Ω from
OUTx to GND
650
ns
tDEAD
Output dead time
Body diode conducting
300
ns
PROTECTION CIRCUITS
VUVLO
Supply undervoltage lockout (UVLO)
VUVLO_HYS
Supply UVLO hysteresis
tUVLO
Supply undervoltage deglitch time
VCPUV
Charge pump undervoltage lockout
IOCP
Overcurrent protection trip point
tOCP
Overcurrent protection deglitch time
tRETRY
Overcurrent protection retry time
TTSD
Thermal shutdown temperature
THYS
Thermal shutdown hysteresis
VVM rising
4.3
4.45
4.6
VVM falling
4.2
4.35
4.5
VCP with respect to VM, VVCP falling
3.5
V
100
mV
10
µs
2.25
V
5.5
A
3
µs
2
160
V
175
20
ms
190
°C
°C
EN/IN1 or
PH/IN2
ttPDt
OUTx (V)
ttPDt
tRISE
tFALL
OUTx (A)
Figure 6-1. Timing Parameter Diagram
6
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6.6 Typical Characteristics
1.4
2
VVM = 4.5 V
VVM = 13.5 V
VVM = 24 V
VVM = 37 V
1.2
1.6
Supply Current (µA)
Supply Current (µA)
1
0.8
0.6
1.2
0.8
0.4
TJ = -40°C
TJ = 25°C
TJ = 85°C
TJ = 125°C
TJ = 150°C
0.2
0.4
0
0
5
10
15
20
25
Supply Voltage (V)
30
35
0
-40
40
Figure 6-2. Sleep Current (IVMQ) vs. Supply Voltage
(VVM)
20
40
60
80 100
Junction Temperature (°C)
120
140
160
D002
3.5
TJ = -40°C
TJ = 25°C
TJ = 85°C
TJ = 125°C
TJ = 150°C
VVM = 4.5 V
VVM = 13.5 V
VVM = 24 V
VVM = 37 V
3.25
Supply Current (mA)
3.25
Supply Current (mA)
0
Figure 6-3. Sleep Current (IVMQ) vs. Junction
Temperature
3.5
3
2.75
3
2.75
2.5
0
5
10
15
20
25
Supply Voltage (V)
30
35
2.5
-40
40
0
0.7
0.7
0.6
0.6
RDS(on) (:)
0.8
0.5
0.4
0.3
20
40
60
80 100
Junction Temperature (°C)
120
140
160
D004
Figure 6-5. Active Current (IVM) vs. Junction
Temperature
0.8
0.5
0.4
0.3
VVM = 4.5 V
VVM = 13.5 V
VVM = 24 V
VVM = 37 V
0.2
0.1
-40
-20
D003
Figure 6-4. Active Current (IVM) vs. Supply Voltage
(VVM)
RDS(on) (:)
-20
D001
-20
0
20
40
60
80 100
Junction Temperature (°C)
120
140
VVM = 4.5 V
VVM = 13.5 V
VVM = 24 V
VVM = 37 V
0.2
160
0.1
-40
D005
Figure 6-6. Low-Side RDS(on) vs. Junction
Temperature
-20
0
20
40
60
80 100
Junction Temperature (°C)
120
140
160
D006
Figure 6-7. High-Side RDS(on) vs. Junction
Temperature
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7 Detailed Description
7.1 Overview
The DRV887x family of devices are brushed DC motor drivers that operate from 4.5 to 37-V supporting a wide
range of output load currents for various types of motors and loads. The devices integrate an H-bridge output
power stage that can be operated in different control modes set by the PMODE pin setting. This allows for
driving a single bidirectional brushed DC motor, two unidirectional brushed DC motors, or other output load
configurations. The devices integrate a charge pump regulator to support more efficient high-side N-channel
MOSFETs and 100% duty cycle operation. The devices operate from a single power supply input (VM) which
can be directly connected to a battery or DC voltage supply. The nSLEEP pin provides an ultra-low power mode
to minimize current draw during system inactivity.
A variety of integrated protection features protect the device in the case of a system fault. These
include undervoltage lockout (UVLO), charge pump undervoltage (CPUV), overcurrent protection (OCP), and
overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin.
7.2 Functional Block Diagram
VM
VM
0.1 …F
VCP
VM
Gate Driver
VVCP
VVCP
0.1 …F
VCP
Charge
Pump
CPH
0.022 …F
HS
OUT1
VDD
CPL
LS
VDD
GND
Internal
Regulator
Power
Digital
Core
nSLEEP
EN/IN1
HS
PH/IN2
PMODE
IMODE
VM
Gate Driver
VVCP
OUT2
VDD
Control
Inputs
LS
3-Level
PGND
VVCC
4-Level
VCC
RSVD1
RPU
Fault Output
nFAULT
RSVD2
8
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7.3 Feature Description
7.3.1 External Components
Table 7-1 lists the recommended external components for the device.
Table 7-1. Recommended External Components
COMPONENT
PIN 1
PIN 2
RECOMMENDED
CVM1
VM
GND
0.1-µF, low ESR ceramic capacitor, VM-rated.
CVM2
VM
GND
Section 9.1, VM-rated.
CVCP
VCP
VM
X5R or X7R, 100-nF, 16-V ceramic capacitor
CFLY
CPH
CPL
X5R or X7R, 22-nF, VM-rated ceramic capacitor
RIMODE
IMODE
GND
See Section 7.3.3.3.
RPMODE
PMODE
GND
See Section 7.3.2.
RnFAULT
VCC
nFAULT
Pullup resistor, IOD ≤ 5-mA
7.3.2 Control Modes
The DRV887x family of devices provides three modes to support different control schemes with the EN/IN1 and
PH/IN2 pins. The control mode is selected through the PMODE pin with either logic low, logic high, or setting
the pin Hi-Z as shown in Table 7-2. The PMODE pin state is latched when the device is enabled through the
nSLEEP pin. The PMODE state can be changed by taking the nSLEEP pin logic low, waiting the tSLEEP time,
changing the PMODE pin input, and then enabling the device by taking the nSLEEP pin back logic high.
Table 7-2. PMODE Functions
PMODE STATE
CONTROL MODE
PMODE = Logic Low
PH/EN
PMODE = Logic High
PWM
PMODE = Hi-Z
Independent Half-Bridge
VM
VM
1
OUT1
1 Forward drive
1 Reverse drive
2 Slow decay (brake)
22 Slow decay (brake)
1
3 High-Z (coast)
OUT2
OUT1
3 High-Z (coast)
OUT2
2
2
3
3
Forward
Reverse
Figure 7-1. H-Bridge States
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The inputs can accept static or pulse-width modulated (PWM) voltage signals for either 100% or PWM drive
modes. The device input pins can be powered before VM is applied with no issues. By default, the EN/IN1 and
PH/IN2 pins have an internal pulldown resistor to ensure the outputs are Hi-Z if no inputs are present.
The sections below show the truth table for each control mode. Additionally, the DRV887x family of devices
automatically handles the dead-time generation when switching between the high-side and low-side MOSFET of
a half-bridge.
Figure 7-1 describes the naming and configuration for the various H-bridge states.
7.3.2.1 PH/EN Control Mode (PMODE = Logic Low)
When the PMODE pin is logic low on power up, the device is latched into PH/EN mode. PH/EN mode allows
for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is
shown in Table 7-3.
Table 7-3. PH/EN Control Mode
nSLEEP
EN
PH
OUT1
OUT2
DESCRIPTION
0
X
X
Hi-Z
Hi-Z
1
0
X
L
L
Brake, (Low-Side Slow Decay)
1
1
0
L
H
Reverse (OUT2 → OUT1)
1
1
1
H
L
Forward (OUT1 → OUT2)
Sleep, (H-Bridge Hi-Z)
7.3.2.2 PWM Control Mode (PMODE = Logic High)
When the PMODE pin is logic high on power up, the device is latched into PWM mode. PWM mode allows for
the H-bridge to enter the Hi-Z state without taking the nSLEEP pin logic low. The truth table for PWM mode is
shown in Table 7-4.
Table 7-4. PWM Control Mode
nSLEEP
IN1
IN2
OUT1
OUT2
0
X
X
Hi-Z
Hi-Z
Sleep, (H-Bridge Hi-Z)
DESCRIPTION
1
0
0
Hi-Z
Hi-Z
Coast, (H-Bridge Hi-Z)
1
0
1
L
H
Reverse (OUT2 → OUT1)
1
1
0
H
L
Forward (OUT1 → OUT2)
1
1
1
L
L
Brake, (Low-Side Slow Decay)
7.3.2.3 Independent Half-Bridge Control Mode (PMODE = Hi-Z)
When the PMODE pin is Hi-Z on power up, the device is latched into independent half-bridge control mode. This
mode allows for each half-bridge to be directly controlled in order to support high-side slow decay or driving two
independent loads. The truth table for independent half-bridge mode is shown in Table 7-5.
Table 7-5. Independent Half-Bridge Control Mode
10
nSLEEP
INx
OUTx
0
X
Hi-Z
DESCRIPTION
Sleep, (H-Bridge Hi-Z)
1
0
L
OUTx Low-Side On
1
1
H
OUTx High-Side On
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7.3.3 Protection Circuits
The DRV887x family of devices are fully protected against supply undervoltage, charge pump undervoltage,
output overcurrent, and device overtemperature events.
7.3.3.1 VM Supply Undervoltage Lockout (UVLO)
If at any time the supply voltage on the VM pin falls below the undervoltage lockout threshold voltage (VUVLO), all
MOSFETs in the H-bridge will be disabled and the nFAULT pin driven low. The charge pump is disabled in this
condition. Normal operation will resume when the undervoltage condition is removed and VM rises above the
VUVLO threshold.
7.3.3.2 VCP Charge Pump Undervoltage Lockout (CPUV)
If at any time the charge pump voltage on the VCP pin falls below the undervoltage lockout threshold voltage
(VCPUV), all MOSFETs in the H-bridge will be disabled and the nFAULT pin driven low. Normal operation will
resume when the undervoltage condition is removed and VCP rises above the VCPUV threshold.
7.3.3.3 OUTx Overcurrent Protection (OCP)
An analog current limit circuit on each MOSFET limits the peak current out of the device even in hard short
circuit events.
If the output current exceeds the overcurrent threshold, IOCP, for longer than tOCP, all MOSFETs in the H-bridge
will be disabled and the nFAULT pin driven low. The overcurrent response can be configured through the IMODE
pin as shown in Table 7-6.
Table 7-6. IMODE Functions
Overcurrent
Response
IMODE STATE
RIMODE = GND
Automatic Retry
RIMODE = Hi-Z
Outputs Latched Off
In automatic retry mode, the MOSFETs will be disabled and nFAULT pin driven low for a duration of tRETRY. After
tRETRY, the MOSFETs are re-enabled according to the state of the EN/IN1 and PH/IN2 pins. If the overcurrent
condition is still present, the cycle repeats; otherwise normal device operation resumes.
In latched off mode, the MOSFETs will remain disabled and nFAULT pin driven low until the device is reset
through either the nSLEEP pin or by removing the VM power supply.
In Section 7.3.2.3, the OCP behavior is slightly modified. If an overcurrent event is detected, only the
corresponding half-bridge will be disabled and the nFAULT pin driven low. The other half-bridge will continue
normal operation. This allows for the device to manage independent fault events when driving independent
loads. If an overcurrent event is detected in both half-bridges, both half-bridges will be disabled and the
nFAULT pin driven low. In automatic retry mode, both half-bridges share the same overcurrent retry timer. If
an overcurrent event occurs first in one half-bridge and then later in the secondary half-bridge, but before tRETRY
has expired, the retry timer for the first half-bridge will be reset to tRETRY and both half-bridges will enable again
after the retry timer expires.
7.3.3.4 Thermal Shutdown (TSD)
If the die temperature exceeds the overtemperature limit TTSD, all MOSFET in the H-bridge will be disabled and
the nFAULT pin driven low. Normal operation will resume when the overtemperature condition is removed and
the die temperature drops below the TTSD threshold.
7.3.3.5 Fault Condition Summary
Table 7-7. Fault Condition Summary
FAULT
CONDITION
REPORT
H-BRIDGE
RECOVERY
VM Undervoltage Lockout (UVLO)
VM < VUVLO
nFAULT
Disabled
VM > VUVLO
VCP Undervoltage Lockout (CPUV)
VCP < VCPUV
nFAULT
Disabled
VCP > VCPUV
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Table 7-7. Fault Condition Summary (continued)
FAULT
Overcurrent (OCP)
Thermal Shutdown (TSD)
CONDITION
REPORT
H-BRIDGE
RECOVERY
IOUT > IOCP
nFAULT
Disabled
tRETRY or Reset
(Set by IMODE)
TJ > TTSD
nFAULT
Disabled
TJ < TTSD – THYS
7.3.4 Pin Diagrams
7.3.4.1 Logic-Level Inputs
Figure 7-2 shows the input structure for the logic-level input pins EN/IN1, PH/IN2, and nSLEEP.
100 k
Figure 7-2. Logic-Level Input
7.3.4.2 Tri-Level Inputs
Figure 7-3 shows the input structure for the tri-level input pin PMODE.
5V
156 k
+
±
+
44 k
±
Figure 7-3. PMODE Tri-Level Input
7.3.4.3 Quad-Level Inputs
Figure 7-4 shows the input structure for the quad-level input pin IMODE. For DRV8876N, this pin should be
connected to ground or left floating as described by Table 7-6.
+
5V
68 k
±
+
±
+
136 k
±
Figure 7-4. Quad-Level Input
7.4 Device Functional Modes
The DRV887x family of devices have several different modes of operation depending on the system inputs.
7.4.1 Active Mode
After the supply voltage on the VM pin has crossed the undervoltage threshold VUVLO, the nSLEEP pin is logic
high, and tWAKE has elapsed, the device enters its active mode. In this mode, the H-bridge, charge pump, and
12
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internal logic are active and the device is ready to receive inputs. The input control mode (PMODE) and OCP
modes (IMODE) will be latched when the device enters active mode.
7.4.2 Low-Power Sleep Mode
The DRV887x family of devices support a low power mode to reduce current consumption from the VM pin
when the driver is not active. This mode is entered by setting the nSLEEP pin logic low and waiting for tSLEEP
to elapse. In sleep mode, the H-bridge, charge pump, internal 5-V regulator, and internal logic are disabled. The
device relies on a weak pulldown to ensure all of the internal MOSFETs remain disabled. The device will not
respond to any inputs besides nSLEEP while in low-power sleep mode.
7.4.3 Fault Mode
The DRV887x family of devices enter a fault mode when a fault is encountered. This is utilized to protect the
device and the output load. The device behavior in the fault mode is described in Table 7-7 and depends on the
fault condition. The device will leave the fault mode and re-enter the active mode when the recovery condition is
met.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
The DRV887x family of devices can be used in a variety of applications that require either a half-bridge or
H-bridge power stage configuration. Common application examples include brushed DC motors, solenoids,
and actuators. The device can also be utilized to drive many common passive loads such as LEDs, resistive
elements, relays, etc. The application examples below will highlight how to use the device in bidirectional current
control applications requiring an H-bridge driver and dual unidirectional current control applications requiring two
half-bridge drivers.
8.2 Typical Application
8.2.1 Primary Application
In the primary application example, the device is configured to drive a bidirectional current through an external
load (such as a brushed DC motor) using an H-bridge configuration. The H-bridge polarity and duty cycle are
controlled with a PWM and IO resource from the external controller to the EN/IN1 and PH/IN2 pins. The device is
configured for the PH/EN control mode by tying the PMODE pin to GND.
VCC
Controller
1
PWM
EN/IN1
DRV8876N
16
PMODE
2
I/O
VCC
15
PH/IN2
GND
nSLEEP
CPL
3
I/O
10 k
14
4
I/O
13
nFAULT
VCC
0.022 …F
5
RSVD1
Thermal
Pad
CPH
12
0.1 …F
VM
VCP
6
11
RSVD2
VM
IMODE
OUT2
OUT1
PGND
7
10
8
0.1 …F
CBulk
9
BDC
Figure 8-1. Typical Application Schematic
8.2.1.1 Design Requirements
Table 8-1. Design Parameters
14
REFERENCE
DESIGN PARAMETER
EXAMPLE VALUE
VM
Motor and driver supply voltage
24 V
VCC
Controller supply voltage
3.3 V
IRMS
Output RMS current
0.5 A
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Table 8-1. Design Parameters (continued)
REFERENCE
DESIGN PARAMETER
EXAMPLE VALUE
fPWM
Switching frequency
20 kHz
TA
PCB ambient temperature
–20 to 85 °C
TJ
Device max junction temperature
150 °C
RθJA
Device junction to ambient thermal resistance
35 °C/W
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Power Dissipation and Output Current Capability
The output current and power dissipation capabilities of the device are heavily dependent on the PCB design
and external system conditions. This section provides some guidelines for calculating these values.
Total power dissipation for the device is composed of three main components. These are the quiescent supply
current dissipation, the power MOSFET switching losses. and the power MOSFET RDS(on) (conduction) losses.
While other factors may contribute additional power losses, these other items are typically insignificant compared
to the three main items.
PTOT = PVM + PSW + PRDS
(1)
PVM can be calculated from the nominal supply voltage (VM) and the IVM active mode current specification.
PVM = VM x IVM
(2)
PVM = 0.096 W = 24 V x 4 mA
(3)
PSW can be calculated from the nominal supply voltage (VM), average output current (IRMS), switching frequency
(fPWM) and the device output rise (tRISE) and fall (tFALL) time specifications.
PSW = PSW_RISE + PSW_FALL
(4)
PSW_RISE = 0.5 x VM x IRMS x tRISE x fPWM
(5)
PSW_FALL = 0.5 x VM x IRMS x tFALL x fPWM
(6)
PSW_RISE = 0.018 W = 0.5 x 24 V x 0.5 A x 150 ns x 20 kHz
(7)
PSW_FALL = 0.018 W = 0.5 x 24 V x 0.5 A x 150 ns x 20 kHz
(8)
PSW = 0.036 W = 0.018 W + 0.018 W
(9)
PRDS can be calculated from the device RDS(on) and average output current (IRMS)
PRDS = IRMS 2 x (RDS(ON)_HS + RDS(ON)_LS)
(10)
It should be noted that RDS(ON) has a strong correlation with the device temperature. A curve showing the
normalized RDS(on) with temperature can be found in the Typical Characteristics curves. Assuming a device
temperature of 85 °C it can be expected that RDS(on) will see an increase of ~1.25 based on the normalized
temperature data.
PRDS = 0.219 W = (0.5 A)2 x (350 mΩ x 1.25 + 350 mΩ x 1.25)
(11)
By adding together the different power dissipation components it can be verified that the expected power
dissipation and device junction temperature is within design targets.
PTOT = PVM + PSW + PRDS
(12)
PTOT = 0.351 W = 0.096 W + 0.036 W + 0.219 W
(13)
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The device junction temperature can be calculated with the PTOT, device ambient temperature (TA), and package
thermal resistance (RθJA). The value for RθJA is heavily dependent on the PCB design and copper heat sinking
around the device.
TJ = (PTOT x RθJA) + TA
(14)
TJ = 97°C = (0.351 W x 35 °C/W) + 85°C
(15)
It should be ensured that the device junction temperature is within the specified operating region. Other methods
exist for verifying the device junction temperature depending on the measurements available.
Additional information on motor driver current ratings and power dissipation can be found in Section 8.2.1.2.2
and Section 11.1.1.
8.2.1.2.2 Thermal Performance
The datasheet-specified junction-to-ambient thermal resistance, RθJA, is primarily useful for comparing various
drivers or approximating thermal performance. However, the actual system performance may be better or worse
than this value depending on PCB stackup, routing, number of vias, and copper area around the thermal
pad. The length of time the driver drives a particular current will also impact power dissipation and thermal
performance. This section considers how to design for steady-state and transient thermal conditions.
The data in this section was simulated using the following criteria:
•
2-layer PCB, standard FR4, 1-oz (35 mm copper thickness) or 2-oz copper thickness.
•
•
Top layer: DRV887x HTSSOP package footprint and copper plane heatsink. Top layer copper area is varied
in simulation.
Bottom layer: ground plane thermally connected through vias under the thermal pad for DRV887x. Bottom
layer copper area varies with top copper area. Thermal vias are only present under the thermal pad (grid
pattern with 1.2mm spacing).
•
4-layer PCB, standard FR4. Outer planes are 1-oz (35 mm copper thickness) or 2-oz copper thickness.
•
Top layer: DRV887x HTSSOP package footprint and copper plane heatsink. Top layer copper area is varied
in simulation. Inner planes were kept at 1-oz.
Mid layer 1: GND plane thermally connected to DRV887x thermal pad through vias. The area of the ground
plane is 74.2 mm x 74.2 mm.
Mid layer 2: power plane, no thermal connection.
Bottom layer: signal layer with small copper pad underneath DRV887x and thermally connected through via
stitching from the TOP and internal GND planes. Bottom layer thermal pad is the same size as the package
(5 mm x 4.4 mm). Bottom pad size remains constant as top copper plane is varied. Thermal vias are only
present under the thermal pad (grid pattern with 1.2mm spacing).
•
•
•
Figure 8-2 shows an example of the simulated board for the HTSSOP package. Table 8-2 shows the dimensions
of the board that were varied for each simulation.
16
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A
Trace 0.22 mm x 34.5 mm
at 0.65-mm pitch
2.46 mm
A
PTH via at 1.2 mm
Drill diameter = 300 m;
plating = 25 m
6.0 mm
Figure 8-2. HTSSOP PCB model top layer
Table 8-2. Dimension A for 16-pin PWP package
Cu area
(mm2)
Dimension A (mm)
2
17.0
4
22.8
8
31.0
16
42.8
8.2.1.2.2.1 Steady-State Thermal Performance
"Steady-state" conditions assume that the motor driver operates with a constant RMS current over a long
period of time. Figure 8-3, Figure 8-4, Figure 8-5, and Figure 8-6 show how RθJA and ΨJB (junction-to-board
characterization parameter) change depending on copper area, copper thickness, and number of layers of the
PCB for the HTSSOP package. More copper area, more layers, and thicker copper planes decrease RθJA and
ΨJB, which indicate better thermal performance from the PCB layout.
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