FDS8876

DATA SHEET www.onsemi.com MOSFET – N-Channel, POWERTRENCH) VDSS MAX rDS(on) MAX ID MAX 30 V 8.2 mW @ 10 V 12.5 A 10.2 mW @ 4.5 V 30 V, 12.5 A, 8.2 mW FDS8876, FDS8876-F40 8 7 65 General Description This N−Channel MOSFET has been designed specifically to improve the overall efficiency of DC/DC converters using either synchronous or conventional switching PWM controllers. It has been optimized for low gate charge, low rDS(on) and fast switching speed. 12 3 4 SOIC8 (SO−8) CASE 751EB Features • • • • • • rDS(on) = 8.2 mW, VGS = 10 V, ID = 12.5 A rDS(on) = 10.2 mW, VGS = 4.5 V, ID = 11.4 A High Performance Trench Technology for Extremely Low rDS(on) Low Gate Charge High Power and Current Handling Capability These Devices are Pb−Free and are RoHS Compliant Applications MOSFET MAXIMUM RATINGS (TA = 25°C unless otherwise noted) Parameter Ratings Unit 30 V VDSS Drain to Source Voltage VGSS Gate to Source Voltage ±20 V Drain Current Continuous (TA = 25°C, VGS = 10 V, RqJA = 50°C/W) 12.5 A Continuous (TA = 25°C, VGS = 4.5 V, RqJA = 50°C/W) 11.4 A 91 A ID Pulsed EAS Single Pulse Avalanche Energy (Note 1) 105 mJ PD Power Dissipation 2.5 W Derate above 25°C 20 mW/°C –55 to 150 °C TJ, TSTG FDS8876 ALYW FDS8876 • DC/DC Converters Symbol MARKING DIAGRAM Operating and Storage Temperature Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Starting TJ = 25°C, L = 1 mH, IAS = 14.5 A, VDD = 30 V, VGS = 10 V. $Y&Z&2&K FDS 8876 FDS8878−F40 FDS8876 = Device Code A = Assembly Site L = Wafer Lot Number YW = Assembly Start Week $Y = onsemi Logo &Z = Assembly Plant Code &2 = 2−Digit Code Format &K = 2−Digits Lot Run Traceability Code PIN CONNECTIONS 5 4 6 3 7 2 8 1 ORDERING INFORMATION See detailed ordering and shipping information on page 13 of this data sheet. © Semiconductor Components Industries, LLC, 2007 February, 2022 − Rev. 3 1 Publication Order Number: FDS8876/D FDS8876, FDS8876−F40 THERMAL CHARACTERISTICS Symbol Parameter Ratings Unit RqJC Thermal Resistance, Junction−to−Case (Note 2) 25 °C/W RqJA Thermal Resistance, Junction−to−Ambient (Note 2a) 50 °C/W RqJA Thermal Resistance, Junction−to−Ambient (Note 2b) 125 °C/W 2. RqJA is the sum of the junction−to−case and case−to−ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RqJC is guaranteed by design while RqJA is determined by the user’s board design. a. 50°C/W when mounted on a 1in2 pad of 2 oz copper. b. 125°C/W when mounted on a minimum pad. ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Symbol Parameter Test Conditions Min Typ Max Unit OFF CHARACTERISTICS BVDSS Drain to Source Breakdown Voltage ID = 250 mA, VGS = 0 V 30 − − V IDSS Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V − − 1 mA VDS = 24 V, VGS = 0 V, TJ = 150°C − − 250 IGSS Gate to Source Leakage Current VGS = ±20 V − − ±100 nA ON CHARACTERISTICS VGS(TH) Gate to Source Threshold Voltage VGS = VDS, ID = 250 mA 1.2 − 2.5 V rDS(on) Drain to Source On Resistance ID = 12.5 A, VGS = 10 V − 6.8 8.2 mW ID = 11.4 A, VGS = 4.5 V − 8.3 10.2 ID = 12.5 A, VGS = 10 V, TJ = 150°C − 10.9 14.1 VDS = 15 V, VGS = 0 V, f = 1 MHz − 1650 − pF − 330 − pF DYNAMIC CHARACTERISTICS CISS Input Capacitance COSS Output Capacitance CRSS Reverse Transfer Capacitance RG − 180 − pF 0.6 2.3 4.0 W VGS = 0 V to 10 V, VDD = 15 V, ID = 12.5 A, Ig = 1.0 mA − 28 36 nC Total Gate Charge at 5 V VGS = 0 V to 5 V,VDD = 15 V, ID = 12.5 A, Ig = 1.0 mA − 15 20 nC Threshold Gate Charge VGS = 0 V to 1 V, VDD = 15 V, ID = 12.5 A, Ig = 1.0 mA − 1.5 2.0 nC VDD = 15 V, ID = 12.5 A, Ig = 1.0 mA Gate Resistance VGS = 0.5 V, f = 1 MHz Qg(TOT) Total Gate Charge at 10 V Qg(5) Qg(TH) Qgs Gate to Source Gate Charge − 4.3 − nC Qgs2 Gate Charge Threshold to Plateau − 2.8 − nC Qgd Gate to Drain “Miller” Charge − 5.0 − nC − − 63 ns SWITCHING CHARACTERISTICS (VGS = 10 V) tON td(ON) tr td(OFF) tf tOFF Turn−On Time Turn−On Delay Time VDD = 15 V, ID = 12.5 A, VGS = 10 V, RGS = 10 W − 8 − ns Rise Time − 34 − ns Turn−Off Delay Time − 53 − ns Fall Time − 19 − ns Turn−Off Time − − 108 ns ISD = 12.5 A − − 1.25 V DRAIN−SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS VSD trr QRR Source to Drain Diode Voltage ISD = 2.1 A − − 1.0 V Reverse Recovery Time ISD = 12.5 A, dISD/dt = 100 A/ms − − 29 ns Reverse Recovered Charge ISD = 12.5 A, dISD/dt = 100 A/ms − − 15 nC Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 2 FDS8876, FDS8876−F40 TYPICAL CHARACTERISTICS 16 1.2 1.0 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER (TJ = 25°C unless otherwise noted) 0.8 0.6 0.4 0.2 0 0 25 50 75 100 125 12 VGS = 10 V 8 4 0 25 150 TA, AMBIENT TEMPERATURE (°C) ZqJA, NORMALIZED THERMAL IMPEDANCE 0.1 RqJA = 50°C/W 50 75 100 125 150 TA, AMBIENT TEMPERATURE (°C) Figure 1. Normalized Power Dissipation vs. Ambient Temperature 2 1 VGS = 4.5 V Figure 2. Maximum Continuous Drain Current vs. Ambient Temperature DUTY CYCLE−DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 0.01 0.001 0.0005 −4 10 SINGLE PULSE RqJA = 125°C/W 10 −3 10 −2 10 −1 10 0 10 1 10 2 10 3 t, RECTANGULAR PULSE DURATION (s) P(PK), PEAK TRANSIENT POWER (W) Figure 3. Normalized Maximum Transient Thermal Impedance 2000 1000 SINGLE PULSE RqJA = 125°C/W TA = 25°C VGS = 10 V 100 10 1 0.5 −4 10 −3 10 −2 10 −1 0 10 10 1 10 t, PULSE WIDTH (s) Figure 4. Single Pulse Maximum Power Dissipation www.onsemi.com 3 2 10 3 10 FDS8876, FDS8876−F40 TYPICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) (continued) 50 If R = 0 tAV = (L) (IAS) / (1.3 * RATED BVDSS − VDD) If R ≠ 0 tAV = (L / R) ln [(IAS x R) / (1.3 x RATED BVDSS − VDD) +1] ID, DRAI N CURRENT (A) IAS, AVALANCHE CURRENT (A) 100 STARTING TJ = 25°C 10 STARTING TJ = 150°C 1 0.01 0.1 1 10 PULSE DURATION = 80 ms DUTY CYCLE = 0.5% MAX VDD = 15 V 40 TJ = 25°C 30 20 TJ = 150°C 10 0 2.0 100 tAV, TIME IN AVALANCHE (ms) TJ = −55°C 2.5 3.0 3.5 VGS, GATE TO SOURCE VOLTAGE (V) NOTE: Refer to onsemi Application Notes AN−7514 and AN−7515 Figure 6. Transfer Characteristics Figure 5. Unclamped Inductive Switching Capability 50 50 VGS = 5 V 40 rDS(ON), DRAIN TO SOURCE ON RESISTANCE (mW) ID, DRAI N CURRENT (A) VGS = 10 V VGS = 3.5 V 30 VGS = 3 V 20 TA = 25°C PULSE DURATION = 80 ms DUTY CYCLE = 0.5% MAX 10 0 0 0.2 0.4 0.6 PULSE DURATION = 80 ms DUTY CYCLE = 0.5% MAX 40 ID = 12.5 A 30 20 10 0 0.8 ID = 1 A 2 VDS, DRAIN TO SOURCE VOLTAGE (V) PULSE DURATION = 80 ms DUTY CYCLE = 0.5% MAX 1.2 1.0 0.8 VGS = 10 V, ID = 12.5 A 0.6 −80 −40 0 40 80 8 10 Figure 8. Drain to Source On Resistance vs. Gate Voltage and Drain Current NORMALIZED GATE THRESHOLD VOLTAGE NORMALIZED DRAIN TO SOURCE ON RESISTANCE 1.4 6 VGS, GATE TO SOURCE VOLTAGE (V) Figure 7. Saturation Characteristics 1.6 4 120 160 TJ, JUNCTION TEMPERATURE (°C) 1.2 VGS = VDS, ID = 250 mA 1.0 0.8 0.6 0.4 −80 −40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (°C) Figure 9. Normalized Drain to Source On Resistance vs. Junction Temperature Figure 10. Normalized Gate Threshold Voltage vs. Junction Temperature www.onsemi.com 4 FDS8876, FDS8876−F40 TYPICAL CHARACTERISTICS CAPACITANCE (pF) 3000 1000 VGS, GATE TO SOURCE VOLTAGE (V) (TJ = 25°C unless otherwise noted) (continued) CISS = CGS + CGD COSS ≅ CDS + CGD CRSS = CGD 100 0.1 VGS = 0 V, f = 1 MHz 1 10 30 VDS, DRAIN TO SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A) 1 0.1 0.01 0.01 1 ms 10 ms THIS AREA IS LIMITED BY rDS(on) 100 ms 1s SINGLE PULSE TJ = MAX RATED RqJA = 125°C/W TA = 25°C 0.1 10 s DC 1 8 6 4 WAVEFORMS IN DESCENDING ORDER: ID = 12.5 A ID = 1 A 2 0 0 5 10 15 20 25 Figure 12. Gate Charge Waveforms for Constant Gate Currents 100 ms 10 VDD = 15 V Qg, GATE CHARGE (nC) Figure 11. Capacitance vs. Drain to Source Voltage 200 100 10 10 100 VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 13. Forward Bis Safe Operating Area www.onsemi.com 5 30 FDS8876, FDS8876−F40 TEST CIRCUITS AND WAVEFORMS V DS BVDSS tP L VARY tP TO OBTAIN REQUIRED PEAK IAS VDS I AS VDD + VDD − RG VGS DUT tP 0V I AS 0.01 W 0 t AV Figure 14. Unclamped Inductive Load Test Circuit Figure 15. Unclamped Inductive Waveforms VDS VDD Qg(TOT) VDS VGS L VGS = 10 V Qg(5) VGS Qgs2 + VDD − DUT VGS = 1 V 0 I g(REF) VGS = 5 V Qg(TH) Qgs Qgd I g(REF) 0 Figure 16. Gate Charge Test Circuit Figure 17. Gate Charge Waveforms t ON VDS t OFF t d(OFF) t d(ON) RL + VDD − VGS RGS tr VDS tf 90% 90% 10% 0 10% 90% DUT VGS VGS 0 50% 10% Figure 18. Switching Time Test Circuit PULSE WIDTH 50% Figure 19. Switching Time Waveforms www.onsemi.com 6 FDS8876, FDS8876−F40 THERMAL RESISTANCE VS. MOUNTING PAD AREA Thermal resistances corresponding to other copper areas can be obtained from Figure 20 or by calculation using Equation 2. The area, in square inches is the top copper area including the gate and source pads. The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM, in an application. Therefore the application’s ambient temperature, TA (°C), and thermal resistance RqJA (°C/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. P DM + R qJA + 64 ) (eq. 1) In using surface mount devices such as the SO8 package, the environment in which it is applied will have a significant influence on the part’s current and maximum power dissipation ratings. Precise determination of PDM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. onsemi provides thermal information to assist the designer’s preliminary application evaluation. Figure 20 defines the RqJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR−4 board with 1 oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the onsemi device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. ZqJA, THERMAL IMPEDANCE (°C/W) (eq. 2) The transient thermal impedance (ZqJA) is also effected by varied top copper board area. Figure 21 shows the effect of copper pad area on single pulse transient thermal impedance. Each trace represents a copper pad area in square inches corresponding to the descending list in the graph. Spice and SABER thermal models are provided for each of the listed pad areas. Copper pad area has no perceivable effect on transient thermal impedance for pulse widths less than 100 ms. For pulse widths less than 100 ms the transient thermal impedance is determined by the die and package. Therefore, CTHERM1 through CTHERM5 and RTHERM1 through RTHERM5 remain constant for each of the thermal models. A listing of the model component values is available in Table 1. (T JM * T A) R qJA 26 0.23 ) Area 200 RqJA (°C/W) RqJA = 64 + 26 / (0.23 + Area) 150 100 50 0.001 0.01 0.1 10 1 AREA, TOP COPPER AREA (in2) Figure 20. Thermal Resistance vs. Mounting Pad Area 150 120 90 COPPER BOARD AREA − DESCENDING ORDER 0.04 in2 0.28 in2 0.52 in2 0.76 in2 1.00 in2 60 30 0 10 −1 10 0 10 1 10 2 t, RECTANGULAR PULSE DURATION (s) Figure 21. Thermal Impedance vs. Mounting Pad Area www.onsemi.com 7 10 3 FDS8876, FDS8876−F40 PSPICE ELECTRICAL MODEL .SUBCKT FDS8876 2 1 3 ; rev January 2005 Ca 12 8 10.3e−10 Cb 15 14 10.3e−10 Cin 6 8 1.6e−9 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD Ebreak 11 7 17 18 33.7 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1 It 8 17 1 Lgate 1 9 5.29e−9 Ldrain 2 5 1.0e−9 Lsource 3 7 0.18e−10 RLgate 1 9 52.9 RLdrain 2 5 10 RLsource 3 7 1.8 Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 2.6e−3 Rgate 9 20 2.3 RSLC1 5 51 RSLCMOD 1e−6 RSLC2 5 50 1e3 Rsource 8 7 RsourceMOD 3.8e−3 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD Vbat 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e−6*170),5))} .MODEL DbodyMOD D (IS=2.0E−12 IKF=10 N=1.01 RS=5.6e−3 TRS1=8e−4 TRS2=2e−7 +CJO=5.7e−10 M=0.52 TT=7e−11 XTI=2) .MODEL DbreakMOD D (RS=0.2 TRS1=1e−3 TRS2=−8.9e−6) .MODEL DplcapMOD D (CJO=5.3e−10 IS=1e−30 N=10 M=0.37) .MODEL MmedMOD NMOS (VTO=1.9 KP=5 IS=1e−30 N=10 TOX=1 L=1u W=1u RG=2.3) .MODEL MstroMOD NMOS (VTO=2.42 KP=150 IS=1e−30 N=10 TOX=1 L=1u W=1u) .MODEL MweakMOD NMOS (VTO=1.62 KP=0.02 IS=1e−30 N=10 TOX=1 L=1u W=1u RG=23 RS=0.1) www.onsemi.com 8 FDS8876, FDS8876−F40 .MODEL RbreakMOD RES (TC1=8.3e−4 TC2=−8e−7) .MODEL RdrainMOD RES (TC1=8.0e−3 TC2=1.0e−6) .MODEL RSLCMOD RES (TC1=1e−4 TC2=1e−6) .MODEL RsourceMOD RES (TC1=1e−3 TC2=3e−6) .MODEL RvthresMOD RES (TC1=−2.0e−3 TC2=−6e−6) .MODEL RvtempMOD RES (TC1=−1.8e−3 TC2=2e−7) .MODEL S1AMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=−4 VOFF=−3.5) .MODEL S1BMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=−3.5 VOFF=−4) .MODEL S2AMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=−1.5 VOFF=−1.0) .MODEL S2BMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=−1.0 VOFF=−1.5) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub−Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. LDRAIN DPLCAP 5 10 GATE 1 LGATE RLGATE ESLC 11 − + DBREAK + 5 51 + 17 EBREAK 18 − 50 − ESG RLDRAIN RSLC1 51 RSLC2 RDRAIN 6 8 EVTHRES + 19 − 8 EVTEMP RGATE + 18 − 22 9 20 21 16 DBODY MWEAK 6 MMED MSTRO LSOURCE CIN 8 7 RSOURCE 12 S1A S2A 17 18 RVTEMP S2B 13 CB 6 8 − EDS − 19 − VBAT + IT 14 + + EGS RLSOURCE RBREAK 15 14 13 13 8 S1B CA DRAIN 2 5 8 8 RVTHRES Figure 22. www.onsemi.com 9 22 SOURCE 3 FDS8876, FDS8876−F40 SABER ELECTRICAL MODEL REV January 2005 template FDS8876 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=2.0e−12,ikf=10,nl=1.01,rs=5.6e−3,trs1=8e−4,trs2=2e−7,cjo=5.7e−10,m=0.52,tt=7e−11,xti=2) dp..model dbreakmod = (rs=0.2,trs1=1e−3,trs2=−8.9e−6) dp..model dplcapmod = (cjo=5.3e−10,isl=10e−30,nl=10,m=0.37) m..model mmedmod = (type=_n,vto=1.9,kp=5,is=1e−30, tox=1) m..model mstrongmod = (type=_n,vto=2.42,kp=150,is=1e−30, tox=1) m..model mweakmod = (type=_n,vto=1.62,kp=0.02,is=1e−30, tox=1,rs=0.1) sw_vcsp..model s1amod = (ron=1e−5,roff=0.1,von=−4,voff=−3.5) sw_vcsp..model s1bmod = (ron=1e−5,roff=0.1,von=−3.5,voff=−4) sw_vcsp..model s2amod = (ron=1e−5,roff=0.1,von=−1.5,voff=−1.0) sw_vcsp..model s2bmod = (ron=1e−5,roff=0.1,von=−1.0,voff=−1.5) c.ca n12 n8 = 10.3e−10 c.cb n15 n14 = 10.3e−10 c.cin n6 n8 = 1.6e−9 dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod spe.ebreak n11 n7 n17 n18 = 33.7 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evthres n6 n21 n19 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 i.it n8 n17 = 1 l.lgate n1 n9 = 5.29e−9 l.ldrain n2 n5 = 1.0e−9 l.lsource n3 n7 = 0.18e−9 res.rlgate n1 n9 = 52.9 res.rldrain n2 n5 = 10 res.rlsource n3 n7 = 1.8 m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1=8.3e−4,tc2=−8e−7 res.rdrain n50 n16 = 2.6e−3, tc1=8.0e−3,tc2=1.0e−6 res.rgate n9 n20 = 2.3 res.rslc1 n5 n51 = 1e−6, tc1=1e−4,tc2=1e−6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 3.8e−3, tc1=1e−3,tc2=3e−6 res.rvthres n22 n8 = 1, tc1=−2.0e−3,tc2=−6e−6 res.rvtemp n18 n19 = 1, tc1=−1.8e−3,tc2=2e−7 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod www.onsemi.com 10 FDS8876, FDS8876−F40 v.vbat n22 n19 = dc=1 equations { i (n51−>n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e−9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/170))** 5)) } } LDRAIN DPLCAP DRAIN 2 5 10 RLDRAIN RSLC1 51 RSLC2 ISCL ESG + GATE 1 LGATE RLGATE DBREAK 50 − RDRAIN 6 8 EVTEMP RGATE + 18 − 22 9 20 EVTHRES + 19 − 8 21 11 MWEAK 6 EBREAK + 17 18 − MMED MSTRO CIN DBODY 16 8 LSOURCE 7 RSOURCE 12 S1A S2A S1B CA 15 14 13 13 8 17 18 RVTEMP S2B 13 + 6 EGS 8 − RLSOURCE RBREAK CB 19 − VBAT + IT 14 + 5 8 EDS − 8 RVTHRES Figure 23. www.onsemi.com 11 22 SOURCE 3 FDS8876, FDS8876−F40 SPICE THERMAL MODEL th REV January 2005 FDS8876 Copper Area =1.0 in2 CTHERM1 TH 8 2.0e−3 CTHERM2 8 7 5.0e−3 CTHERM3 7 6 1.0e−2 CTHERM4 6 5 4.0e−2 CTHERM5 5 4 9.0e−2 CTHERM6 4 3 2e−1 CTHERM7 3 2 1 CTHERM8 2 TL 3 JUNCTION RTHERM1 CTHERM1 8 CTHERM2 RTHERM2 7 RTHERM1 TH 8 1e−1 RTHERM2 8 7 5e−1 RTHERM3 7 6 1 RTHERM4 6 5 5 RTHERM5 5 4 8 RTHERM6 4 3 12 RTHERM7 3 2 18 RTHERM8 2 TL 25 CTHERM3 RTHERM3 6 CTHERM4 RTHERM4 5 SABER THERMAL MODEL CTHERM5 RTHERM5 SABER thermal model FDS8876 Copper Area = 1.0 in2 template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 8 =2.0e−3 ctherm.ctherm2 8 7 =5.0e−3 ctherm.ctherm3 7 6 =1.0e−2 ctherm.ctherm4 6 5 =4.0e−2 ctherm.ctherm5 5 4 =9.0e−2 ctherm.ctherm6 4 3 =2e−1 ctherm.ctherm7 3 2 1 ctherm.ctherm8 2 tl 3 4 CTHERM6 RTHERM6 3 RTHERM7 CTHERM7 2 rtherm.rtherm1 th 8 =1e−1 rtherm.rtherm2 8 7 =5e−1 rtherm.rtherm3 7 6 =1 rtherm.rtherm4 6 5 =5 rtherm.rtherm5 5 4 =8 rtherm.rtherm6 4 3 =12 rtherm.rtherm7 3 2 =18 rtherm.rtherm8 2 tl =25 } RTHERM8 CTHERM8 tl CASE Figure 24. www.onsemi.com 12 FDS8876, FDS8876−F40 Table 1. THERMAL MODES COMPONANT 0.04 in2 0.28 in2 0.52 in2 0.76 in2 1.0 in2 CTHERM6 1.2e−1 1.5e−1 2.0e−1 2.0e−1 2.0e−1 CTHERM7 0.5 1.0 1.0 1.0 1.0 CTHERM8 1.3 2.8 3.0 3.0 3.0 RTHERM6 26 20 15 13 12 RTHERM7 39 24 21 19 18 RTHERM8 55 38.7 31.3 29.7 25 PACKAGE MARKING AND ORDERING INFORMATION Device Marking Package Type Reel Size Tape Width Shipping† FDS8876 FDS8876 SOIC8 (SO−8) (Pb−Free) 13” 12 mm 2500 / Tape & Reel FDS8876−F40 FDS8876 SOIC8 (SO−8) (Pb−Free) 13” 12 mm 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. POWERTRENCH is registered trademark of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. www.onsemi.com 13 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC8 CASE 751EB ISSUE A DOCUMENT NUMBER: DESCRIPTION: 98AON13735G SOIC8 DATE 24 AUG 2017 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Email Requests to: orderlit@onsemi.com onsemi Website: www.onsemi.com ◊ TECHNICAL SUPPORT North American Technical Support: Voice Mail: 1 800−282−9855 Toll Free USA/Canada Phone: 011 421 33 790 2910 Europe, Middle East and Africa Technical Support: Phone: 00421 33 790 2910 For additional information, please contact your local Sales Representative