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DS100MB203
SNLS396D – JANUARY 2012 – REVISED JANUARY 2016
DS100MB203 10.3125 Gbps Dual Lane 2:1/1:2 Mux/Buffer
With Equalization and De-Emphasis
1 Features
•
1
•
•
•
•
•
10.3125 Gbps Dual Lane 2:1 Mux, 1:2 Switch or
Fan-Out
Low 390 mW Total Power (Typical)
Advanced Signal Conditioning Features:
– Receive Equalization Up to 36 dB at 5 GHz
– Transmit De-Emphasis Up to –12 dB
– Transmit Output Voltage Control: 600 mV to
1300 mV
Programmable Through Pin Selection, EEPROM
or SMBus Interface
Selectable 2.5-V or 3.3-V Supply Voltage
–40°C to 85°C Operating Temperature Range
2 Applications
•
•
•
•
The continuous time linear equalizer (CTLE) of the
receiver provides necessary boost to compensate up
to 40” FR-4 or 10m cable (AWG-24) at 10.3125 Gbps
- This on-chip feature eliminates the need for external
signal conditioners. The transmitter features a
programmable amplitude voltage levels to be
selectable from 600 mVp-p to 1300 mVp-p and DeEmphasis of up to 12 dB.
The DS100MB203 can be configured to support
PCIe, SAS/SATA, 10G-KR or other signaling
protocols. When operating in 10G-KR and PCIe Gen3 mode, the DS100MB203 transparently allows the
host controller and the end point to optimize the full
link and negotiate transmit equalizer coefficients. This
seamless management of the link training protocol
ensures system level interoperability with minimum
latency.
The programmable settings can be applied through
pin settings, SMBus (I2C) protocol or loaded directly
from an external EEPROM. When operating in the
EEPROM mode, the configuration information is
automatically loaded on power up, which eliminates
the need for an external microprocessor or software
driver.
10GE, 10G-KR
PCIe Gen-1/2/3
SAS2/SATA3 (Up to 6 Gbps)
XAUI, RXAUI
3 Description
The DS100MB203 device is a dual port 2:1
multiplexer and 1:2 switch or fan-out buffer with
signal conditioning suitable for 10GE, 10G-KR
(802.3ap),
Fibre
Channel,
PCIe,
Infiniband,
SATA3/SAS2 and other high-speed bus applications
with data rates up to 10.3125 Gbps.
Device Information(1)
PART NUMBER
DS100MB203
PACKAGE
WQFN (54)
10.00 mm × 5.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application
Simplified Functional Block Diagram
MB203
MB203
SEL0
DRIVE 0
S_INA0
S_INA+
S_INA-
D_OUT+
D_OUT-
BODY SIZE (NOM)
EXPANDER
TXA_0
DRIVE 1
D_OUT0
RX
S_INB0
S_INB+
S_INBS_OUTA+
S_OUTA-
D_IN+
D_IN-
TXB_0
TX
S_INA1
TXA_1
D_OUT1
S_OUTB+
S_OUTB-
AD0
Address straps
(pull-up to VIN or
pull-down to
GND)(1)
AD1
S_INA1
TXB_1
GND
1 OF 2
AD2
AD3
SATA/SAS
Mode(4)
MODE
RX
S_OUTA0
VIN
SMBus Slave Mode
(1)
SMBus Slave Mode(1)
SMBus
Slave Mode(1)
3.3V(3)
SMBus Slave
Mode(1)
SEL0
READ_EN / SEL1
ALL_DONE
1 F
VDD_SEL
0.1 F
(x5)
VDD (2.5 V)
S_OUTB0
RXB_0
ENSMB
SDA(2)
SCL(2)
VIN (3.3 V)
10 F
RXA_0
D_IN0
TX
S_OUTA1
To SMBus/I2C
Host Controller
INPUT_EN
RESET
D_IN1
RXA_1
S_OUTB1
SEL1
RXB_1
GND (DAP)
(1) Schematic shows connection for SMBus Slave Mode (ENSMB = 1 k: to VIN)
For SMBus Master Mode or Pin Mode configuration, the connections are different.
(2) SMBus signals must be pulled up elsewhere in the system.
(3) Schematic requires different connections for 2.5 V mode.
(4) Schematic requires pullup resistor for 10G-KR Mode.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DS100MB203
SNLS396D – JANUARY 2012 – REVISED JANUARY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
7
6.1
6.2
6.3
6.4
6.5
6.6
Absolute Maximum Ratings ...................................... 7
ESD Ratings.............................................................. 7
Recommended Operating Conditions....................... 7
Thermal Information .................................................. 7
Electrical Characteristics........................................... 8
Electrical Characteristics – Serial Management Bus
Interface .................................................................. 11
6.7 Timing Requirements – Serial Bus Interface .......... 11
6.8 Typical Characteristics ............................................ 13
7
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 14
7.3 Feature Description................................................. 15
7.4 Device Functional Modes........................................ 15
7.5 Programming .......................................................... 19
7.6 Register Maps ......................................................... 20
8
Application and Implementation ........................ 40
8.1 Application Information............................................ 40
8.2 Typical Application .................................................. 41
9
Power Supply Recommendations...................... 42
9.1 Power Supply Bypassing ........................................ 42
10 Layout................................................................... 44
10.1 Layout Guidelines ................................................. 44
10.2 Layout Example .................................................... 45
11 Device and Documentation Support ................. 46
11.1
11.2
11.3
11.4
11.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
46
46
46
46
46
12 Mechanical, Packaging, and Orderable
Information ........................................................... 46
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (November 2015) to Revision D
•
Changed Signal detect pattern at 8 Gbps .............................................................................................................................. 8
Changes from Revision B (April 2013) to Revision C
•
2
Page
Changed data sheet flow and layout to conform with new TI standards. Added the following sections: Application
and Implementation; Power Supply Recommendations; Layout; Device and Documentation Support; Mechanical,
Packaging, and Ordering Information .................................................................................................................................... 1
Changes from Revision A (April 2013) to Revision B
•
Page
Page
Changed layout of National Data Sheet to TI format ............................................................................................................. 1
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SNLS396D – JANUARY 2012 – REVISED JANUARY 2016
5 Pin Configuration and Functions
RESET
VDD
DEM_S1/SCL
DEM_S0/SDA
ENSMB
EQ_S1/AD2
EQ_S0/AD3
51
50
49
48
47
46
DEM_D0/AD1
53
52
DEM_D1/AD0
54
NJY Package
54-Pin WQFN
Top View (looking down through package)
SMBUS AND CONTROL
NC
1
45
S_INA0+
NC
2
44
S_INA0-
D_OUT0+
3
43
S_INB0+
D_OUT0-
4
42
S_INB0-
NC
5
41
VDD
NC
6
40
S_INA1+
D_OUT1+
7
39
S_INA1-
D_OUT1-
8
38
S_INB1+
37
S_INB1-
TOP VIEW
DAP = GND
VDD
9
D_IN0+
10
36
VDD
D_IN0-
11
35
S_OUTA0+
NC
12
34
S_OUTA0-
NC
13
33
S_OUTB0+
VDD
14
32
S_OUTB0-
D_IN1+
15
31
S_OUTA1+
D_IN1-
16
30
S_OUTA1-
NC
17
29
S_OUTB1+
NC
18
28
S_OUTB1-
19
20
21
22
23
24
25
26
27
EQ_D1
EQ_D0
MODE
INPUT_EN
SEL0
VIN
VDD_SEL
SEL1 / READ_EN
ALL_DONE
LDO REG
3.3V to 2.5V
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SNLS396D – JANUARY 2012 – REVISED JANUARY 2016
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Pin Functions: Common Connections (1)
PIN
NAME
NO.
TYPE
DESCRIPTION
DIFFERENTIAL HIGH-SPEED INPUTS AND OUTPUTS
D_IN0+,
D_IN0-,
D_IN1+,
D_IN1D_OUT0+, D_
OUT0-,
D_OUT1+,
D_OUT1S_INA0+,
S_INA0-,
S_INA1+,
S_INA1S_INB0+,
S_INB0-,
S_INB1+,
S_INB1S_OUTA0+,
S_OUTA0-,
S_OUTA1+,
S_OUTA1S_OUTB0+,
S_OUTB0-,
S_OUTB1+,
S_OUTB1-
10, 11, 15, 16
I
3, 4, 7, 8
O
45, 44, 40, 39
I
43, 42, 38, 37
I
35, 34, 31, 30
O
33, 32, 29, 28
O
Inverting and noninverting CML differential inputs to the equalizer. A gated on-chip 50Ω termination resistor connects D_INn+ to VDD and D_INn- to VDD when enabled. AC
coupling required on high-speed I/O.
Inverting and noninverting low power differential signaling 50-Ω outputs with deemphasis. Fully compatible with AC-coupled CML inputs. AC coupling required on
high-speed I/O.
Inverting and noninverting CML differential inputs to the equalizer. An on-chip 50-Ω
termination resistor connects S_INAn+ to VDD and S_INAn- to VDD. AC coupling
required on high-speed I/O.
Inverting and noninverting CML differential inputs to the equalizer. An on-chip 50-Ω
termination resistor connects S_INBn+ to VDD and S_INBn- to VDD. AC coupling
required on high-speed I/O.
Inverting and noninverting low power differential signaling 50-Ω outputs with deemphasis. Fully compatible with AC-coupled CML inputs.
Inverting and noninverting low power differential signaling 50-Ω outputs with deemphasis. Fully compatible with AC-coupled CML inputs. AC coupling required on
high-speed I/O.
CONTROL PINS - SHARED (LVCMOS)
ENSMB
48
I, FLOAT,
LVCMOS
System Management Bus (SMBus) enable pin
Tie 1 kΩ to VDD = register access SMBus slave mode
FLOAT = read external EEPROM (master SMBUS mode)
Tie 1 kΩ to GND = Pin Mode
CONTROL PINS—BOTH PIN AND SMBus MODES (LVCMOS)
0: Normal operation (device is enabled).
1: low power mode.
RESET
52
I, LVCMOS
VDD_SEL
25
I, FLOAT
GND
DAP
Power
Ground pad (DAP - die attach pad).
VDD
9, 14,36, 41,
51
Power
Power supply pins CML/analog
2.5-V mode, connect to 2.5 V ±5%
3.3-V mode, connect 0.1-uF cap to each VDD pin
VIN
24
Power
In 3.3-V mode, feed 3.3 V ±10% to VIN
In 2.5-V mode, leave floating.
Controls the internal regulator
FLOAT: 2.5-V mode
Tied to GND: 3.3-V mode
POWER
(1)
4
LVCMOS inputs without the “Float” conditions must be driven to a logic low or high at all times or operation is not ensured.
Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%.
For 3.3-V mode operation, VIN pin = 3.3 V and the "VDD" for the 4-level input is 3.3 V.
For 2.5-V mode operation, VDD pin = 2.5 V and the "VDD" for the 4-level input is 2.5 V.
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Pin Functions: SMBus/EEPROM Control
PIN
NAME
NO.
TYPE
DESCRIPTION
ENSMB = 1 (SMBUS SLAVE MODE), FLOAT (SMBUS MASTER MODE)
AD0-AD3
54, 53, 47,
46
I, LVCMOS
ENSMB master or slave mode
SMBus slave address Inputs. In SMBus mode, these pins are the user set SMBus slave
address inputs.
READ_EN
26
I, LVCMOS
ENSMB = FLOAT (SMBUS master mode)
When using an external EEPROM, a transition from high to low starts the load from the
external EEPROM
SCL
50
I, LVCMOS,
O, Opendrain
ENSMB master or slave mode
SMBUS clock input pin is enabled (slave mode)
SMBUS clock output when loading configuration from EEPROM (master mode)
SDA
49
I, LVCMOS,
O, Opendrain
ENSMB Master or Slave mode
The SMBus bidirectional SDA pin is enabled. Data input or open drain (pulldown only)
output.
CONTROL PINS—BOTH PIN AND SMBus MODES (LVCMOS)
INPUT_EN
22
I, 4-LEVEL,
LVCMOS
0: Normal operation, FANOUT is disabled, use SEL0/1 to select the A or B input/output (see
SEL0/1 pin), input always enabled with 50 Ω.
20kΩ to GND: Reserved
FLOAT: AUTO - Use RX Detect, SEL0/1 to determine which input or output to enable,
FANOUT is disable
1: Normal operation, FANOUT is enabled (both S_OUT0/1 are ON). Input always enabled
with 50 Ω.
MODE
21
I, 4-LEVEL,
LVCMOS
0: SATA/SAS, PCIe GEN 1/2 and 10GE
FLOAT: AUTO (PCIe GEN 1/2 or GEN 3)
1: 10-KR
23
I, 4-LEVEL,
LVCMOS
Select pin for Lane 0.
0: selects input S_INB0±, output S_OUTB0±.
20 kΩ to GND: selects input S_INB0±, output S_OUTA0±.
FLOAT: selects input S_INA0±, output S_OUTB0±.
1: selects input S_INA0±, output S_OUTA0±.
26
I, 4-LEVEL,
LVCMOS
Select pin for Lane 1.
0: selects input S_INB1±, output S_OUTB1±.
20 kΩ to GND: selects input S_INB1±, output S_OUTA1±.
FLOAT: selects input S_INA1±, output S_OUTB1±.
1: selects input S_INA1±, output S_OUTA1±.
27
0, LVCMOS
Valid Register Load Status Output
0: External EEPROM load passed
1: External EEPROM load failed
SEL0
SEL1
OUTPUT (LVCMOS)
ALL_DONE
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Pin Functions: Pin Control
PIN
NAME
NO.
TYPE
DESCRIPTION
ENSMB = 0 (PIN MODE)
DEM_S0,
DEM_S1
DEM_D0,
DEM_D1
49, 50, 53,
54
I, 4-LEVEL,
LVCMOS
DEM_D[1:0] and DEM_S[1:0] control the level of VOD and de-emphasis on the high-speed
output. The outputs are organized into two sides. The D side is controlled with the
DEM_D[1:0] pins and the S side is controlled with the DEM_S[1:0] pins. See Table 3.
EQ_D0,
EQ_D1
EQ_S0,
EQ_S1
20, 19, 46,
47
I, 4-LEVEL,
LVCMOS
EQ_D[1:0] and EQ_S[1:0] control the level of equalization on the high-speed input pins. The
inputs are organized into two sides. The D side is controlled with the EQ_D[1:0] pins and the
S side is controlled with the EQ_S[1:0] pins. See Table 2.
CONTROL PINS—BOTH PIN AND SMBus MODES (LVCMOS)
INPUT_EN
22
I, 4-LEVEL,
LVCMOS
0: Normal operation, FANOUT is disabled, use SEL0/1 to select the A or B input/output (see
SEL0/1 pin), input always enabled with 50 Ω.
20kΩ to GND: Reserved
FLOAT: AUTO - Use RX Detect, SEL0/1 to determine which input or output to enable,
FANOUT is disable
1: Normal operation, FANOUT is enabled (both S_OUT0/1 are ON). Input always enabled
with 50 Ω.
MODE
21
I, 4-LEVEL,
LVCMOS
0: SATA/SAS, PCIe GEN 1/2 and 10GE
FLOAT: AUTO (PCIe GEN 1/2 or GEN 3)
1: 10-KR
23
I, 4-LEVEL,
LVCMOS
Select pin for lane 0.
0: selects input S_INB0±, output S_OUTB0±.
20kΩ to GND: selects input S_INB0±, output S_OUTA0±.
FLOAT: selects input S_INA0±, output S_OUTB0±.
1: selects input S_INA0±, output S_OUTA0±.
26
I, 4-LEVEL,
LVCMOS
Select pin for Lane 1.
0: selects input S_INB1±, output S_OUTB1±.
20kΩ to GND: selects input S_INB1±, output S_OUTA1±.
FLOAT: selects input S_INA1±, output S_OUTB1±.
1: selects input S_INA1±, output S_OUTA1±.
SEL0
SEL1
6
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SNLS396D – JANUARY 2012 – REVISED JANUARY 2016
6 Specifications
6.1 Absolute Maximum Ratings
(1) (2) (3)
See
.
MIN
MAX
UNIT
Supply voltage (VDD – 2.5-V mode)
–0.5
2.75
V
Supply voltage (VIN – 3.3-V mode)
–0.5
4
V
LVCMOS input / output voltage
–0.5
4
V
CML input voltage
–0.5
(VDD + 0.5)
V
CML input current
–30
Junction temperature
Soldering (4 sec.) (3)
Lead temperature
Storage temperature, Tstg
(1)
(2)
(3)
–40
30
mA
125
°C
260
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
Soldering Information: SNOA549
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±3000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
2.5-V mode
Supply voltage
3.3-V mode
Ambient temperature
MIN
NOM
MAX
UNIT
2.375
2.5
2.625
V
3
3.3
3.6
V
–40
25
85
°C
3.6
V
100
mVp-p
SMBus (SDA, SCL)
Supply noise up to 50 MHz
(1)
(1)
Allowed supply noise (mVp-p sine wave) under typical conditions.
6.4 Thermal Information
DS100MB203
THERMAL METRIC (1)
NYJ (WQFN)
UNIT
54 PINS
RθJA
Junction-to-ambient thermal resistance, No Airflow, 4 layer JEDEC
26.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
10.8
°C/W
RθJB
Junction-to-board thermal resistance
4.4
°C/W
ψJT
Junction-to-top characterization parameter
0.2
°C/W
ψJB
Junction-to-board characterization parameter
4.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.5
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics (1) (2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD = 2.5-V supply
390
499
mW
VIN = 3.3-V supply
515
684
mW
POWER
PD
Power dissipation
EQ Enabled, VOD = 1 Vp-p,
RESET = 0
LVCMOS / LVTTL DC SPECIFICATIONS
Vih
High-level input
voltage
2
VDD
V
Vil
Low-level input
voltage
0
0.8
V
Voh
High-level output
voltage (ALL_DONE
pin)
Ioh= −4mA
Vol
Low-level output
voltage (ALL_DONE
pin)
Iol= 4mA
Input high current
(RESET pin)
VIN = 3.6 V,
LVCMOS = 3.6 V
Input high current
with internal resistors
(4–level input pin)
VIN = 3.6 V,
LVCMOS = 3.6 V
Input low current
(RESET pin)
Input low current with
internal resistors
(4–level input pin)
Iih
Iil
2
V
0.4
V
–15
15
µA
20
150
µA
VIN = 3.6 V,
LVCMOS = 0 V
–15
15
µA
VIN = 3.6 V,
LVCMOS = 0 V
–160
–40
µA
CML RECEIVER INPUTS (IN_n+, IN_n–)
RX differential return
loss
RLrx-diff
0.05 - 1.25 GHz
–16
dB
1.25 - 2.5 GHz
–16
dB
2.5 - 4.0 GHz
–14
dB
0.05 - 2.5 GHz
–12
dB
2.5 - 4.0 GHz
–8
dB
RLrx-cm
RX common-mode
return loss
Zrx-dc
RX DC commonmode impedance
Tested at VDD = 2.5 V
40
50
60
Ω
Zrx-diff-dc
RX DC differntial
mode impedance
Tested at VDD = 2.5 V
80
100
120
Ω
Vrx-signal-detdiff-pp
Signal detect assert
level for active data
signal
0101 pattern at 8 Gbps
180
mVp-p
0101 pattern at 8 Gbps
110
mVp-p
Signal detect deVrx-idle-det-diffassert level for
pp
electrical idle
HIGH-SPEED OUTPUTS
Vtx-diff-pp
Output voltage
differential swing
Differential measurement with OUT_n+ and OUT_n-,
terminated by 50 Ω to GND,
AC-Coupled, VID = 1 Vp-p,
DEM_x[1:0] = R, F (3)
Vtx-de-ratio_3.5
TX de-emphasis ratio
VOD = 1 Vp-p,
DEM_x[1:0] = R, F
(1)
(2)
(3)
8
0.8
1
–3.5
1.2
Vp-p
dB
Typical values represent most likely parametric norms at VDD = 2.5V, TA = 25°C., and at the Recommended Operation Conditions at
the time of product characterization and are not ensured.
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
In GEN3 mode, the output VOD level is not fixed. It will be adjusted automatically based on the VID input amplitude level. The output
VOD level set by DEM_x[1:0] in GEN3 mode is dependent on the VID level and the frequency content. The DS100MB203 repeater in
GEN3 mode is designed to be transparent, so the TX-FIR (de-emphasis) is passed to the RX to support the PCIe GEN3 handshake
negotiation link training.
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Electrical Characteristics(1)(2) (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Vtx-de-ratio_6
TX de-emphasis ratio
VOD = 1 Vp-p,
DEM_x[1:0] = F, 0
tTX-DJ
Deterministic jitter
VID = 800 mV, PRBS15 pattern, 8.0 0.05 Gbps, VOD
= 1 V, UIpp EQ = 0x00, DE = 0 dB (no input or output
trace loss)
0.05
UIpp
tTX-RJ
Random jitter
VID = 800 mV, 0101 pattern, 8.0 Gbps, 0.3 VOD = 1
V, ps RMS EQ = 0x00, DE = 0 dB, (no input or output
trace loss)
0.3
ps RMS
TTX-RISE-FALL
TX rise/fall time
20% to 80% of differential output voltage
TRF-MISMATCH
TX rise/fall mismatch
20% to 80% of differential output voltage
0.01
0.05 - 1.25 GHz
–16
dB
RLTX-DIFF
TX differential return
loss
1.25 - 2.5 GHz
–12
dB
2.5 - 4 GHz
–11
dB
0.05 - 2.5 GHz
–12
dB
–8
dB
100
Ω
–6
35
dB
45
ps
0.1
UI
RLTX-CM
TX common-mode
return loss
ZTX-DIFF-DC
DC differential TX
impedance
VTX-CM-AC-PP
TX AC commonmode voltage
VOD = 1 Vp-p,
DEM_x[1:0] = R, F
ITX-SHORT
TX short circuit
current limit
Total current the transmitter can supply when shorted
to VDD or GND
VTX-CM-DC-
Absolute delta of DC
common-mode
voltage during L0 and
electrical idle
100
mV
Absolute delta of DC
common-mode
voltage between TX+
and TX-
25
mV
ACTIVE-IDLE-DELTA
VTX-CM-DC-LINEDELTA
2.5 - 4 GHz
100
20
mVpp
mA
TTX-IDLE-DATA
Max time to transition
to differential DATA
signal after IDLE
VID = 1 Vp-p, 8 Gbps
3.5
ns
TTX-DATA-IDLE
Max time to transition
to IDLE after
differential DATA
signal
VID = 1 Vp-p, 8 Gbps
6.2
ns
TPLHD/PHLD
High-to-low and lowto-high differential
propagation delay
EQ = 00 (4)
200
ps
TLSK
Lane-to-lane skew
T = 25°C, VDD = 2.5 V
25
ps
TPPSK
Part-to-part
propagation delay
skew
T = 25°C, VDD = 2.5 V
40
ps
TMUX-SWITCH
Mux / switch time
100
ns
DJE1
35-in 4 mils FR4,
Residual deterministic VID = 0.8 Vp-p,
jitter at 10.3125 Gbps PRBS15, EQ = 1F'h,
DEM = 0 dB
0.3
UI
DJE2
35-in 4 mils FR4,
Residual deterministic VID = 0.8 Vp-p,
jitter at 8 Gbps
PRBS15, EQ = 1F'h,
DEM = 0 dB
0.14
UI
EQUALIZATION
(4)
Propagation Delay measurements will change slightly based on the level of EQ selected. EQ = 00 will result in the shortest propagation
delays.
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Electrical Characteristics(1)(2) (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DJE3
35-in 4 mils FR4,
Residual deterministic VID = 0.8 Vp-p,
jitter at 5 Gbps
PRBS15,EQ = 1F'h,
DEM = 0 dB
0.1
UI
DJE4
35-in 4 mils FR4,
Residual deterministic VID = 0.8 Vp-p,
jitter at 2.5 Gbps
PRBS15, EQ = 1F'h,
DEM = 0 dB
0.05
UI
DJE5
10 meters 30 awg cable,
Residual deterministic VID = 0.8 Vp-p,
jitter at 10.3125 Gbps PRBS15, EQ = 2F'h,
DEM = 0 dB
0.3
UI
DJE6
10 meters 30 awg cable,
Residual deterministic VID = 0.8 Vp-p,
jitter at 8 Gbps
PRBS15, EQ = 2F'h,
DEM = 0 dB
0.16
UI
DJE7
10 meters 30 awg cable,
Residual deterministic VID = 0.8 Vp-p,
jitter at 5 Gbps
PRBS15, EQ = 2F'h,
DEM = 0 dB
0.1
UI
DJE8
10 meters 30 awg cable,
Residual deterministic VID = 0.8 Vp-p,
jitter at 2.5 Gbps
PRBS15, EQ = 2F'h,
DEM = 0 dB
0.05
UI
DJD1
10-in 4 mils FR4,
Residual deterministic VID = 0.8 Vp-p,
jitter at 2.5 Gbps and PRBS15, EQ = 00,
5.0 Gbps
VOD = 1 Vp-p,
DEM = −3.5 dB
0.1
UI
DJD2
20-in 4 mils FR4,
Residual deterministic VID = 0.8 Vp-p,
jitter at 2.5 Gbps and PRBS15, EQ = 00,
5.0 Gbps
VOD = 1 Vp-p,
DEM = −9 dB
0.1
UI
DJD3
20-in 4 mils FR4,
VID = 0.8 Vp-p,
Residual deterministic
PRBS15, EQ = 00,
jitter at 10.3125 Gbps
VOD = 1 Vp-p,
DEM = −9 dB
0.1
UI
DE-EMPHASIS (MODE = 0)
10
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6.6 Electrical Characteristics – Serial Management Bus Interface
Over recommended operating supply and temperature ranges unless other specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SERIAL BUS INTERFACE DC SPECIFICATIONS
VIL
Data, clock input low voltage
VIH
Data, clock input high voltage
IPULLUP
Current through pullup resistor or
current source
VDD
Nominal bus voltage
ILEAK-Bus
Input leakage per bus segment
ILEAK-Pin
Input leakage per device Pin
CI
RTERM
(1)
(2)
(3)
2.1
High power specification
0.8
V
3.6
V
4
mA
2.375
3.6
V
–200
200
µA
See
(1)
Capacitance for SDA and SCL
See
(1) (2)
External termination resistance pull
to VDD = 2.5 V ± 5% OR 3.3 V ±
10%
Pullup VDD = 3.3 V (1) (2) (3)
2000
Ω
(1) (2) (3)
1000
Ω
–15
Pullup VDD = 2.5 V
µA
10
pF
Recommended value.
Recommended maximum capacitance load per bus segment is 400pF.
Maximum termination voltage should be identical to the device supply voltage.
6.7 Timing Requirements – Serial Bus Interface
MIN
NOM
280
400
ENSMB = VDD (slave mode)
MAX
UNIT
400
kHz
520
kHz
FSMB
Bus operating frequency
TBUF
Bus free time between stop and start condition
1.3
µs
THD:STA
Hold time after (repeated) start
condition. After this period, the first
clock is generated.
0.6
µs
TSU:STA
Repeated start condition set-up time
0.6
µs
TSU:STO
Stop condition set-up time
0.6
µs
THD:DAT
Data hold time
0
ns
TSU:DAT
Data set-up time
100
ns
TLOW
Clock low period
1.3
THIGH
Clock high period
0.6
tF
Clock / data fall time
tR
Clock / data rise time
tPOR
Time in which a device must be
operational after power-on reset
(1)
(2)
ENSMB = FLOAT (master mode)
At IPULLUP, maximum
See
See
(1)
(1) (2)
µs
50
µs
300
ns
300
ns
500
ms
Compatible with SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1
SMBus Common AC Specifications for details
Specified by Design. Parameter not tested in production.
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(OUT+)
80%
80%
VOD (p-p) = (OUT+) ± (OUT-)
0V
20%
20%
(OUT-)
tRISE
tFALL
Figure 1. CML Output and Rise and FALL Transition Time
+
IN
0V
tPHLD
tPLHD
+
0V
OUT
-
Figure 2. Propagation Delay Timing Diagram
+
IN
0V
DATA
tIDLE-DATA
tDATA-IDLE
+
OUT
0V
DATA
IDLE
IDLE
Figure 3. Transmit IDLE-DATA and DATA-IDLE Response Time
tLOW
tR
tHIGH
SCL
tHD:STA
tBUF
tHD:DAT
tF
tSU:STA
tSU:DAT
tSU:STO
SDA
SP
ST
SP
ST
Figure 4. SMBus Timing Parameters
12
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6.8 Typical Characteristics
1050
460.0
VDD = 2.625V
450.0
T = 25°C
VDD = 2.5V
440.0
1040
VDD = 2.375V
420.0
VOD (mVp-p)
PD (mW)
430.0
410.0
400.0
390.0
1030
1020
380.0
1010
T = 25°C
370.0
360.0
1000
2.375
350.0
0.8
0.9
1
1.1
1.2
1.3
2.5
2.625
VDD (V)
VOD (Vp-p)
Figure 6. Output Differential Voltage (VOD = 1 Vp-p) vs
Supply Voltage (VDD)
Figure 5. Power Dissipation (PD) vs Output Differential
Voltage (VOD)
1040
VDD = 2.5V
VOD (mVp-p)
1030
1020
1010
1000
- 40
-15
10
35
60
85
TEMPERATURE (°C)
Figure 7. Output Differential Voltage (VOD = 1 Vp-p) vs Temperature
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7 Detailed Description
7.1 Overview
The DS100MB203 is a dual lane 2:1 multiplexer and 1:2 switch or fan-out buffer with signal conditioning. The
DS100MB203 compensates for lossy FR-4 printed-circuit-board backplanes and balanced cables. The
DS100MB203 operates in 3 modes: Pin Control Mode (ENSMB = 0), SMBus Slave Mode (ENSMB = 1) and
SMBus Master Mode (ENSMB = float) to load register information from external EEPROM; please refer to
SMBUS Master Mode for additional information.
7.2 Functional Block Diagram
One of Two 2:1 / 1:2 Ports
VDD
S_INA_n+
EQ
S_INA_nOUTA_n+
VDD
Predriver
Driver
OUTA_n-
S_INB_n+
EQ
S_INB_n-
SEL[1:0]
VDD
D_INn+
EQ
D_INn-
S_OUTA_n+
Predriver
Driver
Predriver
Driver
S_OUTA_n-
ENSMB
EQ_D[1:0]
S_OUTB_n+
S_OUTB_n-
DEM_D[1:0]
EQ_S[1:0]
DEM_S[1:0]
READ_EN
ALL_DONE
AD[3:0]
SCL
SDA
Digital Core and SMBus Registers
Internal voltage
regulator
RESET
SEL[1:0]
VDD_SEL
VIN
14
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7.3 Feature Description
7.3.1 4-Level Input Configuration Guidelines
The 4-level input pins use a resistor divider to help set the four valid control levels and provide a wider range of
control settings when ENSMB = 0. There is an internal 30-kΩ pullup and a 60-kΩ pulldown connected to the
package pin. These resistors, together with the external resistor connection, combine to achieve the desired
voltage level. By using the 1-kΩ pulldown, 20-kΩ pulldown, no connect, and 1-kΩ pullup, the optimal voltage
levels for each of the four input states are achieved as shown in Table 1.
Table 1. 4–Level Control Pin Settings
RESULTING PIN VOLTAGE
LEVEL
SETTING
0
Tie 1 kΩ to GND
0.1 V
0.08 V
R
Tie 20 kΩ to GND
1/3 x VIN
1/3 x VDD
3.3-V MODE
2.5-V MODE
F
Float (leave pin open)
2/3 x VIN
2/3 x VDD
1
Tie 1 kΩ to VIN or VDD
VIN – 0.05 V
VDD – 0.04 V
The typical 4-Level input thresholds are as follows:
• Internal Threshold between 0 and R = 0.2 × VIN or VDD
• Internal Threshold between R and F = 0.5 × VIN or VDD
• Internal Threshold between F and 1 = 0.8 × VIN or VDD
In order to minimize the start-up current associated with the integrated 2.5-V regulator, the 1-kΩ pullup and
pulldown resistors are recommended. If several four level inputs require the same setting, it is possible to
combine two or more 1-kΩ resistors into a single lower value resistor. As an example, combining two inputs with
a single 500-Ω resistor is a valid way to save board space.
7.4 Device Functional Modes
7.4.1 Pin Control Mode
When in pin mode (ENSMB = 0) , the repeater is configurable with external pins. Equalization and de-emphasis
can be selected through pin for each side independently. When de-emphasis is asserted VOD is automatically
adjusted per Table 3. The receiver electrical idle detect threshold is also adjustable via the SD_TH pin.
7.4.2 SMBUS Mode
When in SMBus mode (ENSMB = 1), the VOD (output amplitude), equalization, de-emphasis, and termination
disable features are all programmable on a individual lane basis, instead of grouped by A or B as in the pin mode
case. Upon assertion of ENSMB the MODE, EQx and DEMx functions revert to register control immediately. The
EQx and DEMx pins are converted to AD0-AD3 SMBus address inputs. The other external control pins remain
active unless their respective registers are written to and the appropriate override bit is set, in which case they
are ignored until ENSMB is driven low (pin mode). On power up and when ENSMB is driven low all registers are
reset to their default state. If RESET is asserted while ENSMB is high, the registers retain their current state.
Equalization settings accessible through the pin controls were chosen to meet the needs of most applications. If
additional fine tuning or adjustment is needed, additional equalization settings can be accessed through the
SMBus registers. Each input has a total of 256 possible equalization settings. The tables show the 16 setting
when the device is in pin mode. When using SMBus mode, the equalization, VOD and de-Emphasis levels are
set by registers.
The input control pins have been enhanced to have 4 different levels and provide a wider range of control
settings when ENSMB=0.
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Device Functional Modes (continued)
Table 2. Equalizer Settings
LEVEL
EQ_D1
EQ_S1
EQ_D0
EQ_S0
EQ – 8 BITS [7:0]
dB AT
1.25 GHz
dB AT
2.5 GHz
dB AT
4 GHz
dB AT
5 GHz
SUGGESTED USE (1)
1
0
0
0000 0000 = 0x00
2.1
3.7
4.9
5.3
FR4 < 5 inch trace
2
0
R
0000 0001 = 0x01
3.4
5.8
7.9
8.7
FR4 5 inch 5–mil trace
3
0
Float
0000 0010 = 0x02
4.8
7.7
9.9
10.6
FR4 5 inch 4–mil trace
4
0
1
0000 0011 = 0x03
5.9
8.9
11.0
11.7
FR4 10 inch 5–mil trace
5
R
0
0000 0111 = 0x07
7.2
11.2
14.3
15.6
FR4 10 inch 4–mil trace
6
R
R
0001 0101 = 0x15
6.1
11.4
14.6
16.6
FR4 15 inch 4–mil trace
7
R
Float
0000 1011 = 0x0B
8.8
13.5
17.0
18.3
FR4 20 inch 4–mil trace
8
R
1
0000 1111 = 0x0F
10.2
15.0
18.5
19.7
FR4 25 to 30 inch 4–mil trace
(1)
9
Float
0
0101 0101 = 0x55
7.5
12.8
18.0
20.3
FR4 30 inch 4–mil trace
10
Float
R
0001 1111 = 0x1F
11.4
17.4
22.0
23.6
FR4 35 inch 4–mil trace
11
Float
Float
0010 1111 = 0x2F
13.0
19.7
24.4
25.8
10-m, 30-awg cable
12
Float
1
0011 1111 = 0x3F
14.2
21.1
25.8
27.0
13
1
0
1010 1010 = 0xAA
13.8
21.7
27.4
29.1
14
1
R
0111 1111 = 0x7F
15.6
23.5
29.0
30.7
15
1
Float
1011 1111 = 0xBF
17.2
25.8
31.4
32.7
16
1
1
1111 1111 = 0xFF
18.4
27.3
32.7
33.8
10-m – 12-m cable
FR4 lengths are for reference only. FR4 lengths based on a 100-Ω differential stripline with 5-mil traces and 8-mil trace separation.
Table 3. De-Emphasis and Output Voltage Settings
(1)
16
LEVEL
DEM_D1
DEM_S1
DEM_D0
DEM_S0
VOD Vp-p
DEM dB
INNER AMPLITUDE Vp-p
SUGGESTED USE (1)
1
2
0
0
0.6
0
0.6
FR4