DS125MB203SQE/NOPB

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents DS125MB203 SNLS432C – OCTOBER 2012 – REVISED DECEMBER 2015 DS125MB203 Low-Power 12.5-Gbps Dual-Lane 2:1/1:2 Mux/Buffer With Equalization and De-Emphasis 1 Features 3 Description • The DS125MB203 device is a dual port 2:1 multiplexer and 1:2 switch or fan-out buffer with signal conditioning suitable for 10GE, 10G-KR (802.3ap), Fibre Channel, PCIe, Infiniband, SATA3/SAS2 and other high-speed bus applications with data rates up to 12.5 Gbps. The continuous time linear equalizer (CTLE) of the receiver provides necessary boost to compensate up to 30-inch FR-4 or 8-m cable (AWG-24) at 12.5 Gbps. This on-chip feature eliminates the need for external signal conditioners. The transmitter features a programmable amplitude voltage levels to be selectable from 600 mVp-p to 1300 mVp-p and deemphasis of up to 12 dB. 1 • • • • • 12.5-Gbps Dual Lane 2:1 Mux, 1:2 Switch or Fanout Low 390-mW Total Power (Typical) Advanced Signal Conditioning Features: – Receive Equalization up to 30 dB at 6.25 GHz – Transmit De-Emphasis up to –12 dB – Transmit Output-Voltage Control: 600 mV to 1300 mV Programmable Through Pin Selection, EEPROM or SMBus Interface Selectable 2.5-V or 3.3-V Supply Voltage –40°C to +85°C Operating Temperature Range 2 Applications • • • • 10GE, 10G-KR PCIe Gen-1/2/3 SAS2/SATA3 (Up to 6 Gbps) XAUI, RXAUI The DS125MB203 can be configured to support PCIe, SAS/SATA, 10G-KR or other signaling protocols. When operating in 10G-KR and PCIe Gen3 mode, the DS125MB203 transparently allows the host controller and the end point to optimize the full link and negotiate transmit equalizer coefficients. This seamless management of the link training protocol ensures system level interoperability with minimum latency. Simplified Functional Block Diagram Device Information(1) MB203 PART NUMBER S_INA+ S_INA- D_OUT+ D_OUT- DS125MB203 S_INB+ S_INB- Address straps (pull-up to VIN or pull-down to GND)(1) D_IN+ D_IN- S_OUTA+ S_OUTA- AD0 S_OUTB+ S_OUTB- AD1 Typical Application AD2 AD3 MB203 SATA/SAS Mode(4) MODE VIN SMBus Slave Mode(1) SEL0 SMBus Slave Mode(1) SMBus Slave Mode(1) 3.3V(3) READ_EN / SEL1 ALL_DONE SMBus Slave Mode(1) 1 F VDD_SEL 0.1 F (x5) VDD (2.5 V) SEL0 DRIVE 0 S_INA0 EXPANDER RX TXA_0 DRIVE 1 D_OUT0 S_INB0 TXB_0 TX ENSMB SDA(2) SCL(2) VIN (3.3 V) 10 F BODY SIZE (NOM) 10.00 mm × 5.50 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. GND 1 OF 2 PACKAGE WQFN (54) S_INA1 To SMBus/I2C Host Controller D_OUT1 INPUT_EN RESET GND (DAP) TXA_1 S_INA1 TXB_1 EXPANDER RX S_OUTA0 D_IN0 TX RXA_0 S_OUTB0 (1) Schematic shows connection for SMBus Slave Mode (ENSMB = 1 k: to VIN) For SMBus Master Mode or Pin Mode configuration, the connections are different. (2) SMBus signals must be pulled up elsewhere in the system. (3) Schematic requires different connections for 2.5 V mode. (4) Schematic requires pullup resistor for 10G-KR Mode. D_IN1 S_OUTA1 S_OUTB1 RXB_0 RXA_1 RXB_1 SEL1 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DS125MB203 SNLS432C – OCTOBER 2012 – REVISED DECEMBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Description continued ........................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 7 7.1 7.2 7.3 7.4 7.5 7.6 Absolute Maximum Ratings ...................................... 7 ESD Ratings.............................................................. 7 Recommended Operating Conditions....................... 7 Thermal Information .................................................. 7 Electrical Characteristics........................................... 8 Electrical Characteristics – Serial Management Bus Interface .................................................................. 10 7.7 Timing Requirements – Serial Bus Interface .......... 10 7.8 Typical Characteristics ............................................ 12 8 Detailed Description ............................................ 13 8.1 Overview ................................................................. 13 8.2 Functional Block Diagram ....................................... 13 8.3 8.4 8.5 8.6 9 Feature Description................................................. Device Functional Modes........................................ Programming .......................................................... Register Maps ......................................................... 14 14 18 19 Application and Implementation ........................ 40 9.1 Application Information............................................ 40 9.2 Typical Application .................................................. 41 10 Power Supply Recommendations ..................... 42 10.1 Power Supply Bypassing ...................................... 42 11 Layout................................................................... 44 11.1 Layout Guidelines ................................................. 44 11.2 Layout Example .................................................... 45 12 Device and Documentation Support ................. 46 12.1 12.2 12.3 12.4 12.5 Documentation Support ........................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 46 46 46 46 46 13 Mechanical, Packaging, and Orderable Information ........................................................... 46 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (April 2013) to Revision C Page • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1 • Changed Signal detect pattern at 8 Gbps ............................................................................................................................. 8 Changes from Revision A (April 2013) to Revision B • 2 Page Changed layout of National Data Sheet to TI format ............................................................................................................. 1 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS125MB203 DS125MB203 www.ti.com SNLS432C – OCTOBER 2012 – REVISED DECEMBER 2015 5 Description continued The programmable settings can be applied through pin settings, SMBus (I2C) protocol or loaded directly from an external EEPROM. When operating in the EEPROM mode, the configuration information is automatically loaded on power up, which eliminates the need for an external microprocessor or software driver. 6 Pin Configuration and Functions RESET VDD DEM_S1/SCL DEM_S0/SDA ENSMB EQ_S1/AD2 EQ_S0/AD3 51 50 49 48 47 46 DEM_D0/AD1 53 52 DEM_D1/AD0 54 NJY Package 54-Pin WQFN Top View (looking down through package) SMBUS AND CONTROL NC 1 45 S_INA0+ NC 2 44 S_INA0- D_OUT0+ 3 43 S_INB0+ D_OUT0- 4 42 S_INB0- NC 5 41 VDD NC 6 40 S_INA1+ D_OUT1+ 7 39 S_INA1- D_OUT1- 8 38 S_INB1+ 37 S_INB1- TOP VIEW DAP = GND VDD 9 D_IN0+ 10 36 VDD D_IN0- 11 35 S_OUTA0+ NC 12 34 S_OUTA0- NC 13 33 S_OUTB0+ VDD 14 32 S_OUTB0- D_IN1+ 15 31 S_OUTA1+ D_IN1- 16 30 S_OUTA1- NC 17 29 S_OUTB1+ NC 18 28 S_OUTB1- 19 20 21 22 23 24 25 26 27 EQ_D1 EQ_D0 MODE INPUT_EN SEL0 VIN VDD_SEL SEL1 / READ_EN ALL_DONE LDO REG 3.3V to 2.5V Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS125MB203 3 DS125MB203 SNLS432C – OCTOBER 2012 – REVISED DECEMBER 2015 www.ti.com Pin Functions: Common Connections (1) PIN NAME NO. TYPE DESCRIPTION DIFFERENTIAL HIGH-SPEED INPUTS AND OUTPUTS D_IN0+, D_IN0-, D_IN1+, D_IN1D_OUT0+, D_ OUT0-, D_OUT1+, D_OUT1S_INA0+, S_INA0-, S_INA1+, S_INA1S_INB0+, S_INB0-, S_INB1+, S_INB1S_OUTA0+, S_OUTA0-, S_OUTA1+, S_OUTA1S_OUTB0+, S_OUTB0-, S_OUTB1+, S_OUTB1- 10, 11, 15, 16 I 3, 4, 7, 8 O 45, 44, 40, 39 I 43, 42, 38, 37 I 35, 34, 31, 30 O 33, 32, 29, 28 O Inverting and noninverting CML differential inputs to the equalizer. A gated on-chip 50Ω termination resistor connects D_INn+ to VDD and D_INn– to VDD when enabled. AC coupling required on high-speed I/O. Inverting and noninverting low power differential signaling 50-Ω outputs with deemphasis. Fully compatible with AC-coupled CML inputs. AC coupling required on high-speed I/O. Inverting and noninverting CML differential inputs to the equalizer. An on-chip 50-Ω termination resistor connects S_INAn+ to VDD and S_INAn– to VDD. AC coupling required on high-speed I/O. Inverting and noninverting CML differential inputs to the equalizer. An on-chip 50-Ω termination resistor connects S_INBn+ to VDD and S_INBn– to VDD. AC coupling required on high-speed I/O. Inverting and noninverting low power differential signaling 50-Ω outputs with deemphasis. Fully compatible with AC-coupled CML inputs. Inverting and noninverting low power differential signaling 50-Ω outputs with deemphasis. Fully compatible with AC-coupled CML inputs. AC coupling required on high-speed I/O. CONTROL PINS - SHARED (LVCMOS) ENSMB 48 I, FLOAT, LVCMOS System Management Bus (SMBus) enable pin Tie 1 kΩ to VDD = register access SMBus slave mode FLOAT = Read external EEPROM (master SMBUS mode) Tie 1 kΩ to GND = pin mode CONTROL PINS — BOTH PIN AND SMBus MODES (LVCMOS) 0: Normal operation (device is enabled). 1: Low power mode. RESET 52 I, LVCMOS VDD_SEL 25 I, FLOAT GND DAP Power Ground pad (DAP - die attach pad). VDD 9, 14,36, 41, 51 Power Power supply pins CML/analog 2.5-V mode, connect to 2.5V ±5% 3.3-V mode, connect 0.1-µF cap to each VDD pin VIN 24 Power In 3.3-V mode, feed 3.3 V ±10% to VIN In 2.5-V mode, leave floating. Controls the internal regulator FLOAT: 2.5-V mode Tied to GND: 3.3-V mode POWER (1) 4 LVCMOS inputs without the “Float” conditions must be driven to a logic low or high at all times or operation is not ensured. Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%. For 3.3V mode operation, VIN pin = 3.3V and the "VDD" for the 4-level input is 3.3V. For 2.5V mode operation, VDD pin = 2.5V and the "VDD" for the 4-level input is 2.5V. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS125MB203 DS125MB203 www.ti.com SNLS432C – OCTOBER 2012 – REVISED DECEMBER 2015 Pin Functions: SMBus/EEPROM Control PIN NAME NO. TYPE DESCRIPTION ENSMB = 1 (SMBUS SLAVE MODE), FLOAT (SMBUS MASTER MODE) SCL 50 I, LVCMOS, O, Opendrain ENSMB master or slave mode SMBUS clock input pin is enabled (slave mode) SMBUS clock output when loading configuration from EEPROM (master mode) SDA 49 I, LVCMOS, O, Opendrain ENSMB master or slave mode The SMBus bidirectional SDA pin is enabled. Data input or open-drain (pulldown only) output. AD0-AD3 54, 53, 47, 46 I, LVCMOS ENSMB Master or Slave mode SMBus slave address inputs. In SMBus mode, these pins are the user set SMBus slave address inputs. READ_EN 26 I, LVCMOS ENSMB = FLOAT (SMBUS master mode) When using an external EEPROM, a transition from high to low starts the load from the external EEPROM CONTROL PINS — BOTH PIN AND SMBus MODES (LVCMOS) MODE INPUT_EN SEL0 SEL1 I, 4-LEVEL, LVCMOS 0: SATA/SAS, PCIe GEN 1/2 and 10GE FLOAT: AUTO (PCIe GEN 1/2 or GEN 3) 1: 10-KR I, 4-LEVEL, LVCMOS 0: Normal operation, FANOUT is disabled, use SEL0/1 to select the A or B input/output (see SEL0/1 pin), input always enabled with 50 Ω. 20 kΩ to GND: Reserved FLOAT: AUTO - Use RX Detect, SEL0/1 to determine which input or output to enable, FANOUT is disable 1: Normal operation, FANOUT is enabled (both S_OUT0/1 are ON). Input always enabled with 50 Ω. 23 I, 4-LEVEL, LVCMOS Select pin for lane 0. 0: selects input S_INB0±, output S_OUTB0±. 20 kΩ to GND: Selects input S_INB0±, output S_OUTA0±. FLOAT: selects input S_INA0±, output S_OUTB0±. 1: Selects input S_INA0±, output S_OUTA0±. 26 I, 4-LEVEL, LVCMOS Select pin for lane 1. 0: Selects input S_INB1±, output S_OUTB1±. 20 kΩ to GND: Selects input S_INB1±, output S_OUTA1±. FLOAT: Selects input S_INA1±, output S_OUTB1±. 1: Selects input S_INA1±, output S_OUTA1±. 27 0, LVCMOS Valid register load status output 0: External EEPROM load passed 1: External EEPROM load failed 21 22 OUTPUT (LVCMOS) ALL_DONE Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS125MB203 5 DS125MB203 SNLS432C – OCTOBER 2012 – REVISED DECEMBER 2015 www.ti.com Pin Functions: Pin Control PIN NAME NO. TYPE DESCRIPTION ENSMB = 0 (PIN MODE) EQ_D0, EQ_D1 EQ_S0, EQ_S1 20, 19, 46, 47 I, 4-LEVEL, LVCMOS EQ_D[1:0] and EQ_S[1:0] control the level of equalization on the high-speed input pins. The inputs are organized into two sides. The D side is controlled with the EQ_D[1:0] pins and the S side is controlled with the EQ_S[1:0] pins. See Table 2. DEM_S0, DEM_S1 DEM_D0, DEM_D1 49, 50, 53, 54 I, 4-LEVEL, LVCMOS DEM_D[1:0] and DEM_S[1:0] control the level of VOD and de-emphasis on the high-speed output. The outputs are organized into two sides. The D side is controlled with the DEM_D[1:0] pins and the S side is controlled with the DEM_S[1:0] pins. See Table 3. CONTROL PINS — BOTH PIN AND SMBus MODES (LVCMOS) MODE INPUT_EN SEL0 SEL1 6 I, 4-LEVEL, LVCMOS 0: SATA/SAS, PCIe GEN 1/2 and 10GE FLOAT: AUTO (PCIe GEN 1/2 or GEN 3) 1: 10-KR I, 4-LEVEL, LVCMOS 0: Normal operation, FANOUT is disabled, use SEL0/1 to select the A or B input/output (see SEL0/1 pin), input always enabled with 50 Ω. 20 kΩ to GND: Reserved FLOAT: AUTO - Use RX Detect, SEL0/1 to determine which input or output to enable, FANOUT is disable 1: Normal operation, FANOUT is enabled (both S_OUT0/1 are ON). Input always enabled with 50 Ω. 23 I, 4-LEVEL, LVCMOS Select pin for lane 0. 0: Selects input S_INB0±, output S_OUTB0±. 20 kΩ to GND: Selects input S_INB0±, output S_OUTA0±. FLOAT: Selects input S_INA0±, output S_OUTB0±. 1: Selects input S_INA0±, output S_OUTA0±. 26 I, 4-LEVEL, LVCMOS Select pin for lane 1. 0: Selects input S_INB1±, output S_OUTB1±. 20 kΩ to GND: Selects input S_INB1±, output S_OUTA1±. FLOAT: Selects input S_INA1±, output S_OUTB1±. 1: Selects input S_INA1±, output S_OUTA1±. 21 22 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS125MB203 DS125MB203 www.ti.com SNLS432C – OCTOBER 2012 – REVISED DECEMBER 2015 7 Specifications 7.1 Absolute Maximum Ratings (1) (2) (3) See . MIN MAX UNIT Supply voltage (VDD – 2.5-V mode) –0.5 2.75 V Supply voltage (VIN – 3.3-V mode) –0.5 4 V LVCMOS input / output voltage –0.5 4 V CML input voltage –0.5 (VDD + 0.5) V CML input current –30 Junction temperature Soldering (4 sec.) (3) Lead temperature Storage temperature, Tstg (1) (2) (3) –40 30 mA 125 °C 260 °C 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/Distributors for availability and specifications. For soldering information see Absolute Maximum Ratings for Soldering, SNOA549 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) ±3000 Charged-device model (CDM), per JEDEC specification JESD22-C101, all pins (2) ±1000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions Supply voltage MIN NOM MAX UNIT 2.5-V mode 2.375 2.5 2.625 V 3.3-V mode 3.0 3.3 3.6 V –40 25 85 °C 3.6 V 100 mVp-p Ambient temperature SMBus (SDA, SCL) Supply noise up to 50 MHz (1) (1) Allowed supply noise (mVp-p sine wave) under typical conditions. 7.4 Thermal Information DS125MB203 THERMAL METRIC (1) NYJ (WQFN) UNIT 54 PINS RθJA Junction-to-ambient thermal resistance, No Airflow, 4 layer JEDEC 26.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 10.8 °C/W RθJB Junction-to-board thermal resistance 4.4 °C/W ψJT Junction-to-top characterization parameter 0.2 °C/W ψJB Junction-to-board characterization parameter 4.3 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 1.5 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS125MB203 7 DS125MB203 SNLS432C – OCTOBER 2012 – REVISED DECEMBER 2015 www.ti.com 7.5 Electrical Characteristics See (1) (2) . PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 390 500 mW 515 685 mW POWER PD Power dissipation EQ enabled, VOD = 1 Vp-p, VDD = 2.5-V supply RESET = 0 VIN = 3.3-V supply LVCMOS / LVTTL DC SPECIFICATIONS Vih High-level input voltage 2 3.6 V Vil Low-level input voltage 0 0.8 V Voh High-level output voltage (ALL_DONE pin) Ioh = −4 mA Vol Low-level output voltage (ALL_DONE pin) Iol = 4 mA Input-high current (RESET pin) VIN = 3.6 V, LVCMOS = 3.6 V Input-high current with VIN = 3.6 V, internal resistors LVCMOS = 3.6 V (4–level input pin) Iih Iil 2 V 0.4 V –15 15 µA 20 150 µA Input-low current (RESET pin) VIN = 3.6 V, LVCMOS = 0 V –15 15 µA Input-low current with internal resistors (4–level input pin) VIN = 3.6 V, LVCMOS = 0 V –160 –40 µA CML RECEIVER INPUTS (IN_n+, IN_n-) 0.05 – 7.5 GHz –15 dB 7.5 – 15 GHz –5 dB 0.05 – 5 GHz –10 dB RLrx-diff RX differential return loss RLrx-cm RX common-mode return loss Zrx-dc RX DC commonmode impedance Tested at VDD = 2.5 V 40 50 60 Ω Zrx-diff-dc RX DC differential mode impedance Tested at VDD = 2.5 V 80 100 120 Ω Vrx-diff-dc Differential Rx peak to Tested at pins peak voltage (VID) 0.6 1 1.2 V Vrx-signal-detdiff-pp Signal detect assert level for active data signal 0101 pattern at 8 Gbps 180 mVp-p Vrx-idle-det-diffpp Signal detect deassert 0101 pattern at 8 Gbps level for electrical idle 110 mVp-p HIGH SPEED OUTPUTS Vtx-diff-pp Output voltage differential swing Differential measurement with OUT_n+ and OUT_n-, terminated by 50 Ω to GND, AC-coupled, VID = 1.0 Vp-p, DEM_x[1:0] = R, F (3) Vtx-de-ratio_3.5 TX de-emphasis ratio VOD = 1.0 Vp-p, DEM_x[1:0] = R, F (1) (2) (3) 8 0.8 1 –3.5 1.2 Vp-p dB Typical values represent most likely parametric norms at VDD = 2.5 V, TA = 25°C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics conditions, notes, or both. Typical specifications are estimations only and are not ensured. In GEN3 mode, the output VOD level is not fixed. It will be adjusted automatically based on the VID input amplitude level. The output VOD level set by DEM_x[1:0] in GEN3 mode is dependent on the VID level and the frequency content. The DS125MB203 repeater in GEN3 mode is designed to be transparent, so the TX-FIR (de-emphasis) is passed to the RX to support the PCIe GEN3 handshake negotiation link training. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS125MB203 DS125MB203 www.ti.com SNLS432C – OCTOBER 2012 – REVISED DECEMBER 2015 Electrical Characteristics (continued) See (1)(2). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Vtx-de-ratio_6 TX de-emphasis ratio VOD = 1.0 Vp-p, DEM_x[1:0] = F, 0 tTX-DJ Deterministic jitter VID = 800 mV, PRBS15 pattern, 8.0 0.05 Gbps, VOD = 1.0 V, UIpp EQ = 0x00, DE = 0 dB (no input or output trace loss) tTX-RJ Random jitter VID = 800 mV, 0101 pattern, 8.0 Gbps, 0.3 VOD = 1.0 V, ps RMS EQ = 0x00, DE = 0 dB, (no input or output trace loss) TTX-RISE-FALL TX rise/fall time 20% to 80% of differential output voltage TRF-MISMATCH TX rise/fall mismatch 20% to 80% of differential output voltage 0.01 RLTX-DIFF TX Differential return loss 0.05 - 7.5 GHz –15 dB 7.5 - 15 GHz –5 dB RLTX-CM TX common-mode return loss 0.05 - 5 GHz –10 dB ZTX-DIFF-DC DC differential TX impedance 100 Ω VTX-CM-AC-PP TX AC common-mode VOD = 1.0 Vp-p, voltage DEM_x[1:0] = R, F ITX-SHORT TX short circuit current limit VTX-CM-DC- Absolute delta of DC common-mode voltage during L0 and electrical idle 100 mV Absolute delta of DC common-mode voltage between TX+ and TX– 25 mV ACTIVE-IDLE-DELTA VTX-CM-DC-LINEDELTA Total current the transmitter can supply when shorted to VDD or GND –6 35 dB 0.05 UIpp 0.3 ps RMS 45 ps 0.1 100 20 UI mVpp mA TTX-IDLE-DATA Max time to transition to differential DATA signal after IDLE VID = 1 Vp-p, 8 Gbps 3.5 ns TTX-DATA-IDLE Max time to transition to IDLE after differential DATA signal VID = 1 Vp-p, 8 Gbps 6.2 ns TPLHD/PHLD High-to-low and lowto-high differential propagation delay EQ = 00 (4) 200 ps TLSK Lane-to-lane skew T = 25°C, VDD = 2.5 V 25 ps TPPSK Part-to-part propagation delay skew T = 25°C, VDD = 2.5 V 40 ps TMUX-SWITCH Mux/switch time 100 ns DJE1 Residual deterministic 30-inch 4-mils FR4, VID = 0.6 Vp-p, PRBS15, jitter at 12 Gbps EQ = 07'h, DEM = 0 dB 0.18 UI DJE2 Residual deterministic 30-inch 4-mils FR4, VID = 0.6 Vp-p, PRBS15, jitter at 8 Gbps EQ = 07'h, DEM = 0 dB 0.11 UI DJE3 Residual deterministic 30-inch 4-mils FR4, VID = 0.6 Vp-p, PRBS15, jitter at 5 Gbps EQ = 07'h, DEM = 0 dB 0.07 UI DJE4 Residual deterministic 5 meters 30 awg cable, VID = 0.6 Vp-p, PRBS15, jitter at 12 Gbps EQ = 07'h, DEM = 0 dB 0.25 UI EQUALIZATION (4) Propagation Delay measurements will change slightly based on the level of EQ selected. EQ = 00 will result in the shortest propagation delays. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS125MB203 9 DS125MB203 SNLS432C – OCTOBER 2012 – REVISED DECEMBER 2015 www.ti.com Electrical Characteristics (continued) See (1)(2). PARAMETER TEST CONDITIONS MIN Residual deterministic 8 meters 30 awg cable, VID = 0.6 Vp-p, PRBS15, jitter at 8 Gbps EQ = 0F'h, DEM = 0 dB DJE5 TYP MAX UNIT 0.33 UI 0.1 UI DE-EMPHASIS (MODE = 0) Input channel: 20-inch 5-mils FR4, Output channel: Residual deterministic 10-inch 5-mils FR4, VID = 0.6 Vp-p, PRBS15, jitter at 12 Gbps EQ = 03'h, VOD = 1.0 Vp-p, DEM = −3.5 dB DJD1 7.6 Electrical Characteristics – Serial Management Bus Interface Over recommended operating supply and temperature ranges unless other specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SERIAL BUS INTERFACE DC SPECIFICATIONS VIL Data, clock input low voltage VIH Data, clock input high voltage IPULLUP Current through pullup resistor or current source VDD Nominal bus voltage ILEAK-Bus Input leakage per bus segment ILEAK-Pin Input leakage per device pin 2.1 High power specification See (1) (1) (2) 0.8 V 3.6 V 4 mA 2.375 3.6 V –200 200 µA –15 µA CI Capacitance for SDA and SCL See Pullup VDD = 3.3 V (1) (2) (3) 2000 Ω RTERM External termination resistance pull to VDD = 2.5 V ± 5% OR 3.3 V ± 10% (1) (2) (3) 1000 Ω (1) (2) (3) Pullup VDD = 2.5 V 10 pF Recommended value. Recommended maximum capacitance load per bus segment is 400 pF. Maximum termination voltage should be identical to the device supply voltage. 7.7 Timing Requirements – Serial Bus Interface MIN NOM 280 400 ENSMB = VDD (slave mode) MAX UNIT 400 kHz 520 kHz FSMB Bus operating Frequency TBUF Bus free time between stop and start condition 1.3 µs THD:STA Hold time after (repeated) start condition. After this period, the first clock is generated. 0.6 µs TSU:STA Repeated start condition set-up time 0.6 µs TSU:STO Stop condition set-up time 0.6 µs THD:DAT Data hold time 0 ns TSU:DAT Data set-up time 100 ns TLOW Clock low period 1.3 THIGH Clock high period 0.6 tF Clock / data fall time tR Clock / data rise time tPOR Time in which a device must be operational after power-on reset (1) (2) 10 ENSMB = FLOAT (master mode) At IPULLUP, maximum See See (1) (1) (2) µs 50 µs 300 ns 300 ns 500 ms Compatible with SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1 SMBus common AC specifications for details. Specified by Design. Parameter not tested in production. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS125MB203 DS125MB203 www.ti.com SNLS432C – OCTOBER 2012 – REVISED DECEMBER 2015 (OUT+) 80% 80% VOD (p-p) = (OUT+) ± (OUT-) 0V 20% 20% (OUT-) tRISE tFALL Figure 1. CML Output and Rise and FALL Transition Time + IN 0V tPHLD tPLHD + 0V OUT - Figure 2. Propagation Delay Timing Diagram + IN 0V DATA tIDLE-DATA tDATA-IDLE + OUT 0V DATA IDLE IDLE Figure 3. Transmit IDLE-DATA and DATA-IDLE Response Time tLOW tR tHIGH SCL tHD:STA tBUF tHD:DAT tF tSU:STA tSU:DAT tSU:STO SDA SP ST ST SP Figure 4. SMBus Timing Parameters Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS125MB203 11 DS125MB203 SNLS432C – OCTOBER 2012 – REVISED DECEMBER 2015 www.ti.com 7.8 Typical Characteristics 1050 460.0 VDD = 2.625V 450.0 T = 25°C VDD = 2.5V 440.0 1040 VDD = 2.375V 420.0 VOD (mVp-p) PD (mW) 430.0 410.0 400.0 390.0 1030 1020 380.0 1010 T = 25°C 370.0 360.0 1000 2.375 350.0 0.8 0.9 1 1.1 1.2 1.3 2.5 2.625 VDD (V) VOD (Vp-p) Figure 6. Output Differential Voltage (VOD = 1 Vp-p) vs Supply Voltage (VDD) Figure 5. Power Dissipation (PD) vs Output Differential Voltage (VOD) 1040 VDD = 2.5V VOD (mVp-p) 1030 1020 1010 1000 - 40 -15 10 35 60 85 TEMPERATURE (°C) Figure 7. Output Differential Voltage (VOD = 1 Vp-p) vs Temperature 12 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS125MB203 DS125MB203 www.ti.com SNLS432C – OCTOBER 2012 – REVISED DECEMBER 2015 8 Detailed Description 8.1 Overview The DS125MB203 is a dual lane 2:1 multiplexer and 1:2 switch or fan-out buffer with signal conditioning. The DS125MB203 compensates for lossy FR-4 printed-circuit-board backplanes and balanced cables. The DS125MB203 operates in 3 modes: Pin Control Mode (ENSMB = 0), SMBus Slave Mode (ENSMB = 1) and SMBus Master Mode (ENSMB = float) to load register information from external EEPROM; refer to SMBUS Master Mode for additional information. 8.2 Functional Block Diagram One of Two 2:1 / 1:2 Ports VDD S_INA_n+ EQ S_INA_nOUTA_n+ VDD Predriver Driver OUTA_n- S_INB_n+ EQ S_INB_n- SEL[1:0] VDD D_INn+ EQ D_INn- S_OUTA_n+ Predriver Driver Predriver Driver S_OUTA_n- ENSMB EQ_D[1:0] S_OUTB_n+ S_OUTB_n- DEM_D[1:0] EQ_S[1:0] DEM_S[1:0] READ_EN ALL_DONE AD[3:0] SCL SDA Digital Core and SMBus Registers Internal voltage regulator RESET SEL[1:0] VDD_SEL VIN Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS125MB203 13 DS125MB203 SNLS432C – OCTOBER 2012 – REVISED DECEMBER 2015 www.ti.com 8.3 Feature Description 8.3.1 4-Level Input Configuration Guidelines The 4-level input pins use a resistor divider to help set the four valid control levels and provide a wider range of control settings when ENSMB = 0. There is an internal 30-kΩ pullup and a 60-kΩ pulldown connected to the package pin. These resistors, together with the external resistor connection, combine to achieve the desired voltage level. By using the 1-kΩ pulldown, 20-kΩ pulldown, no connect, and 1-kΩ pullup, the optimal voltage levels for each of the four input states are achieved as shown in Table 1. Table 1. 4–Level Control Pin Settings RESULTING PIN VOLTAGE LEVEL SETTING 0 Tie 1 kΩ to GND 0.1 V 0.08 V R Tie 20 kΩ to GND 1/3 × VIN 1/3 × VDD 3.3-V MODE 2.5-V MODE F Float (leave pin open) 2/3 × VIN 2/3 × VDD 1 Tie 1 kΩ to VIN or VDD VIN – 0.05 V VDD – 0.04 V The typical 4-Level Input thresholds are as follows: • Internal Threshold between 0 and R = 0.2 × VIN or VDD • Internal Threshold between R and F = 0.5 × VIN or VDD • Internal Threshold between F and 1 = 0.8 × VIN or VDD To minimize the start-up current associated with the integrated 2.5-V regulator, the 1-kΩ pullup and pulldown resistors are recommended. If several four level inputs require the same setting, it is possible to combine two or more 1-kΩ resistors into a single lower value resistor. As an example, combining two inputs with a single 500-Ω resistor is a valid way to save board space. 8.4 Device Functional Modes 8.4.1 Pin Control Mode When in pin mode (ENSMB = 0) , the repeater is configurable with external pins. Equalization and de-emphasis can be selected through pin for each side independently. When de-emphasis is asserted VOD is automatically adjusted per Table 3. The receiver electrical idle detect threshold is also adjustable through the SD_TH pin. 8.4.2 SMBUS Mode When in SMBus mode (ENSMB = 1), the VOD (output amplitude), equalization, de-emphasis, and termination disable features are all programmable on a individual lane basis, instead of grouped by A or B as in the pin mode case. Upon assertion of ENSMB the MODE, EQx and DEMx functions revert to register control immediately. The EQx and DEMx pins are converted to AD0-AD3 SMBus address inputs. The other external control pins remain active unless their respective registers are written to and the appropriate override bit is set, in which case they are ignored until ENSMB is driven low (pin mode). On power up and when ENSMB is driven low all registers are reset to their default state. If RESET is asserted while ENSMB is high, the registers retain their current state. Equalization settings accessible through the pin controls were chosen to meet the needs of most applications. If additional fine tuning or adjustment is needed, additional equalization settings can be accessed through the SMBus registers. Each input has a total of 256 possible equalization settings. The tables show the 16 setting when the device is in pin mode. When using SMBus mode, the equalization, VOD and de-emphasis levels are set by registers. The input control pins have been enhanced to have 4 different levels and provide a wider range of control settings when ENSMB=0. 14 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS125MB203 DS125MB203 www.ti.com SNLS432C – OCTOBER 2012 – REVISED DECEMBER 2015 Device Functional Modes (continued) Table 2. Equalizer Settings LEVEL EQ_D1 EQ_S1 EQ_D0 EQ_S0 EQ – 8 BITS [7:0] dB AT 1.5 GHz dB AT 2.5 GHz dB AT 4 GHz dB AT 6 GHz SUGGESTED USE (1) 1 0 0 0000 0000 = 0x00 2.5 3.5 3.8 3.1 FR4 < 5 inch trace 2 0 R 0000 0001 = 0x01 3.8 5.4 6.7 6.7 FR4 5 inch 5–mil trace 3 0 Float 0000 0010 = 0x02 5.0 7.0 8.4 8.4 FR4 5 inch 4–mil trace 4 0 1 0000 0011 = 0x03 5.9 8.0 9.3 9.1 FR4 10 inch 5–mil trace 5 R 0 0000 0111 = 0x07 7.4 10.3 12.8 13.7 FR4 10 inch 4–mil trace 6 R R 0001 0101 = 0x15 6.9 10.2 13.9 16.2 FR4 15 inch 4–mil trace 7 R Float 0000 1011 = 0x0B 9.0 12.4 15.3 15.9 FR4 20 inch 4–mil trace 8 R 1 0000 1111 = 0x0F 10.2 13.8 16.7 17.0 FR4 25 to 30 inch 4–mil trace (1) 9 Float 0 0101 0101 = 0x55 8.5 12.6 17.5 20.7 FR4 30 inch 4–mil trace 10 Float R 0001 1111 = 0x1F 11.7 16.2 20.3 21.8 FR4 35-inch 4–mil trace 11 Float Float 0010 1111 = 0x2F 13.2 18.3 22.8 23.6 10-m, 30-awg cable 12 Float 1 0011 1111 = 0x3F 14.4 19.8 24.2 24.7 13 1 0 1010 1010 = 0xAA 14.4 20.5 26.4 28.0 14 1 R 0111 1111 = 0x7F 16.0 22.2 27.8 29.2 15 1 Float 1011 1111 = 0xBF 17.6 24.4 30.2 30.9 16 1 1 1111 1111 = 0xFF 18.7 25.8 31.6 31.9 10-m – 12-m cable FR4 lengths are for reference only. FR4 lengths based on a 100-Ω differential stripline with 5-mil traces and 8-mil trace separation. Table 3. De-Emphasis and Output Voltage Settings (1) LEVEL DEM_D1 DEM_S1 DEM_D0 DEM_S0 VOD Vp-p DEM dB INNER AMPLITUDE Vp-p SUGGESTED USE (1) 1 2 0 0 0.6 0 0.6 FR4