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DS125BR401A
SNLS466A – SEPTEMBER 2013 – REVISED MARCH 2014
DS125BR401A Low-Power 12 Gbps 4-Lane Linear Repeater With Equalization
1 Features
3 Description
•
The DS125BR401A is an extremely low-power highperformance repeater/redriver designed to support
four lanes carrying high speed interface up to 12
Gbps. The B-Side receiver's continuous time linear
equalizers (CTLE) provide high frequency boost of up
to +24 dB at 6 GHz (12 Gbps) and are capable of
opening an input eye that is completely closed due to
inter symbol interference (ISI) induced by
interconnect medium such as backplane traces or
twinaxial copper cables. The programmable
equalization allows maximum flexibility in the physical
placement within the interconnect channel. The ASide channel has a 10 dB linear equalizer and linear
output driver.
1
•
•
•
•
•
•
•
•
Low 65-mW/Channel (Typ) Power Consumption,
With Option to Power Down Unused Channels
Linear Equalization allows for Link Training in
PCIe and SAS
Supports Out-of-Band (OOB) Signaling
Advanced Signal Conditioning B-Side I/O
– Receive CTLE up to 24 dB at 6 GHz
– Transmit (Tx) DE > 10 dB
– Tx Output Voltage: 700 mV to 1400 mV
Advanced Signal Conditioning A-Side I/O
– Receive CTLE up to 10 dB at 6 GHz
– Linear output drive
– Output voltage range over 1200mV
Programmable via Terminal Selection, EEPROM,
or SMBus Interface
Single Supply Voltage: 2.5 V or 3.3 V
−40°C to 85°C Operating Temperature Range
4 kV HBM ESD Rating
Flow-Thru Layout in 10mmx5.5mm 54-Terminal
Leadless WQFN Package
2 Applications
•
•
•
SAS/SATA
PCI Express
Other Proprietary Interfaces up to 12 Gbps
The A-Side channel has a settable 3-10 dB linear
equalizer coupled to a linear output driver. When
operating in SAS-3 and PCIe Gen-3 applications the
DS125BR401A
preserves
transmit
signal
characteristics allowing the host controller and the
end point to negotiate transmit equalizer coefficients.
This transparency to the link training protocol aides
system level interoperability and minimum latency.
The programmable settings can be applied easily via
Terminals, software (SMBus or I2C), or loaded via an
external EEPROM. In EEPROM mode, the
configuration information is automatically loaded on
power up, which eliminates the need for an external
microprocessor or software driver.
Device Information
ORDER NUMBER
PACKAGE
DS125BR401ANJY
WQFN (48)
BODY SIZE
10 mm x 5,5 mm
SAS-3 Application
SAS-3 Controller 1
SAS-3 Controller 0
DS125BR401A
-24 dB Max
-10 dB Max
RX
OUTB
TX
INA
Channel Loss ~ Equal
INB
TX
OUTA
RX
Channel Loss ~ Equal
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DS125BR401A
SNLS466A – SEPTEMBER 2013 – REVISED MARCH 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Terminal Configuration and Functions................
Specifications.........................................................
1
1
1
2
3
6
6.1
6.2
6.3
6.4
6.5
6.6
Absolute Maximum Ratings ...................................... 6
Handling Ratings....................................................... 6
Recommended Operating Conditions....................... 6
Thermal Information ................................................. 6
Electrical Characteristics........................................... 6
Electrical Characteristics — Serial Management Bus
Interface .................................................................. 10
6.7 Timing Requirements Serial Bus Interface ............. 10
6.8 Typical Characteristics ............................................ 12
7
7.3
7.4
7.5
7.6
7.7
8
Feature Description.................................................
Device Functional Modes........................................
Signal Conditioning Settings ...................................
Programming...........................................................
Register Maps .........................................................
14
14
16
18
25
Applications and Implementation ...................... 38
8.1 Application Information............................................ 38
8.2 Typical Application .................................................. 39
9 Power Supply Recommendations...................... 42
10 Layout................................................................... 43
10.1 Layout Guidelines ................................................. 43
10.2 Layout Example .................................................... 43
11 Device and Documentation Support ................. 44
Detailed Description ............................................ 13
11.1 Trademarks ........................................................... 44
11.2 Electrostatic Discharge Caution ............................ 44
11.3 Glossary ................................................................ 44
7.1 Overview ................................................................. 13
7.2 Functional Block Diagram ....................................... 13
12 Mechanical, Packaging, and Orderable
Information ........................................................... 44
4 Revision History
Changes from Original (September 2013) to Revision A
Page
•
Changed from preview to production data document. .......................................................................................................... 1
•
Changed to new TI datasheet standard: added Handling Ratings table and Device and Documentation section. .............. 1
2
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SNLS466A – SEPTEMBER 2013 – REVISED MARCH 2014
5 Terminal Configuration and Functions
PWDN
VDD
DEMA1/SCL
DEMA0/SDA
ENSMB
EQB1/AD2
EQB0/AD3
51
50
49
48
47
46
DEMB0/AD1
53
52
DEMB1/AD0
54
54-Lead WQFN
Top View
SMBUS AND CONTROL
OUTB_0+
1
45
INB_0+
OUTB_0-
2
44
INB_0-
OUTB_1+
3
43
INB_1+
OUTB_1-
4
42
INB_1-
OUTB_2+
5
41
VDD
OUTB_2-
6
40
INB_2+
OUTB_3+
7
39
INB_2-
OUTB_3-
8
38
INB_3+
VDD
9
37
INB_3-
INA_0+
10
36
VDD
INA_0-
11
35
OUTA_0+
INA_1+
12
34
OUTA_0-
INA_1-
13
33
OUTA_1+
VDD
14
32
OUTA_1-
INA_2+
15
31
OUTA_2+
INA_2-
16
30
OUTA_2-
INA_3+
17
29
OUTA_3+
INA_3-
18
28
OUTA_3-
19
20
21
22
23
24
25
26
27
EQA1
EQA0
MODE_B
RXDET
RES
VIN
VDD_SEL
SD_TH / READ_EN
ALL_DONE
DAP = GND
NOTE: Above 54-lead WQFN graphic is a TOP VIEW, looking down through the package.
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SNLS466A – SEPTEMBER 2013 – REVISED MARCH 2014
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Terminal Functions (1)
TERMINAL
NUMBER
TERMINAL NAME
I/O, TYPE
TERMINAL DESCRIPTION
DIFFERENTIAL HIGH SPEED I/O
INB_0+,
INB_1+,
INB_2+,
INB_3+,
INB_0- ,
INB_1-,
INB_2-,
INB_3-
OUTB_0+,
OUTB_1+,
OUTB_2+,
OUTB_3+,
INA_0+,
INA_1+,
INA_2+,
INA_3+,
OUTB_0-,
OUTB_1-,
OUTB_2-,
OUTB_3-
INA_0- ,
INA_1-,
INA_2-,
INA_3-
OUTA_0+,
OUTA_1+,
OUTA_2+,
OUTA_3+,
OUTA_0-,
OUTA_1-,
OUTA_2-,
OUTA_3-
45, 44, 43, 42
40, 39, 38, 37
I
Inverting and non-inverting CML differential inputs to the equalizer. Onchip 50Ω termination resistor connects INB_n+ to VDD and INB_n- to
VDD when enabled.
AC coupling required on high-speed I/O
1, 2, 3, 4
5, 6, 7, 8
O
Inverting and non-inverting 50Ω driver outputs with de-emphasis.
Compatible with AC coupled CML inputs.
AC coupling required on high-speed I/O
10, 11, 12, 13
15, 16, 17, 18
I
Inverting and non-inverting CML differential inputs to the equalizer. Onchip 50Ω termination resistor connects INA_n+ to VDD and INA_n- to
VDD when enabled.
AC coupling required on high-speed I/O
35, 34, 33, 32
31, 30, 29, 28
O
Inverting and non-inverting 50Ω driver outputs. Compatible with AC
coupled CML inputs.
AC coupling required on high-speed I/O
CONTROL TERMINALS — SHARED (LVCMOS)
ENSMB
48
I, LVCMOS
System Management Bus (SMBus) enable Terminal
Tie 1kΩ to VDD = Register Access SMBus Slave mode
FLOAT = Read External EEPROM (Master SMBUS Mode)
Tie 1kΩ to GND = Terminal Mode
ENSMB = 1 (SMBus MODE)
SCL
50
I, LVCMOS,
O, OPEN Drain
ENSMB Master or Slave mode
SMBus clock input Terminal is enabled (slave mode).
Clock output when loading EEPROM configuration (master mode).
SDA
49
I, LVCMOS,
O, OPEN Drain
ENSMB Master or Slave mode
The SMBus bidirectional SDA Terminal is enabled. Data input or open
drain (pull-down only) output.
AD0-AD3
54, 53, 47, 46
I, LVCMOS
ENSMB Master or Slave mode
SMBus Slave Address Inputs. In SMBus mode, these Terminals are the
user set SMBus slave address inputs.
READ_EN
26
I, LVCMOS
When using an External EEPROM, a logic low on this terminal starts the
load from the external EEPROM
ENSMB = 0 (TERMINAL MODE)
EQA0, EQA1
EQB0, EQB1
20, 19
46, 47
I, 4-LEVEL,
LVCMOS
EQA[1:0] and EQB[1:0] control the level of equalization of the A/B
directions. The Terminals are defined as EQx[1:0] only when ENSMB is
de-asserted (low). Each of the 4 A/B channels have the same level
unless controlled by the SMBus control registers. When ENSMB goes
high the SMBus registers provide independent control of each lane. The
EQB[1:0] Terminals are converted to SMBus AD2, AD3 inputs. See
Table 5.
DEMB0, DEMB1
53, 54
I, 4-LEVEL,
LVCMOS
DEMB[1:0] controls the level of de-emphasis of CHB outputs. The
Terminals are defined as DEMB[1:0] only when ENSMB is de-asserted
(low). Each of the 4 B channels have the same level unless controlled by
the SMBus control registers. When ENSMB goes high the SMBus
registers provide independent control of each lane. The DEMB[1:0]
Terminals are converted to AD0, AD1 inputs. See Table 7.
MODE_B
21
I, 4-LEVEL,
LVCMOS
MODE_B control Terminal selects operating modes for the INB-OUTB
Channels.
Tie 1kΩ to GND = GEN 1,2 and SAS 1,2
Float = Auto Mode Select (for PCIe)
Tie 20kΩ to GND = SAS-3 and GEN-3 without De-emphasis
Tie 1kΩ to VDD = SAS-3 and GEN-3 with De-emphasis
See Table 4.
(1)
4
LVCMOS inputs without the “Float” conditions must be driven to a logic low or high at all times or operation is not ensured.
Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%.
For 3.3V mode operation, VIN Terminal input = 3.3V and the logic "1" reference for the 4-level input is 3.3V.
For 2.5V mode operation, VDD Terminal output= 2.5V and the logic "1" reference for the 4-level input is 2.5V.
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Terminal Functions(1) (continued)
TERMINAL
NUMBER
TERMINAL NAME
I/O, TYPE
TERMINAL DESCRIPTION
DEMA0, DEMA1
49, 50
I, 4-LEVEL,
LVCMOS
DEMA[1:0] controls the CHA output amplitude. The Terminals are
defined as DEMA[1:0] only when ENSMB is de-asserted (low). Each of
the 4 A channels have the same level unless controlled by the SMBus
control registers. When ENSMB goes high the SMBus registers provide
independent control of each lane and the DEMA[1:0] Terminals are
converted to SCL and SDA. See Table 7.
SD_TH
26
I, 4-LEVEL,
LVCMOS
Controls the internal Signal Detect Threshold on the INB-OUTB
Channels. For CHB, the signal detect is used to bring the output into and
out of IDLE. This allows the OOB signaling to pass with minimal
distortion.
See Table 3.
CONTROL TERMINALS — BOTH TERMINAL AND SMBus MODES (LVCMOS)
RXDET
22
I, 4-LEVEL,
LVCMOS
The RXDET Terminal controls the receiver detect function. Depending on
the input level, a 50Ω or >50KΩ termination to the power rail is enabled.
In SAS/SATA system RXDET should be set to a Logic "1" state to keep
the termination always enabled.
See Table 2.
RES
23
I, 4-LEVEL,
LVCMOS
Reserved:
This input must be left Floating.
VDD_SEL
25
I, FLOAT
Controls the internal regulator
Float = 2.5V mode
Tie GND = 3.3V mode
PWDN
52
I, LVCMOS
Tie High = Low power - power down
Tie GND = Normal Operation
See Table 2.
ALL_DONE
27
O, LVCMOS
Valid Register Load Status Output
HIGH = External EEPROM load failed or incomplete
LOW = External EEPROM load passed
VIN
24
Power
In 3.3V mode, feed 3.3V to VIN
In 2.5V mode, leave floating.
VDD
9, 14,36, 41, 51
Power
Power supply Terminals CML/analog
2.5V mode, connect to 2.5V
3.3V mode, connect 0.1 µF cap to each VDD Terminal and GND
GND
DAP
Power
Ground pad (DAP - die attach pad).
POWER
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SNLS466A – SEPTEMBER 2013 – REVISED MARCH 2014
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6 Specifications
6.1 Absolute Maximum Ratings (1)
MIN
MAX
UNIT
Supply Voltage (VDD - 2.5V)
-0.5
+2.75
V
Supply Voltage (VIN - 3.3V)
-0.5
+4.0
V
LVCMOS Input/Output Voltage
-0.5
+4.0
V
CML Input Voltage
-0.5V to (VDD+0.5)
CML Input Current
(1)
-30
+30
mA
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Absolute
Maximum Numbers are ensured for a junction temperature range of -40°C to +125°C. Models are validated to Maximum Operating
Voltages only.
6.2 Handling Ratings
MIN
MAX
UNIT
ESDHBM
HBM, STD - JESD22-A114F
4
kV
ESDCDM
CDM, STD - JESD22-C101-D
1
kV
Tstg
Storage Temperature Range
125
°C
260
°C
Tsolder
(1)
-40
Lead Temperature Range Soldering (4 sec.)
(1)
For soldering specifications: See application note SNOA549.
6.3 Recommended Operating Conditions
MIN
TYP
MAX
UNIT
Supply Voltage (2.5V mode)
2.375
2.5
2.625
V
Supply Voltage (3.3V mode)
3.0
3.3
3.6
V
Ambient Temperature
-40
25
+85
°C
SMBus (SDA, SCL)
3.6
V
Supply Noise up to 50 MHz (1)
100
mVp-p
(1)
Allowed supply noise (mVp-p sine wave) under typical conditions.
6.4 Thermal Information
DS125BR401A
THERMAL METRIC (1)
WQFN
UNIT
54 TERMINALS
RθJA
Junction-to-ambient thermal resistance
26.6
RθJCtop
Junction-to-case (top) thermal resistance
10.8
RθJB
Junction-to-board thermal resistance
4.4
ψJT
Junction-to-top characterization parameter
0.2
ψJB
Junction-to-board characterization parameter
4.3
RθJCbot
Junction-to-case (bottom) thermal resistance
1.5
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER
IDD
6
Current Consumption
DEM0 = Float, ,DEM1 = Float
EQ = 0, VOD = 0.8VP-P,
RXDET = 1, PWDN = 0
200
280
mA
Power Down Current Consumption
PWDN = 1
14
27
mA
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Electrical Characteristics (continued)
PARAMETER
VDD
TEST CONDITIONS
Integrated LDO Regulator
VIN = 3.0 - 3.6 V
MIN
TYP
MAX
UNIT
2.375
2.5
2.625
V
LVCMOS / LVTTL DC SPECIFICATIONS
Vih25
High Level Input Voltage
2.5 V Supply Mode
1.7
VDD
V
Vih33
High Level Input Voltage
3.3 V Supply Mode
1.7
VIN
V
Vil
Low Level Input Voltage
0
0.7
V
Voh
High Level Output Voltage
(ALL_DONE Terminal)
Ioh = −4mA
Vol
Low Level Output Voltage
(ALL_DONE Terminal)
Iol = 4mA
Iih
Input High Current (PWDN Terminal)
VIN = 3.6 V,
LVCMOS = 3.6 V
Iil
Input Low Current (PWDN Terminal)
2.0
V
0.4
V
-15
+15
uA
VIN = 3.6 V,
LVCMOS = 0 V
-15
+15
uA
Input High Current with internal
resistors
(4–level input Terminal)
VIN = 3.6 V,
LVCMOS = 3.6 V
+20
+150
uA
Input Low Current with internal
resistors
(4–level input Terminal)
VIN = 3.6 V,
LVCMOS = 0 V
-160
-40
uA
4-LEVEL INPUT DC SPECIFICATIONS
Iih
Iil
Vth
Threshold 0 / R
0.45
VDD = 2.5V (2.5V supply mode)
Internal LDO Disabled
See Table 1 for details
Threshold R / Float
Threshold Float / 1
Threshold 0 / R
1.2
0.6
VIN = 3.3V (3.3V supply mode)
Internal LDO Enabled
See Table 1 for details.
Threshold R / Float
Threshold Float / 1
V
2
1.6
V
2.6
CML RECEIVER INPUTS (IN_n+, IN_n-)
RLRX-diff
RX Differential return loss
SDD11 10 MHz
-19
SDD11 2 GHz
-14
SDD11 6-11.1 GHz
-8
-10
dB
RLRX-cm
RX Common mode return loss
0.05 - 5 GHz
ZRX-dc
RX DC common mode impedance
Tested at VDD = 2.5 V
40
50
60
Ω
ZRX-diff-dc
RX DC differential mode impedance
Tested at VDD = 2.5 V
80
100
120
Ω
VRX-signal-det-diff-
Signal detect assert level for active
data signal
SD_TH = F (float),
0101 pattern at 12 Gbps
50
mVp-p
Signal detect de-assert level for
electrical idle
SD_TH = F (float),
0101 pattern at 12 Gbps
37
mVp-p
20% to 80% of differential output
voltage
40
ps
20% to 80% of differential output
voltage
0.01
UI
SDD22 10 MHz - 2 GHz
-15
SDD22 5.5 GHz
-12
SDD22 11.1 GHz
-10
dB
pp
VRX-idle-det-diff-pp
dB
HIGH SPEED OUTPUTS
TTX-RISE-FALL
Transmitter rise/fall time
TRF-MISMATCH
Transmitter rise/fall mismatch
(1)
RLTX-DIFF
TX Differential return loss
RLTX-CM
TX Common mode return loss
ZTX-DIFF-DC
DC differential TX impedance
0.05 - 5 GHz
ITX-SHORT
Transmitter short circuit current limit
VTX-CM-DC-
Absolute delta of DC common mode
voltage during L0 and electrical idle
ACTIVE-IDLE-DELTA
(1)
Total current, output shorted to
VDD or GND
dB
-10
dB
100
Ω
20
mA
100
mV
Rise / Fall time measurements will on A-Channels will vary based on EQ setting, Input Amplitude, and input edge rate.
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Electrical Characteristics (continued)
PARAMETER
VTX-CM-DC-LINEDELTA
TEST CONDITIONS
MIN
TYP
Absolute delta of DC common mode
voltage between TX+ and TX-
MAX
UNIT
25
mV
HIGH SPEED OUTPUTS (A-CHANNELS)
VTXA-diff1-pp
Output Voltage Differential Swing
Differential measurement with
OUTA_n+ and OUTA_n-,
AC-Coupled and terminated by
50Ω to GND,
Inputs AC-Coupled,
VID = 600 mVp-p
VOD = 001'b (800mV)
375
465
600
mVp-p
Output Voltage Differential Swing
Differential measurement with
OUTA_n+ and OUTA_n-,
AC-Coupled and terminated by
50Ω to GND,
Inputs AC-Coupled,
VID = 1000 mVp-p
VOD = 001'b (800mV)
550
675
825
mVp-p
Output Voltage Differential Swing
Differential measurement with
OUTA_n+ and OUTA_n-,
AC-Coupled and terminated by
50Ω to GND,
Inputs AC-Coupled,
VID = 600 mVp-p
DEMA[1:0] = 10, VOD = 1300mV
475
600
750
Vp-p
Output Voltage Differential Swing
Differential measurement with
OUTA_n+ and OUTA_n-,
AC-Coupled and terminated by
50Ω to GND,
Inputs AC-Coupled,
VID = 1000 mVp-p
VOD = 110'b (1300mV)
775
915
1125
Vp-p
TTXA-IDLE-DATA
Time to transition to valid differential
signal after idle
VID = 1.0 Vp-p, 3 Gbps
0.04
ns
TTXA-DATA-IDLE
Time to transition to idle after
differential signal
VID = 1.0 Vp-p, 3 Gbps
0.70
ns
TPDEQA
Differential propagation delay Channel A
EQ = Level 1 to Level 4
80
ps
VTXA-diff2-pp
VTXA-diff3-pp
VTXA-diff4-pp
HIGH SPEED OUTPUTS (B-CHANNELS)
VTXB-diff1-pp
Output Voltage Differential Swing
Differential measurement with
OUTB_n+ and OUTB_n-,
AC-Coupled and terminated by
50Ω to GND,
Inputs AC-Coupled,
VID = 1.0 Vp-p, MODE_B = 1
DEMB1 = 0, DEMB0 = 1 (2)
0.8
1.0
1.2
Vp-p
Output Voltage Differential Swing
Differential measurement with
OUTB_n+ and OUTB_n-,
AC-Coupled and terminated by
50Ω to GND,
Inputs AC-Coupled,
VID = 1.0 Vp-p, MODE_B = 0
DEMB1 = 0, DEMB0 = R
670
820
930
mVp-p
Output Voltage Differential Swing
Differential measurement with
OUTB_n+ and OUTB_n-,
AC-Coupled and terminated by
50Ω to GND,
Inputs AC-Coupled,
VID = 1.0 Vp-p, MODE_B = 0
DEMB1 = R, DEMB0 = FLOAT
950
1140
1250
mVp-p
VTXB-diff2-pp
VTXB-diff3-pp
(2)
8
In SAS-3 and PCIe GEN3 mode, the output VOD level is not fixed. It will be adjusted automatically based on the VID input amplitude
level. The output VOD level set by DEMA/B[1:0] in this mode BOUTn is dependent on the VID level and the frequency content. The
DS125BR401A repeater is designed to be transparent in this mode, so the TX-FIR (de-emphasis) is passed to the RX to support the
handshake negotiation link training.
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Electrical Characteristics (continued)
PARAMETER
TEST CONDITIONS
TX de-emphasis ratio
VOD = 1.0 Vp-p,
DEM0 = 0, DEM1 = R, MODE_B
=0
OUTB_n only Gen 1 & 2 mode
−3.5
dB
TX de-emphasis ratio
VOD = 1.0 Vp-p,
DEM0 = R, DEM1 = R, MODE_B
=0
OUTB_n only in Gen 1 & 2 mode
−6
dB
TTXB-IDLE-DATA
Time to transition to valid differential
signal after idle
VID = 1.0 Vp-p, 3 Gbps
3.5
ns
TTXB-DATA-IDLE
Time to transition to idle after
differential signal
VID = 1.0 Vp-p, 3 Gbps
5.0
ns
TPDEQB
Differential propagation delay Channel B
EQ = 00 (3)
135
ps
VTXB-de-ratio_3.5
VTXB-de-ratio_6
MIN
TYP
MAX
UNIT
EQUALIZATION (A-CHANNELS)
DJE1A
Residual deterministic jitter at 6 Gbps
5” Differential Stripline, 5mil trace
width, FR4,
VID = 0.8 Vp-p,
PRBS15, EQ = 01'h,
VOD = 1.3V, DEM = 0 dB
0.06
UI
DJE3A
Residual deterministic jitter at 12 Gbps
5” Differential Stripline, 5mil trace
width, FR4,
VID = 0.8 Vp-p,
PRBS15, EQ = 01'h,
VOD = 1.3V, DEM = 0 dB
0.12
UI
Residual deterministic jitter at 12 Gbps
30” Differential Stripline, 5mil
trace width, FR4,
VID = 0.6 Vp-p,
PRBS15, EQ = 07'h,
DEM = 0 dB
0.18
UI
Residual deterministic jitter at 12 Gbps
5 meters 30 awg cable,
VID = 0.6 Vp-p,
PRBS15, EQ = 07'h,
DEM = 0 dB
0.25
UI
Input Channel: 20" Differential
Stripline, 5mil trace width, FR4,
Output Channel: 10” Differential
Stripline, 5mil trace width, FR4,
VID = 0.6 Vp-p,
PRBS15, EQ = 03'h,
VOD = 1.0 Vp-p,
DEMB = −3.5 dB
0.1
UI
EQUALIZATION (B-CHANNELS)
DJE1B
DJE2B
DE-EMPHASIS (B-CHANNELS, GEN 1&2 MODE ONLY)
DJD1
Residual deterministic jitter at 12 Gbps
(3)
Propagation Delay measurements will change slightly based on the level of EQ selected. EQ = 00 will result in the shortest propagation
delays.
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6.6 Electrical Characteristics — Serial Management Bus Interface
Over recommended operating supply and temperature ranges unless other specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SERIAL BUS INTERFACE DC SPECIFICATIONS
VIL
Data, Clock Input Low Voltage
VIH
Data, Clock Input High Voltage
VOL
Output Low Voltage
VDD
Nominal Bus Voltage
IIH-Terminal
Input Leakage Per Device Terminal
IIL-Terminal
Input Leakage Per Device Terminal
SDA or SCL, IOL = 1.25 mA
0.8
V
2.1
3.6
V
0
0.36
V
2.375
3.6
V
+20
+150
µA
-160
-40
µA
(1) (2)
CI
Capacitance for SDA and SCL
See
50KΩ). MODE_B setting is also Terminal controllable with Terminal selections (Gen 1/2, auto detect, and
SAS-3 / PCIe Gen 3). The receiver electrical signal detect threshold is also adjustable via the SD_TH
Terminal. For A-Side Channels this can only be used for status information, on B-Side Channels this
threshold will determine when the output state, Mute if no signal is present or active with a valid input signal
detected .
7.4.2 SMBus Mode:
When in SMBus mode (ENSMB = 1), the VOD (output amplitude), equalization, de-emphasis, and
termination disable features are all programmable on a individual lane basis, instead of grouped by A or B as
in the Terminal mode case. Upon assertion of ENSMB, the EQx and DEMx functions revert to register
control immediately. The EQx and DEMx Terminals are converted to AD0-AD3 SMBus address inputs. The
other external control Terminals (MODE_B, RXDET and SD_TH) remain active unless their respective
registers are written to and the appropriate override bit is set, in which case they are ignored until ENSMB is
driven low (Terminal mode). On power-up or when ENSMB is driven low all registers are reset to their default
state. If PWDN is asserted while ENSMB is high, the registers retain their current state.
14
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Device Functional Modes (continued)
Equalization settings accessible via the Terminal controls were chosen to meet the needs of most high speed
applications. If additional fine tuning or adjustment is needed, additional equalization settings can be
accessed via the SMBus registers. Each input has a total of 256 possible equalization settings. The tables
show the 16 settings when the device is in Terminal mode. When using SMBus mode, the equalization, VOD
and de- Emphasis levels are set by registers.
The 4-level input Terminals utilize a resistor divider to help set the 4 valid levels and provide a wider range of
control settings when ENSMB=0. There is an internal 30K pull-up and a 60K pull-down connected to the
package Terminal. These resistors, together with the external resistor connection combine to achieve the
desired voltage level. Using the 1K pull-up, 1K pull-down, no connect, and 20K pull-down provide the optimal
voltage levels for each of the four input states.
Table 2. RX-Detect Settings
PWDN
RXDET
SMBus REG
(Terminal 52) (Terminal 22)
Bit[3:2]
0
0
INPUT
TERMINATION
RECOMMENDED
USE
Hi-Z
X
Manual RX-Detect, input is high impedance mode
Pre Detect: Hi-Z
Post Detect: 50 Ω
PCIe only
Auto RX-Detect, outputs test every 12 msec for
600 msec then stops; termination is Hi-Z until RX
detection; once detected input termination is 50 Ω
00
COMMENTS
Tie 20kΩ
to GND
01
0
Float
(Default)
10
Pre Detect: Hi-Z
Post Detect: 50 Ω
PCIe only
Auto RX-Detect, outputs test every 12 msec until
detection occurs; termination is Hi-Z until RX
detection; once detected input termination is 50 Ω
0
1
11
50 Ω
All Others
Manual RX-Detect, input is 50 Ω
1
X
High Impedance
X
0
Reset function by pulsing PWDN high for 5 usec
then low again
Power down mode, input is Hi-Z, output drivers are
disabled
Used to reset RX-Detect State Machine when held
high for 5 usec
Table 3. OOB And Signal Detect Threshold Level (1)
(1)
SD_TH
(Terminal 26)
SMBus REG BIT [3:2] and [1:0]
3 Gbps
12 Gbps
3 Gbps
12 Gbps
0
10
18
75
14
55
[3:2] ASSERT LEVEL (mVp-p)
[1:0] DE-ASSERT LEVEL (mVp-p)
R
01
12
40
8
22
F (default)
00
15
50
11
37
1
11
16
58
12
45
VDD = 2.5V, 25°C, 11 00 11 00 pattern at 3 Gbps and 101010 pattern at 12 Gbps
Table 4. Mode Operation With Terminal Control
MODE_B
(Terminal 21)
Driver characteristics
0
Limiting
R
Transparent without DE
F (default)
Automatic
1
Transparent with DE
PCIe
SAS
SATA
10GbE
CPRI
OBSAI
SRIO
(R)XAUI
Interlaken
Infiniband
X (≤ 6G)
X
X
X
X
X
X (SAS-3)
7.4.3 MODE operation with SMBus Registers
When in SMBus mode (Slave or Master), the MODE Terminal retains control of the output driver characteristics.
In order to override this control function, Register 0x08[2] must be written with a "1". Writing this bit enables
MODE control of each channel individually using the channel registers defined in Table 9. For Channel-A outputs
the MODE control bit is not functional. The outputs are always in a linear mode of operation. Changing these bits
while Register 0x08[2]=1 will dramatically reduce the output amplitude.
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7.5 Signal Conditioning Settings
Information in Table 5 and Table 6 shows the level of CTLE or equalization gain for Channel-B and Channel-A.
Table 5. B-Channel Equalizer Settings
Level
EQB1
EQB0
EQ – 8 bits [7:0]
dB at
1.5 GHz
dB at
2.5 GHz
dB at
4 GHz
dB at
6 GHz
Suggested Use (1)
1
0
0
0000 0000 = 0x00
2.5
3.5
3.8
3.1
FR4 < 5 inch trace
2
0
R
0000 0001 = 0x01
3.8
5.4
6.7
6.7
FR4 5-10 inch trace
3
0
Float
0000 0010 = 0x02
5.0
7.0
8.4
8.4
FR4 10 inch trace
4
0
1
0000 0011 = 0x03
5.9
8.0
9.3
9.1
FR4 15-20 inch trace
5
R
0
0000 0111 = 0x07
7.4
10.3
12.8
13.7
FR4 20-30 inch trace
6
R
R
0001 0101 = 0x15
6.9
10.2
13.9
16.2
FR4 25-30 inch trace
7
R
Float
0000 1011 = 0x0B
9.0
12.4
15.3
15.9
FR4 25-30 inch trace
8
R
1
0000 1111 = 0x0F
10.2
13.8
16.7
17.0
8m, 30awg cable
9
Float
0
0101 0101 = 0x55
8.5
12.6
17.5
20.7
> 8m cable
10
Float
R
0001 1111 = 0x1F
11.7
16.2
20.3
21.8
11
Float
Float
0010 1111 = 0x2F
13.2
18.3
22.8
23.6
12
Float
1
0011 1111 = 0x3F
14.4
19.8
24.2
24.7
13
1
0
1010 1010 = 0xAA
14.4
20.5
26.4
28.0
14
1
R
0111 1111 = 0x7F
16.0
22.2
27.8
29.2
15
1
Float
1011 1111 = 0xBF
17.6
24.4
30.2
30.9
16
1
1
1111 1111 = 0xFF
18.7
25.8
31.6
31.9
(1)
Cable and FR4 lengths are for reference only. FR4 lengths based on a 100 Ohm differential stripline with 5-mil traces and 8-mil trace
separation. Optimal EQ setting should be determined via simulation and prototype verification.
Table 6. A-Channel Equalizer Settings
Level
EQA1
EQA0
EQ – 8 bits [7:0]
dB at
1.5 GHz
dB at
2.5 GHz
dB at
4 GHz
dB at
6 GHz
1
N/A
0
xxxx xx00 = 0x00
2.5
3.5
3.8
3.1
2
N/A
R
xxxx xx01 = 0x01
3.8
5.4
6.7
6.7
3
N/A
Float
xxxx xx10 = 0x02
5.0
7.0
8.4
8.4
4
N/A
1
xxxx xx11 = 0x03
5.9
8.0
9.3
9.1
(1)
16
Suggested Use (1)
SAS-3
Cable and FR4 lengths are for reference only. FR4 lengths based on a 100 Ohm differential stripline with 5-mil traces and 8-mil trace
separation. Optimal EQ setting should be determined via simulation and prototype verification.
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SNLS466A – SEPTEMBER 2013 – REVISED MARCH 2014
Table 7. B-Channel Output Voltage And De-Emphasis Settings
(1)
(2)
Level
DEMB1
DEMB0
VOD Vp-p
DEM dB (1)
Inner Amplitude
Vp-p
Suggested Use (2)
1
0
0
0.8
0
0.8
FR4
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