DS125BR401
Low Power 12.5 Gbps 4-lane Repeater with Input Equalization and
Output De-Emphasis
General Description
Features
The DS125BR401 is an extremely low power, high performance multi-protocol repeater/redriver designed to support 4lanes of SAS-3/2/1, PCIe Gen-3/2/1, 10G-KR and other high
speed interface serial protocols up to 12.5 Gbps. The
receiver's continuous time linear equalizer (CTLE) provides a
boost of up to +30 dB at 6.25 GHz (12.5 Gbps) in each of its
eight channels and is capable of opening an input eye that is
completely closed due to inter symbol interference (ISI) induced by interconnect medium such as 30”+ backplane traces
or 8m+ copper cables, hence enabling host controllers to ensure an error free end-to-end link. The transmitter provides a
de-emphasis boost of up to -12 dB and output voltage amplitude control from 700 mV to 1300 mV to allow maximum
flexibility in the physical placement within the interconnect
channel.
When operating in SAS-3, 10G-KR and PCIe Gen-3 mode,
the DS125BR401 transparently allows the host controller and
the end point to optimize the full link and negotiate transmit
equalizer coefficients. This seamless management of the link
training protocol ensures guaranteed system level interoperability with minimum latency. With a low power consumption
of 65 mW/channel (typ) and option to turn-off unused channels, the DS125BR401 enables energy efficient system design. A single supply of 3.3v or 2.5v is required to power the
device.
The programmable settings can be applied easily via pins,
software (SMBus/I2C) or loaded via an external EEPROM.
When operating in the EEPROM mode, the configuration information is automatically loaded on power up, which eliminates the need for an external microprocessor or software
driver.
● Comprehensive family, proven system inter-operability
●
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DS125BR111 : 1-lane, bi-directional repeater
DS125BR210 : 2-channel, uni-directional repeater
DS125BR401 : 4-lane, bi-directional repeater
DS125BR800 : 8-channel, uni-directional repeater
DS125MB203 : 2-port, 2:1/1:2 Mux/Switch
DS125DF410 : 4-channel, uni-directional retimer w/CDR
Low 65 mW/channel (typ) power consumption, with option
to power down unused channels
Transparent management of link training protocol for
PCIe, SAS, 10G-KR
Advanced signal conditioning features
- Receive Equalization up to 30 dB at 6.25 GHz
- Transmit de-emphasis up to -12 dB
- Transmit output voltage control: 700 mV to 1300 mV
Programmable via pin selection, EEPROM or SMBus
interface
Single supply voltage: 2.5V or 3.3V (selectable)
−40 to 85°C operating temperature range
5 kV HBM ESD rating
Flow-thru pinout in 10mmx5.5mm 54-pin leadless QFN
package
Supported Protocols
● SAS-3/2/1, SATA, Fibre Channel (up to 10GFC)
● PCIe Gen-3/2/1, 10G-KR, 10GbE, XAUI, RXAUI
● sRIO, Infiniband, Interlaken, CPRI, OBSAI
● Other proprietary interface up to 12.5 Gbps
Typical Application
30198780
PRODUCTION DATA information is current as of
publication date. Products conform to specifications per
the terms of the Texas Instruments standard warranty.
Production processing does not necessarily include
testing of all parameters.
301987 SNLS419A
Copyright © 1999-2012, Texas Instruments Incorporated
DS125BR401
Block Diagram - Detail View Of Channel (1 Of 8)
30198786
2
Copyright © 1999-2012, Texas Instruments Incorporated
DS125BR401
Pin Diagram
30198792
DS125BR401 Pin Diagram 54-lead QFN
Note: Above 54-lead QFN graphic is a TOP VIEW, looking down through the package.
Ordering Information
ORDERABLE DEVICE
Quantity
Package
DS125BR401SQ/NOPB
Tape & Reel Supplied As 2,000 Units
SQA54A
DS125BR401SQE/NOPB
Tape & Reel Supplied As 250 Units
SQA54A
Copyright © 1999-2012, Texas Instruments Incorporated
3
DS125BR401
Pin Descriptions
Pin Name
Pin Number
I/O, Type
Pin Description
Differential High Speed I/O's
INB_0+, INB_0- ,
INB_1+, INB_1-,
INB_2+, INB_2-,
INB_3+, INB_3-
45, 44, 43, 42 I
40, 39, 38, 37
OUTB_0+, OUTB_0-, 1, 2, 3, 4
OUTB_1+, OUTB_1-, 5, 6, 7, 8
OUTB_2+, OUTB_2-,
OUTB_3+, OUTB_3INA_0+, INA_0- ,
INA_1+, INA_1-,
INA_2+, INA_2-,
INA_3+, INA_3-
O
10, 11, 12, 13 I
15, 16, 17, 18
OUTA_0+, OUTA_0-, 35, 34, 33, 32 O
OUTA_1+, OUTA_1-, 31, 30, 29, 28
OUTA_2+, OUTA_2-,
OUTA_3+, OUTA_3-
Inverting and non-inverting CML differential inputs to the
equalizer. On-chip 50Ω termination resistor connects INB_n+
to VDD and INB_n- to VDD when enabled.
AC coupling required on high-speed I/O
Inverting and non-inverting 50Ω driver outputs with deemphasis. Compatible with AC coupled CML inputs.
AC coupling required on high-speed I/O
Inverting and non-inverting CML differential inputs to the
equalizer. On-chip 50Ω termination resistor connects INA_n+
to VDD and INA_n- to VDD when enabled.
AC coupling required on high-speed I/O
Inverting and non-inverting 50Ω driver outputs with deemphasis. Compatible with AC coupled CML inputs.
AC coupling required on high-speed I/O
Control Pins — Shared (LVCMOS)
ENSMB
48
I, LVCMOS
System Management Bus (SMBus) enable pin
Tie 1kΩ to VDD = Register Access SMBus Slave mode
FLOAT = Read External EEPROM (Master SMBUS Mode)
Tie 1kΩ to GND = Pin Mode
ENSMB = 1 (SMBUS MODE)
SCL
50
I, LVCMOS,
O, OPEN
Drain
ENSMB Master or Slave mode
SMBUS clock input pin is enabled (slave mode).
Clock output when loading EEPROM configuration (master
mode).
SDA
49
I, LVCMOS,
O, OPEN
Drain
ENSMB Master or Slave mode
The SMBus bi-directional SDA pin is enabled. Data input or
open drain (pull-down only) output.
AD0-AD3
54, 53, 47, 46 I, LVCMOS
ENSMB Master or Slave mode
SMBus Slave Address Inputs. In SMBus mode, these pins are
the user set SMBus slave address inputs.
READ_EN
26
I, LVCMOS
When using an External EEPROM, a transition from high to
low starts the load from the external EEPROM
I, 4-LEVEL,
LVCMOS
EQA[1:0] and EQB[1:0] control the level of equalization of the
A/B sides as shown in . The pins are active only when ENSMB
is de-asserted (low). Each of the 4 A/B channels have the
same level unless controlled by the SMBus control registers.
When ENSMB goes high the SMBus registers provide
independent control of each lane. The EQB[1:0] pins are
converted to SMBUS AD2, AD3 inputs. See Table 2:
Equalizer Settings.
ENSMB = 0 (PIN MODE)
EQA0, EQA1
EQB0, EQB1
4
20, 19
46, 47
Copyright © 1999-2012, Texas Instruments Incorporated
DS125BR401
Pin Name
Pin Number
I/O, Type
Pin Description
DEMA0, DEMA1
DEMB0, DEMB1
49, 50
53, 54
I, 4-LEVEL,
LVCMOS
DEMA[1:0] and DEMB[1:0] control the level of de-emphasis
of the A/B sides as shown in . The pins are only active when
ENSMB is de-asserted (low). Each of the 4 A/B channels have
the same level unless controlled by the SMBus control
registers. When ENSMB goes high the SMBus registers
provide independent control of each lane. The DEMA[1:0]
pins are converted to SMBUS SCL/SDA and DEMB[1:0] pins
are converted to AD0, AD1 inputs. See Table 3: Output
Voltage and De-emphasis Settings.
MODE
21
I, 4-LEVEL,
LVCMOS
MODE control pin selects operating modes.
Tie 1kΩ to GND = GEN 1,2 and SAS 1,2
Float = Auto Mode Select (for PCIe and SAS-3)
Tie 20kΩ to GND = SAS-3 and GEN-3 without De-emphasis
Tie 1kΩ to VDD = SAS-3 and GEN-3 with De-emphasis
See Table 6: MODE operation with Pin Control
SD_TH
26
I, 4-LEVEL,
LVCMOS
Controls the internal Signal Detect Threshold.
See Table 5: Signal Detect Threshold Level.
Control Pins — Both Pin and SMBus Modes (LVCMOS)
RXDET
22
I, 4-LEVEL,
LVCMOS
The RXDET pin controls the receiver detect function.
Depending on the input level, a 50Ω or >50KΩ termination to
the power rail is enabled.
See Table 4: RX-Detect Settings .
LPBK
23
I, 4-LEVEL,
LVCMOS
Controls the loopback function
VDD_SEL
PWDN
25
52
I, FLOAT
I, LVCMOS
Tie 1kΩ to GND = Root Complex Loopback (INA_n to
OUTB_n
Float = Normal Operation
Tie 1kΩ to VDD = End-point Loopback (INB_n to OUTA_n)
Controls the internal regulator
Float = 2.5V mode
Tie GND = 3.3V mode
Tie High = Low power - power down
Tie GND = Normal Operation
See Table 4: RX-Detect Settings .
Outputs
ALL_DONE
27
O, LVCMOS
Valid Register Load Status Output
HIGH = External EEPROM load failed
LOW = External EEPROM load passed
VIN
24
Power
In 3.3V mode, feed 3.3V to VIN
In 2.5V mode, leave floating.
VDD
9, 14,36, 41,
51
Power
Power supply pins CML/analog
2.5V mode, connect to 2.5V
3.3V mode, connect 0.1 uF cap to each VDD pin
Power
GND
DAP
Power
Ground pad (DAP - die attach pad).
Notes:
LVCMOS inputs without the “Float” conditions must be driven to a logic low or high at all times or operation is not
guaranteed.
Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%.
For 3.3V mode operation, VIN pin = 3.3V and the "VDD" for the 4-level input is 3.3V.
For 2.5V mode operation, VDD pin = 2.5V and the "VDD" for the 4-level input is 2.5V.
Copyright © 1999-2012, Texas Instruments Incorporated
5
DS125BR401
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for
availability and specifications.
Supply Voltage (VDD - 2.5V)
Supply Voltage (VIN - 3.3V)
LVCMOS Input/Output Voltage
CML Input Voltage
CML Input Current
Junction Temperature
Storage Temperature
Lead Temperature Range Soldering
(4 sec.)
SQA54A Package
Derate SQA54A Package
ESD Rating
HBM, STD - JESD22-A114F
MM, STD - JESD22-A115-A
CDM, STD - JESD22-C101-D
Thermal Resistance
-0.5V to +2.75V
-0.5V to +4.0V
-0.5V to +4.0V
-0.5V to (VDD+0.5)
-30 to +30 mA
125°C
-40°C to +125°C
+260°C
52.6mW/°C above +25°C
5 kV
150 V
1000 V
θJC
11.5°C/W
θJA, No Airflow, 4 layer JEDEC
For soldering specifications: See Application Note SNOA549C: http://www.ti.com/lit/an/snoa549c/snoa549c.pdf
19.1°C/W
Min
2.375
3.0
-40
Supply Voltage (2.5V mode)
Supply Voltgae (3.3V mode)
Ambient Temperature
SMBus (SDA, SCL)
Supply Noise up to 50 MHz
(Note 4)
Symbol
Parameter
Conditions
Typ
2.5
3.3
25
Min
Max
2.625
3.6
+85
3.6
100
Units
V
V
°C
V
mVp-p
Typ
Max
Units
VDD = 2.5 V supply,
EQ Enabled,
VOD = 1.0 Vp-p,
RXDET = 1, PWDN = 0
500
700
mW
VIN = 3.3 V supply,
EQ Enabled,
VOD = 1.0 Vp-p,
RXDET = 1, PWDN = 0
660
900
mW
Power
PD
Power Dissipation
LVCMOS / LVTTL DC Specifications
Vih
High Level Input
Voltage
2.0
3.6
V
Vil
Low Level Input
Voltage
0
0.8
V
Voh
High Level Output
Voltage
(ALL_DONE pin)
Ioh = −4mA
Vol
Low Level Output
Voltage
(ALL_DONE pin)
Iol = 4mA
Iih
Input High Current
(PWDN pin)
VIN = 3.6 V,
LVCMOS = 3.6 V
Input High Current
with internal resistors
(4–level input pin)
6
2.0
V
0.4
V
-15
+15
uA
+20
+150
uA
Copyright © 1999-2012, Texas Instruments Incorporated
DS125BR401
Symbol
Parameter
Conditions
Min
Iil
Input Low Current
(PWDN pin)
VIN = 3.6 V,
LVCMOS = 0 V
Input Low Current
with internal resistors
(4–level input pin)
Typ
Max
Units
-15
+15
uA
-160
-40
uA
CML Receiver Inputs (IN_n+, IN_n-)
RLrx-diff
RX Differential return
loss
0.05 - 7.5 GHz
-15
dB
7.5 - 15 GHz
-5
dB
RLrx-cm
RX Common mode
return loss
0.05 - 5 GHz
-10
dB
Zrx-dc
RX DC common mode Tested at VDD = 2.5 V
impedance
40
50
60
Ω
Zrx-diff-dc
RX DC differntial mode Tested at VDD = 2.5 V
impedance
80
100
120
Ω
Vrx-diff-dc
Differential RX peak to Tested at pins
peak voltage (VID)
0.6
1.0
1.2
V
Vrx-signal-det- Signal detect assert
diff-pp
level for active data
signal
SD_TH = F (float),
0101 pattern at 8 Gbps
180
mVp-p
Vrx-idle-detdiff-pp
SD_TH = F (float),
0101 pattern at 8 Gbps
110
mVp-p
Signal detect deassert level for
electrical idle
Copyright © 1999-2012, Texas Instruments Incorporated
7
DS125BR401
Symbol
Parameter
Conditions
Min
Typ
Max
Units
0.8
1.0
1.2
mVp-p
High Speed Outputs
Vtx-diff-pp
Output Voltage
Differential Swing
Differential measurement
with Out_n+ and OUT_n-,
terminated by 50Ω to GND,
AC-Coupled, VID = 1.0 Vpp,
DEM0 = 1, DEM1 = 0
(Note 7)
Vtx-de-ratio_3.5
TX de-emphasis ratio
VOD = 1.0 Vp-p,
DEM0 = 0, DEM1 = R,
Gen 1 & 2 modes only
−3.5
dB
Vtx-de-ratio_6
TX de-emphasis ratio
VOD = 1.0 Vp-p,
DEM0 = R, DEM1 = R,
Gen 1 & 2 modes only
−6
dB
TTX-HF-DJ-DD
TX Dj > 1.5 MHz
0.15
UI
TTX-HF-DJ-DD
TX RMS jitter < 1.5
MHz
3.0
ps RMS
TTX-RISE-FALL
Transmitter rise/fall
time
20% to 80% of differential
output voltage
TRF-MISMATCH
Transmitter rise/fall
mismatch
20% to 80% of differential
output voltage
0.01
RLTX-DIFF
TX Differential return
loss
0.05 - 7.5 GHz
-15
dB
7.5 - 15 GHz
-5
dB
RLTX-CM
TX Common mode
return loss
0.05 - 5 GHz
-10
dB
ZTX-DIFF-DC
DC differential TX
impedance
100
Ω
VTX-CM-AC-PP
TX AC common mode VOD = 1.0 Vp-p,
voltage
DEM0 = 1, DEM1 = 0
ITX-SHORT
Transmitter short
circuit current limit
VTX-CM-DC-
Absolute delta of DC
common mode voltage
during L0 and
electrical idle
100
mV
VTX-CM-DC-LINE- Absolute delta of DC
common mode voltgae
DELTA
between TX+ and TX-
25
mV
ACTIVE-IDLEDELTA
8
Total current the transmitter
can supply when shorted to
VDD or GND
35
45
ps
0.1
100
20
UI
mVp-p
mA
TTX-IDLE-DATA
Max time to transition
to valid differential
signal after idle
VID = 1.0 Vp-p, 8 Gbps
3.5
ns
TTX-DATA-IDLE
Max time to transition VID = 1.0 Vp-p, 8 Gbps
to idle after differential
signal
6.2
ns
TPDEQ
Differential
propagation delay
EQ = 00, (Note 6)
200
ps
TLSK
Lane to lane skew
T = 25C, VDD = 2.5V
25
ps
TPPSK
Part to part
propagation delay
skew
T = 25C, VDD = 2.5V
40
ps
Copyright © 1999-2012, Texas Instruments Incorporated
DS125BR401
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DJE1
Residual
deterministic jitter at
12 Gbps
30” 5mils FR4,
VID = 0.6 Vp-p,
PRBS15, EQ = 07'h,
DEM = 0 dB
0.18
UI
DJE2
Residual
30” 5mils FR4,
deterministic jitter at 8 VID = 0.6 Vp-p,
Gbps
PRBS15, EQ = 07'h,
DEM = 0 dB
0.11
UI
DJE3
Residual
30” 5mils FR4,
deterministic jitter at 5 VID = 0.6 Vp-p,
Gbps
PRBS15, EQ = 07'h,
DEM = 0 dB
0.07
UI
DJE4
Residual
deterministic jitter at
12 Gbps
5 meters 30 awg cable,
VID = 0.6 Vp-p,
PRBS15, EQ = 07'h,
DEM = 0 dB
0.25
UI
DJE5
Residual
deterministic jitter at
12 Gbps
8 meters 30 awg cable,
VID = 0.6 Vp-p,
PRBS15, EQ = 0F'h,
DEM = 0 dB
0.33
UI
Input Channel: 20" 5mils FR4,
0.1
UI
Equalization
De-emphasis (GEN 1&2 mode only)
DJD1
Residual
deterministic jitter at
12 Gbps
Output Channel: 10” 5mils
FR4,
VID = 0.6 Vp-p,
PRBS15, EQ = 03'h,
VOD = 1.0 Vp-p,
DEM = −3.5 dB,
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions. Absolute Maximum Numbers are guaranteed for a junction temperature range of -40°C to +125°C. Models
are validated to Maximum Operating Voltages only.
Note 2: Typical values represent most likely parametric norms at VDD = 2.5V, TA = 25°C., and at the Recommended Operation Conditions at the time of product
characterization and are not guaranteed.
Note 3: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified or
specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 4: Allowed supply noise (mVp-p sine wave) under typical conditions.
Note 5: Guaranteed by device characterization.
Note 6: Propagation Delay measurements will change slightly based on the level of EQ selected. EQ = 00 will result in the shortest propagation delays.
Note 7: In SAS-3 and PCIe GEN3 mode, the output VOD level is not fixed. It will be adjusted automatically based on the VID input amplitude level. The output
VOD level set by DEMA/B[1:0] in this MODE is dependent on the VID level and the frequency content. The DS125BR401 repeater is designed to be transparent
in this MODE, so the TX-FIR (de-emphasis) is passed to the RX to support the handshake negotiation link training.
Copyright © 1999-2012, Texas Instruments Incorporated
9
DS125BR401
Electrical Characteristics — Serial Management Bus Interface
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
0.8
V
3.6
V
SERIAL BUS INTERFACE DC SPECIFICATIONS
VIL
Data, Clock Input Low Voltage
VIH
Data, Clock Input High Voltage
IPULLUP
Current Through Pull-Up Resistor High Power Specification
or Current Source
VDD
Nominal Bus Voltage
2.375
3.6
V
ILEAK-Bus
Input Leakage Per Bus Segment (Note 8)
-200
+200
µA
ILEAK-Pin
Input Leakage Per Device Pin
CI
Capacitance for SDA and SCL
RTERM
External Termination Resistance Pullup VDD = 3.3V,
pull to VDD = 2.5V ± 5% OR 3.3V (Note 8, Note 9, Note 10)
± 10%
Pullup VDD = 2.5V,
(Note 8, Note 9, Note 10)
2.1
4
mA
-15
(Note 8, Note 9)
µA
10
pF
2000
Ω
1000
Ω
SERIAL BUS INTERFACE TIMING SPECIFICATIONS
FSMB
Bus Operating Frequency
ENSMB = VDD (Slave Mode)
ENSMB = FLOAT (Master Mode)
TBUF
Bus Free Time Between Stop and
Start Condition
THD:STA
Hold time after (Repeated) Start
Condition. After this period, the
first clock is generated.
280
400
400
kHz
520
kHz
1.3
µs
0.6
µs
At IPULLUP, Max
TSU:STA
Repeated Start Condition Setup
Time
0.6
µs
TSU:STO
Stop Condition Setup Time
0.6
µs
THD:DAT
Data Hold Time
0
ns
TSU:DAT
Data Setup Time
100
ns
TLOW
Clock Low Period
THIGH
Clock High Period
(Note 11)
tF
Clock/Data Fall Time
tR
tPOR
1.3
0.6
µs
50
µs
(Note 11)
300
ns
Clock/Data Rise Time
(Note 11)
300
ns
Time in which a device must be
operational after power-on reset
(Note 11, Note 12)
500
ms
Note 8: Recommended value.
Note 9: Recommended maximum capacitance load per bus segment is 400pF.
Note 10: Maximum termination voltage should be identical to the device supply voltage.
Note 11: Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1 SMBus common
AC specifications for details.
Note 12: Guaranteed by Design. Parameter not tested in production.
10
Copyright © 1999-2012, Texas Instruments Incorporated
DS125BR401
Timing Diagrams
30198702
FIGURE 1. CML Output and Rise and FALL Transition Time
30198703
FIGURE 2. Propagation Delay Timing Diagram
30198704
FIGURE 3. Transmit IDLE-DATA and DATA-IDLE Response Time
30198794
FIGURE 4. SMBus Timing Parameters
Copyright © 1999-2012, Texas Instruments Incorporated
11
DS125BR401
Functional Description
The DS125BR401 is a low power media compensation 4 lane repeater optimized for SAS-3. The DS125BR401 compensates for
lossy FR-4 printed circuit board backplanes and balanced cables. The DS125BR401 operates in 3 modes: Pin Control Mode
(ENSMB = 0), SMBus Slave Mode (ENSMB = 1) and SMBus Master Mode (ENSMB = float) to load register informations from
external EEPROM; please refer to SMBUS Master Mode for additional information.
Pin Control Mode:
When in pin mode (ENSMB = 0), equalization and de-emphasis can be selected via pin for each side independently. When deemphasis is asserted VOD is automatically adjusted per the De- Emphasis table below. For PCIe applications, the RXDET pins
provides automatic and manual control for input termination (50Ω or >50KΩ). MODE setting is also pin controllable with pin selections (Gen 1/2, auto detect and SAS-3 / PCIe Gen 3). The receiver electrical idle detect threshold is also adjustable via the SD_TH
pin.
SMBUS Mode:
When in SMBus mode (ENSMB = 1), the VOD (output amplitude), equalization, de-emphasis, and termination disable features are
all programmable on a individual lane basis, instead of grouped by A or B as in the pin mode case. Upon assertion of ENSMB, the
EQx and DEMx functions revert to register control immediately. The EQx and DEMx pins are converted to AD0-AD3 SMBus address
inputs. The other external control pins (MODE, RXDET and SD_TH) remain active unless their respective registers are written to
and the appropriate override bit is set, in which case they are ignored until ENSMB is driven low (pin mode). On power-up and
when ENSMB is driven low all registers are reset to their default state. If PWDN is asserted while ENSMB is high, the registers
retain their current state.
Equalization settings accessible via the pin controls were chosen to meet the needs of most high speed applications. If additional
fine tuning or adjustment is needed, additional equalization settings can be accessed via the SMBus registers. Each input has a
total of 256 possible equalization settings. The tables show the 16 setting when the device is in pin mode. When using SMBus
mode, the equalization, VOD and de- Emphasis levels are set by registers.
The 4-level input pins utilize a resistor divider to help set the 4 valid levels and provide a wider range of control settings when
ENSMB=0. There is an internal 30K pull-up and a 60K pull-down connected to the package pin. These resistors, together with the
external resistor connection combine to achieve the desired voltage level. Using the 1K pull-up, 1K pull-down, no connect, and 20K
pull-down provide the optimal voltage levels for each of the four input states.
Table 1: 4–Level Control Pin Settings
Level
Setting
3.3V Mode
2.5V Mode
0
Tie 1kΩ to GND
0.10 V
0.08 V
R
Tie 20kΩ to GND
1/3 x VIN
1/3 x VDD
Float
Float (leave pin open)
2/3 x VIN
2/3 x VDD
Tie 1kΩ to VIN or VDD
VIN - 0.05 V
VDD - 0.04 V
1
Typical 4-Level Input Thresholds
Level 1 - 2 = 0.2 * VIN or VDD
Level 2 - 3 = 0.5 * VIN or VDD
Level 3 - 4 = 0.8 * VIN or VDD
In order to minimize the startup current associated with the integrated 2.5V regulator the 1K pull-up / pull-down resistors are
recommended. If several 4 level inputs require the same setting, it is possible to combine two or more 1K resistors into a single
lower value resistor. As an example; combining two inputs with a single 500 Ohm resistor is a good way to save board space.
12
Copyright © 1999-2012, Texas Instruments Incorporated
DS125BR401
3.3V or 2.5V Supply Mode Operation
The DS125BR401 has an optional internal voltage regulator to provide the 2.5V supply to the device. In 3.3V mode operation, the
VIN pin = 3.3V is used to supply power to the device. The internal regulator will provide the 2.5V to the VDD pins of the device and
a 0.1 uF cap is needed at each of the 5 VDD pins for power supply de-coupling (total capacitance should be ≤0.5 uF), and the
VDD pins should be left open. The VDD_SEL pin must be tied to GND to enable the internal regulator. In 2.5V mode operation,
the VIN pin should be left open and 2.5V supply must be applied to the 5 VDD pins to power the device. The VDD_SEL pin must
be left open (no connect) to disable the internal regulator.
30198706
FIGURE 5. 3.3V or 2.5V Supply Connection Diagram
Copyright © 1999-2012, Texas Instruments Incorporated
13
DS125BR401
PCIe Signal Integrity
When using the DS125BR401 in PCIe GEN-3 systems, there are specific signal integrity settings to ensure signal integrity margin.
The settings were optimized by extensive testing. Please contact your field representative for more information regarding the testing
completed to achieve these settings.
For tuning the in the downstream direction (from CPU to EP).
• EQ: use the guidelines outlined in table 2.
• De-Emphasis: use the guidelines outlined in table 3.
• VOD: use the guidelines outlined in table 3.
For tuning in the upstream direction (from EP to CPU).
• EQ: use the guidelines outlined in table 2.
• De-Emphasis:
— For trace lengths < 15” set to -3.5 dB
— For trace lengths > 15” set to -6 dB
• VOD: set to 900 mV
Table 2: Equalizer Settings
Level
EQA1
EQB1
EQA0
EQB
EQ – 8 bits [7:0]
dB at
1.5 GHz
dB at
2.5 GHz
dB at
4 GHz
dB at
6 GHz
Suggested Use
1
0
0
0000 0000 = 0x00
2.5
3.5
3.8
3.1
FR4 < 5 inch trace
2
0
R
0000 0001 = 0x01
3.8
5.4
6.7
6.7
FR4 5-10 inch trace
3
0
Float
0000 0010 = 0x02
5.0
7.0
8.4
8.4
FR4 10 inch trace
4
0
1
0000 0011 = 0x03
5.9
8.0
9.3
9.1
FR4 15-20 inch trace
5
R
0
0000 0111 = 0x07
7.4
10.3
12.8
13.7
FR4 20-30 inch trace
6
R
R
0001 0101 = 0x15
6.9
10.2
13.9
16.2
FR4 25-30 inch trace
7
R
Float
0000 1011 = 0x0B
9.0
12.4
15.3
15.9
FR4 25-30 inch trace
8
R
1
0000 1111 = 0x0F
10.2
13.8
16.7
17.0
8m, 30awg cable
> 8m cable
9
Float
0
0101 0101 = 0x55
8.5
12.6
17.5
20.7
10
Float
R
0001 1111 = 0x1F
11.7
16.2
20.3
21.8
11
Float
Float
0010 1111 = 0x2F
13.2
18.3
22.8
23.6
12
Float
1
0011 1111 = 0x3F
14.4
19.8
24.2
24.7
13
1
0
1010 1010 = 0xAA
14.4
20.5
26.4
28.0
14
1
R
0111 1111 = 0x7F
16.0
22.2
27.8
29.2
15
1
Float
1011 1111 = 0xBF
17.6
24.4
30.2
30.9
16
1
1
1111 1111 = 0xFF
18.7
25.8
31.6
31.9
Note: Cable and FR4 lengths are for reference only. FR4 lengths based on a 100 Ohm differential stripline with 5-mil traces and
8-mil trace separation. Optimal EQ setting should be determined via simulation and prototype verification.
14
Copyright © 1999-2012, Texas Instruments Incorporated
DS125BR401
Table 3: Output Voltage and De-emphasis Settings
DEMA0
DEMB0
VOD Vp-p
DEM dB
(see note
below)
Inner Amplitude
Vp-p
Suggested Use
0
0
0.8
0
0.8
FR4
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