DS15MB200
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SNLS196E – NOVEMBER 2005 – REVISED MARCH 2013
DS15MB200 Dual 1.5 Gbps 2:1/1:2 LVDS Mux/Buffer with Pre-Emphasis
Check for Samples: DS15MB200
FEATURES
DESCRIPTION
•
•
The DS15MB200 is a dual-port 2 to 1 multiplexer and
1 to 2 repeater/buffer. High-speed data paths and
flow-through pinout minimize internal device jitter and
simplify board layout, while pre-emphasis overcomes
ISI jitter effects from lossy backplanes and cables.
The differential inputs and outputs interface to LVDS
or Bus LVDS signals such as those on Texas
Instrument's 10-, 16-, and 18-bit Bus LVDS SerDes,
or to CML or LVPECL signals.
1
2
•
•
•
•
•
•
•
•
1.5 Gbps Data Rate Per Channel
Configurable Off/On Pre-emphasis Drives
Lossy Backplanes and Cables
LVDS/BLVDS/CML/LVPECL Compatible Inputs,
LVDS Compatible Outputs
Low Output Skew and Jitter
On-chip 100Ω Input and Output Termination
15 kV ESD Protection on LVDS Inputs/Outputs
Hot Plug Protection
Single 3.3V Supply
Industrial -40 to +85°C Temperature Range
48-pin WQFN Package
The 3.3V supply, CMOS process, and robust I/O
ensure high performance at low power over the entire
industrial -40 to +85°C temperature range.
Switch
Fabric B
Mux Buffer
LVDS
LVDS
Switch
Fabric A
Backplane or Cable
Typical Application
FPGA
or
ASIC
Figure 1.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2013, Texas Instruments Incorporated
DS15MB200
SNLS196E – NOVEMBER 2005 – REVISED MARCH 2013
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Block Diagram
PREA_0
ENA_0
PREB_0
ENB_0
SOA_0
LI_0
SOB_0
PREL_0
ENL_0
SIA_0
LO_0
SIB_0
MUX_S0
Channel 0
Channel 1
Figure 2.
PIN DESCRIPTIONS
Pin
Name
WQFN Pin
Number
I/O, Type
Description
SWITCH SIDE DIFFERENTIAL INPUTS
SIA_0+
SIA_0−
30
29
I, LVDS
Switch A-side Channel 0 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or
LVPECL compatible.
SIA_1+
SIA_1−
19
20
I, LVDS
Switch A-side Channel 1 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or
LVPECL compatible.
SIB_0+
SIB_0−
28
27
I, LVDS
Switch B-side Channel 0 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or
LVPECL compatible.
SIB_1+
SIB_1−
21
22
I, LVDS
Switch B-side Channel 1 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or
LVPECL compatible.
LINE SIDE DIFFERENTIAL INPUTS
LI_0+
LI_0−
40
39
I, LVDS
Line-side Channel 0 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or
LVPECL compatible.
LI_1+
LI_1−
9
10
I, LVDS
Line-side Channel 1 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or
LVPECL compatible.
SWITCH SIDE DIFFERENTIAL OUTPUTS
SOA_0+
SOA_0−
34
33
O, LVDS
Switch A-side Channel 0 inverting and non-inverting differential outputs. LVDS compatible (1) (2).
SOA_1+
SOA_1−
15
16
O, LVDS
Switch A-side Channel 1 inverting and non-inverting differential outputs. LVDS compatible (1) (2).
SOB_0+
SOB_0−
32
31
O, LVDS
Switch B-side Channel 0 inverting and non-inverting differential outputs. LVDS compatible (1) (2).
SOB_1+
SOB_1−
17
18
O, LVDS
Switch B-side Channel 1 inverting and non-inverting differential outputs. LVDS compatible (1) (2).
LINE SIDE DIFFERENTIAL OUTPUTS
LO_0+
LO_0−
42
41
O, LVDS
Line-side Channel 0 inverting and non-inverting differential outputs. LVDS compatible (1) (2).
LO_1+
LO_1−
7
8
O, LVDS
Line-side Channel 1 inverting and non-inverting differential outputs. LVDS compatible (1) (2).
(1)
(2)
2
For interfacing LVDS outputs to CML or LVPECL compatible inputs, refer to the applications section of this datasheet (planned).
The LVDS outputs do not support a multidrop (BLVDS) environment. The LVDS output characteristics of the DS15MB200 device have
been optimized for point-to-point backplane and cable applications.
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PIN DESCRIPTIONS (continued)
Pin
Name
WQFN Pin
Number
I/O, Type
Description
DIGITAL CONTROL INTERFACE
MUX_S0
MUX_S1
38
11
I, LVTTL
Mux Select Control Inputs (per channel) to select which Switch-side input, A or B, is passed through
to the Line-side.
PREA_0
PREA_1
PREB_0
PREB_1
26
23
25
24
I, LVTTL
Output pre-emphasis control for Switch-side outputs. Each output driver on the Switch A-side and Bside has a separate pin to control the pre-emphasis on or off.
PREL_0
PREL_1
44
5
I, LVTTL
Output pre-emphasis control for Line-side outputs. Each output driver on the Line A-side and B-side
has a separate pin to control the pre-emphasis on or off.
ENA_0
ENA_1
ENB_0
ENB_1
36
13
35
14
I, LVTTL
Output Enable Control for Switch A-side and B-side outputs. Each output driver on the A-side and
B-side has a separate enable pin.
ENL_0
ENL_1
45
4
I, LVTTL
Output Enable Control for The Line-side outputs. Each output driver on the Line-side has a separate
enable pin.
VDD
2, 6, 12,
37, 43, 46,
48
I, Power
VDD = 3.3V ±0.3V.
GND
3, 47 (3)
I, Power
Ground reference for LVDS and CMOS circuitry.
For the WQFN package, the DAP is used as the primary GND connection to the device. The DAP is
the exposed metal contact at the bottom of the WQFN-48 package. It should be connected to the
ground plane with at least 4 vias for optimal AC and thermal performance.
POWER
(3)
Note that the DAP on the backside of the WQFN package is the primary GND connection for the device when using the WQFN
package.
VDD
N/C
VDD
GND
1
48
ENL_1
2
PREL_1
N/C
3
VDD
VDD
4
LO-1+
GND
5
LO_1-
ENL_1
6
LI_1+
PREL_1
7
LI_1-
VDD
8
MUX_S1
LO-1+
9
VDD
LO_1-
LI_1-
12 11 10
13
LI_1+
ENA_1
MUX_S1
VDD
Connection Diagrams
VDD
ENA_1
Channel 1
47
15
46
VDD
SOA_1+
VDD
SOA_1-
16
45
ENL_0
SOA_1-
ENL_0
SOB_1+
17
44
PREL_0
SOB_1+
SOB_1-
18
43
VDD
SOB_1-
VDD
SIA_1+
19
42
LO_0+
SIA_1+
LO_0+
SIA_1-
20
41
LO_0-
SIA_1-
LO_0-
SIB_1+
21
40
LI_0+
SIB_1+
LI_0+
SIB_1-
22
39
LI_0-
SIB_1-
LI_0-
PREA_1
23
38
MUX_S0
PREA_1
MUX_S0
PREB_1
37
24
25 26 27 28 29 30 31 32 33 34 35 36
VDD
PREB_1
VDD
Figure 3. WQFN Top View
DAP = GND
ENB_1
GND
PREL_0
ENA_0
ENB_0
SOA_0+
SOA_0-
SOB_0+
SOB_0-
SIA_0+
SIA_0-
SIB_0+
SIB_0-
PREA_0
Channel 0
PREB_0
ENB_0
SOA_0+
SOA_0-
SOB_0+
SOB_0-
SIA_0+
SIA_0-
SIB_0+
SIB_0-
PREA_0
DAP
(GND)
ENA_0
14
SOA_1+
PREB_0
ENB_1
GND
Figure 4. Directional Signal Paths Top View
(Refer to pin names for signal polarity)
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Output Characteristics
The output characteristics of the DS15MB200 have been optimized for point-to-point backplane and cable
applications, and are not intended for multipoint or multidrop signaling.
A 100Ω output (source) termination resistor is incorporated in the device to eliminate the need for an external
resistor, providing excellent drive characteristics by locating the source termination as close to the output as
physically possible.
Pre-Emphasis Controls
The pre-emphasis is used to compensate for long or lossy transmission media. Separate pins are provided for
each output to minimize power consumption. Pre-emphasis is programmable to be off or on per the Preemphasis Control Table.
(1)
PREx_n (1)
Output Pre-Emphasis
0
0%
1
100%
Applies to PREA_0, PREA_1, PREB_0, PREB_1, PREL_0, PREL_1
Multiplexer Truth Table (2) (3)
Data Inputs
(2)
(3)
Control Inputs
Output
SIA_0
SIB_0
MUX_S0
ENL_0
LO_0
X
valid
0
1
SIB_0
valid
X
1
1
SIA_0
X
X
X
0
Z
Same functionality for channel 1
X = Don't Care
Z = High Impedance (TRI-STATE)
Repeater/Buffer Truth Table (1) (2)
Data Input
(1)
(2)
Control Inputs
Outputs
LI_0
ENA_0
ENB_0
SOA_0
SOB_0
X
0
0
Z
Z
valid
0
1
Z
LI_0
valid
1
0
LI_0
Z
valid
1
1
LI_0
LI_0
Same functionality for channel 1
X = Don't Care
Z = High Impedance (TRI-STATE)
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
4
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Absolute Maximum Ratings (1)
Value
Unit
Supply Voltage (VDD)
−0.3 to +4.0
V
CMOS Input Voltage
-0.3 to
(VDD+0.3)
V
-0.3 to
(VDD+0.3)
V
LVDS Receiver Input Voltage
(2)
LVDS Driver Output Voltage
-0.3 to
(VDD+0.3)
V
+40
mA
Junction Temperature
+150
°C
Storage Temperature
−65 to +150
°C
Lead Temperature (Solder, 4sec)
260
°C
Max Pkg Power Capacity @ 25°C
5.2
W
Thermal Resistance (θJA)
24
°C/W
41.7
mW/°C
8
kV
15
kV
250
V
1000
V
LVDS Output Short Circuit Current
Package Derating above +25°C
HBM, 1.5kΩ, 100pF
LVDS pins to GND only
ESD Last Passing Voltage
EIAJ, 0Ω, 200pF
CDM
(1)
(2)
Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met,
without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables.
Texas Instruments does not recommend operation of products outside of recommended operation conditions.
VID max < 2.4V
Recommended Operating Conditions
Min
Supply Voltage (VCC)
Input Voltage (VI) (1)
Output Voltage (VO)
Operating Temperature (TA) Industrial
(1)
Max
Unit
3.0
3.6
V
0
VCC
V
0
VCC
V
−40
+85
°C
VID max < 2.4V
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Electrical Characteristics
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
Min
Typ (1)
Max
Units
V
LVTTL DC SPECIFICATIONS (MUX_Sn, PREA_n, PREB_n, PREL_n, ENA_n, ENB_n, ENL_n)
VIH
High Level Input Voltage
2.0
VDD
VIL
Low Level Input Voltage
GND
0.8
V
IIH
High Level Input Current
VIN = VDD = VDDMAX
−10
+10
µA
IIHR
High Level Input Current
PREA_n, PREB_n, PREL_n
40
200
µA
IIL
Low Level Input Current
VIN = VSS, VDD = VDDMAX
−10
+10
µA
CIN1
Input Capacitance
Any Digital Input Pin to VSS
COUT1
Output Capacitance
Any Digital Output Pin to VSS
VCL
Input Clamp Voltage
ICL = −18 mA
−1.5
2.0
pF
4.0
pF
−0.8
V
LVDS INPUT DC SPECIFICATIONS (SIA±, SIB±, LI±)
Differential Input High Threshold (2)
VTH
(2)
VCM = 0.8V or 1.2V or 3.55V,
VDD = 3.6V
0
VCM = 0.8V or 1.2V or 3.55V,
VDD = 3.6V
100
mV
VTL
Differential Input Low Threshold
VID
Differential Input Voltage
VCM = 0.8V to 3.55V, VDD = 3.6V
100
2400
VCMR
Common Mode Voltage Range
VID = 150 mV, VDD = 3.6V
0.05
3.55
CIN2
Input Capacitance
IN+ or IN− to VSS
IIN
Input Current
VIN = 3.6V, VDD = VDDMAX or 0V
−15
+15
µA
VIN = 0V, VDD = VDDMAX or 0V
−15
+15
µA
500
mV
35
mV
1.475
V
35
mV
-40
mA
−100
0
mV
2.0
mV
V
pF
LVDS OUTPUT DC SPECIFICATIONS (SOA_n±, SOB_n±, LO_n±)
VOD
Differential Output Voltage,
0% Pre-emphasis (2)
RL is the internal 100Ω between OUT+
and OUT−
ΔVOD
Change in VOD between
Complementary States
-35
VOS
Offset Voltage (3)
1.05
ΔVOS
Change in VOS between
Complementary States
-35
IOS
Output Short Circuit Current
OUT+ or OUT− Short to GND
−21
COUT2
Output Capacitance
OUT+ or OUT− to GND when TRISTATE
4.0
All inputs and outputs enabled and
active, terminated with external load of
100Ω between OUT+ and OUT-.
225
275
mA
ENA_0 = ENB_0 = ENL_0 = ENA_1 =
ENB_1 = ENL_1 = L
0.6
4.0
mA
170
250
ps
170
250
ps
1.0
2.5
ns
1.0
2.5
ns
250
360
1.22
pF
SUPPLY CURRENT (Static)
ICC
Supply Current
ICCZ
Supply Current - Powerdown Mode
SWITCHING CHARACTERISTICS—LVDS OUTPUTS
tLHT
Differential Low to High Transition
Time
tHLT
Differential High to Low Transition
Time
tPLHD
Differential Low to High Propagation
Delay
tPHLD
Differential High to Low Propagation
Delay
tSKD1
Pulse Skew
|tPLHD–tPHLD| (4)
25
75
ps
tSKCC
Output Channel to Channel Skew
Difference in propagation delay (tPLHD or
tPHLD) among all output channels. (4)
50
115
ps
(1)
(2)
(3)
(4)
6
Use an alternating 1 and 0 pattern at 200
Mb/s, measure between 20% and 80% of
VOD. (4)
Use an alternating 1 and 0 pattern at 200
Mb/s, measure at 50% VOD between
input to output.
Typical parameters are measured at VDD = 3.3V, TA = 25°C. They are for reference purposes, and are not production-tested.
Differential output voltage VOD is defined as ABS(OUT+–OUT−). Differential input voltage VID is defined as ABS(IN+–IN−).
Output offset voltage VOS is defined as the average of the LVDS single-ended output voltages at logic high and logic low states.
Not production tested. Guaranteed by statistical analysis on a sample basis at the time of characterization.
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Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless other specified.
Symbol
tJIT
Parameter
Jitter (0% Pre-emphasis)
Conditions
(5)
RJ - Alternating 1 and 0 at 750MHz
Min
(6)
Typ (1)
Max
Units
1.1
1.5
psrms
DJ - K28.5 Pattern, 1.5 Gbps (7)
20
34
psp-p
TJ - PRBS 27-1 Pattern, 1.5 Gbps (8)
14
28
psp-p
tON
LVDS Output Enable Time
Time from ENA_n, ENB_n, or ENL_n to
OUT± change from TRI-STATE to active.
0.5
1.5
µs
tON2
LVDS Output Enable Time from
Powerdown Mode
Time from ENA_n, ENB_n, or ENL_n to
OUT± change from Powerdown Mode to
active.
10
20
µs
LVDS Output Disable Time
Time from ENA_n, ENB_n, or ENL_n to
OUT± change from active to TRI-STATE
or Powerdown mode.
12
ns
tOFF
(5)
(6)
(7)
(8)
Jitter is not production tested, but guaranteed through characterization on a sample basis.
Random Jitter, or RJ, is measured RMS with a histogram including 1500 histogram window hits. The input voltage = VID = 500mV, 50%
duty cycle at 750MHz, tr = tf = 50ps (20% to 80%).
Deterministic Jitter, or DJ, is measured to a histogram mean with a sample size of 350 hits. Stimulus and fixture jitter have been
subtracted. The input voltage = VID = 500mV, K28.5 pattern at 1.5 Gbps, tr = tf = 50ps (20% to 80%). The K28.5 pattern is repeating bit
streams of (0011111010 1100000101).
Total Jitter, or TJ, is measured peak to peak with a histogram including 3500 window hits. Stimulus and fixture jitter have been
subtracted. The input voltage = VID = 500mV, 27-1 PRBS pattern at 1.5 Gbps, tr = tf = 50ps (20% to 80%).
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WQFN Performance Characteristics
Power Supply Current vs. Bit Data Rate
300
250
200
Total Jitter vs. Bit Data Rate
60
50
PRE-EMPHASIS ON
TOTAL JITTER (ps)
POWER SUPPLY CURRENT (mA)
350
PRE-EMPHASIS OFF
150
100
40
30
VCM = 1.2V
20
VCM = 0.25V
10
50
VCM = 3.0V
0
0
0
500
1000
2000
1500
0
500
BIT DATA RATE (Mbps)
1000
1500
2000
BIT DATA RATE (Mbps)
Total Jitter measured at 0V differential while running a PRBS 27-1
pattern with one channel active, all other channels are disabled.
VDD = 3.3V, TA = +25°C, VID = 0.5V, pre-emphasis off.
Dynamic power supply current was measured with all channels
active and toggling at the bit data rate. Data pattern has no effect
on the power consumption.
VDD = 3.3V, TA = +25°C, VID = 0.5V, VCM = 1.2V
Figure 5.
Figure 6.
Total Jitter vs. Temperature
30
TOTAL JITTER (ps)
25
20
15
10
5
0
-40
0
-20
20
40
60
80
100
TEMPERATURE (°C)
7
Total Jitter measured at 0V differential while running a PRBS 2 -1 pattern with one channel active, all other channels are disabled. VDD =
3.3V, VID = 0.5V, VCM = 1.2V, 1.5 Gbps data rate, pre-emphasis off.
Figure 7.
8
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TRI-STATE AND POWERDOWN MODES
The DS15MB200 has output enable control on each of the six onboard LVDS output drivers. This control allows
each output individually to be placed in a low power TRI-STATE mode while the device remains active, and is
useful to reduce power consumption on unused channels. In TRI-STATE mode, some outputs may remain active
while some are in TRI-STATE.
When all six of the output enables (all drivers on both channels) are deasserted (LOW), then the device enters a
Powerdown mode that consumes only 0.5mA (typical) of supply current. In this mode, the entire device is
essentially powered off, including all receiver inputs, output drivers and internal bandgap reference generators.
When returning to active mode from Powerdown mode, there is a delay until valid data is presented at the
outputs because of the ramp to power up the internal bandgap reference generators.
Any single output enable that remains active will hold the device in active mode even if the other five outputs are
in TRI-STATE.
When in Powerdown mode, any output enable that becomes active will wake up the device back into active
mode, even if the other five outputs are in TRI-STATE.
Input Failsafe Biasing
External pull up and pull down resistors may be used to provide enough of an offset to enable an input failsafe
under open-circuit conditions. This configuration ties the positive LVDS input pin to VDD thru a pull up resistor
and the negative LVDS input pin is tied to GND by a pull down resistor. The pull up and pull down resistors
should be in the 5kΩ to 15kΩ range to minimize loading and waveform distortion to the driver. The commonmode bias point ideally should be set to approximately 1.2V (less than 1.75V) to be compatible with the internal
circuitry. Please refer to application note AN-1194, “Failsafe Biasing of LVDS Interfaces” (SNLA051) for more
information.
Interfacing LVPECL to LVDS
An LVPECL driver consists of a differential pair with coupled emitters connected to GND via a current source.
This drives a pair of emitter-followers that require a 50 ohm to VCC-2.0 load. A modern LVPECL driver will
typically include the termination scheme within the device for the emitter follower. If the driver does not include
the load, then an external scheme must be used. The 1.3 V supply is usually not readily available on a PCB,
therefore, a load scheme without a unique power supply requirement may be used.
50:
15MB200
LVPECL
50:
R1
150:
R2
150:
Figure 8. DC Coupled LVPECL to LVDS Interface
Figure 8 is a separated π termination scheme for a 3.3 V LVPECL driver. R1 and R2 provides proper DC load for
the driver emitter followers, and may be included as part of the driver device (1). The DS15MB200 includes a 100
ohm input termination for the transmission line. The common mode voltage will be at the normal LVPECL
levels – around 2 V. This scheme works well with LVDS receivers that have rail-to-rail common mode voltage,
VCM, range. Most Texas Instrument's LVDS receivers have wide VCM range. The exceptions are noted in devices’
respective datasheets. Those LVDS devices that do have a wide VCM range do not vary in performance
significantly when receiving a signal with a common mode other than standard LVDS VCM of 1.2 V.
(1)
The bias networks shown above for LVPECL drivers and receivers may or may not be present within the driver device. The LVPECL
driver and receiver specification must be reviewed closely to ensure compatibility between the driver and receiver terminations and
common mode operating ranges.
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0.1 PF
50:
15MB200
LVPECL
50:
R1
150:
0.1 PF
R2
150:
Figure 9. AC Coupled LVPECL to LVDS Interface
An AC coupled interface is preferred when transmitter and receiver ground references differ more than 1 V. This
is a likely scenario when transmitter and receiver devices are on separate PCBs. Figure 9 illustrates an AC
coupled interface between a LVPECL driver and LVDS receiver. R1 and R2, if not present in the driver device(2),
provide DC load for the emitter followers and may range between 140-220 ohms for most LVPECL devices for
this particular configuration. The DS15MB200 includes an internal 100 ohm resistor to terminate the transmission
line for minimal reflections. The signal after AC coupling capacitors will swing around a level set by internal
biasing resistors (i.e. fail-safe) which is either VDD/2 or 0 V depending on the actual failsafe implementation. If
internal biasing is not implemented, the signal common mode voltage will slowly wander to GND level.
Interfacing LVDS to LVPECL
An LVDS driver consists of a current source (nominal 3.5mA) which drives a CMOS differential pair. It needs a
differential resistive load in the range of 70 to 130 ohms to generate LVDS levels. In a system, the load should
be selected to match transmission line characteristic differential impedance so that the line is properly
terminated. The termination resistor should be placed as close to the receiver inputs as possible. When
interfacing an LVDS driver with a non-LVDS receiver, one only needs to bias the LVDS signal so that it is within
the common mode range of the receiver. This may be done by using separate biasing voltage which demands
another power supply. Some receivers have required biasing voltage available on-chip (VT, VTT or VBB).
50:
LVPECL
15MB200
50:
R1
50:
R2
50:
VT
Figure 10. DC Coupled LVDS to LVPECL Interface
Figure 10 illustrates interface between an LVDS driver and a LVPECL with a VT pin available. R1 and R2, if not
present in the receiver (2), provide proper resistive load for the driver and termination for the transmission line,
and VT sets desired bias for the receiver.
(2)
10
The bias networks shown above for LVPECL drivers and receivers may or may not be present within the driver device. The LVPECL
driver and receiver specification must be reviewed closely to ensure compatibility between the driver and receiver terminations and
common mode operating ranges.
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Product Folder Links: DS15MB200
DS15MB200
www.ti.com
SNLS196E – NOVEMBER 2005 – REVISED MARCH 2013
VDD
0.1 PF
R1
83:
R2
83:
50:
LVPECL
15MB200
50:
0.1 PF
R3
130:
R4
130:
Figure 11. AC Coupled LVDS to LVPECL Interface
Figure 11 illustrates AC coupled interface between an LVDS driver and LVPECL receiver without a VT pin
available. The resistors R1, R2, R3, and R4, if not present in the receiver (2), provide a load for the driver,
terminate the transmission line, and bias the signal for the receiver.
Packaging Information
The Leadless Leadframe Package (WQFN) is a leadframe based chip scale package (CSP) that may enhance
chip speed, reduce thermal impedance, and reduce the printed circuit board area required for mounting. The
small size and very low profile make this package ideal for high density PCBs used in small-scale electronic
applications such as cellular phones, pagers, and handheld PDAs. The WQFN package is offered in the no
Pullback configuration. In the no Pullback configuration the standard solder pads extend and terminate at the
edge of the package. This feature offers a visible solder fillet after board mounting.
The WQFN has the following advantages:
• Low thermal resistance
• Reduced electrical parasitics
• Improved board space efficiency
• Reduced package height
• Reduced package mass
For more details about WQFN packaging technology, refer to applications note AN-1187, "Leadless Leadframe
Package" (SNOA401).
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Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: DS15MB200
11
DS15MB200
SNLS196E – NOVEMBER 2005 – REVISED MARCH 2013
www.ti.com
REVISION HISTORY
Changes from Revision D (March 2013) to Revision E
•
12
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 11
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Product Folder Links: DS15MB200
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
DS15MB200TSQ/NOPB
ACTIVE
WQFN
RHS
48
250
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
15M200
DS15MB200TSQX/NOPB
ACTIVE
WQFN
RHS
48
2500
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
15M200
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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