DS25MB200
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SNLS220G – MARCH 2006 – REVISED APRIL 2013
DS25MB200 Dual 2.5 Gbps 2:1/1:2 CML Mux/Buffer with Transmit Pre-Emphasis and
Receive Equalization
Check for Samples: DS25MB200
FEATURES
DESCRIPTION
•
•
•
•
The DS25MB200 is a dual signal conditioning 2:1
multiplexer and 1:2 fan-out buffer designed for use in
backplane
redundancy
applications.
Signal
conditioning features include input equalization and
programmable output pre-emphasis that enable data
communication in FR4 backplanes up to 2.5 Gbps.
Each input stage has a fixed equalizer to reduce ISI
distortion from board traces. All output drivers have 4
selectable steps of pre-emphasis to compensate for
transmission losses from long FR4 backplanes and
reduce deterministic jitter. The pre-emphasis levels
can be independently controlled for the line-side and
switch-side drivers. The internal loopback paths from
switch-side input to switch-side output enable atspeed system testing. All receiver inputs are internally
terminated with 100Ω differential terminating
resistors. All drivers are internally terminated with
50Ω to VCC.
1
2
•
•
•
•
•
•
0.6–2.5 Gbps Low Jitter Operation
Fixed Input Equalization
Programmable Output Pre-Emphasis
Independent Switch and Line Side PreEmphasis Controls
Programmable Switch-Side Loopback Modes
On-Chip Terminations
HBM ESD Rating 6 kV on All Pins
+3.3V Supply
Lead-Less WQFN-48 Package (7mm x 7mm x
0.8mm, 0.5mm Pitch)
-40°C to +85°C Operating Temperature Range
APPLICATIONS
•
•
Backplane or Cable Driver
Redundancy and Signal Conditioning
Applications
Functional Block Diagram
Switch Side
Line Side
LO_0 ±
MUX_S0
EQ
SIA_0 ±
EQ
SIB_0 ±
PRE_L
LB0A
Port 0
SOA_0 ±
PRE_S
LI_0 ±
SOB_0 ±
EQ
PRE_S
LB0B
LO_1 ±
EQ
SIA_1 ±
EQ
SIB_1 ±
PRE_L
MUX_S1
LB1A
Port 1
SOA_1 ±
PRE_S
LI_1 ±
SOB_1 ±
EQ
PRE_S
LB1B
PreL_0
PreL_1
PreS_0
PreS_1
Pre-emphasis
Control
PRE_L
VCC
PRE_S
GND
RSV
All CML inputs and outputs must be AC coupled for optimal performance.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated
DS25MB200
SNLS220G – MARCH 2006 – REVISED APRIL 2013
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Simplified Block Diagram
DS25MB200
VCC
1.5V
50
50
SIA_0+
50
50
LO_0+
LO_0-
Input stage
+EQ
M
U
X
CML
driver
SIA_0-
SIB_0+
Input stage
+EQ
SIB_0-
PRE_L
50
50
1.5V
MUX_S0
VCC
PORT 0
LB0A
PRE_S
LB0B
50
50
SOA_0+
2
M
U
X
LI_0+
2
Input stage
+EQ
LI_0-
CML
driver
SOA_0-
SOB_0+
2
50
50
1.5V
M
U
X
2
CML
driver
SOB_0-
50
PRE_S
PreL_0
50
VCC
PRE_L
PreL_1
PreS_0
Pre-emphasis
Control
PRE_S
1.5V
PreS_1
50
50
SIA_1+
VCC
Input stage
+EQ
50
LO_1+
LO_1-
SIA_1-
50
M
U
X
CML
driver
SIB_1+
Input stage
+EQ
PRE_L
SIB_1-
50
50
1.5V
MUX_S1
VCC
PORT 1
LB1A
PRE_S
LB1B
50
50
SOA_1+
2
LI_1+
2
Input stage
+EQ
LI_1-
M
U
X
CML
driver
M
U
X
CML
driver
SOA_1-
2
50
50
1.5V
2
SOB_1+
SOB_150
50
PRE_S
VCC pins
2
GND pins
and DAP
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LB0A
SOA_0+
SOA_0-
VCC
SIB_0+
SIB_0-
GND
SIA_0+
SIA_0-
VCC
MUX_S0
44
43
42
41
40
39
38
37
36
PreS0
35
VCC
3
34
LO_0-
SOB_0+
4
33
LO_0+
GND
5
32
GND
LI_0+
6
31
LI_1-
LI_0-
7
30
LI_1+
VCC
8
29
VCC
LO_1+
9
28
SOB_1+
LO_1-
10
27
SOB_1-
GND
11
26
RSV
PreL0
12
25
PreS1
DAP = GND
16
17
18
19
20
21
22
23
24
SOA_1-
SOA_1+
LB1A
LB1B
15
VCC
14
SIB_1+
13
SIB_1-
WQFN-48
Top View Shown
GND
SOB_0-
45
SIA_1+
2
46
SIA_1-
VCC
47
VCC
1
48
MUX_S1
PreL1
LB0B
Connection Diagram
Figure 1. 48 Pin (Top View)
See Package Number NJU0048D
PIN DESCRIPTIONS (1)
Pin Name
Pin Number
I/O
(2)
Description
LINE SIDE HIGH SPEED DIFFERENTIAL IO's
LI_0+
LI_0−
6
7
I
Inverting and non-inverting differential inputs of port_0 at the line side. LI_0+ and LI_0− have an
internal 50Ω connected to an internal reference voltage. See Figure 7.
LO_0+
LO_0−
33
34
O
Inverting and non-inverting differential outputs of port_0 at the line side. LO_0+ and LO_0− have an
internal 50Ω connected to VCC.
LI_1+
LI_1−
30
31
I
Inverting and non-inverting differential inputs of port_1 at the line side. LI_1+ and LI_1− have an
internal 50Ω connected to an internal reference voltage. See Figure 7.
LO_1+
LO_1−
9
10
O
Inverting and non-inverting differential outputs of port_1 at the line side. LO_1+ and LO_1− have an
internal 50Ω connected to VCC.
SWITCH SIDE HIGH SPEED DIFFERENTIAL IO's
SOA_0+
SOA_0−
46
45
O
Inverting and non-inverting differential outputs of mux_0 at the switch_A side. SOA_0+ and SOA_0−
have an internal 50Ω connected to VCC.
SOB_0+
SOB_0−
4
3
O
Inverting and non-inverting differential outputs of mux_0 at the switch_B side. SOB_0+ and SOB_0−
have an internal 50Ω connected to VCC.
SIA_0+
SIA_0−
40
39
I
Inverting and non-inverting differential inputs to the mux_0 at the switch_A side. SIA_0+ and SIA_0−
have an internal 50Ω connected to an internal reference voltage. See Figure 7.
SIB_0+
SIB_0−
43
42
I
Inverting and non-inverting differential inputs to the mux_0 at the switch_B side. SIB_0+ and SIB_0−
have an internal 50Ω connected to an internal reference voltage. See Figure 7.
(1)
(2)
All CML Inputs or Outputs must be AC coupled.
I = Input, O = Output, P = Power
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PIN DESCRIPTIONS(1) (continued)
Pin Number
I/O (2)
SOA_1+
SOA_1−
22
21
O
Inverting and non-inverting differential outputs of mux_1 at the switch_A side. SOA_1+ and SOA_1−
have an internal 50Ω connected to VCC.
SOB_1+
SOB_1−
28
27
O
Inverting and non-inverting differential outputs of mux_1 at the switch_B side. SOB_1+ and SOB_1−
have an internal 50Ω connected to VCC.
SIA_1+
SIA_1−
16
15
I
Inverting and non-inverting differential inputs to the mux_1 at the switch_A side. SIA_1+ and SIA_1−
have an internal 50Ω connected to an internal reference voltage. See Figure 7.
SIB_1+
SIB_1−
19
18
I
Inverting and non-inverting differential inputs to the mux_1 at the switch_B side. SIB_1+ and SIB_1−
have an internal 50Ω connected to an internal reference voltage. See Figure 7.
Pin Name
Description
CONTROL (3.3V LVCMOS)
MUX_S0
37
I
A logic low at MUX_S0 selects mux_0 to switch B. MUX_S0 is internally pulled high. Default state for
mux_0 is switch A.
MUX_S1
13
I
A logic low at MUX_S1 selects mux_1 to switch B. MUX_S0 is internally pulled high. Default state for
mux_1 is switch A.
PREL_0
PREL_1
12
1
I
PREL_0 and PREL_1 select the output pre-emphasis of the line side drivers (LO_0± and LO_1±).
PREL_0 and PREL_1 are internally pulled high. See Table 3 for line side pre-emphasis levels.
PRES_0
PRES_1
36
25
I
PRES_0 and PRES_1 select the output pre-emphasis of the switch side drivers (SOA_0±, SOB_0±,
SOA_1± and SOB_1±). PRES_0 and PRES_1 are internally pulled high. See Table 4 for switch side
pre-emphasis levels.
LB0A
47
I
A logic low at LB0A enables the internal loopback path from SIA_0± to SOA_0±. LB0A is internally
pulled high.
LB0B
48
I
A logic low at LB0B enables the internal loopback path from SIB_0± to SOB_0±. LB0B is internally
pulled high.
LB1A
23
I
A logic low at LB1A enables the internal loopback path from SIA_1± to SOA_1±. LB1A is internally
pulled high.
LB1B
24
I
A logic low at LB1B enables the internal loopback path from SIB_1± to SOB_1±. LB1B is internally
pulled high.
RSV
26
I
Reserve pin to support factory testing. This pin can be left open, or tied to GND, or tied to GND
through an external pull-down resistor.
VCC
2, 8, 14, 20,
29, 35, 38,
44
P
VCC = 3.3V ± 5%.
Each VCC pin should be connected to the VCC plane through a low inductance path, typically with a
via located as close as possible to the landing pad of the VCC pin.
It is recommended to have a 0.01 μF or 0.1 μF, X7R, size-0402 bypass capacitor from each VCC pin
to ground plane.
GND
5, 11, 17, 32,
41
P
Ground reference. Each ground pin should be connected to the ground plane through a low
inductance path, typically with a via located as close as possible to the landing pad of the GND pin.
GND
DAP
P
Die Attach Pad (DAP) is the metal contact at the bottom side, located at the center of the WQFN-48
package. It should be connected to the GND plane with at least 4 via to lower the ground impedance
and improve the thermal performance of the package.
POWER
Functional Description
The DS25MB200 is a signal conditioning 2:1 multiplexer and a 1:2 buffer designed to support port redundancy up
to 2.5 Gbps. The high speed inputs are self-biased to about 1.3V and are designed for AC coupling. See
Figure 7 for details. The inputs are compatible to most AC coupling differential signals such as LVDS, LVPECL
and CML. The DS25MB200 is not designed to operate with data rates below 250 Mbps or with a DC bias applied
to the CML inputs or outputs. Most high speed links are encoded for DC balance and have been defined to
include AC coupling capacitors allowing the DS25MB200 to be directly inserted into the datapath without any
limitation. The ideal AC coupling capacitor value is often based on the lowest frequency component embedded
within the serial link. A typical AC coupling capacitor value ranges between 100 and 1000nF. Some
specifications with scrambled data may require a larger capacitor for optimal performance. To reduce unwanted
parasitics around and within the AC coupling capacitor, a body size of 0402 is recommended. Figure 6 shows the
AC coupling capacitor placement in an AC test circuit.
4
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Each input stage has a fixed equalizer that provides equalization to compensate about 5 dB of transmission loss
from a short backplane trace (about 10 inches backplane). The output driver has Pre-emphasis (driver-side
equalization) to compensate the transmission loss of the backplane that it is driving. The driver conditions the
output signal such that the lower frequency and higher frequency pulses reach approximately the same
amplitude at the end of the backplane, and minimize the deterministic jitter caused by the amplitude disparity.
The DS25MB200 provides four steps of user-selectable Pre-emphasis ranging from 0, -3, -6 and –9 dB to handle
different lengths of backplane. Figure 2 shows a driver Pre-emphasis waveform. The Pre-emphasis duration is
188ps nominal, corresponds to 0.47 bit-width at 2.5 Gbps. The Pre-emphasis levels of switch-side and line-side
can be individually programmed.
Table 1. LOGIC TABLE FOR MULTIPLEX CONTROLS
MUX_S0
Mux Function
0
MUX_0 select switch_B input, SIB_0±.
1 (default)
MUX_0 select switch_A input, SIA_0±.
MUX_S1
Mux Function
0
MUX_1 select switch_B input, SIB_1±.
1 (default)
MUX_1 select switch_A input, SIA_0±.
LB0A
Loopback Function
0
Enable loopback from SIA_0± to SOA_0±.
1 (default)
Normal mode. Loopback disabled.
LB0B
Loopback Function
0
Enable loopback from SIB_0± to SOB_0±.
1 (default)
Normal mode. Loopback disabled.
LB1A
Loopback Function
0
Enable loopback from SIA_1± to SOA_1±.
1 (default)
Normal mode. Loopback disabled.
LB1B
Loopback Function
0
Enable loopback from SIB_1± to SOB_1±.
1 (default)
Normal mode. Loopback disabled.
Table 2. LOGIC TABLE FOR LOOPBACK CONTROLS
Table 3. LINE-SIDE PRE-EMPHASIS CONTROLS
PreL_[1:0]
Pre-Emphasis Level in mVPP
(VODB)
De-Emphasis Level in
mVPP (VODPE)
Pre-Emphasis in dB
(VODPE/VODB)
Typical FR4 board
trace
00
1200
1200
0
10 inches
01
1200
849.53
−3
20 inches
10
1200
600
−6
30 inches
1 1 (default)
1200
425.78
−9
40 inches
Table 4. SWITCH-SIDE PRE-EMPHASIS CONTROLS
PreS_[1:0]
Pre-Emphasis Level in mVPP
(VODB)
De-Emphasis Level in
mVPP (VODPE)
Pre-Emphasis in dB
(VODPE/VODB)
Typical FR4 board
trace
00
1200
1200
0
10 inches
01
1200
849.53
−3
20 inches
10
1200
600
−6
30 inches
1 1 (default)
1200
425.78
−9
40 inches
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1 to N bits
1-bit
1 to N bits
0 dB
-3 dB
-6 dB
VODB
-9 dB
VODPE3
0V
VODPE2
VODPE1
Figure 2. Driver Pre-Emphasis Differential Waveform (showing all 4 pre-emphasis steps)
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2)
−0.3V to 4V
Supply Voltage (VCC)
CMOS/TTL Input Voltage
−0.3V to (VCC +0.3V)
CML Input/Output Voltage
−0.3V to (VCC +0.3V)
Junction Temperature
+150°C
Storage Temperature
−65°C to +150°C
Lead Temperature
Soldering, 4 sec
+260°C
Thermal Resistance, θJA
33.7°C/W
Thermal Resistance, θJC-top
20.7°C/W
Thermal Resistance, θJC-bottom
5.8°C/W
Thermal Resistance, ΦJB
18.2°C/W
ESD Rating HBM, 1.5 kΩ, 100 pF
(1)
(2)
6 kV
Absolute Maximum Ratings are the ratings beyond which the safety of the device cannot be ensured. They are not meant to imply that
the device should be operated at these limits.
If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
Recommended Operating Ratings
Supply Voltage (VCC-GND)
Min
Typ
Max
3.135
3.3
3.465
V
50
mVPP
85
°C
100
°C
Supply Noise Amplitude (10 Hz to 2 GHz)
Ambient Temperature
–40
Case Temperature
6
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Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Parameter
Test Conditions
Min
Typ (1)
Max
Units
LVCMOS DC SPECIFICATIONS
VIH
High Level Input
Voltage
2.0
VCC +0.3
V
VIL
Low Level Input
Voltage
−0.3
0.8
V
IIH
High Level Input
Current
VIN = VCC
−10
10
µA
IIL
Low Level Input
Current
VIN = GND
75
124
µA
RPU
Pull-High Resistance
94
35
kΩ
RECEIVER SPECIFICATIONS
VID
Differential Input
Voltage Range
AC Coupled Differential Signal
Below 1.25 Gbps
Above 1.25 Gbps
Measured at input pins.
VICM
Common Mode Voltage Measured at receiver inputs reference to ground.
at Receiver Inputs
RITD
Input Differential
Termination
On-chip differential termination between IN+ or IN−.
100
100
1750
1560
mVP-P
mVP-P
1.5
V
84
100
116
Ω
1000
1200
1400
mVP-P
DRIVER SPECIFICATIONS
VODB
VPE
tPE
Output Differential
Voltage Swing without
Pre-Emphasis
RL = 100Ω ±1%
PRES_1=PRES_0=0
PREL_1=PREL_0=0
Driver pre-emphasis disabled.
Running K28.7 pattern at 2.5 Gbps.
See Figure 6 for test circuit.
Output Pre-Emphasis
Voltage Ratio
20*log(VODPE/VODB)
RL = 100Ω ±1%
Running K28.7 pattern at 2.5 Gbps
PREx_[1:0]=00
PREx_[1:0]=01
PREx_[1:0]=10
PREx_[1:0]=11
x=S for switch side pre-emphasis control
x=L for line side pre-emphasis control
See Figure 2 on waveform.
See Figure 6 for test circuit.
Pre-Emphasis Width
Tested at −9 dB pre-emphasis level, PREx[1:0]=11
x=S for switch side pre-emphasis control
x=L for line side pre-emphasis control
See Figure 5 on measurement condition.
125
188
400
ps
42
50
58
Ω
ROTSE
Output Termination
On-chip termination from OUT+ or OUT− to VCC
ROTD
Output Differential
Termination
On-chip differential termination between OUT+ and
OUT−
ΔROTSE
Mis-Match in Output
Termination Resistors
Mis-match in output terminations at OUT+ and
OUT−
VOCM
Output Common Mode
Voltage
0
−3
−6
−9
dB
dB
dB
dB
Ω
100
2.4
5
%
2.9
V
1
W
POWER DISSIPATION
PD
(1)
Power Dissipation
VDD = 3.465V
All outputs terminated by 100Ω ±1%.
PREL_[1:0]=0, PRES_[1:0]=0
Running PRBS 27-1 pattern at 2.5 Gbps
Typical parameters measured at VCC = 3.3V, TA = 25°C. They are for reference purposes and are not production-tested.
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Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Parameter
Test Conditions
Min
Typ (1)
Max
Units
AC CHARACTERISTICS
tR
Differential Low to High Measured with a clock-like pattern at 100 MHz,
Transition Time
between 20% and 80% of the differential output
voltage. Pre-emphasis disabled.
Differential High to Low
Transition time is measured with fixture as shown in
Transition Time
Figure 6, adjusted to reflect the transition time at
the output pins.
tF
80
ps
80
ps
tPLH
Differential Low to High Measured at 50% differential voltage from input to
Propagation Delay
output.
0.5
2
ns
tPHL
Differential High to Low
Propagation Delay
0.5
2
ns
tSKP
Pulse Skew
|tPHL–tPLH|
20
ps
Difference in propagation delay between two
outputs in the same device.
200
ps
Difference in propagation delay between the same
output from devices operating under identical
conditions.
500
ps
6
ns
2
2
psrms
psrms
(2)
tSKO
Output Skew
tSKPP
Part-to-Part Skew
tSM
Mux Switch Time
RJ
Device Random
Jitter (3)
Measured from VIH or VIL of the mux-control or
loopback control to 50% of the valid differential
output.
See Figure 6 for test circuit.
Alternating-1-0 pattern. Pre-emphasis disabled.
At 1.25 Gbps
At 2.5 Gbps
DJ
Device Deterministic
Jitter (4)
See Figure 6 for test circuit.
Pre-emphasis disabled.
Between 0.8 and 2.5 Gbps with PRBS7 pattern for
DS25MB200 @ –40°C to 85°C
DRMAX
Maximum Data Rate
Tested with alternating 1-0 pattern (5)
DRMIN
Minimum Data Rate
(2)
(3)
(4)
(5)
8
1.8
30
2.5
pspp
Gbps
0.6
Gbps
tSKO is the magnitude difference in the propagation delays among data paths between switch A and switch B of the same port and
similar data paths between port 0 and port 1. An example is the output skew among data paths from SIA_0± to LO_0±, SIB_0± to
LO_0±, SIA_1± to LO_1± and SIB_1± to LO_1±. Another example is the output skew among data paths from LI_0± to SOA_0±, LI_0± to
SOB_0±, LI_1± to SOA_1± and LI_1± to SOB_1±. tSKO also refers to the delay skew of the loopback paths of the same port and
between similar data paths between port 0 and port 1. An example is the output skew among data paths SIA_0± to SOA_0±, SIB_0± to
SOB_0±, SIA_1± to SOA_1± and SIB_1± to SOB_1±.
Device output random jitter is a measurement of the random jitter contribution from the device. It is derived by the equation sqrt(RJOUT2–
RJIN2), where RJOUT is the random jitter measured at the output of the device in psrms, RJIN is the random jitter of the pattern generator
driving the device.
Device output deterministic jitter is a measurement of the deterministic jitter contribution from the device. It is derived by the equation
(DJOUT–DJIN), where DJOUT is the peak-to-peak deterministic jitter measured at the output of the device in pspp, DJIN is the peak-topeak deterministic jitter of the pattern generator driving the device.
For operation under 1 Gbps, encoded data transmission is recommended (i.e. 8b10b).
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Timing Diagrams
80%
80%
VODB
0V
20%
20%
tR
tF
Figure 3. Driver Output Transition Time
50% VID
IN
tPLH
tPHL
50% VOD
OUT
Figure 4. Propagation Delay from Input to Output
1-bit
1 to N bits
1-bit
1 to N bits
tPE
20%
-9 dB
80%
0V
VODPE3
Figure 5. Test Condition for Output Pre-Emphasis Duration
Pattern
Generator
DS25MB200
Test Fixture
DC
Block
VCC
DS25MB200
INPUT
25-inch
TLine
D-
Oscilloscope or
Jitter Measurement
Instrument
Coax
Coax
D+
DC
Block
50: TL
IN+
IN-
EQ
R
M
U
X
50+-1%
OUT+
< 2"
D
OUT-
Coax
1000 mVpp
Differential
Coax
GND
50: TL
50 +-1%
Figure 6. AC Test Circuit
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Product Folder Links: DS25MB200
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DS25MB200
SNLS220G – MARCH 2006 – REVISED APRIL 2013
www.ti.com
VCC
5k
IN +
50
1.5V
EQ
50
IN 3.9k
180 pF
Figure 7. Receiver Input Termination and Biasing Circuit
APPLICATION INFORMATION
The DS25MB200 input equalizer provides equalization to compensate about 5 dB of transmission loss from a
short backplane transmission line. For characterization purposes, a 25-inch FR4 coupled micro-strip board trace
is used in place of the short backplane link. The 25-inch microstrip board trace has approximately 5 dB of
attenuation between 375 MHz and 1.875 GHz, representing closely the transmission loss of the short backplane
transmission line. The 25-inch microstrip is connected between the pattern generator and the differential inputs of
the DS25MB200 for AC measurements.
Trace Length
Finished Trace
Width W
Separation between
Traces
Dielectric Height H
Dielectric Constant
εR
Loss Tangent
25 inches
8.5 mil
11.5 mil
6 mil
3.8
0.022
Passive Backplane
Line Cards
DS25MB200
HT
TD
SOB
T_ CLK
ASIC
PHY
SOA
LI
SerDes
SIA
RD
R_CLK
HR
LO
SIB
REFCLK
Mux/Buf
Clock
Distribution
ASIC or FPGA with integrated SerDes
PC
Switch Card 2
Switch Card 1
SerDes
TD
Switch
ASIC
HT
T_ CLK
RD
R_CLK
HR
REFCLK
Clock
Distribution
ASIC or FPGA with integrated SerDes
Figure 8. Application Diagram (showing data paths of port 0)
10
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Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: DS25MB200
DS25MB200
www.ti.com
SNLS220G – MARCH 2006 – REVISED APRIL 2013
REVISION HISTORY
Changes from Revision F (April 2013) to Revision G
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 10
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Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: DS25MB200
11
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
DS25MB200TSQ/NOPB
ACTIVE
WQFN
NJU
48
250
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
25MB200
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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