DS64EV100SDX/NOPB

DS64EV100 www.ti.com SNLS232E – OCTOBER 2006 – REVISED FEBRUARY 2013 DS64EV100 Programmable Single Equalizer Check for Samples: DS64EV100 FEATURES DESCRIPTION • • • • • • The DS64EV100 programmable equalizer provides compensation for transmission medium losses and reduces the medium-induced deterministic jitter for NRZ data channel. The DS64EV100 is optimized for operation up to 10 Gbps for both cables and FR4 traces. The equalizer channel has eight levels of input equalization that can be programmed by three control pins. 1 2 • • • • • • Equalizes up to 24 dB loss at 10 Gbps Equalizes up to 22 dB loss at 6.4 Gbps 8 levels of programmable equalization Operates up to 10 Gbps with 30” FR4 traces Operates up to 6.4 Gbps with 40” FR4 traces 0.175 UI residual deterministic jitter at 6.4 Gbps with 40” FR4 traces Single 2.5V or 3.3V power supply Supports AC or DC-Coupling with wide input common-mode Low power consumption: 100 mW Typ at 2.5V Small 3 mm x 4 mm 14-pin WSON package > 8 kV HBM ESD Rating -40 to 85°C operating temperature range The equalizer supports both AC and DC-coupled data paths for long run length data patterns such as PRBS-31, and balanced codes such as 8b/10b. The device uses differential current-mode logic (CML) inputs and outputs. The DS64EV100 is available in a 3 mm x 4 mm 14-pin leadless WSON package. Power is supplied from either a 2.5V or 3.3V supply. Simplified Application Diagram Tx ASIC/FPGA High Speed I/O Rx DS64EV100 OUT IN Switch Fabric Card Backplane/Cable Sub-system Line Card Tx ASIC/FPGA High Speed I/O Rx DS64EV100 OUT IN 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2013, Texas Instruments Incorporated DS64EV100 SNLS232E – OCTOBER 2006 – REVISED FEBRUARY 2013 www.ti.com Pin Diagram NC 1 14 BST_2 GND 2 13 GND IN+ 3 12 OUT_+ IN- 4 11 OUT_- VDD 5 10 GND GND 6 9 GND BST_1 7 8 BST_0 DS64EV100 TOP VIEW DAP = GND Figure 1. 14-Pin WSON Package (3 mm x 4 mm x 0.8 mm, 0.5 mm pitch) See Package Number NHK0014A Table 1. Pin Descriptions Pin Name Pin # I/O, Type Description HIGH SPEED DIFFERENTIAL I/O IN+ IN− 3 4 I, CML Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω terminating resistor is connected between IN+ and IN-. Refer to Figure 4. OUT+ OUT− 12 11 O, CML Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω terminating resistor connects OUT+ to VDD and OUT- to VDD. EQUALIZATION CONTROL BST_2 BST_1 BST_0 14 7 8 I, CMOS BST_2, BST_1, and BST_0 select the equalizer strength. BST_2 is internally pulled high. BST_1 and BST_0 are internally pulled low. VDD 5 I, Power VDD = 2.5V ±5% or 3.3V ±10%. VDD pins should be tied to VDD plane through low inductance path. A 0.01μF bypass capacitor should be connected between each VDD pin to GND planes. GND 2, 6, 9, 10, 13 I, Power Ground reference. GND should be tied to a solid ground plane through a low impedance path. DAP PAD I, Power Ground reference. The exposed pad at the center of the package must be connected to ground plane of the board. POWER OTHER NC 1 Reserved. Do not connect. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 2 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS64EV100 DS64EV100 www.ti.com SNLS232E – OCTOBER 2006 – REVISED FEBRUARY 2013 Absolute Maximum Ratings (1) (2) Supply Voltage (VDD) −0.5V to +4V CMOS Input Voltage −0.5V to +4.0V CMOS Output Voltage −0.5V to +4.0V CML Input/Output Voltage −0.5V to +4.0V Junction Temperature +150°C Storage Temperature −65°C to +150°C Lead Temperature Soldering, 4 sec +260°C ESD Rating HBM, 1.5 kΩ, 100 pF > 8 kV EIAJ, 0Ω, 200 pF > 250 V Thermal Resistance, θJA, No Airflow (1) 40 °C/W “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Absolute Maximum Numbers are guaranteed for a junction temperature range of –40°C to +125°C. Models are validated to Maximum Operating Voltages only. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office / Distributors for availability and specifications. (2) Recommended Operating Conditions MIN TYP MAX UNIT VDD2.5 to GND 2.375 2.5 2.625 V VDD3.3 to GND 3.0 3.3 3.6 V −40 25 +85 °C Supply Voltage (1) Ambient Temperature (1) The VDD2.5 is VDD = 2.5V ± 5% and VDD3.3 is VDD = 3.3V ± 10%. Electrical Characteristics Over recommended operating supply and temperature ranges unless other specified. (1) (2) TYP (1) MAX UNIT VDD3.3 140 200 mW VDD2.5 100 150 50 Hz – 100 Hz 100 Hz – 10 MHz 10 MHz – 1.6 GHz 100 40 10 PARAMETER TEST CONDITIONS MIN POWER P N Power Supply Consumption Supply Noise Tolerance (3) mW mVP-P mVP-P mVP-P LVTTL DC SPECIFICATIONS VIH Low Level Input Voltage VOH High Level Input Voltage VOL Low Level Input Voltage (2) (3) 1.6 VIL 2.0 VDD2. V 5 High Level Input Voltage VIL (1) VDD2.5 VDD3. V 3 −0.3 IOH = –3 mA, VDD3.3 2.4 IIN 2.0 IOL = 3 mA 0.8 V V V 0.4 V Typical values represent most likely parametric norms at VDD = 3.3V or 2.5V, TA = 25°C., and at the Recommended Operation Conditions at the time of product characterization and are not guaranteed. The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed. Allowed supply noise (mVP-P sine wave) under typical conditions. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS64EV100 3 DS64EV100 SNLS232E – OCTOBER 2006 – REVISED FEBRUARY 2013 www.ti.com Electrical Characteristics (continued) Over recommended operating supply and temperature ranges unless other specified. (1) (2) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT +1.8 +15 µA POWER IIN Input Current IIN-P Input Leakage Current with Internal PullDown/Up Resistors VIN = VDD −15 VIN = GND VIN = GND, with internal pull-down resistors VIN = GND, with internal pull-up resistors –20 400 0 µA +95 µA µA CML RECEIVER INPUTS (IN+, IN−) VTX Source Transmit Launch Signal Level (IN diff) AC-Coupled or DC-Coupled Requirement, Differential measurement at point A. Figure 1 VINTRE Input Threshold Voltage Differential measurement at point B . Figure 1 VDDTX Supply Voltage of Transmitter to EQ DC-Coupled Requirement VICMDC Input Common-Mode Voltage DC-Coupled Requirement Differential measurement at point A. Figure 1 (4) RLI Differential Input Return Loss 100 MHz – 3.2 GHz, with fixture’s effect de-embedded RIN Input Resistance Differential Across IN+ and IN-. Figure 4 85 100 115 Ω Differential measurement with OUT+ and OUTterminated by 50Ω to GND, AC-Coupled Figure 2 550 620 725 mVP-P VDD-0.2 VDD0.1 V 20 60 ps 58 Ω 1600 mVP-P 120 mVP-P 1.6 VDD V VDDTX-0.8 VDDT X-0.2 V 10 dB CML OUTPUTS (OUT+, OUT−) VOD Output Differential Voltage Level (OUT diff) VOCM Output Common-Mode Voltage tR, tF Transition Time Single-ended measurement DC-Coupled with 50Ω terminations (5) 20% to 80% of differential output voltage, measured within 1” from output pins. Figure 2 (5) RO Output Resistance Single-ended to VDD RLO Differential Output Return Loss 100 MHz – 1.6 GHz, with fixture’s effect deembedded. IN+ = static high. 42 tPLHD Differential Low to High Propagation Delay tPHLD Differential High to Low Propagation Delay Propagation delay measurement at 50% VOD between input to output, 100 Mbps Figure 3 (5) 50 10 dB 240 ps 240 ps 30” of 6 mil microstrip FR4, EQ Setting 0x06, PRBS-7 (27-1) pattern 0.20 UIP-P 40” of 6 mil microstrip FR4, EQ Setting 0x06, PRBS-7 (27-1) pattern 0.17 0.26 UIP-P 40” of 6 mil microstrip FR4, EQ Setting 0x07, PRBS-7 (27-1) pattern 0.12 0.20 UIP-P 40” of 6 mil microstrip FR4, EQ Setting 0x07, PRBS-7 (27-1) pattern 0.10 0.16 UIP-P EQUALIZATION DJ1 Residual Deterministic Jitter at 10 Gbps DJ2 Residual Deterministic Jitter at 6.4 Gbps DJ3 Residual Deterministic Jitter at 5 Gbps DJ4 Residual Deterministic Jitter at 2.5 Gbps (4) (5) (6) (7) 4 (6) (7) (6) (7) (6) (7) (6) (7) Measured with clock-like {11111 00000} pattern. Measured with clock-like {11111 00000} pattern. Specification is guaranteed by characterization at optimal boost setting and is not tested in production. Deterministic jitter is measured at the differential outputs (point C of Figure 1), minus the deterministic jitter before the test channel (point A of Figure 1). Random jitter is removed through the use of averaging or similar means. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS64EV100 DS64EV100 www.ti.com SNLS232E – OCTOBER 2006 – REVISED FEBRUARY 2013 Electrical Characteristics (continued) Over recommended operating supply and temperature ranges unless other specified. (1) (2) PARAMETER TEST CONDITIONS TYP (1) MIN MAX UNIT POWER RJ (8) Random Jitter (5) (8) 0.5 psrms Random jitter contributed by the equalizer is defined as sqrt (JOUT2 – JIN2). JOUT is the random jitter at equalizer outputs in psrms, see point C of Figure 1; JIN is the random jitter at the input of the equalizer in psrms, see Figure 1. TIMING DIAGRAMS B A 6 mils Trace Width, FR4 Microstrip Test Channel C DS64EV100 Signal Source INPUT SMA Connector OUTPUT SMA Connector Figure 2. Test Setup Diagram 80% 80% OUT diff = (OUT+) ± (OUT-) 0V 20% 20% tR tF Figure 3. CML Output Transition Times IN diff 0V tPLHD OUT diff tPHLD 0V Figure 4. Propagation Delay Timing Diagram Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS64EV100 5 DS64EV100 SNLS232E – OCTOBER 2006 – REVISED FEBRUARY 2013 www.ti.com TIMING DIAGRAMS (continued) VDD 10k IN + 50 VDD 6k EQ 10k 50 IN 6k Figure 5. Simplified Receiver Input Termination Circuit DS64EV100 APPLICATIONS INFORMATION The DS64EV100 is a programmable equalizer optimized for operation up to 10 Gbps for backplane and cable applications. The equalizer channel consists of an equalizer stage, a limiting amplifier, a DC offset correction block, and a CML driver as shown in Figure 5. DC Offset Correction IN+ IN - Input Limiting Amplifier Equalizer Termination OUT + OUT - BST CNTL BST_0 : BST_2 3 3 Figure 6. Simplified Block Diagram EQUALIZER BOOST CONTROL The equalizer channel supports eight programmable levels of equalization boost, and is controlled by the Boost Set pins (BST_[2:0]) in accordance with Table 2. The eight levels of boost settings enables the DS64EV100 to address a wide range of media loss and data rates. Table 2. EQ Boost Control Table 6 mil Microstrip FR4 Trace Length (in) 24 AWG Twin-AX Cable Length (m) Channel Loss at 3.2 GHz (db) Channel Loss at 5 GHz (dB) BST_N [2, 1, 0] 0 0 0 0 000 5 2 5 6 001 10 3 7.5 10 010 15 4 10 14 011 20 5 12.5 18 1 0 0 (Default) 25 6 15 21 101 30 7 17 24 110 40 10 22 30 111 GENERAL RECOMMENDATIONS The DS64EV100 is a high performance circuit capable of delivering excellent performance. Careful attention must be paid to the details associated with high-speed design as well as providing a clean power supply. Refer to the LVDS Owner’s Manual for more detailed information on high-speed design tips to address signal integrity design issues. 6 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS64EV100 DS64EV100 www.ti.com SNLS232E – OCTOBER 2006 – REVISED FEBRUARY 2013 PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL PAIRS The CML inputs and outputs must have a controlled differential impedance of 100Ω. It is preferable to route CML lines exclusively on one layer of the board, particularly for the input traces. The use of vias should be avoided if possible. If vias must be used, they should be used sparingly and must be placed symmetrically for each side of a given differential pair. Route the CML signals away from other signals and noise sources on the printed circuit board. See AN-1187 for additional information on WSON packages. POWER SUPPLY BYPASSING Two approaches are recommended to ensure that the DS64EV100 is provided with an adequate power supply. First, the supply (VDD) and ground (GND) pins should be connected to power planes routed on adjacent layers of the printed circuit board. The layer thickness of the dielectric should be minimized so that the VDD and GND planes create a low inductance supply with distributed capacitance. Second, careful attention to supply bypassing through the proper use of bypass capacitors is required. A 0.01μF bypass capacitor should be connected to each VDD pin such that the capacitor is placed as close as possible to the DS64EV100. Smaller body size capacitors can help facilitate proper component placement. Additionally, three capacitors with capacitance in the range of 2.2 μF to 10 μF should be incorporated in the power supply bypassing design as well. These capacitors can be either tantalum or an ultra-low ESR ceramic and should be placed as close as possible to the DS64EV100. DC COUPLING The DS64EV100 supports both AC coupling with external ac coupling capacitor, and DC coupling to its upstream driver, or downstream receiver. With DC coupling, users must ensure the input signal common mode is within the range of the electrical specification VICMDC and the device output is terminated with 50 Ω to VDD. TYPICAL PERFORMANCE EYE DIAGRAMS AND CURVES Figure 7. Equalized Signal (40 in FR4, 2.5 Gbps, PRBS7, 0x07 Setting) Figure 8. Equalized Signal (40 in FR4, 5 Gbps, PRBS7, 0x07 Setting) Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS64EV100 7 DS64EV100 SNLS232E – OCTOBER 2006 – REVISED FEBRUARY 2013 www.ti.com Figure 9. Equalized Signal (40 in FR4, 6.4 Gbps, PRBS7, 0x06 Setting) Figure 10. Equalized Signal (40 in FR4, 6.4 Gbps, PRBS31, 0x06 Setting) Figure 11. Equalized Signal (30 in FR4, 10 Gbps, PRBS7, 0x06 Setting) Figure 12. Equalized Signal (10m 24 AWG Twin-AX Cable, 6.4 Gbps, PRBS7, 0x06 Setting) Figure 13. Equalized Signal (32 in Tyco XAUI Backplane, 6.25 Gbps, PRBS7, 0x06 Setting) 8 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS64EV100 DS64EV100 www.ti.com SNLS232E – OCTOBER 2006 – REVISED FEBRUARY 2013 0.5 40 in 0.4 DJ (UI) 30 in 0.3 20 in 0.2 10 in 0.1 0 000 001 6 in 010 011 100 101 110 111 EQ SETTING (BST_2, BST_1, BST_0) Figure 14. DJ vs. EQ Setting (6.4 Gbps) Figure 15. DJ vs. EQ Setting (10 Gbps) Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS64EV100 9 DS64EV100 SNLS232E – OCTOBER 2006 – REVISED FEBRUARY 2013 www.ti.com REVISION HISTORY Changes from Revision D (February 2013) to Revision E • 10 Page Changed layout of National Data Sheet to TI format ............................................................................................................ 9 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS64EV100 PACKAGE OPTION ADDENDUM www.ti.com 30-May-2018 PACKAGING INFORMATION Orderable Device Status (1) DS64EV100SD/NOPB LIFEBUY Package Type Package Pins Package Drawing Qty WSON NHK 14 1000 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM Op Temp (°C) Device Marking (4/5) -40 to 85 D64E1SD (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of