DS90C032BTMX

DS90C032B www.ti.com SNLS052C – MARCH 1999 – REVISED APRIL 2013 DS90C032B LVDS Quad CMOS Differential Line Receiver Check for Samples: DS90C032B FEATURES DESCRIPTION • • The DS90C032B is a quad CMOS differential line receiver designed for applications requiring ultra low power dissipation and high data rates. The device supports data rates in excess of 155.5 Mbps (77.7 MHz) and uses Low Voltage Differential Signaling (LVDS) technology. 1 2 • • • • • • • • • >155.5 Mbps (77.7 MHz) Switching Rates Accepts Small Swing (350 mV) Differential Signal Levels High Impedance LVDS Inputs with Power Down Ultra Low Power Dissipation 600 ps Maximum Differential Skew (5V, 25°C) 6.0 ns Maximum Propagation Delay Industrial Operating Temperature Range Available in Surface Mount Packaging (SOIC) Pin Compatible with DS26C32A, MB570 (PECL) and 41LF (PECL) Supports OPEN and Terminated Input Failsafe Conforms to ANSI/TIA/EIA-644 LVDS Standard The DS90C032B accepts low voltage (350 mV) differential input signals and translates them to CMOS (TTL compatible) output levels. The receiver supports a TRI-STATE function that may be used to multiplex outputs. The receiver also supports OPEN Failsafe and terminated (100Ω) input Failsafe with the addition of external failsafe biasing. Receiver output will be HIGH for both Failsafe conditions. The DS90C032B provides power-off high impedance LVDS inputs. This feature assures minimal loading effect on the LVDS bus lines when VCC is not present. The DS90C032B and companion line driver (DS90C031B) provide a new alternative to high power pseudo-ECL devices for high-speed point-topoint interface applications. Connection Diagram Functional Diagram Figure 1. Dual-In-Line Top View See Package Number D (R-PDSO-G16) 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1999–2013, Texas Instruments Incorporated DS90C032B SNLS052C – MARCH 1999 – REVISED APRIL 2013 www.ti.com Table 1. Receiver Truth Table ENABLES EN EN* L H All other combinations of ENABLE inputs INPUTS OUTPUT RIN+ − RIN− ROUT X Z VID ≥ 0.1V H VID ≤ −0.1V L Failsafe OPEN or Terminated H These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) −0.3V to +6V Supply Voltage (VCC) −0.3V to +5.8V Input Voltage (RIN+, RIN−) Enable Input Voltage −0.3V to (VCC + 0.3V) (EN, EN*) −0.3V to (VCC + 0.3V) Output Voltage (ROUT) Maximum Package Power Dissipation at +25°C 1025 mW Derate Power Dissipation 8.2 mW/°C above +25°C −65°C to +150°C Storage Temperature Range Maximum Lead Temperature, Soldering (4 seconds) +260°C Maximum Junction Temperature ESD Ratings (1) +150°C ≥ 2kV HBM, 1.5 kΩ, 100 pF EIAJ, 0 Ω, 200 pF ≥ 250V “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be ensured. They are not meant to imply that the devices should be operated at these limits. “Electrical Characteristics” specifies conditions of device operation. Recommended Operating Conditions Min Typ Max Units Supply Voltage (VCC) +4.5 +5.0 +5.5 V Receiver Input Voltage GND Operating Free Air Temperature (TA) −40 2 Submit Documentation Feedback +25 2.4 V +85 °C Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: DS90C032B DS90C032B www.ti.com SNLS052C – MARCH 1999 – REVISED APRIL 2013 Electrical Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (1) (2) Symbol Parameter Conditions VTH Differential Input High Threshold VTL Differential Input Low Threshold IIN Input Current VOH Output High Voltage VOL Output Low Voltage RIN+, RIN− −100 Typ Max Units +100 mV mV −10 ±1 +10 μA −10 ±1 +10 μA IOH = −0.4 mA, VID = +200 mV 3.8 4.9 IOH = −0.4 mA, Input terminated 3.8 4.9 VIN = +2.4V VIN = 0V VCC = 5.5V or 0V IOL = 2 mA, VID = −200 mV ROUT (3) Output Short Circuit Current Enabled, VOUT = 0V IOZ Output TRI-STATE Current Disabled, VOUT = 0V or VCC VIH Input High Voltage VIL Input Low Voltage II Input Current VCL Input Clamp Voltage ICC No Load Supply Current, Receivers EN, EN* = VCC or GND, Inputs Open Enabled EN, EN* = 2.4 or 0.5, Inputs Open ICCZ No Load Supply Current, Receivers EN = GND, EN* = VCC, Inputs Open Disabled (2) (3) Min VCM = +1.2V IOS (1) Pin V V 0.07 0.3 V −15 −60 −100 mA −10 ±1 +10 μA 2.0 EN, EN* ICL = −18 mA V 0.8 V +10 μA 3.5 10 mA 3.7 11 mA 3.5 10 mA −10 ±1 −1.5 −0.8 VCC V Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground unless otherwise specified. All typicals are given for: VCC = +5.0V, TA = +25°C. Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, do not exceed maximum junction temperature specification. Switching Characteristics VCC = +5.0V, TA = +25°C (1) (2) (3) Min Typ Max Units tPHLD Symbol Differential Propagation Delay High to Low 1.5 3.40 5.0 ns tPLHD Differential Propagation Delay Low to High 1.5 3.48 5.0 ns tSKD Differential Skew |tPHLD − tPLHD| 0 80 600 ps tSK1 Channel-to-Channel Skew (4) 0 0.6 1.0 ns tTLH Rise Time 0.5 2.0 ns tTHL Fall Time 0.5 2.0 ns tPHZ Disable Time High to Z 10 15 ns tPLZ Disable Time Low to Z 10 15 ns tPZH Enable Time Z to High 4 10 ns tPZL Enable Time Z to Low 4 10 ns (1) (2) (3) (4) Parameter Conditions CL = 5 pF, VID = 200 mV, See Figure 2 and Figure 3 RL = 2 kΩ, CL = 10 pF, See Figure 4 and Figure 5 All typicals are given for: VCC = +5.0V, TA = +25°C. Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50Ω, tr and tf (0%–100%) ≤ 1 ns for RIN and tr and tf ≤ 6 ns for EN or EN*. CL includes probe and jig capacitance. Channel-to-Channel Skew is defined as the difference between the propagation delay of one channel and that of the others on the same chip with an event on the inputs. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: DS90C032B 3 DS90C032B SNLS052C – MARCH 1999 – REVISED APRIL 2013 www.ti.com Switching Characteristics VCC = +5.0V ± 10%, TA = −40°C to +85°C (1) (2) (3) Symbol Parameter Conditions Min Typ Max Units tPHLD Differential Propagation Delay High to Low 1.0 3.40 6.0 ns tPLHD Differential Propagation Delay Low to High 1.0 3.48 6.0 ns tSKD Differential Skew |tPHLD − tPLHD| 0 0.08 1.2 ns tSK1 Channel-to-Channel Skew (4) 0 0.6 1.5 ns (5) CL = 5 pF, VID = 200 mV, See Figure 2 and Figure 3 tSK2 Chip to Chip Skew 5.0 ns tTLH Rise Time 0.5 2.5 ns tTHL Fall Time 0.5 2.5 ns tPHZ Disable Time High to Z 10 20 ns tPLZ Disable Time Low to Z 10 20 ns tPZH Enable Time Z to High 4 15 ns tPZL Enable Time Z to Low 4 15 ns (1) (2) (3) (4) (5) RL = 2 kΩ, CL = 10 pF, See Figure 4 and Figure 5 All typicals are given for: VCC = +5.0V, TA = +25°C. Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50Ω, tr and tf (0%–100%) ≤ 1 ns for RIN and tr and tf ≤ 6 ns for EN or EN*. CL includes probe and jig capacitance. Channel-to-Channel Skew is defined as the difference between the propagation delay of one channel and that of the others on the same chip with an event on the inputs. Chip to Chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays. Parameter Measurement Information Figure 2. Receiver Propagation Delay and Transition Time Test Circuit Figure 3. Receiver Propagation Delay and Transition Time Waveforms 4 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: DS90C032B DS90C032B www.ti.com SNLS052C – MARCH 1999 – REVISED APRIL 2013 Parameter Measurement Information (continued) CL includes load and test jig capacitance. S1 = VCC for tPZL and tPLZ measurements. S1 = GND for tPZH and tPHZ measurements. Figure 4. Receiver TRI-STATE Delay Test Circuit Figure 5. Receiver TRI-STATE Delay Waveforms Typical Application Figure 6. Point-to-Point Application Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: DS90C032B 5 DS90C032B SNLS052C – MARCH 1999 – REVISED APRIL 2013 www.ti.com APPLICATIONS INFORMATION LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as is shown in Figure 6. This configuration provides a clean signaling environment for the quick edge rates of the drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair cable, a parallel pair cable, or simply PCB traces. Typically the characteristic impedance of the media is in the range of 100Ω. A termination resistor of 100Ω should be selected to match the media, and is located as close to the receiver input pins as possible. The termination resistor converts the current sourced by the driver into a voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as ground shifting, noise margin limits, and total termination loading must be taken into account. TheDS90C032B differential line receiver is capable of detecting signals as low as 100 mV, over a ±1V commonmode range centered around +1.2V. This is related to the driver offset voltage which is typically +1.2V. The driven signal is centered around this voltage and may shift ±1V around this center point. The ±1V shifting may be the result of a ground potential difference between the driver's ground reference and the receiver's ground reference, the common-mode effects of coupled noise, or a combination of the two. Both receiver input pins should honor their specified operating input voltage range of 0V to +2.4V (measured from each pin to ground), exceeding these limits may turn on the ESD protection circuitry which will clamp the bus voltages. RECEIVER FAILSAFE The LVDS receiver is a high gain, high speed device that amplifies a small differential signal (20mV) to CMOS logic levels. Due to the high gain and tight threshold of the receiver, care should be taken to prevent noise from appearing as a valid signal. The receiver's internal failsafe circuitry is designed to source/sink a small amount of current, providing failsafe protection (a stable known state of HIGH output voltage) for floating and terminated (100Ω) receiver inputs in low noise environment (differential noise < 10mV). 1. Open Input Pins. TheDS90C032B is a quad receiver device, and if an application requires only 1, 2, or 3 receivers, the unused channel(s) inputs should be left OPEN. Do not tie unused receiver inputs to ground or any other voltages. The input is biased by internal high value pull up and pull down resistors to set the output to a HIGH state. This internal circuitry will ensure a HIGH, stable output state for open inputs. 2. Terminated Input. TheDS90C032B requires external failsafe biasing for terminated input failsafe. Terminated input failsafe is the case of a receiver that has a 100Ω termination across its inputs and the driver is in the following situations. Unplugged from the bus, or the driver output is in TRI-STATE or in poweroff condition. The use of external biasing resistors provide a small bias to set the differential input voltage while the line is un-driven, and therefore the receiver output will be in HIGH state. If the driver is removed from the bus but the cable is still present and floating, the unplugged cable can become a floating antenna that can pick up noise. The LVDS receiver is designed to detect very small amplitude and width signals and recover them to standard logic levels. Thus, if the cable picks up more than 10mV of differential noise, the receiver may respond. To insure that any noise is seen as common-mode and not differential, a balanced interconnect and twisted pair cables is recommended, as they help to ensure that noise is coupled common to both lines and rejected by the receivers. 3. Operation in environment with greater than 10mV differential noise. TI recommends external failsafe biasing on its LVDS receivers for a number of system level and signal quality reasons. First, only an application that requires failsafe biasing needs to employ it. Second, the amount of failsafe biasing is now an application design parameter and can be custom tailored for the specific application. In applications in low noise environments, they may choose to use a very small bias if any. For applications with less balanced interconnects and/or in high noise environments they may choose to boost failsafe further. TI's "LVDS Owner’s Manual provides detailed calculations for selecting the proper failsafe biasing resistors. Third, the common-mode voltage is biased by the resistors during the un-driven state. This is selected to be close to the nominal driver offset voltage (VOS). Thus when switching between driven and un-driven states, the common-mode modulation on the bus is held to a minimum. 6 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: DS90C032B DS90C032B www.ti.com SNLS052C – MARCH 1999 – REVISED APRIL 2013 For additional Failsafe Biasing information, please refer to Application Note AN-1194 for more detail. The footprint of theDS90C032B is the same as the industry standard 26LS32 Quad Differential (RS-422) Receiver. For additional LVDS application information, please refer to TI's LVDS Owner's Manual available through TI's website http://www.ti.com/lvds Pin Descriptions Pin No. Name 2, 6, 10, 14 RIN+ Non-inverting receiver input pin Description 1, 7, 9, 15 RIN− Inverting receiver input pin 3, 5, 11, 13 ROUT Receiver output pin 4 EN Active high enable pin, OR-ed with EN* 12 EN* Active low enable pin, OR-ed with EN 16 VCC Power supply pin, +5V ± 10% 8 GND Ground pin Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: DS90C032B 7 DS90C032B SNLS052C – MARCH 1999 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics 8 Output High Voltage vs Power Supply Voltage Output High Voltage vs Ambient Temperature Figure 7. Figure 8. Output Low Voltage vs Power Supply Voltage Output Low Voltage vs Ambient Temperature Figure 9. Figure 10. Output Short Circuit Current vs Power Supply Voltage Output Short Circuit Current vs Ambient Temperature Figure 11. Figure 12. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: DS90C032B DS90C032B www.ti.com SNLS052C – MARCH 1999 – REVISED APRIL 2013 Typical Performance Characteristics (continued) Differential Propagation Delay vs Power Supply Voltage Differential Propagation Delay vs Ambient Temperature Figure 13. Figure 14. Differential Skew vs Power Supply Voltage Differential Skew vs Ambient Temperature Figure 15. Figure 16. Transition Time vs Power Supply Voltage Transition Time vs Ambient Temperature Figure 17. Figure 18. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: DS90C032B 9 DS90C032B SNLS052C – MARCH 1999 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision B (April 2013) to Revision C • 10 Page Changed layout of National Data Sheet to TI format ............................................................................................................ 9 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: DS90C032B PACKAGE OPTION ADDENDUM www.ti.com 13-Apr-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking (4/5) (6) DS90C032BTM NRND SOIC D 16 48 Non-RoHS & Green Call TI Level-1-235C-UNLIM -40 to 85 DS90C032BTM DS90C032BTM/NOPB ACTIVE SOIC D 16 48 RoHS & Green Call TI | SN Level-1-260C-UNLIM -40 to 85 DS90C032BTM DS90C032BTMX NRND SOIC D 16 2500 Non-RoHS & Green Call TI Level-1-235C-UNLIM -40 to 85 DS90C032BTM DS90C032BTMX/NOPB ACTIVE SOIC D 16 2500 RoHS & Green Call TI | SN Level-1-260C-UNLIM -40 to 85 DS90C032BTM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of