DS90CF384AMTD/NOPB

DS90CF364A, DS90CF384A www.ti.com SNLS040I – JUNE 2000 – REVISED APRIL 2013 DS90CF384A/DS90CF364A +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link - 65 MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link - 65 MHz Check for Samples: DS90CF364A, DS90CF384A FEATURES DESCRIPTION • • • The DS90CF384A receiver converts the four LVDS data streams (Up to 1.8 Gbps throughput or 227 Megabytes/sec bandwidth) back into parallel 28 bits of CMOS/TTL data (24 bits of RGB and 4 bits of Hsync, Vsync, DE and CNTL). Also available is the DS90CF364A that converts the three LVDS data streams (Up to 1.3 Gbps throughput or 170 Megabytes/sec bandwidth) back into parallel 21 bits of CMOS/TTL data (18 bits of RGB and 3 bits of Hsync, Vsync and DE). Both Receivers' outputs are Falling edge strobe. A Rising edge or Falling edge strobe transmitter (DS90C383A/DS90C363A) will interoperate with a Falling edge strobe Receiver without any translation logic. 1 2 • • • • • • • 20 to 65 MHz Shift Clock Support 50% Duty Cycle on Receiver Output Clock Best-in-Class Set & Hold Times on RxOUTPUTs Rx Power Consumption 700V (EIAJ) Supports VGA, SVGA, XGA and Dual Pixel SXGA. PLL Requires no External Components Compatible with TIA/EIA-644 LVDS Standard Low Profile 56-lead or 48-lead Packages The DS90CF384A / DS90CF364A devices are enhanced over prior generation receivers and provided a wider data valid time on the receiver output. This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces. BLOCK DIAGRAMS Figure 1. DS90CF384A DGG-56 (TSSOP) Figure 2. DS90CF364A DGG-48 (TSSOP) 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2000–2013, Texas Instruments Incorporated DS90CF364A, DS90CF384A SNLS040I – JUNE 2000 – REVISED APRIL 2013 www.ti.com Absolute Maximum Ratings (1) (2) −0.3V to +4V Supply Voltage (VCC) CMOS/TTL Input Voltage −0.3V to (VCC + 0.3V) CMOS/TTL Output Voltage −0.3V to (VCC + 0.3V) LVDS Receiver Input Voltage −0.3V to (VCC + 0.3V) Junction Temperature +150°C Storage Temperature −65°C to +150°C Lead Temperature (Soldering, 4 sec) +260°C Solder Reflow Temperature (20 sec for FBGA) Maximum Package Power Dissipation Capacity @ 25°C Package Derating ESD Rating +220°C DGG-56 (TSSOP) Package DS90CF384A 1.61 W DGG-48 (TSSOP) Package DS90CF364A 1.89 W DS90CF384AMTD 12.4 mW/°C above +25°C DS90CF364AMTD 15 mW/°C above +25°C (HBM, 1.5 kΩ, 100 pF) > 7 kV (EIAJ, 0Ω, 200 pF) (1) (2) > 700V “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be verified. They are not meant to imply that the device should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. Recommended OperatingConditions Min Nom Max Units Supply Voltage (VCC) 3.0 3.3 3.6 V Operating Free Air Temperature (TA ) −10 +25 +70 °C Receiver Input Range 0 Supply Noise Voltage (VCC) 2.4 V 100 mVPP Electrical Characteristics (1) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units CMOS/TTL DC SPECIFICATIONS (For Power Down Pin) VIH High Level Input Voltage 2.0 VCC V VIL Low Level Input Voltage GND 0.8 V VCL Input Clamp Voltage ICL = −18 mA −0.79 −1.5 V IIN Input Current V IN = 0.4V, 2.5V or VCC +1.8 +10 μA V IN = GND −10 0 μA 2.7 3.3 V CMOS/TTL DC SPECIFICATIONS VOH High Level Output Voltage IOH = −0.4 mA VOL Low Level Output Voltage IOL = 2 mA 0.06 0.3 V IOS Output Short Circuit Current VOUT = 0V −60 −120 mA (1) 2 Typical values are given for VCC = 3.3V and TA = +25C. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: DS90CF364A DS90CF384A DS90CF364A, DS90CF384A www.ti.com SNLS040I – JUNE 2000 – REVISED APRIL 2013 Electrical Characteristics(1) (continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units +100 mV LVDS RECEIVER DC SPECIFICATIONS VTH Differential Input High Threshold VTL Differential Input Low Threshold IIN Input Current V CM = +1.2V −100 mV V IN = +2.4V, VCC = 3.6V ±10 μA V IN = 0V, VCC = 3.6V ±10 μA 65 mA RECEIVER SUPPLY CURRENT (2) ICCRW ICCRW ICCRG ICCRZ (2) Receiver Supply Current Worst Case Receiver Supply Current Worst Case Receiver Supply Current, 16 Grayscale Receiver Supply Current Power Down CL = 8 pF, Worst Case Pattern, DS90CF384A (Figure 3 Figure 6) f = 32.5 MHz 49 f = 37.5 MHz 53 70 mA f = 65 MHz 81 105 mA CL = 8 pF, Worst Case Pattern, DS90CF364A (Figure 3 Figure 6) f = 32.5 MHz 49 55 mA f = 37.5 MHz 53 60 mA f = 65 MHz 78 90 mA CL = 8 pF, f = 32.5 MHz 16 Grayscale Pattern, f = 37.5 MHz (Figure 4 Figure 5 Figure 6) f = 65 MHz 28 45 mA 30 47 mA 43 60 mA Power Down = Low Receiver Outputs Stay Low during Power Down Mode 10 55 μA Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise specified (except VOD and ΔV OD). Receiver Switching Characteristics (1) Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter CLHT CMOS/TTL Low-to-High Transition Time (Figure 6) CHLT CMOS/TTL High-to-Low Transition Time (Figure 6) RSPos0 Receiver Input Strobe Position for Bit 0 (Figure 13, Figure 14) RSPos1 Min Typ Max Units 2 5 ns 1.8 5 ns 1.20 1.96 2.82 ns Receiver Input Strobe Position for Bit 1 6.91 7.67 8.53 ns RSPos2 Receiver Input Strobe Position for Bit 2 12.62 13.38 14.24 ns RSPos3 Receiver Input Strobe Position for Bit 3 18.33 19.09 19.95 ns RSPos4 Receiver Input Strobe Position for Bit 4 24.04 24.80 25.66 ns RSPos5 Receiver Input Strobe Position for Bit 5 29.75 30.51 31.37 ns RSPos6 Receiver Input Strobe Position for Bit 6 35.46 36.22 37.08 ns RSPos0 Receiver Input Strobe Position for Bit 0 (Figure 13, Figure 14) 0.7 1.1 1.4 ns RSPos1 Receiver Input Strobe Position for Bit 1 2.9 3.3 3.6 ns RSPos2 Receiver Input Strobe Position for Bit 2 5.1 5.5 5.8 ns RSPos3 Receiver Input Strobe Position for Bit 3 7.3 7.7 8.0 ns RSPos4 Receiver Input Strobe Position for Bit 4 9.5 9.9 10.2 ns RSPos5 Receiver Input Strobe Position for Bit 5 11.7 12.1 12.4 ns RSPos6 Receiver Input Strobe Position for Bit 6 13.9 14.3 14.6 ns RSKM (1) (2) RxIN Skew Margin (2) (Figure 15) f = 25 MHz f = 65 MHz f = 25 MHz 750 ps f = 65 MHz 500 ps Typical values are given for VCC = 3.3V and TA = +25C. Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the DS90C383B transmitter pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window RSPos). The RSKM will change when different transmitters are used. This margin allows for LVDS interconnect skew, inter-symbol interference (both dependent on type/length of cable), and clock jitter (less than 250 ps). Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: DS90CF364A DS90CF384A Submit Documentation Feedback 3 DS90CF364A, DS90CF384A SNLS040I – JUNE 2000 – REVISED APRIL 2013 www.ti.com Receiver Switching Characteristics(1) (continued) Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter RCOP RxCLK OUT Period (Figure 7) RCOH RxCLK OUT High Time (Figure 7) RCOL Min Typ Max Units 15 T 50 ns 5.0 7.6 9.0 ns RxCLK OUT Low Time (Figure 7) 5.0 6.3 9.0 ns RSRC RxOUT Setup to RxCLK OUT (Figure 7) 4.5 7.3 RHRC RxOUT Hold to RxCLK OUT (Figure 7) 4.0 6.3 RCCD RxCLK IN to RxCLK OUT Delay @ 25°C, VCC = 3.3V (Figure 8) 3.5 5.0 RPLLS RPDD f = 65 MHz ns ns 7.5 ns Receiver Phase Lock Loop Set (Figure 9) 10 ms Receiver Power Down Delay (Figure 12 ) 1 μs AC Timing Diagrams Figure 3. “Worst Case” Test Pattern 4 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: DS90CF364A DS90CF384A DS90CF364A, DS90CF384A www.ti.com SNLS040I – JUNE 2000 – REVISED APRIL 2013 (1) The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O. (2) The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed to produce groups of 16 vertical stripes across the display. (3) Figure 3 and Figure 5 show a falling edge data strobe (TxCLK IN/RxCLK OUT). (4) Recommended pin to signal mapping. Customer may choose to define differently. Figure 4. “16 Grayscale” Test Pattern (DS90CF384A) Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: DS90CF364A DS90CF384A Submit Documentation Feedback 5 DS90CF364A, DS90CF384A SNLS040I – JUNE 2000 – REVISED APRIL 2013 Device Pin Name Signal TxCLK IN / RxCLK OUT Dot Clk www.ti.com Signal Pattern Signal Frequency f TxIN0 / RxOUT0 R0 f / 16 TxIN1 / RxOUT1 R1 f/8 TxIN2 / RxOUT2 R2 f/4 TxIN3 / RxOUT3 R3 f/2 TxIN4 / RxOUT4 R4 Steady State, Low TxIN5 / RxOUT5 R5 Steady State, Low TxIN6 / RxOUT6 G0 f / 16 TxIN7 / RxOUT7 G1 f/8 TxIN8 / RxOUT8 G2 f/4 TxIN9 / RxOUT9 G3 f/2 TxIN10 / RxOUT10 G4 Steady State, Low TxIN11 / RxOUT11 G5 Steady State, Low TxIN12 / RxOUT12 B0 f / 16 TxIN13 / RxOUT13 B1 f/8 TxIN14 / RxOUT14 B2 f/4 TxIN15 / RxOUT15 B3 f/2 TxIN16 / RxOUT16 B4 Steady State, Low TxIN17 / RxOUT17 B5 Steady State, Low TxIN18 / RxOUT18 HSYNC Steady State, High TxIN19 / RxOUT19 VSYNC Steady State, High TxIN20 / RxOUT20 ENA Steady State, High (1) The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O. (2) The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed to produce groups of 16 vertical stripes across the display. (3) Figure 3 and Figure 5 show a falling edge data strobe (TxCLK IN/RxCLK OUT). (4) Recommended pin to signal mapping. Customer may choose to define differently. Figure 5. “16 Grayscale” Test Pattern (DS90CF364A) 6 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: DS90CF364A DS90CF384A DS90CF364A, DS90CF384A www.ti.com SNLS040I – JUNE 2000 – REVISED APRIL 2013 Figure 6. DS90CF384A/DS90CF364A (Receiver) CMOS/TTL Output Load and Transition Times Figure 7. DS90CF384A/DS90CF364A (Receiver) Setup/Hold and High/Low Times Figure 8. DS90CF384A/DS90CF364A (Receiver) Clock In to Clock Out Delay Figure 9. DS90CF384A/DS90CF364A (Receiver) Phase Lock Loop Set Time Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: DS90CF364A DS90CF384A Submit Documentation Feedback 7 DS90CF364A, DS90CF384A SNLS040I – JUNE 2000 – REVISED APRIL 2013 www.ti.com Figure 10. 28 Parallel TTL Data Inputs Mapped to LVDS Outputs - DS90CF384A Figure 11. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs - DS90CF364A Figure 12. DS90CF384A/DS90CF364A (Receiver) Power Down Delay 8 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: DS90CF364A DS90CF384A DS90CF364A, DS90CF384A www.ti.com SNLS040I – JUNE 2000 – REVISED APRIL 2013 Figure 13. DS90CF384A (Receiver) LVDS Input Strobe Position Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: DS90CF364A DS90CF384A Submit Documentation Feedback 9 DS90CF364A, DS90CF384A SNLS040I – JUNE 2000 – REVISED APRIL 2013 www.ti.com Figure 14. DS90CF364A (Receiver) LVDS Input Strobe Position C—Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max Tppos—Transmitter output pulse position (min and max) RSKM = Cable Skew (type, length) + Source Clock Jitter (cycle to cycle)(1) + ISI (Inter-symbol interference)(2) Cable Skew—typically 10 ps–40 ps per foot, media dependent Cycle-to-cycle jitter is less than 250 ps at 65 MHz. ISI is dependent on interconnect length; may be zero. Figure 15. Receiver LVDS Input Skew Margin 10 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: DS90CF364A DS90CF384A DS90CF364A, DS90CF384A www.ti.com SNLS040I – JUNE 2000 – REVISED APRIL 2013 DS90CF384A PIN DESCRIPTIONS — 56 Lead TSSOP Package — 24-Bit FPD Link Receiver Pin Name I/O No. Description RxIN+ I 4 Positive LVDS differentiaI data inputs. RxIN− I 4 Negative LVDS differential data inputs. RxOUT O 28 TTL level data outputs. This includes: 8 Red, 8 Green, 8 Blue, and 3 control lines—FPLINE, FPFRAME, DRDY (also referred to as HSYNC, VSYNC, Data Enable). RxCLK IN+ I 1 Positive LVDS differential clock input. RxCLK IN− I 1 Negative LVDS differential clock input. RxCLK OUT O 1 TTL Ievel clock output. The falling edge acts as data strobe. PWR DOWN I 1 TTL level input. When asserted (low input) the receiver outputs are low. VCC I 4 Power supply pins for TTL outputs. GND I 5 Ground pins for TTL outputs. PLL VCC I 1 Power supply for PLL. PLL GND I 2 Ground pin for PLL. LVDS VCC I 1 Power supply pin for LVDS inputs. LVDS GND I 3 Ground pins for LVDS inputs. DS90CF364A PIN DESCRIPTIONS — 48 Lead TSSOP Package — 18-Bit FPD Link Receiver Pin Name RxIN+ I/O No. I 3 Positive LVDS differentiaI data inputs. Description RxIN− I 3 Negative LVDS differential data inputs. RxOUT O 21 TTL level data outputs. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines—FPLINE, FPFRAME, DRDY (also referred to as HSYNC, VSYNC, Data Enable). RxCLK IN+ I 1 Positive LVDS differential clock input. RxCLK IN− I 1 Negative LVDS differential clock input. RxCLK OUT O 1 TTL Ievel clock output. The falling edge acts as data strobe. PWR DOWN I 1 TTL level input. When asserted (low input) the receiver outputs are low. VCC I 4 Power supply pins for TTL outputs. GND I 5 Ground pins for TTL outputs. PLL VCC I 1 Power supply for PLL. PLL GND I 2 Ground pin for PLL. LVDS VCC I 1 Power supply pin for LVDS inputs. LVDS GND I 3 Ground pins for LVDS inputs. Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: DS90CF364A DS90CF384A Submit Documentation Feedback 11 DS90CF364A, DS90CF384A SNLS040I – JUNE 2000 – REVISED APRIL 2013 www.ti.com Pin Diagram for TSSOP Packages Figure 16. DS90CF384A DGG-56 Package 12 Submit Documentation Feedback Figure 17. DS90CF364A DGG-48 Package Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: DS90CF364A DS90CF384A DS90CF364A, DS90CF384A www.ti.com SNLS040I – JUNE 2000 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision H (April 2013) to Revision I • Page Changed layout of National Data Sheet to TI format .......................................................................................................... 12 Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: DS90CF364A DS90CF384A Submit Documentation Feedback 13 PACKAGE OPTION ADDENDUM www.ti.com 30-Sep-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking (4/5) (6) DS90CF364AMTD NRND TSSOP DGG 48 38 Non-RoHS & Green Call TI Level-2-235C-1 YEAR -10 to 70 DS90CF364AMTD >B DS90CF364AMTD/NOPB ACTIVE TSSOP DGG 48 38 RoHS & Green SN Level-2-260C-1 YEAR -10 to 70 DS90CF364AMTD >B DS90CF364AMTDX NRND TSSOP DGG 48 1000 Non-RoHS & Green Call TI Level-2-235C-1 YEAR -10 to 70 DS90CF364AMTD >B DS90CF364AMTDX/NOPB ACTIVE TSSOP DGG 48 1000 RoHS & Green SN Level-2-260C-1 YEAR -10 to 70 DS90CF364AMTD >B DS90CF384AMTD/NOPB ACTIVE TSSOP DGG 56 34 RoHS & Green SN Level-2-260C-1 YEAR -10 to 70 DS90CF384AMTD >B DS90CF384AMTDX/NOPB ACTIVE TSSOP DGG 56 1000 RoHS & Green SN Level-2-260C-1 YEAR -10 to 70 DS90CF384AMTD >B (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of