DS90CP02SPX/NOPB

DS90CP02 www.ti.com SNLS267A – NOVEMBER 2008 – REVISED MARCH 2013 DS90CP02 1.5 Gbps 2x2 LVDS Crosspoint Switch Check for Samples: DS90CP02 FEATURES DESCRIPTION • • The DS90CP02 is a 1.5 Gbps 2 x 2 LVDS crosspoint switch optimized for high-speed signal routing and switching over lossy FR-4 printed circuit board backplanes and balanced cables. Fully differential signal paths ensure exceptional signal integrity and noise immunity. The non-blocking architecture allows connections of any input to any output or outputs. 1 2 • • • • • • • • 1.5 Gbps per Channel Low Power: 70 mA in Dual Repeater Mode @1.5 Gbps Low Output Jitter Non-Blocking Architecture Allows 1:2 Splitter, 2:1 Mux, Crossover, and Dual Buffer Configurations Flow-Through Pinout LVDS/BLVDS/CML/LVPECL Inputs, LVDS Outputs Single 3.3V Supply Separate Control of Inputs and Outputs Allows for Power Savings Industrial -40 to +85°C Temperature Range 28-lead UQFN-28 Space Saving Package Wide input common mode range allows the switch to accept signals with LVDS, CML and LVPECL levels; the output levels are LVDS. A very small package footprint requires a minimal space on the board while the flow-through pinout allows easy board layout. The 3.3V supply, CMOS process, and LVDS I/O ensure high performance at low power over the entire industrial -40 to +85°C temperature range. Block Diagram 2:1 Mux1 IN0+ OUT0+ OUT0- 2:1 Mux2 IN0- IN1+ OUT1+ OUT1- IN1- SEL0 Control Logic SEL1 EN0 EN1 Figure 1. DS90CP02 Block Diagram 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008–2013, Texas Instruments Incorporated DS90CP02 SNLS267A – NOVEMBER 2008 – REVISED MARCH 2013 www.ti.com Table 1. PIN DESCRIPTIONS Pin Name Pin Number I/O, Type Description DIFFERENTIAL INPUTS COMMON TO ALL MUXES IN0+ IN0− 9 10 I, LVDS Inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or LVPECL compatible. IN1+ IN1− 12 13 I, LVDS Inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or LVPECL compatible. SWITCHED DIFFERENTIAL OUTPUTS OUT0+ OUT0− 27 26 O, LVDS Inverting and non-inverting differential outputs. OUT0± can be connected to any one pair IN0±, or IN1±. LVDS compatible . OUT1+ OUT1− 24 23 O, LVDS Inverting and non-inverting differential outputs. OUT1± can be connected to any one pair IN0±, or IN1±. LVDS compatible . DIGITAL CONTROL INTERFACE SEL0, SEL1 6 5 I, LVTTL Select Control Inputs EN0, EN1 7 15 I, LVTTL Output Enable Inputs N/C 8, 20, 28 Not Connected POWER VDD 11, 14, 16, 18, 19, 22, 25 I, Power VDD = 3.3V ±0.3V. At least 4 low ESR 0.01 µF bypass capacitors should be connected from VDD to GND plane. GND DAP, 1, 2, 3, 4, 17, 21 I, Power Ground reference to LVDS and CMOS circuitry. For the UQFN package, the DAP is used as the primary GND connection to the device. The DAP is the exposed metal contact at the bottom of the UQFN-28 package. It should be connected to the ground plane with at least 4 vias for optimal AC and thermal performance. EN0 SEL0 SEL1 GND GND GND GND Connection Diagram 7 6 5 4 3 2 1 N/C 8 28 N/C IN0+ 9 27 OUT0+ IN0- 10 26 OUT0- 25 VDDA DAP (GND) VDDA 11 IN1+ 12 24 OUT1+ IN1- 13 23 OUT1- VDD 14 22 VDD N/C GND VDD VDD GND VDD EN1 15 16 17 18 19 20 21 Figure 2. UQFN Top View DAP = GND See Package Number NJD0028A 2 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS90CP02 DS90CP02 www.ti.com SNLS267A – NOVEMBER 2008 – REVISED MARCH 2013 Configuration Select Truth Table SEL0 SEL1 EN0 EN1 OUT0 OUT1 0 0 0 0 IN0 IN0 1:2 Splitter (IN1 powered down) Mode 0 1 0 0 IN0 IN1 Dual Channel Repeater 1 0 0 0 IN1 IN0 Dual Channel Switch 1 1 0 0 IN1 IN1 1:2 Splitter (IN0 powered down) 0 1 0 1 IN0 PD Single Channel Repeater (Channel 1 powered down) 1 1 0 1 IN1 PD Single Channel Switch (IN0 and OUT1 powered down) 0 0 1 0 PD IN0 Single Channel Switch (IN1 and OUT0 powered down) 0 1 1 0 PD IN1 Single Channel Repeater (Channel 0 powered down) X X 1 1 PD PD Both Channels in Power Down Mode 0 0 0 1 Invalid State* 1 0 0 1 Invalid State* 1 0 1 0 Invalid State* 1 1 1 0 Invalid State* Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS90CP02 3 DS90CP02 SNLS267A – NOVEMBER 2008 – REVISED MARCH 2013 www.ti.com APPLICATION INFORMATION Dual Channel Repeater (SEL0=0, SEL1=1, EN0=0, EN1=0) 1:2 Splitter (SEL0=0, SEL1=0, EN0=0, EN1=0) IN0+ OUT0+ IN0+ OUT0+ IN0- OUT0- IN0- OUT0- IN1+ OUT1+ IN1+ OUT1+ IN1- OUT1- IN1- OUT1- 1:2 Splitter (SEL0=1, SEL1=1, EN0=0, EN1=0) Dual Channel Switch (SEL0=1, SEL1=0, EN0=0, EN1=0) IN0+ OUT0+ IN0+ OUT0+ IN0- OUT0- IN0- OUT0- IN1+ OUT1+ IN1+ OUT1+ IN1- OUT1- IN1- OUT1- Single Channel Repeater (SEL0=0, SEL1=1, EN0=0, EN1=1) Single Channel Crossover Switch (SEL0=0, SEL1=0, EN0=1, EN1=0) IN0+ OUT0+ IN0+ OUT0+ IN0- OUT0- IN0- OUT0- IN1+ OUT1+ IN1+ OUT1+ IN1- OUT1- IN1- OUT1- Single Channel Crossover Switch (SEL0=1, SEL1=1, EN0=0, EN1=1) Single Channel Repeater (SEL0=0, SEL1=1, EN0=1, EN1=0) IN0+ OUT0+ IN0+ OUT0+ IN0- OUT0- IN0- OUT0- IN1+ OUT1+ IN1+ OUT1+ IN1- OUT1- IN1- OUT1- Figure 3. DS90CP02 Configuration Select Decode 4 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS90CP02 DS90CP02 www.ti.com SNLS267A – NOVEMBER 2008 – REVISED MARCH 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) Supply Voltage (VDD) −0.3V to +4.0V CMOS Input Voltage −0.3V to (VDD +0.3V) LVDS Receiver Input Voltage −0.3V to +3.6V LVDS Driver Output Voltage −0.3V to +3.6V LVDS Output Short Circuit Current 40mA Junction Temperature +150°C Storage Temperature −65°C to +150°C Lead Temperature (Soldering, 4sec.) +260°C Maximum Package Power Dissipation at 25°C UQFN-28 4.31 W Derating above 25°C UQFN-28 34.5 mW/°C Thermal Resistance, θJA UQFN-28 29°C/W ESD Rating (1) (2) HBM, 1.5 kΩ, 100 pF 6.5 kV EIAJ, 0Ω, 200 pF >250V “Absolute Maximum Ratings” are the ratings beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. Recommended Operating Conditions Supply Voltage (VDD– GND) Receiver Input Voltage Operating Free Air Temperature Min Typ Max Unit 3.0 3.3 3.6 V 3.6 V 85 °C 150 °C 0 −40 Junction Temperature 25 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS90CP02 5 DS90CP02 SNLS267A – NOVEMBER 2008 – REVISED MARCH 2013 www.ti.com Electrical Characteristics Over recommended operating supply and temperature ranges unless other specified. Symbol Parameter Conditions Min Typ (1) Max Units LVTTL DC SPECIFICATIONS (SEL0, SEL1, EN1, EN2) VIH High Level Input Voltage 2.0 VDD V VIL Low Level Input Voltage GND 0.8 V IIH High Level Input Current VIN = VDD = VDDMAX −10 +10 µA IIL Low Level Input Current VIN = VSS, VDD = VDDMAX −10 +10 µA CIN1 Input Capacitance Any Digital Input Pin to VSS VCL Input Clamp Voltage ICL = −18 mA −1.5 3.5 pF −0.8 V LVDS INPUT DC SPECIFICATIONS (IN0±, IN1±) (2) VTH Differential Input High Threshold VTL Differential Input Low Threshold VCM = 0.8V or 1.2V or 3.55V, VDD = 3.6V VCM = 0.8V or 1.2V or 3.55V, VDD = 3.6V 0 VID Differential Input Voltage VCM = 0.8V to 3.55V, VDD = 3.6V 100 VCMR Common Mode Voltage Range VID = 150 mV, VDD = 3.6V 0.05 CIN2 Input Capacitance IN+ or IN− to VSS IIN Input Current VIN = 3.6V, VDD = VDDMAX or 0V −10 +10 µA VIN = 0V, VDD = VDDMAX or 0V −10 +10 µA 575 mV 35 mV 1.475 V 35 mV -90 mA −100 100 0 mV mV mV 3.55 3.5 V pF LVDS OUTPUT DC SPECIFICATIONS (OUT0±, OUT1±) VOD Differential Output Voltage, 0% Pre-emphasis (2) RL = 100Ω between OUT+ and OUT− ΔVOD Change in VOD between Complementary States VOS Offset Voltage ΔVOS Change in VOS between Complementary States IOS Output Short Circuit Current, One Complementary Output OUT+ or OUT− Short to GND COUT Output Capacitance OUT+ or OUT− to GND when TRISTATE 5.5 All inputs and outputs enabled and active, terminated with differential load of 100Ω between OUT+ and OUT-. 42 60 mA 250 400 −35 (3) 1.09 1.25 −35 −60 pF SUPPLY CURRENT (Static) ICC0 Supply Current ICC1 Supply Current - one channel powered down Single channel crossover switch or single channel repeater modes (1 channel active, one channel in power down mode) 22 30 mA ICC2 Supply Current - one input powered down Splitter mode (One input powered down, both outputs active) 30 40 mA ICCZ TRI-STATE Supply Current Both input/output Channels in Power Down Mode 1.4 2.5 mA 70 150 215 ps 50 135 180 ps 0.5 2.4 3.5 ns 0.5 2.4 3.5 ns 55 120 ps SWITCHING CHARACTERISTICS—LVDS OUTPUTS (Figure 4, Figure 5) tLHT Differential Low to High Transition Time tHLT Differential High to Low Transition Time tPLHD Differential Low to High Propagation Delay tPHLD Differential High to Low Propagation Delay tSKD1 Pulse Skew (1) (2) (3) 6 Use an alternating 1 and 0 pattern at 200 Mb/s, measure between 20% and 80% of VOD. Use an alternating 1 and 0 pattern at 200 Mb/s, measure at 50% VOD between input to output. |tPLHD–tPHLD| Typical parameters are measured at VDD = 3.3V, TA = 25°C. They are for reference purposes, and are not production-tested. Differential output voltage VOD is defined as ABS(OUT+–OUT−). Differential input voltage VID is defined as ABS(IN+–IN−). Output offset voltage VOS is defined as the average of the LVDS single-ended output voltages at logic high and logic low states. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS90CP02 DS90CP02 www.ti.com SNLS267A – NOVEMBER 2008 – REVISED MARCH 2013 Electrical Characteristics (continued) Over recommended operating supply and temperature ranges unless other specified. Symbol tSKCC tJIT Parameter Output Channel to Channel Skew Jitter (4) Conditions Min Difference in propagation delay (tPLHD or tPHLD) among all output channels in Splitter mode (any one input to all outputs). 0 (1) Max Units 130 315 ps 1.4 2.5 psrms DJ - K28.5 Pattern 1.5 Gbps (6) 42 75 psp-p TJ - PRBS 223-1 Pattern 1.5 Gbps (7) 93 126 psp-p 110 150 ns 5 12 ns 110 150 ns RJ - Clock Pattern 750 MHz (5) tON LVDS Output Enable Time Time from ENx to OUT± change from TRI-STATE to active. tOFF LVDS Output Disable Time Time from ENx to OUT± change from active to TRI-STATE. tSW LVDS Switching Time SELx to OUT± Time from configuration select (SELx) to new switch configuration effective for OUT±. (4) (5) (6) (7) Typ 50 Jitter is not production tested, but guaranteed through characterization on a sample basis. Random Jitter, or RJ, is measured RMS with a histogram including 1500 histogram window hits. The input voltage = VID = 500mV, 50% duty cycle at 750MHz, tr = tf = 50ps (20% to 80%). Deterministic Jitter, or DJ, is measured to a histogram mean with a sample size of 350 hits. The input voltage = VID = 500mV, K28.5 pattern at 1.5 Gbps, tr = tf = 50ps (20% to 80%). The K28.5 pattern is repeating bit streams of (0011111010 1100000101). Total Jitter, or TJ, is measured peak to peak with a histogram including 3500 window hits. Stimulus and fixture jitter has been subtracted. The input voltage = VID = 500mV, 223-1 PRBS pattern at 1.5 Gbps, tr = tf = 50ps (20% to 80%). Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS90CP02 7 DS90CP02 SNLS267A – NOVEMBER 2008 – REVISED MARCH 2013 www.ti.com Timing Diagrams IN+ VOS=1.2V typical IN- IN+ VID IN- Figure 4. LVDS Signals (OUT+ - OUT-) 80% 80% 0V 20% 20% tLHT tHLT OUT+ VOD OUT- Figure 5. LVDS Output Transition Time (IN+ - IN-) 0.0V tPLHD tPHLD (OUT+ - OUT-) 0.0V Figure 6. LVDS Output Propagation Delay 8 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS90CP02 DS90CP02 www.ti.com SNLS267A – NOVEMBER 2008 – REVISED MARCH 2013 Load Configuration "A" Load Configuration "B" LOAD or SELx tSW tSW OUT± Configuration "B" Configuration "A" tOFF tON 50% OUT+ 50% 1.2V 1.2V OUT- 50% 50% Figure 7. Configuration and Output Enable/Disable Timing Typical Performance Total Jitter (TJ) vs. Bit Data Rate 120 Total Jitter (TJ) vs. Temperature 120 VCM = 0.5V 115 100 110 80 60 VCM = 2.4V 40 TOTAL JITTER (ps) TOTAL JITTER (ps) VCM = 1.2V 105 100 VCM = 3.1V 95 90 85 20 80 0 0.5 0.7 0.9 1.1 1.3 75 -40 1.5 -20 0 20 40 60 80 TEMPERATURE (°C) BIT DATA RATE (Gbps) Total Jitter measured at 0V differential while running a PRBS 223-1 pattern in single channel repeater mode. VCC = 3.3V, TA = +25°C, VID = 0.5V Figure 8. Total Jitter measured at 0V differential while running a PRBS 223-1 pattern in dual channel repeater mode. VCC = 3.3V, VID = 0.5V, VCM = 1.2V, 1.5 Gbps data rate Figure 9. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS90CP02 9 DS90CP02 SNLS267A – NOVEMBER 2008 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Original (March 2013) to Revision A • 10 Page Changed layout of National Data Sheet to TI format ............................................................................................................ 9 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS90CP02 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) DS90CP02SP/NOPB ACTIVE UQFN NJD 28 1000 RoHS & Green SN Level-3-260C-168 HR -40 to 85 CP02SP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of