DS90LV028ATMX

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents DS90LV028A SNLS013F – JUNE 1998 – REVISED JUNE 2016 DS90LV028A 3-V LVDS Dual CMOS Differential Line Receiver 1 Features 3 Description • • • • • • • • • • The DS90LV028A is a dual CMOS differential line receiver designed for applications requiring ultra low power dissipation, low noise and high data rates. The device is designed to support data rates in excess of 400-Mbps (200 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology. 1 • • • • >400-Mbps (200 MHz) Switching Rates 50-ps Differential Skew (Typical) 0.1-ns Channel-to-Channel Skew (Typical) 2.5-ns Maximum Propagation Delay 3.3-V Power Supply Design Flow-Through Pinout Power Down High Impedance on LVDS Inputs Low Power Design (18 mW at 3.3-V static) Interoperable with Existing 5-V LVDS Networks Accepts Small Swing (350 mV Typical) Differential Signal Levels Supports Open, Short and Terminated Input FailSafe Conforms to ANSI/TIA/EIA-644 Standard Industrial Temperature Operating Range: −40°C to 85°C Available in SOIC and Space Saving WSON Package 2 Applications • • • • The DS90LV028A accepts low voltage (350 mV typical) differential input signals and translates them to 3-V CMOS output levels. The receiver also supports open, shorted and terminated (100 Ω) input fail-safe. The receiver output is HIGH for all fail-safe conditions. The DS90LV028A has a flow-through design for easy PCB layout. The DS90LV028A and companion LVDS line driver provide a new alternative to high power PECL/ECL devices for high speed point-to-point interface applications. Device Information(1) PART NUMBER DS90LV028A PACKAGE BODY SIZE (NOM) SOIC (8) 4.90 mm × 3.91 mm WSON (8) 4.00 mm × 4.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Multi-Function Printers LVDS-to-LVCMOS Translation Building and Factory Automation Grid Infrastructure Functional Diagram RIN 1± R ROUT1 R ROUT2 RIN 1+ RIN 2± RIN 2+ Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DS90LV028A SNLS013F – JUNE 1998 – REVISED JUNE 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 4 4 4 4 5 5 6 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics .......................................... Typical Characteristics .............................................. Parameter Measurement Information .................. 9 Detailed Description ............................................ 10 8.1 Overview ................................................................. 10 8.2 Functional Block Diagram ....................................... 10 8.3 Feature Description................................................. 10 8.4 Device Functional Modes........................................ 11 9 Application and Implementation ........................ 12 9.1 Application Information .......................................... 12 9.2 Typical Application .................................................. 12 10 Power Supply Recommendations ..................... 14 11 Layout................................................................... 14 11.1 Layout Guidelines ................................................. 14 11.2 Layout Examples................................................... 15 12 Device and Documentation Support ................. 16 12.1 12.2 12.3 12.4 12.5 12.6 Documentation Support ........................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 16 16 16 16 16 16 13 Mechanical, Packaging, and Orderable Information ........................................................... 16 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (April 2013) to Revision F Page • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................................................................................................. 1 • Added Thermal Information values......................................................................................................................................... 4 Changes from Revision D (April 2013) to Revision E • 2 Page Changed layout of National Semiconductor Data Sheet to TI format .................................................................................... 1 Submit Documentation Feedback Copyright © 1998–2016, Texas Instruments Incorporated Product Folder Links: DS90LV028A DS90LV028A www.ti.com SNLS013F – JUNE 1998 – REVISED JUNE 2016 5 Pin Configuration and Functions D Package 8-Pin SOIC Top View NGN Package 8-Pin WSON Top View Pin Functions PIN NAME NO. I/O DESCRIPTION GND 5 — RIN+ 2, 3 I Ground pin Noninverting receiver input pin RIN– 1, 4 I Inverting receiver input pin ROUT 6, 7 O Receiver output pin VCC 8 — Power supply pin, 3.3 V ±0.3 V Submit Documentation Feedback Copyright © 1998–2016, Texas Instruments Incorporated Product Folder Links: DS90LV028A 3 DS90LV028A SNLS013F – JUNE 1998 – REVISED JUNE 2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT Supply voltage, VCC –0.3 4 V Input voltage, RIN+, RIN− –0.3 3.9 V Output voltage, ROUT –0.3 VCC + 0.3 V 1025 mW 8.2 mW/°C above 25°C °C 3.3 W 25.6 mW/°C above 25°C °C Lead temperature range, soldering (4 s) 260 °C Junction temperature, TJ 150 °C 150 °C D package Derate D package Maximum package power dissipation at 25°C NGN package Derate NGN package Storage temperature, Tstg (1) –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) UNIT ±7000 Machine model (MM) (2) V ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. EIAJ, 0 Ω, 200 pF 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) VCC Supply voltage Receiver input voltage TA MIN NOM MAX 3 3.3 3.6 3 V 25 85 °C GND Operating free-air temperature –40 UNIT V 6.4 Thermal Information DS90LV028A THERMAL METRIC (1) Low-K thermal resistance D (SOIC) NGN (WSON) 8 PINS 8 PINS — 35.9 212 — UNIT RθJA Junction-to-ambient thermal resistance 122 — RθJC(top) Junction-to-case (top) thermal resistance 69.1 24.2 °C/W RθJB Junction-to-board thermal resistance 47.7 13.2 °C/W ψJT Junction-to-top characterization parameter 15.2 0.2 °C/W ψJB Junction-to-board characterization parameter 47.2 13.3 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance — 2.9 °C/W High-K thermal resistance (1) 4 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 1998–2016, Texas Instruments Incorporated Product Folder Links: DS90LV028A DS90LV028A www.ti.com SNLS013F – JUNE 1998 – REVISED JUNE 2016 6.5 Electrical Characteristics over operating free-air temperature range (unless otherwise noted) (1) PARAMETER TEST CONDITIONS MIN (3) VTH Differential input high threshold VCM = 1.2 V, 0 V, 3 V, RIN+, RIN− pins VTL Differential input low threshold VCM = 1.2 V, 0 V, 3 V, RIN+, RIN− pins (3) IIN VCC = 3.6 V or 0 V, RIN+, RIN− pins Input current TYP (2) MAX UNIT 100 mV –100 mV VIN = 2.8 V –10 ±1 10 VIN = 0 V –10 ±1 10 VCC = 0 V, VIN = 3.6 V, RIN+, RIN− pins –20 IOH = –0.4 mA, VID = 200 mV, ROUT pin 2.7 3.1 IOH = –0.4 mA, inputs terminated, ROUT pin 2.7 3.1 IOH = –0.4 mA, inputs shorted, ROUT pin 2.7 3.1 μA 20 VOH Output high voltage VOL Output low voltage IOL = 2 mA, VID = –200 mV, ROUT pin 0.3 0.5 IOS Output short-circuit current VOUT = 0 V, ROUT pin (4) –15 –50 –100 mA VCL Input clamp voltage ICL = –18 mA, ROUT pin –1.5 –0.8 ICC No load supply current VCC pin, inputs open 9 mA (1) (2) (3) (4) 5.4 V V V Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground unless otherwise specified (such as VID). All typicals are given for: VCC = 3.3 V and TA = 25°C. VCC is always higher than RIN+ and RIN− voltage. RIN+ and RIN− are allowed to have voltage range –0.05 V to 3.05 V. VID is not allowed to be greater than 100 mV when VCM = 0 V or 3 V. Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output must be shorted at a time, do not exceed maximum junction temperature specification. 6.6 Switching Characteristics VCC = 3.3 V ±10%, and TA = −40°C to 85°C (unless otherwise noted) (1) (2) MIN TYP MAX tPHLD Differential propagation delay high to low PARAMETER CL = 15 pF TEST CONDITIONS 1 1.6 2.5 UNIT ns tPLHD Differential propagation delay low to high VID = 200 mV 1 1.7 2.5 ns tSKD1 Differential pulse skew |tPHLD − tPLHD| (3) See Figure 18 and Figure 19 0 50 400 ps tSKD2 Differential channel-to-channel skew-same device (4) 0 0.1 0.5 ns tSKD3 Differential part to part skew (5) 0 1 ns tSKD4 Differential part to part skew (6) 0 1.5 ns tTLH Rise Time 325 800 ps tTHL Fall Time 225 800 fMAX Maximum operating frequency (7) (1) (2) (3) (4) (5) (6) (7) 200 250 ps MHz CL includes probe and jig capacitance. Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50 Ω, tr and tf (0% to 100%) ≤ 3 ns for RIN. tSKD1 is the magnitude difference in differential propagation delay time between the positive-going-edge and the negative-going-edge of the same channel. tSKD2 is the differential channel-to-channel skew of any event on the same device. This specification applies to devices having multiple receivers within the integrated circuit. tSKD3, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range. tSKD4, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over the recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Maximum − Minimum| differential propagation delay. fMAX generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, differential (1.05V to 1.35 peak to peak). Output criteria: 60%/40% duty cycle, VOL (max 0.4V), VOH (min 2.7V), load = 15 pF (stray plus probes). Submit Documentation Feedback Copyright © 1998–2016, Texas Instruments Incorporated Product Folder Links: DS90LV028A 5 DS90LV028A SNLS013F – JUNE 1998 – REVISED JUNE 2016 www.ti.com 6.7 Typical Characteristics 6 Figure 1. Output High Voltage vs Power Supply Voltage Figure 2. Output Low Voltage vs Power Supply Voltage Figure 3. Output Short Circuit Current vs Power Supply Voltage Figure 4. Differential Transition Voltage vs Power Supply Voltage Figure 5. Power Supply Current vs Ambient Temperature Figure 6. Differential Propagation Delay vs Power Supply Voltage Submit Documentation Feedback Copyright © 1998–2016, Texas Instruments Incorporated Product Folder Links: DS90LV028A DS90LV028A www.ti.com SNLS013F – JUNE 1998 – REVISED JUNE 2016 Typical Characteristics (continued) Figure 7. Differential Propagation Delay vs Ambient Temperature Figure 8. Differential Skew vs Power Supply Voltage Figure 9. Differential Skew vs Ambient Temperature Figure 10. Differential Propagation Delay vs Common Mode Voltage Figure 11. Differential Propagation Delay vs Differential Input Voltage Figure 12. Transition Time vs Power Supply Voltage Submit Documentation Feedback Copyright © 1998–2016, Texas Instruments Incorporated Product Folder Links: DS90LV028A 7 DS90LV028A SNLS013F – JUNE 1998 – REVISED JUNE 2016 www.ti.com Typical Characteristics (continued) Figure 13. Transition Time vs Ambient Temperature Figure 14. Differential Propagation Delay vs Load Figure 15. Transition Time vs Load Figure 16. Differential Propagation Delay vs Load Figure 17. Transition Time vs Load 8 Submit Documentation Feedback Copyright © 1998–2016, Texas Instruments Incorporated Product Folder Links: DS90LV028A DS90LV028A www.ti.com SNLS013F – JUNE 1998 – REVISED JUNE 2016 7 Parameter Measurement Information Figure 18. Receiver Propagation Delay and Transition Time Test Circuit Figure 19. Receiver Propagation Delay and Transition Time Waveforms Submit Documentation Feedback Copyright © 1998–2016, Texas Instruments Incorporated Product Folder Links: DS90LV028A 9 DS90LV028A SNLS013F – JUNE 1998 – REVISED JUNE 2016 www.ti.com 8 Detailed Description 8.1 Overview LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as is shown in Figure 20. This configuration provides a clean signaling environment for the fast edge rates of the drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair cable, a parallel pair cable, or simply PCB traces. Typically, the characteristic impedance of the media is in the range of 100 Ω. A termination resistor of 100 Ω (selected to match the media), and is placed as close to the receiver input pins as possible. The termination resistor converts the driver output (current mode) into a voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as ground shifting, noise margin limits, and total termination loading must be considered. 8.2 Functional Block Diagram RIN 1± R ROUT1 R ROUT2 RIN 1+ RIN 2± RIN 2+ Copyright © 2016, Texas Instruments Incorporated 8.3 Feature Description The DS90LV028A differential line receiver is capable of detecting signals as low as 100 mV, over a ±1-V common mode range centered around 1.2 V. This is related to the driver offset voltage which is typically 1.2 V. The driven signal is centered around this voltage and may shift ±1 V around this center point. The ±1-V shifting may be the result of a ground potential difference between the driver's ground reference and the receiver's ground reference, the common mode effects of coupled noise, or a combination of the two. The AC parameters of both receiver input pins are optimized for a recommended operating input voltage range of 0 V to 2.4 V (measured from each pin to ground). The device operates for receiver input voltages up to VCC, but exceeding VCC turns on the ESD protection circuitry which clamps the bus voltages. 10 Submit Documentation Feedback Copyright © 1998–2016, Texas Instruments Incorporated Product Folder Links: DS90LV028A DS90LV028A www.ti.com SNLS013F – JUNE 1998 – REVISED JUNE 2016 Feature Description (continued) 8.3.1 Fail-Safe Feature The LVDS receiver is a high gain, high speed device that amplifies a small differential signal (20 mV) to CMOS logic levels. Due to the high gain and tight threshold of the receiver, take care to prevent noise from appearing as a valid signal. The internal fail-safe circuitry of the receiver is designed to source or sink a small amount of current, providing fail-safe protection (a stable known state of HIGH output voltage) for floating, terminated or shorted receiver inputs. 1. Open Input Pins: The DS90LV028A is a dual receiver device, and if an application requires only 1 receiver, the unused channel inputs must be left OPEN. Do not tie unused receiver inputs to ground or any other voltages. The input is biased by internal high value pull up and pull down resistors to set the output to a HIGH state. This internal circuitry ensures a HIGH, stable output state for open inputs. 2. Terminated Input: If the driver is disconnected (cable unplugged), or if the driver is in a power-off condition, the receiver output is again in a HIGH state, even with the end of cable 100Ω termination resistor across the input pins. The unplugged cable can become a floating antenna which can pick up noise. If the cable picks up more than 10 mV of differential noise, the receiver may see the noise as a valid signal and switch. To insure that any noise is seen as common mode and not differential, a balanced interconnect must be used. Twisted pair cable offers better balance than flat ribbon cable. 3. Shorted Inputs: If a fault condition occurs that shorts the receiver inputs together, thus resulting in a 0 V differential input voltage, the receiver output remains in a HIGH state. Shorted input fail-safe is not supported across the common mode range of the device (GND to 2.4 V). It is only supported with inputs shorted and no external common mode voltage applied. External lower value pull up and pull down resistors (for a stronger bias) may be used to boost fail-safe in the presence of higher noise levels. The pull up and pull down resistors must be in the 5-kΩ to 15-kΩ range to minimize loading and waveform distortion to the driver. The common mode bias point must be set to approximately 1.2 V (less than 1.75 V) to be compatible with the internal circuitry. Refer to AN-1194 Failsafe Biasing of LVDS Interfaces (SNLA051) for more information. 8.3.2 Cables and Connectors When choosing cable and connectors for LVDS it is important to remember: Use controlled impedance media. The cables and connectors you use must have a matched differential impedance of about 100 Ω. They must not introduce major impedance discontinuities. Balanced cables (for example, twisted pair) are usually better than unbalanced cables (ribbon cable, simple coax) for noise reduction and signal quality. Balanced cables tend to generate less EMI due to field canceling effects and also tend to pick up electromagnetic radiation a common mode (not differential mode) noise which is rejected by the receiver. For cable distances < 0.5 M, most cables can be made to work effectively. For distances 0.5 M ≤ d ≤ 10 M, CAT 3 (category 3) twisted pair cable works well, is readily available, and relatively inexpensive. 8.4 Device Functional Modes Table 1 lists the functional modes of the DS90LV028A. Table 1. Truth Table INPUTS OUTPUT [RIN+] − [RIN−] ROUT VID ≥ 0.1 V H VID ≤ −0.1 V L Full fail-safe OPEN/SHORT or Terminated H Submit Documentation Feedback Copyright © 1998–2016, Texas Instruments Incorporated Product Folder Links: DS90LV028A 11 DS90LV028A SNLS013F – JUNE 1998 – REVISED JUNE 2016 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The DS90LV028A has a flow-through pinout that allows for easy PCB layout. The LVDS signals on one side of the device easily allows for matching electrical lengths of the differential pair trace lines between the driver and the receiver as well as allowing the trace lines to be close together to couple noise as common mode. Noise isolation is achieved with the LVDS signals on one side of the device and the TTL signals on the other side. 9.2 Typical Application Any LVDS Driver Data Input ½ DS90LV028A RT 100 Ÿ + Data Output ± Copyright © 2016, Texas Instruments Incorporated Figure 20. Point-to-Point Application 9.2.1 Design Requirements When using LVDS devices, it is important to remember to specify controlled impedance PCB traces, cable assemblies, and connectors. All components of the transmission media must have a matched differential impedance of about 100 Ω. They must not introduce major impedance discontinuities. Balanced cables (for example, twisted pair) are usually better than unbalanced cables (ribbon cable) for noise reduction and signal quality. Balanced cables tend to generate less EMI due to field canceling effects and also tend to pick up electromagnetic radiation as common mode (not differential mode) noise which is rejected by the LVDS receiver. For cable distances < 0.5 M, most cables can be made to work effectively. For distances 0.5 M ≤ d ≤ 10 M, CAT5 (Category 5) twisted pair cable works well, is readily available, and relatively inexpensive. 9.2.2 Detailed Design Procedure 9.2.2.1 Probing LVDS Transmission Lines Always use high impedance (>100 kΩ), low capacitance (