DS90UA101TRTVTQ1

DS90UA101-Q1 www.ti.com SNLS441A – JULY 2013 – REVISED SEPTEMBER 2013 DS90UA101-Q1 Multi-Channel Digital Audio Link Check for Samples: DS90UA101-Q1 FEATURES APPLICATIONS • • • • • 1 • • • • • • • • • • • • • • Digital Audio Serializer Flexible Digital Audio Inputs, supporting I2S (Stereo) or TDM (Multi-Channel) Formats Coaxial or Single Differential Pair Interconnect High Speed Serial Output Interface Very Low Latency (ƒ/40, ƒ = 10 MHz – 50 MHz Units 0.1 ns T The Electrical Characteristics tables list verified specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not verified. Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD, ΔVOD, VTH and VTL which are differential voltages. Typical values represent most likely parametric norms at 1.8V or 3.3V, TA = +25°C, and at the Recommended Operation Conditions at the time of product characterization and are not verified. Recommended Input Timing Requirements are input specifications and not tested in production. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DS90UA101-Q1 9 DS90UA101-Q1 SNLS441A – JULY 2013 – REVISED SEPTEMBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS: Serializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2) (3) Typ Max Units tLHT Symbol CML Low-to-High Transition Time Parameter RL = 100Ω (Figure 6) 150 330 ps tHLT CML High-to-Low Transition Time RL = 100Ω (Figure 6) 150 330 ps tDIS Data Input Setup to SCK tDIH Data Input Hold from SCK Serializer Data Inputs (Figure 10) tPLD Serializer PLL Lock Time tSD Serializer Delay tJIND (5) Serializer Output Deterministic Jitter Conditions RL = 100Ω Min 2 ns 2 ns (4) (5) , (Figure 11) RT = 100Ω Register 0x03h b[0] (TRFB = 1) (Figure 12) Serializer output intrinsic deterministic jitter . Measured (cycle-cycle) with PRBS-7 test pattern 11.75T 1 2 ms 13T 15T ns 0.13 UI 0.04 UI 0.396 UI (3) (6) tJINR tJINT Serializer Output Random Jitter Serializer output intrinsic random jitter (cycle-cycle). Alternating-1,0 pattern. Peak-to-peak Serializer Output Jitter Serializer output peak-to-peak jitter includes deterministic jitter, random jitter, and jitter transfer from Serializer input. Measured (cycle-cycle) with PRBS-7 test pattern. (3) (6) (3) (6) λSTXBW Serializer Jitter Transfer Function -3 dB Bandwidth (7) SCK = 50MHz 2.2 δSTX Serializer Jitter Transfer Function (Peaking) (7) SCK = 50MHz 1.16 δSTXf Serializer Jitter Transfer Function (Peaking Frequency) (7) SCK = 50MHz 600 (1) (2) (3) (4) (5) (6) (7) 10 MHz dB kHz The Electrical Characteristics tables list verified specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not verified. Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD, ΔVOD, VTH and VTL which are differential voltages. Typical values represent most likely parametric norms at 1.8V or 3.3V, TA = +25°C, and at the Recommended Operation Conditions at the time of product characterization and are not verified. tPLD and tDDLT is the time required by the Serializer and Deserializer to obtain lock when exiting power-down state with an active SCK. Specification is verified by design. UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with SCK frequency. Specification is by characterization and is not tested in production. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DS90UA101-Q1 DS90UA101-Q1 www.ti.com SNLS441A – JULY 2013 – REVISED SEPTEMBER 2013 BIDIRECTIONAL CONTROL BUS TIMING SPECIFICATIONS Bidirectional Control Bus: AC Timing Specifications (SCL, SDA) - I2C Compliant Over recommended supply and temperature ranges unless otherwise specified. (Figure 4) Symbol Parameter Conditions Min Typ Max Units Standard Mode 100 kHz Fast Mode 400 kHz Recommended Input Timing Requirements fSCL SCL Clock Frequency tLOW SCL Low Period Standard Mode 4.7 µs Fast Mode 1.3 µs Standard Mode 4.0 µs tHIGH SCL High Period Fast Mode 0.6 µs tHD:STA Hold time for a start or a repeated start condition Standard Mode 4.0 µs Fast Mode 0.6 µs tSU:STA Set Up time for a start or a repeated start condition Standard Mode 4.7 µs Fast Mode 0.6 tHD:DAT Data Hold Time tSU:DAT Data Set Up Time tSU:STO Set Up Time for STOP Condition tBUF Bus Free time between Stop and Start tr SCL & SDA Rise Time tf SCL & SDA Fall Time µs Standard Mode 0 3.45 µs Fast Mode 0 900 ns Standard Mode 250 Fast Mode 100 ns ns Standard Mode 4.0 µs Fast Mode 0.6 µs Standard Mode 4.7 µs Fast Mode 1.3 µs Standard Mode 1000 ns Fast Mode 300 ns Standard Mode 300 ns Fast Mode 300 ns Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DS90UA101-Q1 11 DS90UA101-Q1 SNLS441A – JULY 2013 – REVISED SEPTEMBER 2013 www.ti.com Bidirectional Control Bus: DC Timing Specifications (SCL, SDA) - I2C Compliant (1) Over recommended supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units VDDIO V Recommended Input Timing Requirements VIH Input High Level SDA and SCL 0.7*VDDIO VIL Input Low Level SDA and SCL GND VHY Input Hysteresis VOL Output Low Level SDA, IOL=0.5mA IIN Input Current SDA or SCL, VIN=VDDIO OR GND tR SDA Rise Time-READ 430 ns tF SDA Fall Time-READ SDA, RPU = 10kΩ, Cb ≤ 400pF(Figure 4) 20 ns tSU;DAT (Figure 4) 560 ns tHD;DAT (Figure 4) 615 ns tSP CIN (1) 12 0.3*VDDIO >50 SDA or SCL 0 -10 V mV 0.4 V 10 µA 50 ns DES A --> DSP. • If Master transmits an I2C transaction for address 0xA0, then DES A with I2C pass-through enabled will transfer that I2C command to SER A, which will then transfer it to remote slave Device A. Responses from Device A will travel from Device A --> SER A --> DES A --> DSP. • As for DES B with I2C pass-through disabled, any I2C commands for SER B or Device B will NOT be passed on the I2C bus to SER B/Device B. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DS90UA101-Q1 27 DS90UA101-Q1 SNLS441A – JULY 2013 – REVISED SEPTEMBER 2013 www.ti.com Serializer A Digital Audio Source DIN[7:0], BCK,LRCK SCK SDA SCL Device A Remote Slave ID: (0xA0) DOUT[7:0], BCK,LRCK, SCK I2C SER A: Remote I2C Master Proxy Serializer B Digital Audio Source Deserializer A I2C DES A: Local I2C Slave Pass-Through Enabled Device B Remote Slave ID: (0xA0) DSP Deserializer B DIN[7:0], BCK,LRCK SCK SDA SCL SDA SCL DOUT[7:0], BCK,LRCK, SCK I2C SER B: Remote I2C Master Proxy I2C SDA SCL DES B: Local I2C Slave Pass-Through Disabled Master Figure 25. I2C Pass-Through To setup I2C pass-through on the Serializer, set 0x03[2] = 1 and configure registers 0x06, 0x07, 0x08, and 0x09 as needed (Deserializer I2C ID, Deserializer Alias ID, remote slave I2C ID, remote slave Alias ID, respectively). Refer to Multiple Device Addressing for information about Alias IDs and refer to DS90UA101-Q1 REGISTER INFORMATION for information to set these registers. To communicate with the remote Deserializer from the Serializer side, registers 0x06 and 0x07 must be configured (register 0x06 is auto-loaded by default if there is LOCK). To communicate with the remote slave connected to the remote Deserializer, configure registers 0x08 and 0x09. To setup I2C pass-through on the Deserializer, set 0x03[3] = 1 and configure registers 0x06 - 0x17 as needed. To communicate with the remote Serializer from the Deserializer side, registers 0x06 and 0x07 must be configured (register 0x06 is auto-loaded by default if there is LOCK). To communicate with one or more remote slaves connected to the remote Serializer, configure 0x08 - 0x17 accordingly. Multiple Device Addressing Some applications require multiple devices with the same fixed address to be accessed on the same I2C bus. The DS90UA101-Q1/DS90UA102-Q1 provides slave ID aliasing to generate different target slave addresses when connecting two or more identical devices remotely. Instead of addressing their actual I2C addresses, each remote device can be addressed through a unique alias ID by programming the Slave Alias ID register on the Serializer/Deserializer. By addressing the Slave Alias IDs, I2C slaves with identical, fixed addresses can now be addressed independently. On the DS90UA101-Q1, up to 1 Slave Alias ID index is supported. On the DS90UA102-Q1, up to 8 Slave Alias IDs can be supported. The Audio Module/DSP (I2C Master) must keep track of the alias list in order to properly address the correct device. Refer to Figure 26 for an example of this function: • There is a local I2C bus between Audio Module, DES A, and DES B. Audio Module is the I2C Master, and DES A and DES B are I2C slaves. • The I2C protocol is bridged from DES A to SER A and from DES B to SER B. SER A is the master of its own local I2C bus, and Source A and its µC/EEPROM are slaves on this bus. SER B is also the master of its local I2C bus, and Source B and its µC/EEPROM are the slaves. • Audio Module can now address remote slaves connected to SER A and SER B independently. • Case 1: If Audio Module transmits to I2C slave 0xA0, DES A (address 0xC0) will forward the transaction to SER A, which then forwards it to remote slave Source A. Responses from Source A will travel from Source A --> SER A --> DES A --> Audio Module. • Case 2: If Audio Module transmits to slave address 0xA4, DES B (address 0xC2) will recognize that 0xA4 is mapped to 0xA0 and will transmit the command to SER B, which then forwards it to remote slave Source B. 28 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DS90UA101-Q1 DS90UA101-Q1 www.ti.com • SNLS441A – JULY 2013 – REVISED SEPTEMBER 2013 Responses from Source B will travel from Source B --> SER B --> DES B --> Audio Module. Case 3: If Audio Module sends command to address 0xA6, DES B (address 0xC2) will forward the transaction to SER B, which then forwards it to Source B's µC/EEPROM. Responses from Source B's µC/EEPROM will travel from Source B's µC/EEPROM --> SER B --> DES B --> Audio Module. Source A Serializer A Slave ID: (0xA0) Digital Audio Source DIN[7:0], BCK, LRCK, SCK DOUT[7:0], BCK, LRCK, SCK 2 SDA SCL I C SER A: ID[x] (0xB0) PC/ EEPROM Slave ID: (0xA2) Source B Serializer B Slave ID: (0xA0) Digital Audio Source Deserializer A DES A: ID[x] (0xC0) SLAVE ID0 (0xA0) SLAVE ALIAS ID0 (0xA0) SLAVE ID1 (0xA2) SLAVE ALIAS ID1 (0xA2) PC/ EEPROM Slave ID: (0xA2) Audio Module Deserializer B DOUT[7:0], BCK, LRCK, SCK DIN[7:0], BCK, LRCK, SCK SDA SCL SDA SCL 2 I C 2 I C SER B: ID[x] (0xB2) 2 I C SDA SCL DES B: ID[x] (0xC2) SLAVE ID0 (0xA0) SLAVE ALIAS ID0 (0xA4) SLAVE ID1 (0xA2) SLAVE ALIAS ID1 (0xA6) DSP Master Figure 26. Multiple Device Addressing NOTE The alias ID must be set in order to communicate with any remote device. For example: • When there is only one SER/DES pair and no remote slaves: if I2C Master on the DES side wants to communicate with the remote SER, I2C pass-through must be enabled on the DES and the SER Alias ID must also be set before the I2C Master can communicate with the remote SER (the SER ID is automatically configured by default if there is LOCK). • When there is only one SER/DES pair and one remote slave connected to the SER: if I2C Master on the DES side (with pass-through enabled) wants to communicate with the remote slave, the Slave ID and Slave Alias ID must be set before the I2C Master can communicate with the remote slave, even if there is only one remote slave. Slave Clock Stretching To communicate and synchronize with remote devices on the I2C bus through the Bidirectional Control Channel, the chipset utilizes bus clock stretching (holding the SCL line low) during data transmission. On the 9th clock of every I2C transfer (before the ACK signal), the local I2C slave pulls the SCL line low until a response is received from the remote I2C bus located on the other end of the serial interface. The slave device will not control the clock and only stretches it until the remote peripheral has responded. The I2C Master must support slave clock stretching in order to communicate with remote devices. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DS90UA101-Q1 29 DS90UA101-Q1 SNLS441A – JULY 2013 – REVISED SEPTEMBER 2013 www.ti.com General Purpose Inputs, Outputs (GPIs, GPOs, GPIOs) Descriptions There are 4 dedicated general purpose inputs (GPIs) on the DS90UA101-Q1 and 4 dedicated general purpose outputs (GPOs) on the DS90UA102-Q1. Inputs to the GPI pins on the Serializer are fed to the GPO outputs on the Deserializer. The maximum GPI data rate is defined by the SCK source (up to 50 Mbps). In addition, there are also 4 GPOs on the DS90UA101-Q1 and 4 GPIOs on the DS90UA102-Q1. The GPOs on the Serializer can be configured as outputs for the input signals that are fed into the Deserializer GPIOs. The GPIO maximum data rate is up to 66 kbps when configured for communication between Deserializer GPIO to Serializer GPO. Both the GPOs on the Serializer and GPIOs on the Deserializer can also behave as outputs whose values are set from local registers. LVCMOS VDDIO Option 1.8V/3.3V Serializer inputs are user configurable to provide compatibility with 1.8V and 3.3V system interfaces. Power Up Requirements and PDB Pin The Serializer is active when the PDB pin is driven HIGH. Driving the PDB pin LOW powers down the device and clears all control register configurations to default values. The PDB pin must be held low until the power supplies (VDDn and VDDIO) have settled to the recommended operating voltage. This can be done by driving PDB externally, or an RC network can be connected to the PDB pin to ensure PDB arrives after all the power supplies have stabilized. Powerdown The PDB pin's function on the Serializer is to ENABLE or powerdown the device. This pin can be controlled by the system and can be used to disable the SER to save power. If PDB = HIGH, the SER will lock to the valid input SCK and transmit data to the DES by sending a serial stream at 28 times the SCK frequency. If SCK is idle or missing, the SER will output a serial stream based on its internal oscillator frequency (Table 1). When PDB = LOW, the high-speed driver outputs are static HIGH. SCK Clock Edge Select (TRFB) The TRFB selects which edge of the input clock is used to latch input data. If TRFB register is 1, data is latched on the rising edge of the SCK. If TRFB register is 0, data is latched on the falling edge of the SCK. SCK DIN TRFB: 0 TRFB: 1 Figure 27. Programmable SCK Strobe Select Built In Self Test (BIST) An optional at-speed built in self test (BIST) feature supports the testing of the high speed serial link and lowspeed back channel. This is useful in the prototype stage, equipment production, and in-system test and also for system diagnostics. BIST Configuration and Status The DS90UA101-Q1/DS90UA102-Q1 chipset can be programmed into BIST mode using either pins or registers. By default BIST configuration is controlled through pins on the DS90UA102-Q1. BIST can also be configured via registers using BIST Control Register 0x24 on the DS90UA102-Q1. Pin based configuration is defined as follows: • BISTEN (on DS90UA102-Q1) = HIGH: Enable the BIST mode, BISTEN = LOW: Disable the BIST mode. • GPIO3 and GPIO2 of DS90UA102-Q1: Defines the BIST clock source (SCK vs. various internal oscillator frequencies). See Table 3 below. 30 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DS90UA101-Q1 DS90UA101-Q1 www.ti.com SNLS441A – JULY 2013 – REVISED SEPTEMBER 2013 Table 3. BIST Pin Configuration on DS90UA102-Q1 Deserializer (1) (1) DS90UA102-Q1 Deserializer GPIO[3:2] Oscillator Source BIST Frequency (MHz) 00 External SCK 01 Internal ~25 10 Internal ~50 11 Internal ~12.5 Note: These pin settings will only be active when 0x24[3] = 1 and BIST is on. The BIST mode provides various options for the clock source. Either external pins (GPIO3 and GPIO2 of DES) or register 0x24 on DES can be used to configure the BIST to use SCK or various internal oscillator frequencies as the clock source. Refer to Table 4 below for BIST register settings. Table 4. BIST Register Configuration on DS90UA102-Q1 Deserializer (1) (1) DS90UA102-Q1 Deserializer 0x24[2:1] Oscillator Source BIST Frequency (MHz) 00 External SCK 01 Internal ~50 10 Internal ~25 11 Internal ~12.5 Note: These register settings will only be active when 0x24[3] = 0 and BIST is on. The BIST status can be monitored real-time on the PASS pin. For every frame with error(s), the PASS pin toggles low momentarily. If two consecutive frames have errors, PASS will toggle twice to allow counting of frames with errors. Once the BIST is done, the PASS pin reflects the pass/fail status momentarily (pass = no errors, fail = one or more errors). The BIST result can also be read through I2C for the number of frames that errored. The status register retains results until it is reset by a new BIST session or a device reset. For all practical purposes, the BIST status can be monitored from the BIST Error Count register 0x25 on the DS90UA102-Q1 Deserializer. Sample BIST Sequence (Refer to Figure 28) Step 1: BIST mode is enabled via the BISTEN pin on the DS90UA102-Q1 Deserializer, or through the Deserializer control registers. The clock source is selected through the GPIO3 and GPIO2 pins as shown in Table 3. Step 2: The DS90UA101-Q1 Serializer BIST start command is activated through the back channel. Step 3: The BIST pattern is generated and sent through the serial interface to the Deserializer. Once the Serializer and Deserializer are in the BIST mode and the Deserializer acquires LOCK, the PASS pin of the Deserializer goes high and BIST starts checking the data stream. If an error in the payload is detected the PASS pin will switch low momentarily. During the BIST test, the PASS output can be monitored and counted to determine the payload error rate. Step 4: To stop the BIST mode, the Deserializer BISTEN pin is set low and the Deserializer stops checking the data. The final test result is not maintained on the PASS pin. To check the number of BIST errors, check the BIST Error Count register, 0x25 on the Deserializer. The link returns to normal operation after the Deserializer BISTEN pin is low. Figure 29 below shows the waveform diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2 shows one with multiple errors. In most cases, it is difficult to generate errors due to the robustness of the link (differential data transmission, adaptive equalization, etc.), thus they may be introduced by greatly extending the cable length, increasing the frequency, or by reducing signal condition enhancements (Rx equalization). Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DS90UA101-Q1 31 DS90UA101-Q1 SNLS441A – JULY 2013 – REVISED SEPTEMBER 2013 www.ti.com Normal Step 1: DES in BIST BIST Wait Step 2: Wait, SER in BIST BIST start Step 3: SER/DES in BIST ± monitor PASS BIST stop Step 4: DES/SER in Normal, check register 0x25 on DES Figure 28. BIST System Flow Diagram DES Outputs BISTEN (DES) LOCK SCK (RFB = L) Case 1 - Pass SSO DOUT[7:0] DATA (internal) PASS Prior Result PASS PASS X X X FAIL Prior Result Normal Case 2 - Fail X = bit error(s) DATA (internal) BIST Test BIST Duration BIST Result Held Normal Figure 29. BIST Timing Diagram 32 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DS90UA101-Q1 DS90UA101-Q1 www.ti.com SNLS441A – JULY 2013 – REVISED SEPTEMBER 2013 APPLICATIONS INFORMATION AC Coupling The SER/DES supports only AC-coupled interconnects through an integrated DC-balanced coding scheme. External AC coupling capacitors must be placed in series with the serial interface signal path as illustrated in Figure 30 or Figure 31. Applications utilizing STP cable require a 0.1 µF coupling capacitor on both outputs (DOUT+, DOUT-). Applications utilizing single-ended 50Ω coaxial cable require a 0.1 µF capacitor on the true serial interface output (DOUT+). The unused data pin (DOUT-) requires a 0.047 µF capacitor coupled to a 50Ω resistor to GND. DOUT+ RIN+ DOUT- RIN- SER DES Figure 30. AC-Coupled Connection (STP) DOUT+ RIN+ SER DES DOUT- 50Q 50Q RIN- Figure 31. AC-Coupled Connection (Coaxial) For high-speed serial transmissions, the smallest available package should be used for the AC coupling capacitor. This will help minimize degradation of signal quality due to package parasitics. Typical Application Connection Figure 32 and Figure 33 show typical application connections of the DS90UA101-Q1 Serializer. The serial interface outputs must have external 0.1 µF coupling capacitors connected to the high-speed interconnect. The Serializer has internal termination. Bypass capacitors are placed near the power supply pins. Ferrite beads should also be used for effective noise suppression. The digital audio electrical interface is LVCMOS format. The VDDIO pin may be connected to 3.3V or 1.8V. Device I2C address select is configured via the IDx pin. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DS90UA101-Q1 33 DS90UA101-Q1 SNLS441A – JULY 2013 – REVISED SEPTEMBER 2013 www.ti.com DS90UA101-Q1 VDDIO VDDIO C3 1.8V VDDT C4 C8 C9 C13 1.8V VDDPLL C5 SCK LRCK BCK DIN0 DIN1 DIN2 DIN3 DIN4 DIN5 DIN6 DIN7 Digital Audio Interface C14 C10 FB1 1.8V VDDCML C6 C11 C15 C7 C12 FB2 1.8V VDDD C1 DOUT+ DOUT- Serial Interface C2 50Q 1.8V PDB GPI Interface GPO Interface GPI0 GPI1 GPI2 GPI3 IDx GPO0 GPO1 GPO2 GPO3 SET 10 kQ 1.8V RID 10kQ 100kQ VDDIO RPU I2C Bus Interface RPU SCL SDA RES0 DAP (GND) NOTE: C1 = 0.1 µF (50 WV) C2 = 0.047 µF (50 WV) C3 ± C7 = 0.01 µF C8 - C12 = 0.1 µF C13 - C14 = 4.7 µF C15 = 22 µF RPU = 4.7 kQ RID (see IDx Resistor Value Table) FB1, FB2: Impedance = 1 kQ (@ 100 MHz) low DC resistance (