Sample &
Buy
Product
Folder
Support &
Community
Tools &
Software
Technical
Documents
DS90UB921-Q1
SNLS488 – MARCH 2016
DS90UB921-Q1 5 - 96 MHz 24-bit Color FPD-Link III Serializer with Bidirectional Control
Channel
1 Features
3 Description
•
•
The DS90UB921-Q1 serializer, in conjunction with a
DS90UB922-Q1, DS90UB926Q-Q1, DS90UB928QQ1, DS90UB948-Q1, or DS90UB940-Q1 deserializer,
provides a complete digital interface for concurrent
transmission of high-speed video, audio, and control
data for automotive display and image sensing
applications.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 2: -40℃ to +105℃
Ambient Operating Temperature Range
– Device HBM ESD Classification Level ±8kV
– Device CDM ESD Classification Level C6
Supports Extended High Definition
(1920x720p/60Hz) Digital Video Format
5 – 96MHz PCLK Supported (STP mode)
15 – 96MHz PCLK Supported (Coax mode)
RGB888 + VS, HS, and DE
Parallel LVCMOS Video Inputs
Spread Spectrum Tolerant Input
4 Optional Bidirectional GPIO Channels
Bidirectional Control Interface Channel Interface
with I2C Compatible Serial Control Bus
Optional I2S Support
AC-Coupled Coax or STP Interconnect Up to 10
meters
Single 3.3 V Operation with 1.8 V or 3.3 V
Compatible LVCMOS I/O Interface
DC-Balanced and Scrambled Data with
Embedded Clock
Internal Pattern Generation
Low Power Modes Minimize Power Dissipation
>8kV ISO 10605 ESD Rating
The chipset is ideally suited for automotive videodisplay systems with WVGA and HD formats. The
DS90UB921-Q1
incorporates
an
embedded
bidirectional control channel and low latency GPIO
controls. This chipset translates a parallel interface
into a single pair high-speed serialized interface. The
serial bus scheme, FPD-Link III, supports full duplex
of high-speed video data transmission and
bidirectional control communication over a single link.
Consolidation of video data and control over a single
differential pair (or single wire) reduces the
interconnect size and weight, while also eliminating
skew issues and simplifying system design.
The DS90UB921-Q1 serializer embeds the clock, DC
scrambles & balances the data payload, and level
shifts the signals to high-speed low voltage
differential (or single-ended) signaling. Up to 24 data
bits are serialized along the video control signals.
EMI is minimized by the use of low voltage swing
signaling, data scrambling and randomization and
spread spectrum clocking compatibility.
Remote interrupts from the downstream deserializer
are mirrored to a local output pin.
Device Information
2 Applications
•
•
•
PART NUMBER
Automotive Touch Screen Display
Automotive Display for Navigation
Automotive Instrument Cluster
DS90UB921-Q1
RGB Digital Display Interface
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
SCL
SDA
IDx
7.00 mm × 7.00 mm
VDDIO
VDD33
(3.3V) (1.8V or 3.3V)
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
FPD-Link III
1 Coax / AC Coupled
DOUT+
RIN+
DOUT-
RIN-
DS90UB921-Q1
Serializer
PDB
I2S AUDIO
(STEREO)
WQFN (48)
BODY SIZE (NOM)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
VDDIO
VDD33
(1.8V or 3.3V) (3.3V)
HOST
Graphics
Processor
PACKAGE
(1)
3
MODE_SEL
INTB
DAP
PDB
OSS_SEL
OEN
MODE_SEL
DS90UB922-Q1
Deserializer
SCL
SDA
IDx
LOCK
PASS
3
INTB_IN
RGB Display
720p
24-bit color depth
I2S AUDIO
(STEREO)
MCLK
DAP
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DS90UB921-Q1
SNLS488 – MARCH 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
7
7.4 Device Functional Modes........................................ 24
7.5 Programming .......................................................... 27
7.6 Register Maps ........................................................ 28
1
1
1
2
3
6
8
Application and Implementation ........................ 40
8.1 Application Information............................................ 40
8.2 AVMUTE Operation ................................................ 40
8.3 Typical Application .................................................. 41
Absolute Maximum Ratings ..................................... 6
ESD Ratings - JEDEC ............................................. 6
ESD Ratings—IEC and ISO...................................... 6
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 7
DC Electrical Characteristics .................................... 7
AC Electrical Characteristics..................................... 9
PCLK Timing Requirements ..................................... 9
Recommended Timing for the Serial Control Bus .. 10
Switching Characteristics ...................................... 13
Typical Charateristics ........................................... 14
9
Power Supply Recommendations...................... 45
9.1 Power Up Requirements and PDB Pin ................... 45
9.2 CML Interconnect Guidelines.................................. 46
10 Layout................................................................... 47
10.1 Layout Guidelines ................................................. 47
10.2 Layout Example .................................................... 48
11 Device and Documentation Support ................. 51
11.1
11.2
11.3
11.4
11.5
Detailed Description ............................................ 15
7.1 Overview ................................................................. 15
7.2 Functional Block Diagram ....................................... 15
7.3 Feature Description................................................. 15
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
51
51
51
51
51
12 Mechanical, Packaging, and Orderable
Information ........................................................... 51
4 Revision History
2
DATE
REVISION
NOTES
March 2016
*
Initial release.
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: DS90UB921-Q1
DS90UB921-Q1
www.ti.com
SNLS488 – MARCH 2016
5 Pin Configuration and Functions
DIN9 / G1 / GPIO3
DIN8 / G0 / GPIO2
DIN7 / R7
DIN6 / R6
DIN5 / R5
INTB
VDDIO
DIN4 / R4
DIN3 / R3
DIN2 / R2
DIN1 / R1 / GPIO1
DIN0 / R0 / GPIO0
36
35
34
33
32
31
30
29
28
27
26
25
DS90UB921-Q1
48 Pin WQFN (RHS)
Top View
G2 / DIN10
37
24
MODE_SEL
G3 / DIN11
38
23
CMF
G4 / DIN12
39
22
VDD33
G5 / DIN13
40
21
PDB
20
DOUT+
19
DOUT-
18
RES1
G6 / DIN14
41
G7 / DIN15
42
GPO_REG4 / B0 / DIN16
43
GPO_REG5 / B1 / DIN17
44
17
CAPHS12
B2 / DIN18
45
16
REM_INTB
DS90UB921-Q1
TOP VIEW
DAP = GND
8
9
10
11
12
SCL
PCLK
GPO_REG6 / I2S_DA
GPO_REG7 / I2S_WC
7
SDA
6
IDx
CAPL12
HS
5
I2S_CLK
4
13
VS
48
DE
B5 / DIN21
3
CAPP12
1
FSEL
14
2
15
47
B7 / DIN23
46
B4 / DIN20
B6 / DIN22
B3 / DIN19
Pin Functions
PIN
NAME
NUMBER
I/O, TYPE
DESCRIPTION
LVCMOS PARALLEL INTERFACE - Layout note: for unused LVCMOS input pins, tie to an external pulldown
DIN[23:18],
DIN[15:10],
DIN[7:2] /
R[7:2],
G[7:2],
B[7:2]
27, 28, 29, 32, 33,
34, 37, 38, 39, 40,
41, 42, 45, 46, 47,
48, 1, 2
I, LVCMOS,
PD
Parallel Interface Data Input Pins
DIN[1:0],
DIN[9:8],
DIN[17:16] /
R[1:0],
G[1:0],
B[1:0]
25, 26, 35, 36, 43,
44
Multi-function
pin
I/O, LVCMOS,
PD
Parallel Interface Data Input Pins
DIN0 / R0 can optionally be used as GPIO0 and DIN1 / R1 can optionally be used as
GPIO1
DIN8 / G0 can optionally be used as GPIO2 and DIN9 /G1 can optionally be used as
GPIO3
DIN16 / B0 can optionally be used as GPO_REG4 and DIN17 / B1 can optionally be
used as GPO_REG5
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: DS90UB921-Q1
3
DS90UB921-Q1
SNLS488 – MARCH 2016
www.ti.com
Pin Functions (continued)
PIN
NAME
NUMBER
I/O, TYPE
DESCRIPTION
HS
3
I, LVCMOS,
PD
Horizontal Sync Input Pin
Video control signal pulse width must be 3 PCLKs or longer to be transmitted when
the Control Signal Filter is enabled. There is no restriction on the minimum transition
pulse when the Control Signal Filter is disabled. The signal is limited to 2 transitions
per 130 PCLKs.
See Video Control Signal Filter.
VS
4
I, LVCMOS,
PD
Vertical Sync Input Pin
Video control signal is limited to 1 transition per 130 PCLKs. Thus, the minimum pulse
width is 130 PCLKs.
See Video Control Signal Filter.
DE
5
I, LVCMOS,
PD
Data Enable Input Pin
Video control signal pulse width must be 3 PCLKs or longer to be transmitted when
the Control Signal Filter is enabled. There is no restriction on the minimum transition
pulse when the Control Signal Filter is disabled. The signal is limited to 2 transitions
per 130 PCLKs.
See Video Control Signal Filter.
PCLK
10
I, LVCMOS,
PD
Pixel Clock Input Pin. Strobe edge set by TRFB configuration register. See Table 7
0x03[0].
13, 12, 11
Multi-function
pin
I, LVCMOS,
PD
Digital Audio Interface Data Input Pins
Leave open if unused
I2S_CLK can optionally be used as GPO_REG8, I2S_WC can optionally be used as
GPO_REG7, and I2S_DA can optionally be used as GPO_REG6.
I2S_CLK,
I2S_WC,
I2S_DA
OPTIONAL PARALLEL INTERFACE - Layout note: for unused interface pins, tie to an external pulldown
GPIO[3:0]
36, 35, 26, 25
Multi-function
pin
I/O, LVCMOS,
PD
General Purpose IOs. Available only in 18-bit color mode, and set by MODE_SEL pin
or configuration register. See Table 7 0x0D - 0x0F.
Leave open if unused.
Shared with DIN9, DIN8, DIN1 and DIN0
GPO_REG[
7:4]
12, 11, 44, 43
Multi-function
pin
O, LVCMOS,
PD
General Purpose Outputs and set by configuration register. See Table 7 0x0F - 0x11.
Share with I2S_WC, I2S_DA, or DIN17, DIN16.
PDB
21
I, LVCMOS,
PD
Power-down Mode Input Pin
PDB = H, device is enabled (normal operation)
Refer to Power Up Requirements and PDB Pin section.
PDB = L, device is powered down.
When the device is in the powered down state, the Driver Outputs are both HIGH, the
PLL is shutdown, and IDD is minimized. Control Registers are RESET.
MODE_SEL
24
S
FSEL
15
I, LVCMOS,
PU
IDx
6
S
SCL
8
I/O, Open
Drain
I2C Clock Input / Output Interface
Must have an external pull-up to VDD33, DO NOT FLOAT.
Recommended pull-up: 4.7kΩ.
SDA
9
I/O, Open
Drain
I2C Data Input / Output Interface
Must have an external pull-up to VDD33, DO NOT FLOAT.
Recommended pull-up: 4.7kΩ.
CONTROL
Device Configuration Select. See Table 5.
Frequency Mode Select. Enables Intermediate Frequency mode for coaxial operation.
See Frequency Mode Optimizations.
I2C
4
I2C Serial Control Bus Device ID Address Select
External pull-up to VDD33 is required under all conditions, DO NOT FLOAT.
Connect to external pull-up and pull-down resistor to create a voltage divider. See
Table 6.
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: DS90UB921-Q1
DS90UB921-Q1
www.ti.com
SNLS488 – MARCH 2016
Pin Functions (continued)
PIN
NAME
NUMBER
I/O, TYPE
DESCRIPTION
STATUS - Layout note: for unused interface pins, leave as No Connect
INTB
31
REM_INTB
16
O, Open Drain Interrupt
INTB = H, normal
INTB = L, Interrupt request
Typically connected with 4.7kΩ to VDDIO.
O, LVCMOS,
PD
Interrupt. Mirrors status of INTB_IN from the remote deserializer. Note: REM_INTB
will be driven LOW until lock is achieved with the downstream deserializer.
REM_INTB = H, normal
REM_INTB = L, interrupt request
FPD-LINK III SERIAL INTERFACE
DOUT+
20
O, LVDS
True Output
The output must be AC-coupled per the typical connection diagram.
DOUT-
19
O, LVDS
Inverting Output
The output must be AC-coupled per the typical connection diagram.
CMF
23
CAP
POWER AND GROUND
Common Mode Filter.
Typically connected with 0.1µF to GND
(1)
VDD33
22
Power
Power to on-chip regulator 3.0 V - 3.6 V. Typically connected with 4.7 uF to GND
VDDIO
30
Power
LVCMOS I/O Power 1.71 V - 1.89 V OR 3.0 V - 3.6 V. Typically connected with 4.7
uF to GND
DAP
Ground
DAP is the large metal contact at the bottom side, located at the center of the WQFN
package. Connect to the ground plane (GND) with at least 9 vias.
17, 14
CAP
Decoupling capacitor connection for on-chip regulator. Typically connected with 4.7uF
to GND at each CAP pin.
7
CAP
Decoupling capacitor connection for on-chip regulator. Typically connected with two
4.7uF to GND at this CAP pin.
18
GND
Reserved. Tie to Ground.
GND
REGULATOR CAPACITOR
CAPHS12,
CAPP12
CAPL12
OTHERS
RES1
(1)
The VDD (VDD33 and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise.
The definitions below define the functionality of the I/O cells for each pin. I/O TYPE:
• CAP = Capacitor connection
• LVCMOS = LVCMOS pin; Referenced to VDDIO IO supply
• I = Input
• O = Output
• I/O = Input/Output
• S = Strap pin. All strap pins have weak internal pull-ups or pull-downs. If the default strap value is needed to
be changed then an external resistor should be used.
• PD, PU = Weak Internal Pull-Down/Pull-Up
• Multi-function pin
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: DS90UB921-Q1
5
DS90UB921-Q1
SNLS488 – MARCH 2016
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
MAX
UNIT
Supply voltage – VDD33
–0.3
4
V
Supply voltage – VDDIO
–0.3
4
V
LVCMOS I/O voltage
–0.3
VDDIO + 0.3
V
Serializer output voltage - DOUT±
–0.3
2.75
V
150
°C
150
°C
Junction temperature
Storage temperature, Tstg
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
6.2 ESD Ratings - JEDEC
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
±8000
Charged-device model (CDM), per AEC Q100-011
±1500
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 ESD Ratings—IEC and ISO
VALUE
RD = 330 Ω, CS = 150 pF
V(ESD)
Electrostatic discharge
RD = 330 Ω, CS = 150 and 330 pF
RD = 2 kΩ, CS = 150 and 330 pF
IEC, powered-up only contact discharge
(DOUT+, DOUT-)
±8000
IEC, powered-up only air-gap discharge
(DOUT+, DOUT-)
±18000
ISO10605 contact discharge (DOUT+,
DOUT-)
±8000
ISO10605 air-gap discharge (DOUT+,
DOUT-)
±18000
ISO10605 contact discharge (DOUT+,
DOUT-)
±8000
ISO10605 air-gap discharge (DOUT+,
DOUT-)
±18000
UNIT
V
V
V
6.4 Recommended Operating Conditions
MIN
NOM
MAX
3
3.3
3.6
V
V
Supply voltage (VDD33)
LVCMOS supply voltage (VDDIO)
Operating free-air temperature (TA)
UNIT
3
3.3
3.6
1.71
1.8
1.89
V
−40
25
105
°C
PCLK frequency, Coax operation, high frequency mode (1)
48
96
MHz
PCLK frequency, Coax operation, intermediate frequency mode (1)
24
48
MHz
PCLK frequency, Coax operation, low frequency mode (1)
15
24
MHz
(1)
15
96
MHz
5
15
MHz
100
mVP-P
PCLK frequency, STP operation, high frequency mode
PCLK frequency, STP operation, low frequency mode (1)
Supply noise -- (DC-50MHz)
(1)
6
For configuration of cable type and frequency mode, refer to Frequency Mode Optimizations.
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: DS90UB921-Q1
DS90UB921-Q1
www.ti.com
SNLS488 – MARCH 2016
6.5 Thermal Information
DS90UB921-Q1
THERMAL METRIC (1)
RHS (WQFN)
UNIT
48 PINS
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
11.7
RθJB
Junction-to-board thermal resistance
5.0
ψJT
Junction-to-top characterization parameter
0.1
ψJB
Junction-to-board characterization parameter
6.0
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.7
(1)
29
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.6 DC Electrical Characteristics
over operating free-air temperature range (unless otherwise noted) (1) (2) (3)
PARAMETER
TEST CONDITIONS
PIN/FREQ.
MIN
TYP
MAX
UNIT
LVCMOS I/O DC SPECIFICATIONS
VIH
High-level input voltage VDDIO = 3 V to 3.6 V
VIL
Low-level input voltage
VDDIO = 3 V to 3.6 V
IIN
Input current
VIN = 0 V or
VIN = VDDIO (3 V to 3.6 V)
VIH
High-level input voltage
VIL
Low-level input voltage
IIN
Input current
PDB
VDDIO = 1.71 V to 1.89 V
VOH
High-level output
voltage
VDDIO = 1.71 V to 1.89 V
VIN = 0 V or
VIN = VDDIO
IOH = –4 mA
Low-level output
voltage
IOH = 4 mA
IOS
Output short-circuit
current
VOUT = 0 V
IOZ
TRI-STATE output
current
VOUT = 0 V or
VOUT = VDDIO
PDB = L
VOL
(1)
(2)
(3)
VDDIO = 3 V to
3.6 V
VDDIO
V
GND
0.8
V
10
µA
2
VDDIO
V
0.65 ×
VDDIO
VDDIO
V
GND
0.8
V
GND
0.35 ×
VDDIO
V
–10
VDDIO = 3 V to 3.6 V
VDDIO = 3 V to 3.6 V
2
DIN[23:0], HS,
VS, DE, PCLK,
I2S_CLK,
I2S_WC,
I2S_DA
±1
–10
±1
10
µA
VDDIO = 1.71 V
to 1.89 V
–10
±1
10
µA
VDDIO = 3 V to
3.6 V
2.4
VDDIO
V
VDDIO = 1.71 V
to 1.89 V
VDDIO –
0.45
VDDIO
V
GND
0.4
V
GND
0.35
V
VDDIO = 3 V to
3.6 V
VDDIO = 1.71 V
to 1.89 V
GPIO[3:0],
GPO_REG[7:4],
REM_INTB
–50
–10
mA
10
µA
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Typical values represent most likely parametric norms at nominal conditions at the time of product characterization and are not ensured.
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD and ΔVOD, which are differential voltages.
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: DS90UB921-Q1
7
DS90UB921-Q1
SNLS488 – MARCH 2016
www.ti.com
DC Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)(1)(2)(3)
PARAMETER
TEST CONDITIONS
PIN/FREQ.
MIN
TYP
MAX
UNIT
FPD-LINK III CML DRIVER DC SPECIFICATIONS
VOD
Differential output
voltage (DOUT+) –
(DOUT–)
RL = 100 Ω, see Figure 1
700
800
1000
mVp-p
VOUT
Single-ended output
voltage (DOUT+ or
DOUT-)
RL = 50 Ω
See Figure 2
350
400
500
mV
ΔVOD
Output voltage
unbalance
1
50
mV
VOS
Offset voltage —
single-ended
ΔVOS
Offset voltage
unbalanced singleended
IOS
Output short-circuit
current
RT
Internal termination
resistor — singleended
RL = 100 Ω
See Figure 1
2.5 –
0.5 ×
VOD
DOUT±
1
DOUT± = 0 V, PDB = L or H
V
50
–38
40
50
mV
mA
62
Ω
VDD33
V
0.3 ×
VDD33
V
SERIAL CONTROL BUS
0.7 ×
VDD33
VIH
Input high level, I2C
VIL
Input low-level voltage,
I2C
VHY
Input hysteresis, I2C
VOL
Output Low Level, I2C
IOL = +1.25mA
IIN
Input Current, I2C
VIN = 0V or
VIN = VDD33
CIN
Input capacitance, I2C
> 50
SDA, SCL
mV
0
0.36
V
–10
10
µA
f/10
Bit Error Rate ≥10-10 (2) (3)
(1)
(2)
(3)
TEST CONDITIONS
R[7:0],
G[7:0],
B[7:0], HS,
VS, DE,
PCLK
See Figure 6
See Figure 8
RL = 100Ω
f = 96MHz
See Figure 9
MIN
DOUT+,
DOUT-
See Figure 5
See Figure 7
PIN/FREQ.
(1)
TYP
MAX
UNIT
80
ps
80
ps
2.0
ns
2.0
ns
f=596MHz
131*T
ns
f=596MHz
145*T
ns
DOUT+,
DOUT-
0.25
0.30
UI
tPLD is the time required by the device to obtain lock when exiting power-down state with an active PCLK
Specification is ensured by characterization and is not tested in production.
UI – Unit Interval is equivalent to one serialized data bit width 1UI = 1 / (35*PCLK). The UI scales with PCLK frequency.
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: DS90UB921-Q1
13
DS90UB921-Q1
SNLS488 – MARCH 2016
www.ti.com
Time (2.0 ns/DIV)
Time (1.0 ns/DIV)
Note: On the rising edge of each clock period, the CML driver outputs
a low Stop bit, high Start bit, and 33 DC-scrambled data bits.
Figure 11. Serializer CML Driver Output with 96 MHz TX
Pixel Clock
14
96 MHz TX Pixel Clock Input
(200 mV/DIV)
CML Serializer Data Throughput
(80 mV/DIV)
CML Serializer Data Throughput
(80 mV/DIV)
6.11 Typical Charateristics
Figure 12. Serializer CMLOUT Driver Output and 96 MHz
LVCMOS PCLK Input
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: DS90UB921-Q1
DS90UB921-Q1
www.ti.com
SNLS488 – MARCH 2016
7 Detailed Description
7.1 Overview
The DS90UB921-Q1 serializer transmits a 35-bit symbol over a single serial FPD-Link III channel operating up to
3.36 Gbps line rate. The serial stream contains an embedded clock, video control signals and DC-balanced video
data and audio data which enhance signal quality to support AC coupling. The serializer is intended for use with
the DS90UB926Q-Q1, DS90UB928Q-Q1, DS90UB948-Q1, or DS90UB940-Q1 deserializers.
The DS90UB921-Q1 serializer and compatible deserializer incorporate an I2C compatible interface. The I2C
compatible interface allows programming of serializer or deserializer devices from a local host controller. In
addition, the devices incorporate a bidirectional control channel (BCC) that allows communication between
serializer/deserializer as well as remote I2C slave devices.
The bidirectional control channel is implemented via embedded signaling in the high-speed forward channel
(serializer to deserializer) as well as lower speed signaling in the reverse channel (deserializer to serializer).
Through this interface, the BCC provides a mechanism to bridge I2C transactions across the serial link from one
I2C bus to another. The implementation allows for arbitration with other I2C compatible masters at either side of
the serial link.
There are two operating modes available on DS90UB921-Q1, display mode and camera mode. In display mode,
I2C transactions originate from the host controller attached to the serializer and target either the deserializer or an
I2C slave attached to the deserializer. Transactions are detected by the I2C slave in the serializer and forwarded
to the I2C master in the deserializer. Similarly, in camera mode, I2C transactions originate from a controller
attached to the deserializer and target either the serializer or an I2C slave attached to the serializer. Transactions
are detected by the I2C slave in the deserializer and forwarded to the I2C master in the serializer.
7.2 Functional Block Diagram
REGULATOR
PDB
MODE_SEL
INTB
REM_INTB
SDA
SCL
IDx
Parallel to Serial
3
DC Balance Encoder
I2S_CLK
I2S_WC
I2S_DA
CMF
24
Input latch
DIN [23:0]
HS
VS
DE
PCLK
DOUT +
D
DOUT -
PLL
Timing
and
Control
DS90UB921-Q1
Serializer
7.3 Feature Description
7.3.1 High Speed Forward Channel Data Transfer
The High Speed Forward Channel (HS_FC) is composed of 35 bits of data containing DIN[23:0] or RGB[7:0] or
YUV data, sync signals, I2C, and I2S audio transmitted from Serializer to Deserializer. Figure 13 illustrates the
serial stream per PCLK cycle. This data payload is optimized for signal transmission over an AC coupled link.
Data is randomized, balanced and scrambled.
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: DS90UB921-Q1
15
DS90UB921-Q1
SNLS488 – MARCH 2016
www.ti.com
Feature Description (continued)
C1
C0
Figure 13. FPD-Link III Serial Stream
The device supports clocks in the range of 5 MHz to 96 MHz. The actual line rate is 3.36 Gbps maximum and
525 Mbps Minimum.
7.3.2 Low Speed Back Channel Data Transfer
The Low-Speed Backward Channel (LS_BC) of the DS90UB921-Q1 provides bidirectional communication
between the display and host processor. The information is carried back from the Deserializer to the Serializer
per serial symbol. The back channel control data is transferred over the single serial link along with the highspeed forward data, DC balance coding and embedded clock information. This architecture provides a backward
path across the serial link together with a high speed forward channel. The back channel contains the I2C, CRC
and 4 bits of standard GPIO information with 3.1 Mbps line rate in Coax mode and low frequency STP mode,
and 4.4Mbps line rate in high frequency STP mode. The back channel data rate is configured automatically when
STP or Coax is selected (see Frequency Mode Optimizations).
7.3.3 Common Mode Filter Pin (CMF)
The serializer provides access to the center tap of the internal termination. A capacitor must be placed on this pin
for additional common-mode filtering of the differential pair. This can be useful in high noise environments for
additional noise rejection capability. A 0.1 μF capacitor must be connected to this pin to Ground.
7.3.4 Video Control Signal Filter
When operating the devices in Normal Mode, the Video Control Signals (DE, HS, VS) have the following
restrictions:
• Normal Mode with Control Signal Filter Enabled: DE and HS — Only 2 transitions per 130 clock cycles are
transmitted, the transition pulse must be 3 PCLK or longer.
• Normal Mode with Control Signal Filter Disabled: DE and HS — Only 2 transitions per 130 clock cycles are
transmitted, no restriction on minimum transition pulse.
• VS — Only 1 transition per 130 clock cycles are transmitted, minimum pulse width is 130 clock cycles.
Video Control Signals are defined as low frequency signals with limited transitions. Glitches of a control signal
can cause a visual display error. This feature allows for the chipset to validate and filter out any high frequency
noise on the control signals. See Figure 14.
16
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: DS90UB921-Q1
DS90UB921-Q1
www.ti.com
SNLS488 – MARCH 2016
Feature Description (continued)
PCLK
IN
HS/VS/DE
IN
Latency
PCLK
OUT
HS/VS/DE
OUT
Pulses 1 or 2
PCLKs wide
Filetered OUT
Figure 14. Video Control Signal Filter Waveform
7.3.5 EMI Reduction Features
7.3.5.1 Input SSC Tolerance (SSCT)
The DS90UB921-Q1 serializer is capable of tracking a triangular input spread spectrum clocking (SSC) profile up
to ±2.5% amplitude deviations (center spread), up to 35 kHz modulation at 5–96 MHz, from a host source.
7.3.6 LVCMOS VDDIO Option
1.8 V or 3.3 V Inputs and Outputs are powered from a separate VDDIO supply to offer compatibility with external
system interface signals.
NOTE
When configuring the VDDIO power supplies, all the single-ended data and control input
pins for device need to scale together with the same operating VDDIO levels.
7.3.7 Power Down (PDB)
The Serializer has a PDB input pin to ENABLE or POWER DOWN the device. This pin can be controlled by the
host or through the VDDIO, where VDDIO = 3.0V to 3.6V or VDD33. To save power disable the link when the
display is not needed (PDB = LOW). When the pin is driven by the host, make sure to release it after VDD33 and
VDDIO have reached final levels; no external components are required. In the case of driven by the VDDIO =
3.0V to 3.6V or VDD33 directly, a 10 kohm resistor to the VDDIO = 3.0V to 3.6V or VDD33 , and a >10uF
capacitor to the ground are required (See Figure 26).
7.3.8 Remote Auto Power-Down Mode
The DS90UB921-Q1 serializer features a Remote Auto Power Down mode. This feature is enabled and disabled
through the register bit 0x01[7] (Table 7). When the back channel is not detected, either due to an idle or
powered-down deserializer, the serializer enters remote auto power down mode. Power dissipation of the
serializer is significantly reduced in this mode. The serializer automatically attempts to resume normal operation
upon detection of an active back channel from the deserializer. To complete the wake-up process and reactivate
forward channel operation, the remote power-down feature must be disabled by either a local I2C host, or by an
auto-ACK I2C transaction from a remote I2C host located at the deserializer. The Remote Auto Power Down
Sleep/Wake cycle is shown below in Figure 15:
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: DS90UB921-Q1
17
DS90UB921-Q1
SNLS488 – MARCH 2016
www.ti.com
Feature Description (continued)
Enable
Set reg_0x01[7]=1
Back Channel IDLE
Remote Auto Power
Down Enabled
Forward-channel
OFF
Normal Operation
Disable
Set reg_0x01[7]=0
Sleep
Back Channel ACTIVE
Figure 15. Remote Auto Power Down Sleep/Wake Cycle
To resume normal operation, the Remote Auto Power Down feature must be disabled in the device control
register. This may be accomplished from a local I2C controller by writing reg_0x01[7]=0 (Table 7). To disable
from a remote I2C controller located at the deserializer, perform the following procedure to complete the wake-up
process:
1. Power up remote deserializer (back channel must be active)
2. Enable I2C PASS-THROUGH ALL by setting deserializer register reg_0x05[7]=1
3. Enable I2C AUTO ACK by setting deserializer register reg_0x03[2]=1
4. Disable Remote Auto Power Down by setting serializer register reg_0x01[7]=0
5. Disable I2C AUTO ACK by setting deserializer register reg_0x03[2]=0
6. Disable I2C PASS-THROUGH ALL by setting deserializer register reg_0x05[7]=0
7.3.9 Input PCLK Loss Detect
The serializer can be programmed to enter a low power SLEEP state when the input clock (PCLK) is lost. This is
done via register 0x03[1] (see Table 7). A clock loss condition is detected when PCLK drops below
approximately 1MHz. When a PCLK is detected again, the serializer will then lock to the incoming PCLK. Note –
when PCLK is lost, the Serial Control Bus Registers values are still RETAINED.
18
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: DS90UB921-Q1
DS90UB921-Q1
www.ti.com
SNLS488 – MARCH 2016
Feature Description (continued)
7.3.10 Serial Link Fault Detect
The serial link fault detection is able to detect any of following seven (7) conditions:
1. cable open
2. “+” to “-“ short
3. “+” short to GND
4. “-“ short to GND
5. “+” short to battery
6. “-“ short to battery
7. Cable is linked correctly
If any one of the fault conditions (first 6 conditions above) occurs, The Link Detect Status is 0 (cable is not
detected) on bit 0 of address 0x0C Table 7.
7.3.11 Pixel Clock Edge Select (TRFB)
The TRFB control register bit selects which edge of the Pixel Clock is used. For the serializer, this pin determines
the edge that the data is latched on. If TRFB is HIGH (‘1’), data is latched on the Rising edge of the PCLK. If
TRFB is LOW (‘0’), data is latched on the Falling edge of the PCLK.
7.3.12 Frequency Mode Optimizations
HFMODE, LFMODE, and IFMODE are set through a combination of the FSEL pin and MODE_SEL pin, with
register overrides for both. These pins (or register overrides) will configure the DS90UB921-Q1 into either Low
Frequency Mode (LFMODE), Intermediate Frequency mode (IFMODE), or High Frequency mode (HFMODE).
See Table 1 for details on how each mode is enabled.
Table 1. HFMODE / LFMODE / IFMODE Configuration Table
FSEL (pin 15, or
register 0x35[7:6])
ALTERNATE
FREQUENCY (set by
MODE_SEL pin, or
register 0x04[1:0])
MODE
PCLK RANGE for COAX
PCLK RANGE for STP
L
L
HFMODE
N/A
15 - 96 MHz
H
L
HFMODE
48 - 96 MHz
N/A
H
H
IFMODE
24 - 48 MHz
N/A
L
H
LFMODE
15 - 24 MHz
5 - 15 MHz
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: DS90UB921-Q1
19
DS90UB921-Q1
SNLS488 – MARCH 2016
www.ti.com
7.3.13 Interrupt Pins – Funtional Description and Usage (INTB, REM_INTB)
The REM_INTB pin mirrors the status of INTB_IN from the remote deserializer. Any change in INTB_IN status of
the remote device will be reflected at the REM_INTB output of the serializer. REM_INTB will remain LOW until
lock is achieved with the downstream deserializer. Alternately, the INTB pin can be set to trigger on remote
interrupts by following the steps below.
1. On DS90UB921-Q1, read register 0xC7.
2. On DS90UB921-Q1, set register 0xC6[5] = 1 and 0xC6[0] = 1
3. Deserializer INTB_IN is set LOW by some downstream device.
4. DS90UB921-Q1 serializer pulls INTB (pin 31) LOW. The signal is active low, so a LOW indicates an interrupt
condition.
5. External controller detects INTB = LOW; to determine interrupt source, read ISR register 0xC7.
6. A read to ISR will clear the interrupt at the DS90UB921-Q1, releasing INTB.
7. The external controller typically must then access the remote device to determine downstream interrupt
source and clear the interrupt driving INTB_IN. This would be when the downstream device releases the
INTB_IN on the deserializer. The system is now ready to return to step (1) at next falling edge of INTB_IN.
If using the REM_INTB pin instead of INTB for remote interrupts, the IS_RX_INT bit (0xC6[5]) of the serializer's
ICR register must be set low (default) masking remote interrupts to the INTB pin.
7.3.14 Internal Pattern Generation
The DS90UB921-Q1 serializer supports the internal pattern generation feature. It allows basic testing and
debugging of an integrated panel through the FPD-Link III output stream. The test patterns are simple and
repetitive and allow for a quick visual verification of panel operation. As long as the device is not in power down
mode, the test pattern will be displayed even if no parallel input is applied. If no PCLK is received, the test
pattern can be configured to use a programmed oscillator frequency. For detailed information, refer to Application
Note AN-2198 (SNLA132).
7.3.15 GPIO[3:0] and GPO_REG[7:4]
In 18-bit RGB operation mode, the optional R[1:0] and G[1:0] of the DS90UB921-Q1 can be used as the general
purpose IOs GPIO[3:0] in either forward channel (Inputs) or back channel (Outputs) applications.
7.3.15.1 GPIO[3:0] Enable Sequence
See Table 2 for the GPIO enable sequencing.
Step 1: Enable the 18-bit mode either through the configuration register bit Table 7 on DS90UB921-Q1 only. The
deserializer is automatically configured as in the 18-bit mode.
Step 2: To enable GPIO3 forward channel, write 0x03 to address 0x0F on DS90UB921-Q1, then write 0x05 to
address 0x1F on the deserializer.
Table 2. GPIO Enable Sequencing Table
#
DESCRIPTION
DEVICE
FORWARD CHANNEL
BACK CHANNEL
1
Enable 18-bit
mode
DS90UB921-Q1
0x12 = 0x04
0x12 = 0x04
DS90UB926Q-Q1
Auto Load from DS90UB921-Q1
Auto Load from DS90UB921-Q1
2
GPIO3
DS90UB921-Q1
0x0F = 0x03
0x0F = 0x05
DS90UB926Q-Q1
0x1F = 0x05
0x1F = 0x03
3
4
5
20
GPIO2
GPIO1
GPIO0
DS90UB921-Q1
0x0E = 0x30
0x0E = 0x50
DS90UB926Q-Q1
0x1E = 0x50
0x1E = 0x30
DS90UB921-Q1
0x0E = 0x03
0x0E = 0x05
DS90UB926Q-Q1
0x1E = 0x05
0x1E = 0x03
DS90UB921-Q1
0x0D = 0x93
0x0D = 0x95
DS90UB926Q-Q1
0x1D = 0x95
0x1D = 0x93
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: DS90UB921-Q1
DS90UB921-Q1
www.ti.com
SNLS488 – MARCH 2016
Note: GPO_REG4 of the DS90UB921-Q1 can be used as a forward channel GPIO, outputting on GPIO0 of
DS90UB928Q-Q1. This is configured as follows:
• Set DS90UB921-Q1 in 18-bit mode by register 0x12[2] = 1.
• Set DS90UB928Q-Q1 register 0x1D[0] = 1 and 0x1D[2] = 1; this enables GPIO0 of DS90UB928Q-Q1 as an
output.
• Set DS90UB921-Q1 register 0x0F[4] = 1 and 0x0F[5] = 1; this enables GPO_REG4 of DS90UB921-Q1 as an
input.
Similarly GPO_REG5 of DS90UB921-Q1 can output to GPIO1 of DS90UB928Q-Q1:
• Set DS90UB921-Q1 in 18-bit mode by register 0x12[2] = 1.
• Set DS90UB928Q-Q1 register 0x1E[0] = 1 and 0x1E[2] = 1; this enables GPIO1 of DS90UB928Q-Q1 as an
output.
• Set DS90UB921-Q1 register 0x10[0] = 1 and 0x10[1] = 1; this enables GPO_REG5 DS90UB921-Q1 as an
input.
7.3.15.2 GPO_REG[7:4] Enable Sequence
GPO_REG[7:4] are the outputs only pins. They must be programmed through the local register bits. See Table 3
for the GPO_REG enable sequencing.
Step 1: Enable the 18-bit mode either through the configuration register bit Table 7 on DS90UB921-Q1 only. The
deserializer is automatically configured as in the 18-bit mode.
Step 2: To enable GPO_REG7 outputs an “1”, write 0x09 to address 0x11 on DS90UB921-Q1.
Table 3. GPO_REG Enable Sequencing Table
#
DESCRIPTION
DEVICE
LOCAL ACCESS
1
Enable 18-bit mode
DS90UB921-Q1
0x12 = 0x04
2
GPO_REG7
DS90UB921-Q1
0x11 = 0x09
“1”
0x11 = 0x01
“0”
0x10 = 0x90
“1”
0x10 = 0x10
“0”
3
GPO_REG6
DS90UB921-Q1
LOCAL OUTPUT
4
GPO_REG5
DS90UB921-Q1
0x10 = 0x09
“1”
0x10 = 0x01
“0”
5
GPO_REG4
DS90UB921-Q1
0x0F = 0x90
“1”
0x0F = 0x10
“0”
7.3.16 I2S Transmitting
In normal 24-bit RGB operation mode, the DS90UB921-Q1 supports 3 bits of I2S. They are I2S_CLK, I2S_WC
and I2S_DA. The optionally packetized audio information can be transmitted during the video blanking (data
island transport) or during active video (forward channel frame transport). Note: The bit rates of any I2S bits must
maintain one fourth of the PCLK rate. Table 4 covers the range of I2S sample rates.
Table 4. Audio Interface Frequencies
SAMPLE RATE (kHz)
I2S DATA WORD SIZE (BITS)
I2S CLK (MHz)
32
16
1.024
44.1
16
1.411
48
16
1.536
96
16
3.072
192
16
6.144
32
24
1.536
44.1
24
2.117
48
24
2.304
96
24
4.608
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: DS90UB921-Q1
21
DS90UB921-Q1
SNLS488 – MARCH 2016
www.ti.com
Table 4. Audio Interface Frequencies (continued)
SAMPLE RATE (kHz)
I2S DATA WORD SIZE (BITS)
I2S CLK (MHz)
192
24
9.216
32
32
2.048
44.1
32
2.822
48
32
3.072
96
32
6.144
192
32
12.288
7.3.17 Built In Self Test (BIST)
An optional At-Speed Built In Self Test (BIST) feature supports the testing of the high speed serial link and the
low- speed back channel. This is useful in the prototype stage, equipment production, in-system test and also for
system diagnostics.
7.3.17.1 BIST Configuration and Status
The BIST mode is enabled at the deseralizer by the Pin select (BISTEN and BISTC) or configuration register
(Table 7) through the deserializer. When LFMODE = 0, the pin based configuration defaults to external PCLK or
33 MHz internal Oscillator clock (OSC) frequency. In the absence of PCLK, the user can select the desired OSC
frequency (default 33 MHz or 25MHz) through the register bit. When LFMODE = 1, the pin based configuration
defaults to external PCLK or 12.5MHz MHz internal Oscillator clock (OSC) frequency.
When BISTEN of the deserializer is high, the BIST mode enable information is sent to the serializer through the
Back Channel. The serializer outputs a test pattern and drives the link at speed. The deserializer detects the test
pattern and monitors it for errors. The PASS output pin toggles to flag any payloads that are received with 1 to
35 bit errors.
The BIST status is monitored real time on PASS pin. The result of the test is held on the PASS output until reset
(new BIST test or Power Down). A high on PASS indicates NO ERRORS were detected. A Low on PASS
indicates one or more errors were detected. The duration of the test is controlled by the pulse width applied to
the deserializer BISTEN pin. This BIST feature also contains a Link Error Count and a Lock Status. If the
connection of the serial link is broken, then the link error count is shown in the register. When the PLL of the
deserializer is locked or unlocked, the lock status can be read in the register. See Table 7.
7.3.17.1.1 Sample BIST Sequence
See Figure 16 for the BIST mode flow diagram.
Step 1: BIST Mode is enabled via the BISTEN pin of the deserializer. The desired clock source is selected
through BISTC pin.
Step 2: The DS90UB921-Q1 serializer is woken up through the back channel if it is not already on. The all zero
pattern on the data pins is sent through the FPD-Link III to the deserializer. Once the serializer and the
deserializer are in BIST mode and the deserializer acquires Lock, the PASS pin of the deserializer goes high and
BIST starts checking the data stream. If an error in the payload (1 to 35) is detected, the PASS pin will switch low
for one half of the clock period. During the BIST test, the PASS output can be monitored and counted to
determine the payload error rate.
Step 3: To Stop the BIST mode, the deserializer BISTEN pin is set Low. The deserializer stops checking the
data. The final test result is held on the PASS pin. If the test ran error free, the PASS output will be High. If there
was one or more errors detected, the PASS output will be Low. The PASS output state is held until a new BIST
is run, the device is RESET, or Powered Down. The BIST duration is user controlled by the duration of the
BISTEN signal.
Step 4: The Link returns to normal operation after the deserializer BISTEN pin is low. Figure 17 shows the
waveform diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2 shows one with multiple
errors. In most cases it is difficult to generate errors due to the robustness of the link (differential data
transmission etc.), thus they may be introduced by greatly extending the cable length, faulting the interconnect,
reducing signal condition enhancements (Rx Equalization).
22
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: DS90UB921-Q1
DS90UB921-Q1
www.ti.com
SNLS488 – MARCH 2016
Normal
Step 1: DES in BIST
BIST
Wait
Step 2: Wait, SER in BIST
BIST
start
Step 3: DES in Normal Mode check PASS
BIST
stop
Step 4: DES/SER in Normal
Figure 16. Bist Mode Flow Diagram
7.3.17.2 Forward Channel And Back Channel Error Checking
While in BIST mode, the serializer stops sampling RGB input pins and switches over to an internal all-zero
pattern. The internal all-zeroes pattern goes through scrambler, dc-balancing etc. and goes over the serial link to
the deserializer. The deserializer on locking to the serial stream compares the recovered serial stream with allzeroes and records any errors in status registers and dynamically indicates the status on PASS pin. The
deserializer then outputs a simultaneous switching output (SSO) pattern on the RGB output pins.
The back-channel data is checked for CRC errors once the serializer locks onto back-channel serial stream as
indicated by link detect status (register bit 0x0C[0]). The CRC errors are recorded in an 8-bit register. The
register is cleared when the serializer enters the BIST mode. As soon as the serializer exits BIST mode, the
functional mode CRC register starts recording the CRC errors. The BIST mode CRC error register is active in
BIST mode only and keeps the record of last BIST run until cleared or enters BIST mode again.
DES Outputs
BISTEN
(DES)
Case 1 - Pass
PCLK
(RFB = L)
ROUT[23:0]
HS, VS, DE
DATA
(internal)
PASS
Prior Result
PASS
PASS
X
X
X
FAIL
Prior Result
Normal
SSO
Case 2 - Fail
X = bit error(s)
DATA
(internal)
BIST Test
BIST Duration
BIST
Result
Held
Normal
Figure 17. Bist Waveforms
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: DS90UB921-Q1
23
DS90UB921-Q1
SNLS488 – MARCH 2016
www.ti.com
7.4 Device Functional Modes
7.4.1 Configuration Select (MODE_SEL)
Configuration of the device may be done via the MODE_SEL input pin, or via the configuration register bit. A pullup resistor and a pull-down resistor of suggested values may be used to set the voltage ratio of the MODE_SEL
input (VR4) and VDD33 to select one of the other 7 possible selected modes. The voltage range in between the
Minimum and Maximum VR4 must be adhered even when taking resistor tolerances into account. The 1%
suggested resistors meet this for all cases, but others that also meet the desired voltage range are also
acceptable. See Figure 18 and Table 5.
VDD33
R3
VR4
MODE_SEL
R4
SER
Figure 18. MODE_SEL Connection Diagram
Table 5. Configuration Select (MODE_SEL)
#
MINIMUM
VR4 (V) (1)
MAXIMUM
VR4 (V) (1)
SUGGESTED
RESISTOR R3
kΩ (1% tol)
SUGGESTED
RESISTOR R4
kΩ (1% tol)
ALTERNATE
FREQUENCY
REPEATER
18–BIT MODE
1
0.000
0.150
Open
40.2 or Any
2
0.530
0.596
90.9
18.7
L
L
L
L
H
3
0.725
0.800
93.1
L
28.0
L
H
H
4
0.930
1.012
71.5
30.1
H
L
L
5
1.165
6
1.480
1.284
68.1
40.2
H
L
H
1.599
82.5
71.5
H
H
7
1.750
L
1.905
73.2
90.9
H
H
H
Alternate Frequency:
See Frequency Mode Optimizations
Repeater:
L = Repeater OFF (Default)
H = Repeater ON
18-bit Mode:
L = Normal 24-bit RGB Mode (Default)
H = 18-bit RGB Mode. Note: use of GPIO(s) on unused inputs must be enabled by register.
7.4.2 Repeater Application
The DS90UB921-Q1 and DS90UB926Q-Q1 can be configured to extend data transmission over multiple links to
multiple display devices. Setting the devices into repeater mode provides a mechanism for transmitting to all
receivers in the system.
7.4.2.1 Repeater Configuration
In the repeater application, in this document, the DS90UB921-Q1 is referred to as the Transmitter or transmit
port (TX), and the DS90UB926Q-Q1 is referred to as the Receiver (RX). Figure 19 shows the maximum
configuration supported for Repeater implementations using the DS90UB921-Q1 (TX) and DS90UB926Q-Q1
(RX). Two levels of Repeaters are supported with a maximum of three Transmitters per Receiver.
(1)
24
Voltage indicated assumes nominal VDD33.
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: DS90UB921-Q1
DS90UB921-Q1
www.ti.com
SNLS488 – MARCH 2016
Device Functional Modes (continued)
1:3 Repeater
1:3 Repeater
TX
Source
TX
TX
RX
Display
TX
RX
Display
TX
RX
Display
TX
RX
Display
TX
RX
Display
TX
RX
Display
TX
RX
Display
TX
RX
Display
TX
RX
Display
RX
RX
TX
TX
1:3 Repeater
RX
1:3 Repeater
RX
Figure 19. Maximum Repeater Application
In a repeater application, the I2C interface at each TX and RX may be configured to transparently pass I2C
communications upstream or downstream to any I2C device within the system. This includes a mechanism for
assigning alternate IDs (Slave Aliases) to downstream devices in the case of duplicate addresses.
At each repeater node, the parallel LVCMOS interface fans out to up to three serializer devices, providing parallel
RGB video data, HS/VS/DE control signals and, optionally, packetized audio data (transported during video
blanking intervals). Alternatively, the I2S audio interface may be used to transport digital audio data between
receiver and transmitters in place of packetized audio. All audio and video data is transmitted at the output of the
Receiver and is received by the Transmitter.
Figure 20 provides more detailed block diagram of a 1:2 repeater configuration.
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: DS90UB921-Q1
25
DS90UB921-Q1
SNLS488 – MARCH 2016
www.ti.com
Device Functional Modes (continued)
DS90UB921-Q1
Transmitter
I2C
Master
upstream
Transmitter
downstream
Receiver
or
Repeater
I2C
Slave
I2C
Parallel
LVCMOS
DS90UB926-Q1
Receiver
DS90UB921-Q1
Transmitter
I2S Audio
downstream
Receiver
or
Repeater
I2C
Slave
FPD-Link III interfaces
Figure 20. 1:2 Repeater Configuration
7.4.2.2 Repeater Connections
The Repeater requires the following connections between the Receiver and each Transmitter Figure 21.
1. Video Data – Connect PCLK, RGB and control signals (DE, VS, HS).
2. I2C – Connect SCL and SDA signals. Both signals should be pulled up to VDD33 with 4.7 kΩ resistors.
3. Audio – Connect I2S_CLK, I2S_WC, and I2S_DA signals.
4. IDx pin – Each Transmitter and Receiver must have an unique I2C address.
5. MODE_SEL pin – All Transmitter and Receiver must be set into the Repeater Mode.
6. Interrupt pin – Connect DS90UB926Q-Q1 INTB_IN pin to DS90UB921-Q1 INTB pin. The signal must be
pulled up to VDDIO.
DS90UB926-Q1
DS90UB921-Q1
RGB[7:0) / ROUT[23:0]
VDD33
DIN[23:0] / RGB[7:0]
DE
DE
VS
VS
HS
HS
I2S_CLK
I2S_CLK
I2S_WC
I2S_WC
I2S_DA
I2S_DA
Optional
MODE_SEL
VDD33
MODE_SEL
VDDIO
INTB_IN
Optional
INTB
VDD33
VDD33
ID[x]
VDD33
SDA
SDA
SCL
SCL
ID[x]
Figure 21. Repeater Connection Diagram
26
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: DS90UB921-Q1
DS90UB921-Q1
www.ti.com
SNLS488 – MARCH 2016
7.5 Programming
The DS90UB921-Q1 is configured by the use of a serial control bus that is I2C protocol compatible. Multiple
serializer devices may share the serial control bus since 9 device addresses are supported. Device address is
set via R1 and R2 values on IDx pin. See Figure 22.
The serial control bus consists of two signals and a configuration pin. The SCL is a Serial Bus Clock Input /
Output. The SDA is the Serial Bus Data Input / Output signal. Both SCL and SDA signals require an external
pull-up resistor to VDD33. For most applications a 4.7 k pull-up resistor to VDD33 may be used. The resistor
value may be adjusted for capacitive loading and data rate requirements. The signals are either pulled High, or
driven Low.
VDD33
R1
VDD33
VR2
4.7k
HOST
or
Slave SCL
4.7k
IDx
R2
DS90UB921-Q1
SCL
SDA
SDA
To other
Devices
Figure 22. Serial Control Bus Connection
The configuration pin is the IDx pin. This pin sets one of 8 possible device addresses. A pull-up resistor and a
pull-down resistor of suggested values may be used to set the voltage ratio of the IDx input (VR2) and VDD33 to
select one of the other 8 possible addresses. The voltage range in between the Minimum and Maximum VR2
must be adhered even when taking resistor tolerances into account. The 1% suggested resistors meet this for all
cases, but others that also meet the desired voltage range are also acceptable. See Table 6.
Table 6. Serial Control Bus Addresses for IDx
(1)
#
Minimum Voltage
VR2 (V) (1)
Maximum Voltage
VR2
(V) (1)
1
0.000
0.150
Open
40.2 or Any
0x0C
0x18
2
0.535
0.578
86.6
17.4
0x0E
0x1C
3
0.723
0.775
90.9
26.7
0x10
0x20
4
0.947
0.995
71.5
30.1
0x12
0x24
5
1.203
1.258
84.5
49.9
0x14
0x28
6
1.493
1.565
54.9
47.5
0x16
0x2C
7
1.789
1.855
78.7
97.6
0x18
0x30
8
2.469
2.515
30.9
95.3
0x1A
0x34
Suggested Resistor Suggested Resistor
R1 kΩ (1% tol)
R2 kΩ (1% tol)
Address 7'b
Address 8'b
Appended
Voltage indicated assumes nominal VDD33.
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: DS90UB921-Q1
27
DS90UB921-Q1
SNLS488 – MARCH 2016
www.ti.com
The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when
SCL transitions Low while SDA is High. A STOP occurs when SDA transition High while SCL is also HIGH. See
Figure 23.
SDA
SCL
S
P
START condition, or
START repeat condition
STOP condition
Figure 23. Start and Stop Conditions
To communicate with a remote device, the host controller (master) sends the slave address and listens for a
response from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is
addressed correctly, it Acknowledges (ACKs) the master by driving the SDA bus low. If the address doesn't
match a device's slave address, it Not-acknowledges (NACKs) the master by letting SDA be pulled High. ACKs
also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs after
every data byte is successfully received. When the master is reading data, the master ACKs after every data
byte is received to let the slave know it wants to receive another data byte. When the master wants to stop
reading, it NACKs after the last data byte and creates a stop condition on the bus. All communication on the bus
begins with either a Start condition or a Repeated Start condition. All communication on the bus ends with a Stop
condition. A READ is shown in Figure 24 and a WRITE is shown in Figure 25.
If the Serial Bus is not required, the three pins may be left open (NC).
Register Address
Slave Address
S
A
2
A
1
A
0
0
Slave Address
a
c
k
a
c
k
A
2
S
A
1
A
0
Data
1
a
c
k
a
c
k
P
Figure 24. Serial Control Bus — Read
Register Address
Slave Address
S
A
2
A
1
A
0
0
a
c
k
Data
a
c
k
a
c
k
P
Figure 25. Serial Control Bus — Write
7.6 Register Maps
28
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: DS90UB921-Q1
DS90UB921-Q1
www.ti.com
SNLS488 – MARCH 2016
Table 7. Serial Control Bus Registers
ADD
(dec)
ADD
(hex)
0
0x00
1
0x01
REGISTER NAME
I2C Device ID
Reset
DEFAULT
(hex)
BIT(S)
TYPE
7:1
RW
Device ID
7–bit address of Serializer
0
RW
ID Setting
I2C ID Setting
1: Register I2C Device ID (Overrides IDx pin)
0: Device ID is from IDx pin
7
RW
Soft Sleep
1: Enable power down when no Bidirectional Control Channel Link detected.
0: Do not power down when no Bidirectional Control Channel Link detected.
0x00
FUNCTION
6:2
3
0x03
Configuration [0]
DESCRIPTION
Reserved
1
RW
Digital RESET1
Reset the entire digital block including registers
This bit is self-clearing.
1: Reset
0: Normal operation
0
RW
Digital RESET0
Reset the entire digital block except registers
This bit is self-clearing
1: Reset
0: Normal operation
7
RW
Back channel
CRC Checker
Enable
Back Channel Check Enable
1: Enable
0: Disable
0xD2
6
Reserved
5
RW
I2C Remote
Write Auto
Acknowledge
Automatically Acknowledge I2C Remote Write When enabled, I2C writes to
the Deserializer (or any remote I2C Slave, if I2C PASS ALL is enabled) are
immediately acknowledged without waiting for the Deserializer to
acknowledge the write. This allows higher throughput on the I2C bus
1: Enable
0: Disable
4
RW
Filter Enable
HS, VS, DE two clock filter When enabled, pulses less than two full PCLK
cycles on the DE, HS, and VS inputs will be rejected
1: Filtering enable
0: Filtering disable
3
RW
I2C Passthrough
I2C Pass-Through Mode
1: Pass-Through Enabled
0: Pass-Through Disabled
1
RW
PCLK Auto
Switch over to internal OSC in the absence of PCLK
1: Enable auto-switch
0: Disable auto-switch
0
RW
TRFB
Pixel Clock Edge Select
1: Parallel Interface Data is strobed on the Rising Clock Edge.
0: Parallel Interface Data is strobed on the Falling Clock Edge.
2
Reserved
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: DS90UB921-Q1
29
DS90UB921-Q1
SNLS488 – MARCH 2016
www.ti.com
Table 7. Serial Control Bus Registers (continued)
ADD
(dec)
ADD
(hex)
4
0x04
REGISTER NAME
Configuration [1]
BIT(S)
TYPE
DEFAULT
(hex)
7
RW
0x80
FUNCTION
Failsafe State
6
5
Input Failsafe State
1: Failsafe to Low
0: Failsafe to High
Reserved
RW
4
30
DESCRIPTION
CRC Error Reset Clear back channel CRC Error Counters
This bit is NOT self-clearing
1: Clear Counters
0: Normal Operation
RGB
DE Gate
1: Gate RGB data with DE
0: Pass RGB data independent of DE (default)
This bit is recommended to be set to 1 to avoid unintentionally entering
AVMUTE mode. See AVMUTE Operation.
3:2
RW
Reserved
Reserved
1
RW
ALTERNATE
FREQUENCY
select by pin or
register control
Frequency range is set by MODE_SEL pin or register, in conjunction with
FSEL pin or register 0x35[7:6]. See Frequency Mode Optimizations.
1: Frequency range is set by register. Use register bit reg_0x04[0] to set
Alternate Frequency.
0: Frequency range is set by MODE_SEL pin.
0
RW
ALTERNATE
FREQUENCY
Override Value
Frequency range select, in conjunction with FSEL pin or register 0x35[7:6].
See Frequency Mode Optimizations.
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: DS90UB921-Q1
DS90UB921-Q1
www.ti.com
SNLS488 – MARCH 2016
Table 7. Serial Control Bus Registers (continued)
ADD
(dec)
ADD
(hex)
5
0x05
6
7
0x06
0x07
REGISTER NAME
I2C Control
DES ID
Slave ID
BIT(S)
TYPE
7:5
DEFAULT
(hex)
FUNCTION
0x00
DESCRIPTION
Reserved
4:3
RW
SDA Output
Delay
SDA output delay
Configures output delay on the SDA output. Setting this value will increase
output delay in units of 40ns.
Nominal output delay values for SCL to SDA are
00: 240ns
01: 280ns
10: 320ns
11: 360ns
2
RW
Local Write
Disable
Disable remote writes to local registers
Setting the bit to a 1 prevents remote writes to local device registers from
across the control channel. It prevents writes to the Serializer registers from
an I2C master attached to the Deserializer.
Setting this bit does not affect remote access to I2C slaves at the Serializer
1
RW
I2C Bus Timer
Speedup
Speed up I2C bus watchdog timer
1: Watchdog timer expires after ~50 ms.
0: Watchdog Timer expires after ~1 s
0
RW
I2C Bus timer
Disable
Disable I2C bus watchdog timer
When the I2C watchdog timer may be used to detect when the I2C bus is
free or hung up following an invalid termination of a transaction.
If SDA is high and no signalling occurs for ~1 s, the I2C bus assumes to be
free. If SDA is low and no signaling occurs, the device attempts to clear the
bus by driving 9 clocks on SCL
7:1
RW
DES Device ID
7-bit Deserializer Device ID
Configures the I2C Slave ID of the remote Deserializer. A value of 0 in this
field disables I2C access to the remote Deserializer. This field is
automatically configured by the Bidirectional Control Channel once RX Lock
has been detected. Software may overwrite this value, but should also
assert the FREEZE DEVICE ID bit to prevent overwriting by the
Bidirectional Control Channel.
0
RW
Device ID
Frozen
Freeze Deserializer Device ID
Prevents autoloading of the Deserializer Device ID by the Bidirectional
Control Channel. The ID will be frozen at the value written.
7:1
RW
Slave Device ID
7-bit Remote Slave Device ID
Configures the physical I2C address of the remote I2C Slave device
attached to the remote Deserializer. If an I2C transaction is addressed to
the Slave Device Alias ID, the transaction will be remapped to this address
before passing the transaction across the Bidirectional Control Channel to
the Deserializer
0
0x00
0x00
Reserved
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: DS90UB921-Q1
31
DS90UB921-Q1
SNLS488 – MARCH 2016
www.ti.com
Table 7. Serial Control Bus Registers (continued)
ADD
(dec)
ADD
(hex)
8
0x08
REGISTER NAME
Slave Alias
BIT(S)
TYPE
DEFAULT
(hex)
7:1
RW
0x00
FUNCTION
Slave Device
Alias ID
0
10
0x0A
11
0x0B
12
0x0C
13
32
0x0D
CRC Errors
General Status
GPIO0 Configuration
DESCRIPTION
7-bit Remote Slave Device Alias ID
Assigns an Alias ID to an I2C Slave device attached to the remote
Deserializer. The transaction will be remapped to the address specified in
the Slave ID register. A value of 0 in this field disables access to the remote
I2C Slave.
Reserved
7:0
R
0x00
CRC Error LSB
Number of back channel CRC errors – 8 least significant bits
7:0
R
0x00
CRC Error MSB
Number of back channel CRC errors – 8 most significant bits
7:4
0x00
Reserved
3
R
BIST CRC Error
Back channel CRC error during BIST communication with Deserializer.
The bit is cleared upon loss of link, restart of BIST, or assertion of CRC
ERROR RESET in register 0x04.
2
R
PCLK Detect
PCLK Status
1: Valid PCLK detected
0: Valid PCLK not detected
1
R
DES Error
Back channel CRC error during communication with Deserializer.
The bit is cleared upon loss of link or assertion of CRC ERROR RESET in
register 0x04.
0
R
LINK Detect
LINK Status
1: Cable link detected
0: Cable link not detected (Fault Condition)
7:4
R
RESERVED
Reserved
3
RW
0x00
GPIO0 Output
Value
Local GPIO output value
This value is output on the GPIO pin when the GPIO function is enabled,
the local GPIO direction is Output, and remote GPIO control is disabled.
2
RW
GPIO0 Remote
Enable
Remote GPIO control
1: Enable GPIO control from remote Deserializer. The GPIO pin will be an
output, and the value is received from the remote Deserializer.
0: Disable GPIO control from remote Deserializer.
1
RW
GPIO0 Direction
Local GPIO Direction
1: Input
0: Output
0
RW
GPIO0 Enable
GPIO function enable
1: Enable GPIO operation
0: Enable normal operation
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: DS90UB921-Q1
DS90UB921-Q1
www.ti.com
SNLS488 – MARCH 2016
Table 7. Serial Control Bus Registers (continued)
ADD
(dec)
ADD
(hex)
14
0x0E
REGISTER NAME
GPIO2 and GPIO1
Configurations
BIT(S)
TYPE
DEFAULT
(hex)
7
RW
0x00
6
FUNCTION
DESCRIPTION
GPIO2 Output
Value
Local GPIO output value
This value is output on the GPIO pin when the GPIO function is enabled,
the local GPIO direction is Output, and remote GPIO control is disabled.
RW
GPIO2 Remote
Enable
Remote GPIO control
1: Enable GPIO control from remote Deserializer. The GPIO pin will be an
output, and the value is received from the remote Deserializer.
0: Disable GPIO control from remote Deserializer.
5
RW
GPIO2 Direction
Local GPIO Direction
1: Input
0: Output
4
RW
GPIO2 Enable
GPIO function enable
1: Enable GPIO operation
0: Enable normal operation
3
RW
GPIO1 Output
Value
Local GPIO output value
This value is output on the GPIO pin when the GPIO function is enabled,
the local GPIO direction is Output, and remote GPIO control is disabled.
2
RW
GPIO1 Remote
Enable
Remote GPIO control
1: Enable GPIO control from remote Deserializer. The GPIO pin will be an
output, and the value is received from the remote Deserializer.
0: Disable GPIO control from remote Deserializer.
1
RW
GPIO1 Direction
Local GPIO Direction
1: Input
0: Output
0
RW
GPIO1 Enable
GPIO function enable
1: Enable GPIO operation
0: Enable normal operation
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: DS90UB921-Q1
33
DS90UB921-Q1
SNLS488 – MARCH 2016
www.ti.com
Table 7. Serial Control Bus Registers (continued)
ADD
(dec)
ADD
(hex)
15
0x0F
REGISTER NAME
BIT(S)
TYPE
DEFAULT
(hex)
GPO_REG4 and
GPIO3 Configurations
7
RW
0x00
FUNCTION
GPO_REG4
Output Value
6:5
16
0x10
GPO_REG6 and
GPO_REG5
Configurations
Local GPO_REG4 output value
This value is output on the GPO pin when the GPO function is enabled.
(The local GPO direction is Output, and remote GPO control is disabled)
Reserved
4
RW
GPO_REG4
Enable
GPO_REG4 function enable
1: Enable GPO operation
0: Enable normal operation
3
RW
GPIO3 Output
Value
Local GPIO output value
This value is output on the GPIO pin when the GPIO function is enabled,
the local GPIO direction is Output, and remote GPIO control is disabled.
2
RW
GPIO3 Remote
Enable
Remote GPIO control
1: Enable GPIO control from remote Deserializer. The GPIO pin will be an
output, and the value is received from the remote Deserializer.
0: Disable GPIO control from remote Deserializer.
1
RW
GPIO3 Direction
Local GPIO Direction
1: Input
0: Output
0
RW
GPIO3 Enable
GPIO function enable
1: Enable GPIO operation
0: Enable normal operation
7
RW
GPO_REG6
Output Value
Local GPO_REG6 output value
This value is output on the GPO pin when the GPO function is enabled.
(The local GPO direction is Output, and remote GPO control is disabled)
0x00
6:5
Reserved
4
RW
GPO_REG6
Enable
GPO_REG6 function enable
1: Enable GPO operation
0: Enable normal operation
3
RW
GPO_REG5
Output Value
Local GPO_REG5 output value
This value is output on the GPO pin when the GPO function is enabled, the
local GPO direction is Output, and remote GPO control is disabled.
RW
GPO_REG5
Enable
2:1
0
34
DESCRIPTION
Reserved
GPO_REG5 function enable
1: Enable GPO operation
0: Enable normal operation
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: DS90UB921-Q1
DS90UB921-Q1
www.ti.com
SNLS488 – MARCH 2016
Table 7. Serial Control Bus Registers (continued)
ADD
(dec)
ADD
(hex)
17
0x11
REGISTER NAME
GPO_REG7
Configurations
BIT(S)
TYPE
DEFAULT
(hex)
7:4
RW
0x00
Reserved
Reserved
3
RW
GPO_REG7
Output Value
Local GPO_REG7 output value
This value is output on the GPO pin when the GPO function is enabled, the
local GPO direction is Output, and remote GPO control is disabled.
RW
GPO_REG7
Enable
FUNCTION
2:1
0
18
0x12
Data Path Control
Reserved
7:6
0x00
5
RW
DE Polarity
The bit indicates the polarity of the DE (Data Enable) signal.
1: DE is inverted (active low, idle high)
0: DE is positive (active high, idle low)
4
RW
I2S Repeater
Regen
I2S Repeater Regeneration
1: Repeater regenerate I2S from I2S pins
0: Repeater pass through I2S from video pins
2
RW
18-bit Video
Select
18–bit video select
1: Select 18-bit video mode
Note: use of GPIO(s) on unused inputs must be enabled by register.
0: Select 24-bit video mode
1
RW
I2S Transport
Select
I2S Transport Mode Slect
1: Enable I2S Data Forward Channel Frame Transport
0: Enable I2S Data Island Transport
Reserved
0
0x13
Mode Status
GPO_REG7 function enable
1: Enable GPO operation
0: Enable normal operation
Reserved
3
19
DESCRIPTION
Reserved
7:5
0x10
Reserved
4
R
MODE_SEL
MODE_SEL Status
1: MODE_SEL decode circuit is completed
0: MODE_SEL decode circuit is not completed
3
R
Alternate
Alternate Frequency Mode Status
Frequency Mode Indicates either Low Frequency mode or Intermediate Frequency mode,
depending on FSEL status. See Frequency Mode Optimizations.
2
R
Repeater Mode
1
R
0
R
Repeater Mode Status
1: Repeater mode ON
0: Repeater Mode OFF
Reserved
18-Bit Mode
18-bit Mode Strap Status. The initial strap value can be overridden by
register 0x12[2].
1: 18-bit RGB mode
0: 24-bit RGB mode
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: DS90UB921-Q1
35
DS90UB921-Q1
SNLS488 – MARCH 2016
www.ti.com
Table 7. Serial Control Bus Registers (continued)
ADD
(dec)
ADD
(hex)
20
0x14
22
23
0x16
0x17
REGISTER NAME
Oscillator Clock
Source and BIST
Status
BCC Watchdog
Control
I2C Control
BIT(S)
TYPE
7:3
DEFAULT
(hex)
FUNCTION
0x00
2:1
RW
0
R
7:1
RW
0
RW
7
RW
0xFE
0x5E
Reserved
OSC Clock
Source
OSC Clock Source
(When LFMODE = 1, Oscillator = 12.5MHz ONLY)
00: External Pixel Clock
01: 33 MHz Oscillator
10: Reserved
11: 25 MHz Oscillator
BIST Enable
Status
BIST status
1: Enabled
0: Disabled
Timer Value
The watchdog timer allows termination of a control channel transaction if it
fails to complete within a programmed amount of time.
This field sets the Bidirectional Control Channel Watchdog Timeout value in
units of 2 ms.
This field should not be set to 0
Timer Control
Disable Bidirectional Control Channel Watchdog Timer
1: Disables BCC Watchdog Timer operation
0: Enables BCC Watchdog Timer operation
I2C Pass All
I2C Control
1: Enable Forward Control Channel pass-through of all I2C accesses to I2C
Slave IDs that do not match the Serializer I2C Slave ID.
0: Enable Forward Control Channel pass-through only of I2C accesses to
I2C Slave IDs matching either the remote Deserializer Slave ID or the
remote Slave ID.
6
24
36
0x18
SCL High Time
DESCRIPTION
Reserved
5:4
RW
SDA Hold Time
Internal SDA Hold Time
Configures the amount of internal hold time provided for the SDA input
relative to the SCL input. Units are 40 ns
3:0
RW
I2C Filter Depth
Configures the maximum width of glitch pulses on the SCL and SDA inputs
that will be rejected. Units are 5 ns
7:0
RW
SCL HIGH Time
I2C Master SCL High Time
This field configures the high pulse width of the SCL output when the
Serializer is the Master on the local I2C bus. Units are 40 ns for the nominal
oscillator clock frequency. The default value is set to provide a minimum
5us SCL high time with the internal oscillator clock running at 32.5MHz
rather than the nominal 25MHz.
0xA1
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: DS90UB921-Q1
DS90UB921-Q1
www.ti.com
SNLS488 – MARCH 2016
Table 7. Serial Control Bus Registers (continued)
ADD
(dec)
ADD
(hex)
25
0x19
27
53
100
BIT(S)
TYPE
DEFAULT
(hex)
SCL Low Time
7:0
RW
0xA5
SCL LOW Time
I2C SCL Low Time
This field configures the low pulse width of the SCL output when the
Serializer is the Master on the local I2C bus. This value is also used as the
SDA setup time by the I2C Slave for providing data prior to releasing SCL
during accesses over the Bidirectional Control Channel. Units are 40 ns for
the nominal oscillator clock frequency. The default value is set to provide a
minimum 5us SCL low time with the internal oscillator clock running at
32.5MHz rather than the nominal 25MHz.
0x1B
BIST BC Error
7:0
R
0x00
BIST Back
Channel CRC
Error Counter
BIST Mode Back Channel CRC Error Counter
This error counter is active only in the BIST mode. It clears itself at the start
of the BIST run.
0x35
FSEL Override
7
RW
0
FSEL Register
Override Control
FSEL Override. FSEL value is set by pin or through register.
0: FSEL set by pin 15 at power-up
1: FSEL is set by register 0x35[6]
6
RW
0
FSEL Override
Value
This value will be used for FSEL when FSEL Register Override is set
(0x35[7]). See Frequency Mode Optimizations.
5:0
RW
0
RESERVED
Reserved.
7:4
RW
0x10
0x64
REGISTER NAME
Pattern Generator
Control
FUNCTION
Pattern
Fixed Pattern Select
Generator Select This field selects the pattern to output when in Fixed Pattern Mode. Scaled
patterns are evenly distributed across the horizontal or vertical active
regions. This field is ignored when Auto-Scrolling Mode is enabled. The
following table shows the color selections in non-inverted followed by
inverted color mode
0000: Reserved
0001: White/Black
0010: Black/White
0011: Red/Cyan
0100: Green/Magenta
0101: Blue/Yellow
0110: Horizontally Scaled Black to White/White to Black
0111: Horizontally Scaled Black to Red/Cyan to White
1000: Horizontally Scaled Black to Green/Magenta to White
1001: Horizontally Scaled Black to Blue/Yellow to White
1010: Vertically Scaled Black to White/White to Black
1011: Vertically Scaled Black to Red/Cyan to White
1100: Vertically Scaled Black to Green/Magenta to White
1101: Vertically Scaled Black to Blue/Yellow to White
1110: Custom color (or its inversion) configured in PGRS, PGGS, PGBS
registers
1111: Reserved
3:1
0
DESCRIPTION
Reserved
RW
Pattern
Generator
Enable
Pattern Generator Enable
1: Enable Pattern Generator
0: Disable Pattern Generator
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: DS90UB921-Q1
37
DS90UB921-Q1
SNLS488 – MARCH 2016
www.ti.com
Table 7. Serial Control Bus Registers (continued)
ADD
(dec)
ADD
(hex)
101
0x65
REGISTER NAME
Pattern Generator
Configuration
BIT(S)
TYPE
7:5
DEFAULT
(hex)
FUNCTION
0x00
Reserved
4
RW
Pattern
Generator 18
Bits
18-bit Mode Select
1: Enable 18-bit color pattern generation. Scaled patterns will have 64 levels
of brightness and the R, G, and B outputs use the six most significant color
bits.
0: Enable 24-bit pattern generation. Scaled patterns use 256 levels of
brightness.
3
RW
Pattern
Generator
External Clock
Select External Clock Source
1: Selects the external pixel clock when using internal timing.
0: Selects the internal divided clock when using internal timing
This bit has no effect in external timing mode (PATGEN_TSEL = 0).
2
RW
Pattern
Generator
Timing Select
Timing Select Control
1: The Pattern Generator creates its own video timing as configured in the
Pattern Generator Total Frame Size, Active Frame Size. Horizontal Sync
Width, Vertical Sync Width, Horizontal Back Porch, Vertical Back Porch, and
Sync Configuration registers.
0: the Pattern Generator uses external video timing from the pixel clock,
Data Enable, Horizontal Sync, and Vertical Sync signals.
1
RW
Pattern
Generator Color
Invert
Enable Inverted Color Patterns
1: Invert the color output.
0: Do not invert the color output.
0
RW
Pattern
Generator AutoScroll Enable
Auto-Scroll Enable:
1: The Pattern Generator will automatically move to the next enabled
pattern after the number of frames specified in the Pattern Generator Frame
Time (PGFT) register.
0: The Pattern Generator retains the current pattern.
102
0x66
Pattern Generator
Indirect Address
7:0
RW
0x00
Indirect Address
This 8-bit field sets the indirect address for accesses to indirectly-mapped
registers. It should be written prior to reading or writing the Pattern
Generator Indirect Data register.
See AN-2198 (SNLA132).
103
0x67
Pattern Generator
Indirect Data
7:0
RW
0x00
Indirect Data
When writing to indirect registers, this register contains the data to be
written. When reading from indirect registers, this register contains the read
back value.
See AN-2198 (SNLA132)
198
0xC6
ICR
7:6
5
Reserved
RW
IS_RX_INT
RW
INT Enable
4:1
0
38
DESCRIPTION
Interrupt on Receiver interrupt
Enables interrupt on indication from the Receiver. Allows propagation of
interrupts from downstream devices
Reserved
Global Interrupt Enable
Enables interrupt on the interrupt signal to the controller.
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: DS90UB921-Q1
DS90UB921-Q1
www.ti.com
SNLS488 – MARCH 2016
Table 7. Serial Control Bus Registers (continued)
ADD
(dec)
ADD
(hex)
199
0xC7
REGISTER NAME
ISR
BIT(S)
TYPE
DEFAULT
(hex)
FUNCTION
7:6
5
Reserved
R
IS RX INT
R
INT
4:1
0
DESCRIPTION
Interrupt on Receiver interrupt
Receiver has indicated an interrupt request from down-stream device
Reserved
Global Interrupt
Set if any enabled interrupt is indicated
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: DS90UB921-Q1
39
DS90UB921-Q1
SNLS488 – MARCH 2016
www.ti.com
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DS90UB921-Q1, in conjunction with the DS90UB948-Q1, is intended for interface between a host (graphics
processor) and a Display. It supports a 24-bit color depth (RGB888) and extended high definition (1920x720p)
digital video format. It can receive a three 8-bit RGB stream with a pixel rate up to 96 MHz together with three
control bits (VS, HS and DE) and three I2S-bus audio stream with an audio sampling rate up to 192 kHz.
8.2 AVMUTE Operation
When using DS90UB921-Q1, it is possible to send video data during the blanking period (DE = L). If a specific
pattern is sent during the blanking period, the paired Deserializer will enter AVMUTE mode. The pattern that the
Deserializer is looking for is 24'h666666. If the last pixel of the frame is 24'h666666, and the video transmission
extends into the DE = L, period, then AVMUTE mode will be enabled.
Setting 0x04[1] = "1" on the DS90UB921-Q1 will prevent video from being sent during the blanking interval. This
will ensure AVMUTE mode is not entered during normal operation.
40
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: DS90UB921-Q1
DS90UB921-Q1
www.ti.com
SNLS488 – MARCH 2016
8.3 Typical Application
DS90UB921-Q1
3.3V/1.8V
VDDIO
FB1
3.3V
VDD33
C5
FB2
C4
DIN0
DIN1
DIN2
DIN3
DIN4
DIN5
DIN6
DIN7
CAPP12
C6
CAPL12
C7
C8
CAPHS12
DIN8
DIN9
DIN10
DIN11
DIN12
DIN13
DIN14
DIN15
LVCMOS
Parallel
Video
Interface
C9
C1
Serial
FPD-Link III
Interface
DOUT+
DOUTCMF
C2
C3
DIN16
DIN17
DIN18
DIN19
DIN20
DIN21
DIN22
DIN23
VDD33
R3
MODE_SEL
R4
PCLK
R6
R5
INTB
PDB
C10
REM_INTB
I2S_CLK
I2S_WC
I2S_DA
FSEL
C11
VDD33
ID[X]
SCL
SDA
4.7k
LVCMOS
Control
Interface
HS
VS
DE
4.7k
VDDIO VDD33*
R1
R2
C12
NOTE:
FB1-FB2: Impedance = 1 k: @ 100 MHz,
Low DC resistance (10 PF
R1 and R2 (see IDx Resistor Values Table)
R3 and R4 (see MODE_SEL Resistor Values Table)
RES1
DAP (GND)
R5 = 10 k:
R6 = 4.7 k:
* or VDDIO = 3.3V+0.3V
Figure 26. Typical STP Connection Diagram
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: DS90UB921-Q1
41
DS90UB921-Q1
SNLS488 – MARCH 2016
www.ti.com
Typical Application (continued)
DS90UB921-Q1
3.3V/1.8V
VDDIO
FB1
3.3V
VDD33
C5
FB2
C4
DIN0
DIN1
DIN2
DIN3
DIN4
DIN5
DIN6
DIN7
CAPP12
C6
CAPL12
C7
C8
CAPHS12
DIN8
DIN9
DIN10
DIN11
DIN12
DIN13
DIN14
DIN15
LVCMOS
Parallel
Video
Interface
C9
C1
Serial
FPD-Link III
Interface
DOUT+
DOUTCMF
C2
R7
C3
DIN16
DIN17
DIN18
DIN19
DIN20
DIN21
DIN22
DIN23
VDD33
R3
MODE_SEL
R4
PCLK
R6
R5
INTB
PDB
C10
REM_INTB
I2S_CLK
I2S_WC
I2S_DA
FSEL
C11
VDD33
ID[X]
SCL
SDA
4.7k
LVCMOS
Control
Interface
HS
VS
DE
4.7k
VDDIO VDD33*
R1
R2
C12
NOTE:
FB1-FB2: Impedance = 1 k: @ 100 MHz,
Low DC resistance (10 PF
C11-C12 = 0.1 PF
R1 and R2 (see IDx Resistor Values Table)
RES1
DAP (GND)
R3 and R4 (see MODE_SEL Resistor Values Table)
R5 = 10 k:
R6 = 4.7 k:
R7 = 50 :
* or VDDIO = 3.3V+0.3V
Figure 27. Typical Coax Connection Diagram
42
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: DS90UB921-Q1
DS90UB921-Q1
www.ti.com
SNLS488 – MARCH 2016
Typical Application (continued)
VDDIO
VDD33
(3.3V) (1.8V or 3.3V)
HOST
Graphics
Processor
RGB Digital Display Interface
VDDIO
VDD33
(1.8V or 3.3V) (3.3V)
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
DOUT+
RIN+
DOUT-
RIN-
DS90UB921-Q1
Serializer
PDB
I2S AUDIO
(STEREO)
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
FPD-Link III
1 Pair / AC Coupled
3
MODE_SEL
INTB
SCL
SDA
IDx
PDB
OSS_SEL
OEN
MODE_SEL
DS90UB926Q-Q1
Deserializer
LOCK
PASS
3
I2S AUDIO
(STEREO)
MCLK
INTB_IN
SCL
SDA
IDx
DAP
RGB Display
720p
24-bit color depth
DAP
Figure 28. Typical STP System Diagram
HOST
Graphics
Processor
RGB Digital Display Interface
VDDIO
VDD33
(1.8V or 3.3V) (3.3V)
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
FPD-Link
(Open LDI)
FPD-Link III
1 Pair / AC Coupled
CLK1+/-
DOUT+
RIN0+
DOUT-
RIN0-
D0+/D1+/-
DS90UB921-Q1
Serializer
PDB
I2S AUDIO
(STEREO)
VDDIO
VDD33 VDD12
(1.8V or 3.3V) (3.3V) (1.2V)
3
D2+/D3+/-
PDB
DS90UB948-Q1
Deserializer
D4+/-
INTB_IN
MODE_SEL
MODE_SEL[1:0]
INTB
SCL
SDA
IDx
D5+/-
SCL
SDA
IDx
DAP
CLK2+/-
LVDS
Display
720p60
or Graphic
Processor
D6+/D7+/-
Figure 29. Typical Coax Applications Diagram
8.3.1 Design Requirements
For the typical design application, use the following as input parameters.
Table 8. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
VDDIO
1.8 V or 3.3 V
VDD33
3.3 V
AC Coupling Capacitor for DOUT±
100 nF on DOUT+ and 100nF on DOUT- for STP
330nF on DOUT+ and 150nF on DOUT- for Coax
PCLK Frequency
74.25 MHz
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: DS90UB921-Q1
43
DS90UB921-Q1
SNLS488 – MARCH 2016
www.ti.com
8.3.2 Detailed Design Procedure
Figure 26 shows a typical application of the DS90UB921-Q1 serializer for an 96 MHz 24-bit Color Display
Application. The CML outputs must have an external 0.1 μF AC coupling capacitor on the high speed serial lines
for STP applications and 0.33 μF / 0.15 μF AC coupling capacitors for coax applications. The same AC coupling
capacitor values should be used on the paired deserializer board. The serializer has an internal termination.
Bypass capacitors are placed near the power supply pins. At a minimum, six (6) 4.7μF capacitors and two (2)
additional 1μF capacitors should be used for local device bypassing. Ferrite beads are placed on the two (2)
VDDs (VDD33 and VDDIO) for effective noise suppression. The interface to the graphics source is with 3.3V
LVCMOS levels, thus the VDDIO pin is connected to the 3.3 V rail.
CML Serializer Data Throughput
(80 mV/DIV)
CML Serializer Data Throughput
(80 mV/DIV)
Time (2.0 ns/DIV)
Time (200 ps/DIV)
Figure 30. Serializer Eye Diagram with 74.25 MHz TX Pixel
Clock
44
74.25 MHz TX Pixel Clock Input
(200 mV/DIV)
8.3.3 Application Curves
Figure 31. Serializer CML Output with 74.25 MHz TX Pixel
Clock
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: DS90UB921-Q1
DS90UB921-Q1
www.ti.com
SNLS488 – MARCH 2016
9 Power Supply Recommendations
9.1 Power Up Requirements and PDB Pin
When VDDIO and VDD33 are powered separately, the VDDIO supply (1.8V or 3.3V) should ramp 100us before
the other supply, VDD33. If VDDIO is tied with VDD33, both supplies may ramp at the same time. The VDDs
(VDD33 and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If the PDB pin is not
controlled by a microcontroller, a large capacitor on the pin is needed to ensure PDB arrives after all the VDDs
have settled to the recommended operating voltage. When PDB pin is pulled to VDDIO = 3.0V to 3.6V or
VDD33, it is recommended to use a 10 kΩ pull-up and a >10 uF cap to GND to delay the PDB input signal.
A minimum low pulse of 2ms is required when toggling the PDB pin to perform a hard reset.
All inputs must not be driven until VDD33 and VDDIO has reached its steady state value.
t0
VDDIO
GND
t3
VDD33
GND
t1
VDD33
VPDB_HIGH
PDB(*)
VPDB_LOW
t4
GND
(*)
It is recommended to assert PDB (active High) with a microcontroller rather than an RC filter
network to help ensure proper sequencing of PDB pin after settling of power supplies.
Figure 32. Timing Diagram of DS90UB921-Q1
Table 9. Power-Up Sequencing Constraints
Symbol
Description
Test Conditions
VDDIO
VDDIO voltage range
VDD33
VDD33 voltage range
VPDB_LOW
PDB LOW threshold
Note: VPDB should not exceed
limit for respective I/O voltage
before 90% voltage of VDD12
VPDB_HIGH
PDB HIGH threshold
VDDIO = 3.3V ± 10%
t0
VDDIO rise time
These time constants are specified for
rise time of power supply voltage ramp
(10% - 90%)
t3
VDD33 rise time
These time constants are specified for
rise time of power supply voltage ramp
(10% - 90%)
VDDIO = 3.3V ± 10%
Min
Max
Units
3.0
Typ
3.6
V
1.71
1.89
V
3.0
3.6
V
0.8
V
2.0
V
0.05
工商网监
湘ICP备2023018690号
