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DS90UH925AQ-Q1
SNLS481 – JUNE 2014
DS90UH925AQ-Q1 720p 24-bit Color FPD-Link III Serializer with HDCP
1 Features
3 Description
•
The DS90UH925AQ serializer, in conjunction with the
DS90UH926Q deserializer, provides a solution for
secure distribution of content-protected digital video
within automotive entertainment systems. This
chipset translates a parallel RGB Video Interface into
a single pair high-speed serialized interface. The
digital video data is protected using the industry
standard HDCP copy protection scheme. The serial
bus scheme, FPD-Link III, supports video and audio
data transmission and full duplex control including
I2C communication over a single differential link.
Consolidation of video data and control over a single
differential pair reduces the interconnect size and
weight, while also eliminating skew issues and
simplifying system design.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Integrated HDCP Cipher Engine with On-chip Key
Storage
Bidirectional Control Interface Channel Interface
with I2C Compatible Serial Control Bus
Supports High Definition (720p) Digital Video
Format
RGB888 + VS, HS, DE and I2S Audio Supported
5 – 85 MHz PCLK Supported
Single 3.3 V Operation with 1.8 V or 3.3 V
Compatible LVCMOS I/O Interface
AC-coupled STP Interconnect up to 10 meters
Parallel LVCMOS Video Inputs
DC-balanced & Scrambled Data with Embedded
Clock
Supports HDCP Repeater Application
Dedicated Interrupt Pin for Remote Interrupts
Internal Pattern Generation
Low Power Modes Minimize Power Dissipation
Automotive Grade Product: AEC-Q100 Grade 2
Qualified
>8 kV HBM and ISO 10605 ESD rating
Backward Compatible Modes
2 Applications
•
•
•
The DS90UH925AQ serializer embeds the clock,
content protects the data payload, and level shifts the
signals to high-speed low voltage differential
signaling. Up to 24 RGB data bits are serialized along
with three video control signals and up to two I2S
data inputs.
EMI is minimized by the use of low voltage differential
signaling, data scrambling and randomization and
spread spectrum clocking compatibility.
The HDCP cipher engine is implemented in the
serializer and deserializer. HDCP keys are stored in
on-chip memory.
Remote
interrupts
from
the
downstream
DS90UH926Q deserializer are mirrored to a local
output pin.
Automotive Touch Screen Display
Automotive Display for Navigation
Rear Seat Entertainment Systems
Device Information(1)
PART NUMBER
PACKAGE
DS90UH925AQ-Q1
WQFN RHS (48)
BODY SIZE (NOM)
7.00 mm × 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Eye Diagram
4 Simplified Schematic
0.1 PF
SCL
SDA
IDx
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
0.1 PF
DOUT+
RIN+
DOUT-
PDB
I2S AUDIO
(STEREO)
VDDIO
VDD33
(3.3V) (1.8V or 3.3V)
FPD-Link III
1 Pair / AC Coupled
3
/
DS90UH925AQ
Serializer
DAP
RIN100 ohm STP Cable
PDB
OSS_SEL
OEN
MODE_SEL
MODE_SEL
INTB
INTB_IN
REM_INTB
SCL
SDA
IDx
DS90UH926Q
Deserializer
LOCK
PASS
3
/
DAP
I2S AUDIO
(STEREO)
MCLK
RGB Display
720p
24-bit color depth
Magnitude (80 mV/DIV)
HOST
Graphics
Processor
RGB Digital Display Interface
VDD33
VDDIO
(1.8V or 3.3V) (3.3V)
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
Time (100 ps/DIV)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DS90UH925AQ-Q1
SNLS481 – JUNE 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
1
1
1
1
2
3
6
8
Typical Characteristics ........................................ 15
Detailed Description ............................................ 16
8.1 Overview ................................................................. 16
8.2 Device Functional Modes........................................ 23
8.3 Programming........................................................... 27
9
Application and Implementation ........................ 43
9.1 Application Information............................................ 43
9.2 Typical Application .................................................. 43
Absolute Maximum Ratings ...................................... 6
Handling Ratings....................................................... 6
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 7
DC Electrical Characteristics ................................... 8
AC Electrical Characteristics (1) (2) (3) ..................... 10
Recommended Timing for the Serial Control Bus .. 11
DC and AC Serial Control Bus Characteristics....... 12
AC Timing Diagrams and Test Circuits................... 12
Switching Characteristics ...................................... 15
10 Power Supply Recommendations ..................... 46
11 Layout................................................................... 47
11.1 Layout Guidelines ................................................. 47
11.2 Layout Example .................................................... 47
12 Device and Documentation Support ................. 50
12.1 Trademarks ........................................................... 50
12.2 Electrostatic Discharge Caution ............................ 50
12.3 Glossary ................................................................ 50
13 Mechanical, Packaging, and Orderable
Information ........................................................... 50
5 Revision History
2
DATE
REVISION
NOTES
June 2014
*
Initial release.
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SNLS481 – JUNE 2014
6 Pin Configuration and Functions
G1/GPIO3
G0/GPIO2
R7
R6
R5
INTB
VDDIO
R4
R3
R2
R1/GPIO1
R0/GPIO0
36
35
34
33
32
31
30
29
28
27
26
25
DS90UH925AQ Pin Diagram
48 Pins
Top View
G2
37
24
MODE_SEL
G3
38
23
CMF
G4
39
22
VDD33
G5
40
21
PDB
G6
41
20
DOUT+
G7
42
DS90UH925AQ
19
DOUT-
B0/GPO_REG4
43
TOP VIEW
18
RES1
B1/I2S_DB/GPO_REG5
44
17
CAPHS12
B2
45
16
REM_INTB
15
RES0
DAP = GND
5
6
7
8
9
10
11
12
IDx
CAPL12
SCL
SDA
PCLK
I2S_DA/GPO_REG6
I2S_WC/GPO_REG7
I2S_CLK
DE
13
4
48
VS
B5
3
CAPP12
HS
14
2
47
B7
B4
1
46
B6
B3
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SNLS481 – JUNE 2014
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Pin Functions
PIN NAME
PIN #
I/O, TYPE
DESCRIPTION
LVCMOS PARALLEL INTERFACE
R[7:0]
34, 33, 32, 29,
28, 27, 26, 25
I, LVCMOS
w/ pull down
RED Parallel Interface Data Input Pins
Leave open if unused
R0 can optionally be used as GPIO0 and R1 can optionally be used as GPIO1.
G[7:0]
42, 41, 40, 39,
38, 37, 36, 35
I, LVCMOS
w/ pull down
GREEN Parallel Interface Data Input Pins
Leave open if unused
G0 can optionally be used as GPIO2 and G1 can optionally be used as GPIO3.
B[7:0]
2, 1, 48, 47,
46, 45, 44, 43
I, LVCOS
w/ pull down
BLUE Parallel Interface Data Input Pins
Leave open if unused
B0 can optionally be used as GPO_REG4 and B1 can optionally be used as GPO_REG5.
HS
3
I, LVCMOS
w/ pull down
Horizontal Sync Input Pin
Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the
Control Signal Filter is enabled. There is no restriction on the minimum transition pulse when
the Control Signal Filter is disabled. The signal is limited to 2 transitions per 130 PCLKs.
See Table 6
VS
4
I, LVCMOS
w/ pull down
Vertical Sync Input Pin
Video control signal is limited to 1 transition per 130 PCLKs. Thus, the minimum pulse width
is 130 PCLKs.
DE
5
I, LVCMOS
w/ pull down
Data Enable Input Pin
Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the
Control Signal Filter is enabled. There is no restriction on the minimum transition pulse when
the Control Signal Filter is disabled. The signal is limited to 2 transitions per 130 PCLKs.
See Table 6
PCLK
10
I, LVCMOS
w/ pull down
Pixel Clock Input Pin. Strobe edge set by RFB configuration register. See Table 6
13, 12, 11
I, LVCMOS
w/ pull down
Digital Audio Interface Data Input Pins
Leave open if unused
I2S_WC can optionally be used as GPO_REG7, and I2S_DA can optionally be used as
GPO_REG6.
I2S_CLK,
I2S_WC,
I2S_DA
OPTIONAL PARALLEL INTERFACE
I2S_DB
44
I, LVCMOS
w/ pull down
Second Channel Digital Audio Interface Data Input pin at 18–bit color mode and set by
MODE_SEL pin or configuration register
Leave open if unused
I2S_DB can optionally be used as B1 or GPO_REG5.
GPIO[3:0]
36, 35, 26, 25
I/O, LVCMOS General Purpose IOs. Available only in 18-bit color mode, and set by MODE_SEL pin or
w/ pull down configuration register. See Table 6
Leave open if unused
Shared with G1, G0, R1 and R0.
GPO_REG[
7:4]
12, 11, 44, 43
O, LVCMOS
w/ pull down
General Purpose Outputs and set by configuration register. See Table 6
Share with I2S_CLK, I2S_WC, I2S_DA, I2S_DB or B1, B0.
Power-down Mode Input Pin
PDB = H, device is enabled (normal operation)
Refer to ”Power Up Requirements and PDB Pin” in the Applications Information Section.
PDB = L, device is powered down.
When the device is in the powered down state, the Driver Outputs are both HIGH, the PLL is
shutdown, and IDD is minimized. Control Registers are RESET.
CONTROL
PDB
21
I, LVCMOS
w/ pull-down
MODE_SEL
24
I, Analog
Device Configuration Select. See Table 4
IDx
6
I, Analog
I2C Serial Control Bus Device ID Address Select
External pull-up to VDD33 is required under all conditions, DO NOT FLOAT.
Connect to external pull-up and pull-down resistor to create a voltage divider. See Figure 20
SCL
8
I/O, LVCMOS I2C Clock Input / Output Interface
Open Drain Must have an external pull-up to VDD33, DO NOT FLOAT.
Recommended pull-up: 4.7 kΩ.
SDA
9
I/O, LVCMOS I2C Data Input / Output Interface
Open Drain Must have an external pull-up to VDD33, DO NOT FLOAT.
Recommended pull-up: 4.7 kΩ.
I2C
4
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Pin Functions (continued)
PIN NAME
PIN #
I/O, TYPE
DESCRIPTION
INTB
31
O, LVCMOS
Open Drain
Interrupt. Read ISR register to determine source. Interrupt clears on ISR read.
INTB = H, normal
INTB = L, Interrupt request
Recommended pull-up: 4.7 kΩ to VDDIO
REM_INTB
16
O, LVCMOS
Interrupt. Mirrors status of INTB_IN from the remote deserializer. Note: REM_INTB will be
driven LOW until lock is achieved with the downstream serializer.
REM_INTB = H, normal
REM_INTB = L, interrupt request
STATUS
FPD-Link III SERIAL INTERFACE
DOUT+
20
O, LVDS
True Output
The output must be AC-coupled with a 0.1µF capacitor.
DOUT-
19
O, LVDS
Inverting Output
The output must be AC-coupled with a 0.1µF capacitor.
CMF
23
Analog
Common Mode Filter.
Connect 0.1µF to GND
POWER (1) and GROUND
VDD33
22
Power
Power to on-chip regulator 3.0 V - 3.6 V. Requires 4.7 uF to GND
VDDIO
30
Power
LVCMOS I/O Power 1.8 V ±5% OR 3.0 V - 3.6 V. Requires 4.7 uF to GND
GND
DAP
Ground
DAP is the large metal contact at the bottom side, located at the center of the WQFN
package. Connect to the ground plane (GND) with at least 9 vias.
REGULATOR CAPACITOR
CAPHS12,
CAPP12
CAPL12
17, 14
CAP
Decoupling capacitor connection for on-chip regulator. Requires a 4.7uF to GND at each
CAP pin.
7
CAP
Decoupling capacitor connection for on-chip regulator. Requires two 4.7uF to GND at this
CAP pin.
18, 15
GND
Reserved. Tie to Ground.
OTHERS
RES[1:0]
(1)
The VDD (VDD33 and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. Refer to Power Up Requirements and
PDB Pin for details.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VDD33
Supply Voltage
PARAMETER
–0.3
+4.0
V
VDDIO
Supply Voltage
–0.3
+4.0
V
LVCMOS I/O Voltage
–0.3
VDDIO +
0.3
V
Serializer Output Voltage
–0.3
+2.75
V
+150
°C
TJ
Junction Temperature
For soldering specifications:
see product folder at www.ti.com and www.ti.com/lit/an/snoa549c/snoa549c.pdf
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 Handling Ratings
Tstg
Storage temperature range
48 Lead WQFN Package
Human body model (HBM), per AEC Q100-002
(1)
MIN
MAX
UNIT
-65
+150
°C
-8
+8
Charged device model (CDM), per AEC Q100-011
-1.25
+1.25
Machine Model
-250
+250
ESD Rating (IEC 61000-4-2)
RD = 330Ω, CS = 150pF
Air Discharge (DOUT+, DOUT-)
-15
+15
Contact Discharge (DOUT+, DOUT-)
-8
+8
ESD Rating (ISO10605)
RD = 330Ω, CS = 150pF
RD = 2KΩ, CS = 150pF or 330pF
Air Discharge (DOUT+, DOUT-)
-15
+15
Contact Discharge (DOUT+, DOUT-)
-8
+8
V(ESD)
(1)
Electrostatic discharge
kV
V
kV
kV
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
MIN
TYP
MAX
UNIT
Supply Voltage (VDD33)
3.0
3.3
3.6
V
LVCMOS Supply Voltage (VDDIO)
3.0
3.3
3.6
V
OR
LVCMOS Supply Voltage (VDDIO)
1.71
1.8
1.89
V
Operating Free Air Temperature (TA)
−40
+25
+105
°C
85
MHz
100
mVP-P
PCLK Frequency
Supply Noise
(1)
6
5
(1)
Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC coupled to the VDD33 and VDDIOsupplies
with amplitude = 100 mVp-p measured at the device VDD33 and VDDIO pins. Bit error rate testing of input to the Ser and output of the
Des with 10 meter cable shows no error when the noise frequency on the Ser is less than 50 MHz. The Des on the other hand shows no
error when the noise frequency is less than 50 MHz.
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7.4 Thermal Information
THERMAL METRIC (1)
WQFN
48 PINS
RθJA
Junction-to-ambient thermal resistance
35
RθJC(top)
Junction-to-case (top) thermal resistance
5.2
RθJB
Junction-to-board thermal resistance
5.5
ψJT
Junction-to-top characterization parameter
0.1
ψJB
Junction-to-board characterization parameter
5.5
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.3
(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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7.5 DC Electrical Characteristics
(1) (2) (3)
Over recommended operating supply and temperature ranges unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
PIN/FREQ.
MIN
PDB
TYP
MAX
UNIT
2.0
VDDIO
V
GND
0.8
V
+10
μA
2.0
VDDIO
V
0.65*
VDDIO
VDDIO
V
GND
0.8
V
GND
0.35*
VDDIO
V
LVCMOS I/O DC SPECIFICATIONS
VIH
High Level Input Voltage
VDDIO = 3.0 to 3.6 V
VIL
Low Level Input Voltage
VDDIO = 3.0 to 3.6 V
IIN
Input Current
VIN = 0 V or VDDIO = 3.0 to 3.6 V
VIH
High Level Input Voltage
−10
VDDIO = 3.0 to 3.6 V
VDDIO = 1.71 to 1.89 V
VDDIO = 3.0 to 3.6 V
VIL
Low Level Input Voltage
IIN
Input Current
VDDIO = 1.71 to 1.89 V
VIN = 0 V or VDDIO
High Level Output Voltage IOH = −4 mA
VOH
VOL
Low Level Output Voltage
IOL = +4 mA
VDDIO = 3.0
to 3.6 V
R[7:0], G[7:0],
B[7:0], HS, VS,
DE, PCLK,
I2S_CLK,
I2S_WC,
I2S_DA,
I2S_DB
±1
−10
±1
+10
μA
VDDIO = 1.71
to 1.89 V
−10
±1
+10
μA
VDDIO = 3.0
to 3.6 V
2.4
VDDIO
V
VDDIO = 1.71
to 1.89 V
VDDIO 0.45
VDDIO
V
GND
0.4
V
GND
0.35
V
VDDIO = 3.0
to 3.6 V
VDDIO = 1.71
to 1.89 V
IOS
Output Short Circuit
Current
VOUT = 0 V
IOZ
TRI-STATE® Output
Current
VOUT = 0 V or VDDIO, PDB = L,
GPIO[3:0],
GPO_REG[7:4],
REM_INTB
−50
−10
mA
+10
μA
1250
1340
mVp-p
1
50
mV
FPD-LINK III CML DRIVER DC SPECIFICATIONS
VODp-p
Differential Output Voltage
RL = 100 Ω, Figure 1
(DOUT+) – (DOUT-)
ΔVOD
Output Voltage Unbalance
VOS
Offset Voltage – Singleended
ΔVOS
Offset Voltage Unbalance
Single-ended
IOS
Output Short Circuit
Current
RT
Internal Termination
Resistor - Single ended
1160
2.50.25*VO
RL = 100 Ω, Figure 1
DOUT+, DOUT-
(1)
(2)
(3)
8
V
Dp-p
(TYP)
1
50
−38
DOUT+/- = 0 V, PDB = L or H
40
52
mV
mA
62
Ω
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Typical values represent most likely parametric norms at VDD = 3.3 V, Ta = +25ºC, and at the Recommended Operation Conditions at
the time of product characterization and are not ensured.
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD and ΔVOD, which are differential voltages.
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DC Electrical Characteristics (1) (2)
(3)
(continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
PIN/FREQ.
MIN
TYP
MAX
UNIT
148
170
mA
90
180
μA
1
1.6
mA
1.2
2.4
mA
65
150
μA
55
150
μA
SUPPLY CURRENT
IDD1
IDDIO1
VDD33= 3.6 V
Supply Current
(includes load current)
RL = 100 Ω, f = 85 MHz
Checker Board Pattern,
Figure 2
Supply Current Remote
Auto Power Down Mode
0x01[7] = 1, deserializer
is powered down
IDDS1
IDDIOS1
IDDS2
IDDIOS2
Supply Current Power
Down
VDD33
VDDIO = 3.6 V
VDDIO = 1.89
V
VDDIO
VDD33 = 3.6 V
VDD33
VDDIO = 3.6 V
VDDIO = 1.89
V
VDDIO
VDD33 = 3.6 V
PDB = L, All LVCMOS
VDDIO = 3.6 V
inputs are floating or tied
VDDIO = 1.89
to GND
V
VDD33
VDDIO
1
2
mA
65
150
μA
50
150
μA
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7.6 AC Electrical Characteristics (1)
(2) (3)
Over recommended operating supply and temperature ranges unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
PIN/FREQ.
MIN
TYP
MAX
UNIT
GPIO BIT RATE
Forward Channel Bit Rate
BR
Back Channel Bit Rate
See (4)
(5)
See (4)
(5)
f = 5 – 85
MHz
GPIO[3:0]
0.25* f
Mbps
75
kbps
RECOMMENDED TIMING FOR PCLK
tTCP
PCLK Period
tCIH
PCLK Input High Time
tCIL
PCLK Input Low Time
tCLKT
PCLK Input Transition Time
Figure 3 (4) (5)
tIJIT
PCLK Input Jitter Tolerance,
Bit Error Rate ≤10-10
(1)
(2)
(3)
(4)
(5)
(6)
10
f / 40 < Jitter Freq < f / 20 (4)
PCLK
(6)
11.76
T
200
ns
0.4*T
0.5*T
0.6*T
ns
0.4*T
0.5*T
0.6*T
ns
f = 5 MHz
4.0
ns
f = 85 MHz
0.5
ns
f = 5 – 78
MHz
0.4
0.6
UI
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Typical values represent most likely parametric norms at VDD = 3.3 V, Ta = +25ºC, and at the Recommended Operation Conditions at
the time of product characterization and are not ensured.
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD and ΔVOD, which are differential voltages.
Specification is ensured by characterization and is not tested in production.
Specification is ensured by design and is not tested in production.
Jitter Frequency is specified in conjunction with DS90UH926 PLL bandwidth.
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7.7 Recommended Timing for the Serial Control Bus
Over 3.3 V supply and temperature ranges unless otherwise specified.
SYMBOL
fSCL
tLOW
PARAMETER
SCL Clock Frequency
CONDITIONS
MIN
TYP
MAX
UNIT
Standard Mode
0
100
kHz
Fast Mode
0
400
kHz
Standard Mode
4.7
us
Fast Mode
1.3
us
Standard Mode
4.0
us
Fast Mode
0.6
us
Hold time for a start or a
repeated start condition
Figure 8
Standard Mode
4.0
us
Fast Mode
0.6
us
Set Up time for a start or a
repeated start condition
Figure 8
Standard Mode
4.7
us
Fast Mode
0.6
us
Data Hold Time
Figure 8
Standard Mode
0
3.45
us
Fast Mode
0
0.9
us
Data Set Up Time
Figure 8
Standard Mode
250
ns
Fast Mode
100
ns
Set Up Time for STOP Condition, Standard Mode
Figure 8
Fast Mode
4.0
us
0.6
us
Bus Free Time
Between STOP and START,
Figure 8
Standard Mode
4.7
us
tBUF
Fast Mode
1.3
us
tr
SCL & SDA Rise Time,
Figure 8
Standard Mode
1000
ns
Fast Mode
300
ns
SCL & SDA Fall Time,
Figure 8
Standard Mode
300
ns
Fast mode
300
ns
tHIGH
tHD;STA
tSU:STA
tHD;DAT
tSU;DAT
tSU;STO
tf
SCL Low Period
SCL High Period
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DS90UH925AQ-Q1
SNLS481 – JUNE 2014
www.ti.com
7.8 DC and AC Serial Control Bus Characteristics
Over 3.3 V supply and temperature ranges unless otherwise specified. (1)
SYMBOL
PARAMETER
(2) (3)
CONDITIONS
MIN
TYP
MAX
UNIT
VIH
Input High Level
SDA and SCL
0.7*
VDD33
VDD33
V
VIL
Input Low Level Voltage
SDA and SCL
GND
0.3*
VDD33
V
VHY
Input Hysteresis
>50
VOL
SDA, IOL = 1.25 mA
Iin
SDA or SCL, Vin = VDD33 or GND
tR
SDA RiseTime – READ
tF
SDA Fall Time – READ
tSU;DAT
Set Up Time – READ
tHD;DAT
Hold Up Time – READ
tSP
Input Filter
Cin
Input Capacitance
(1)
(2)
(3)
mV
0
0.36
V
-10
+10
µA
430
ns
20
ns
Figure 8
560
ns
Figure 8
615
ns
50
ns
SDA or SCL
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