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DS90UH925Q-Q1
SNLS336J – OCTOBER 2010 – REVISED NOVEMBER 2014
DS90UH925Q-Q1 720p 24-bit Color FPD-Link III Serializer with HDCP
1 Features
3 Description
•
The DS90UH925Q-Q1 serializer, in conjunction with
the DS90UH926Q-Q1 deserializer, provides a
solution for secure distribution of content-protected
digital video within automotive entertainment
systems. This chipset translates a parallel RGB Video
Interface into a single pair high-speed serialized
interface. The digital video data is protected using the
industry standard HDCP copy protection scheme.
The serial bus scheme, FPD-Link III, supports video
and audio data transmission and full duplex control
including I2C communication over a single differential
link. Consolidation of video data and control over a
single differential pair reduces the interconnect size
and weight, while also eliminating skew issues and
simplifying system design.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Integrated HDCP Cipher Engine with On-chip Key
Storage
Bidirectional Control Interface Channel Interface
with I2C Compatible Serial Control Bus
Supports High Definition (720p) Digital Video
Format
RGB888 + VS, HS, DE and I2S Audio Supported
5 to 85 MHz PCLK Supported
Single 3.3V Operation with 1.8 V or 3.3 V
Compatible LVCMOS I/O Interface
AC-coupled STP Interconnect up to 10 meters
Parallel LVCMOS Video Inputs
DC-balanced & Scrambled Data with Embedded
Clock
HDCP Content Protected
Supports HDCP Repeater Application
Internal Pattern Generation
Low Power Modes Minimize Power Dissipation
Automotive Grade Product: AEC-Q100 Grade 2
Qualified
> 8k V HBM and ISO 10605 ESD rating
Backward Compatible Modes
2 Applications
•
•
The DS90UH925Q-Q1 serializer embeds the clock,
content protects the data payload, and level shifts the
signals to high-speed low voltage differential
signaling. Up to 24 RGB data bits are serialized along
with three video control signals and up to two I2S
data inputs.
EMI is minimized by the use of low voltage differential
signaling, data scrambling and randomization and
spread spectrum clocking compatibility.
The HDCP cipher engine is implemented in the
serializer and deserializer. HDCP keys are stored in
on-chip memory.
Device Information (1)
Automotive Display for Navigation
Rear Seat Entertainment Systems
PART NUMBER
DS90UH925Q-Q1
(1)
PACKAGE
WQFN (48)
BODY SIZE
7.00 mm x 7.00 mm
For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
HOST
Graphics
Processor
RGB Digital Display Interface
VDD33
VDDIO
(1.8V or 3.3V) (3.3V)
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
SCL
SDA
IDx
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
FPD-Link III
1 Pair / AC Coupled
0.1 PF
0.1 PF
RIN+
DOUT+
RIN-
DOUT-
PDB
I2S AUDIO
(STEREO)
VDDIO
VDD33
(3.3V) (1.8V or 3.3V)
3
/
DS90UH925Q-Q1
Serializer
DAP
100 ohm STP Cable
PDB
OSS_SEL
OEN
MODE_SEL MODE_SEL
INTB
INTB_IN
SCL
SDA
IDx
DS90UH926Q-Q1
Deserializer
RGB Display
720p
24-bit color depth
LOCK
PASS
3
/
I2S AUDIO
(STEREO)
MCLK
DAP
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DS90UH925Q-Q1
SNLS336J – OCTOBER 2010 – REVISED NOVEMBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
7
1
1
1
2
3
6
Absolute Maximum Ratings ..................................... 6
Handling Ratings....................................................... 6
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 7
DC Electrical Characteristics ................................... 7
AC Electrical Characteristics..................................... 8
DC and AC Serial Control Bus Characteristics......... 9
Recommended Timing for Serial Control Bus .......... 9
Switching Characteristics ........................................ 12
Typical Charateristics ........................................... 13
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 14
7.3
7.4
7.5
7.6
8
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Register Maps .........................................................
14
21
25
27
Applications and Implementation ...................... 42
8.1 Application Information............................................ 42
8.2 Typical Application .................................................. 43
9
Power Supply Recommendations...................... 45
9.1 Power Up Requirements and PDB Pin ................... 45
9.2 CML Interconnect Guidelines.................................. 45
10 Layout................................................................... 46
10.1 Layout Guidelines ................................................. 46
10.2 Layout Example .................................................... 47
11 Device and Documentation Support ................. 49
11.1
11.2
11.3
11.4
Documentation Support ........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
49
49
49
49
12 Mechanical, Packaging, and Orderable
Information ........................................................... 49
4 Revision History
Changes from Revision I (April 2013) to Revision J
Page
•
Added, updated, or renamed the following sections: Device Information Table, Pin Configuration and Functions,
Application and Implementation; Power Supply Recommendations; Layout; Device and Documentation Support;
Mechanical, Packaging, and Ordering Information................................................................................................................. 1
•
Fixed typo for GPIO configuration ........................................................................................................................................ 17
•
Removed two MODE_SEL modes: I2S Channel B, and Backward Compatible.................................................................. 22
•
Removed IDx addresses 0x22, 0x24, 0x2C, 0x2E, 0x30, 0x32, 0x34 ................................................................................. 25
•
Changed suggested resistor values for IDx addresses 0x1E, 0x20, 0x26, 0x28, 0x2A....................................................... 25
Changes from Revision H (October 2010) to Revision I
•
2
Page
Changed layout from National Data Sheet style to TI format................................................................................................. 1
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SNLS336J – OCTOBER 2010 – REVISED NOVEMBER 2014
5 Pin Configuration and Functions
G1/GPIO3
G0/GPIO2
R7
R6
R5
INTB
VDDIO
R4
R3
R2
R1/GPIO1
R0/GPIO0
36
35
34
33
32
31
30
29
28
27
26
25
48-Pin
Package RHS
(Top View)
G2
37
24
MODE_SEL
G3
38
23
CMF
G4
39
22
VDD33
G5
40
21
PDB
G6
41
20
DOUT+
G7
42
DS90UH925Q-Q1
19
DOUT-
B0/GPO_REG4
43
TOP VIEW
18
RES1
B1/I2S_DB/GPO_REG5
44
17
CAPHS12
B2
45
16
NC
B3
46
15
RES0
B4
47
14
CAPP12
B5
48
13
I2S_CLK/GPO_REG8
11
12
I2S_DA/GPO_REG6
10
PCLK
I2S_WC/GPO_REG7
8
9
IDx
CAPL12
SCL
6
7
DE
SDA
5
HS
4
3
B7
VS
1
2
B6
DAP = GND
Pin Functions
PIN
NAME
NUMBER
I/O, TYPE
DESCRIPTION
LVCMOS PARALLEL INTERFACE
R[7:0]
34, 33, 32, 29,
28, 27, 26, 25
I, LVCMOS
w/ pull down
RED Parallel Interface Data Input Pins
Leave open if unused.
R0 can optionally be used as GPIO0 and R1 can optionally be used as GPIO1.
G[7:0]
42, 41, 40, 39,
38, 37, 36, 35
I, LVCMOS
w/ pull down
GREEN Parallel Interface Data Input Pins
Leave open if unused.
G0 can optionally be used as GPIO2 and G1 can optionally be used as GPIO3.
B[7:0]
2, 1, 48, 47,
46, 45, 44, 43
I, LVCOS
w/ pull down
BLUE Parallel Interface Data Input Pins
Leave open if unused
B0 can optionally be used as GPO_REG4 and B1 can optionally be used as GPO_REG5.
HS
3
I, LVCMOS
w/ pull down
Horizontal Sync Input Pin
Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the
Control Signal Filter is enabled. There is no restriction on the minimum transition pulse when
the Control Signal Filter is disabled. The signal is limited to 2 transitions per 130 PCLKs.
See Table 6.
VS
4
I, LVCMOS
w/ pull down
Vertical Sync Input Pin
Video control signal is limited to 1 transition per 130 PCLKs. Thus, the minimum pulse width
is 130 PCLKs.
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Pin Functions (continued)
PIN
NAME
NUMBER
I/O, TYPE
DESCRIPTION
Data Enable Input Pin
Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the
Control Signal Filter is enabled. There is no restriction on the minimum transition pulse when
the Control Signal Filter is disabled. The signal is limited to 2 transitions per 130 PCLKs.
See Table 6.
DE
5
I, LVCMOS
w/ pull down
PCLK
10
I, LVCMOS
w/ pull down
13, 12, 11
I, LVCMOS
w/ pull down
I2S_CLK,
I2S_WC,
I2S_DA
Pixel Clock Input Pin. Strobe edge set by RFB configuration register. See Table 6.
Digital Audio Interface Data Input Pins
Leave open if unused.
I2S_CLK can optionally be used as GPO_REG8, I2S_WC can optionally be used as
GPO_REG7, and I2S_DA can optionally be used as GPO_REG6.
OPTIONAL PARALLEL INTERFACE
I2S_DB
44
I, LVCMOS
w/ pull down
Second Channel Digital Audio Interface Data Input pin at 18–bit color mode and set by
MODE_SEL pin or configuration register
Leave open if unused.
I2S_DB can optionally be used as B1 or GPO_REG5.
GPIO[3:0]
36, 35, 26, 25
General Purpose IOs. Available only in 18-bit color mode, and set by MODE_SEL pin or
I/O, LVCMOS configuration register. See Table 6.
w/ pull down Leave open if unused
Shared with G1, G0, R1 and R0.
GPO_REG[
8:4]
13, 12, 11, 44,
43
O, LVCMOS
w/ pull down
General Purpose Outputs and set by configuration register. See Table 6.
Share with I2S_CLK, I2S_WC, I2S_DA, I2S_DB or B1, B0.
PDB
21
I, LVCMOS
w/ pull-down
Power-down Mode Input Pin
PDB = H, device is enabled (normal operation)
Refer to ”Power Up Requirements and PDB Pin” in the Applications Information Section.
PDB = L, device is powered down.
When the device is in the powered down state, the Driver Outputs are both HIGH, the PLL is
shutdown, and IDD is minimized. Control Registers are RESET.
MODE_SEL
24
I, Analog
Device Configuration Select. See Table 4.
IDx
6
I, Analog
I2C Serial Control Bus Device ID Address Select
External pull-up to VDD33 is required under all conditions, DO NOT FLOAT.
Connect to external pull-up and pull-down resistor to create a voltage divider. See Figure 19.
SCL
8
I/O, LVCMOS I2C Clock Input / Output Interface
Open Drain Must have an external pull-up to VDD33, DO NOT FLOAT.
Recommended pull-up: 4.7kΩ.
SDA
9
I/O, LVCMOS I2C Data Input / Output Interface
Open Drain Must have an external pull-up to VDD33, DO NOT FLOAT.
Recommended pull-up: 4.7kΩ.
CONTROL
I2C
4
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Pin Functions (continued)
PIN
NAME
NUMBER
I/O, TYPE
DESCRIPTION
STATUS
INTB
31
O, LVCMOS
Open Drain
HDCP Interrupt
INTB = H, normal
INTB = L, Interrupt request
Recommended pull-up: 4.7kΩ to VDDIO
FPD-Link III SERIAL INTERFACE
DOUT+
20
O, LVDS
True Output
The output must be AC-coupled with a 0.1µF capacitor.
DOUT-
19
O, LVDS
Inverting Output
The output must be AC-coupled with a 0.1µF capacitor.
CMF
23
Analog
Common Mode Filter.
Connect 0.1µF to GND
Power
Power to on-chip regulator 3.0 V - 3.6 V. Requires 4.7 uF to GND
POWER (1) and GROUND
VDD33
22
VDDIO
30
Power
LVCMOS I/O Power 1.8 V ±5% OR 3.0 V - 3.6 V. Requires 4.7 uF to GND
GND
DAP
Ground
DAP is the large metal contact at the bottom side, located at the center of the WQFN
package. Connect to the ground plane (GND) with at least 9 vias.
REGULATOR CAPACITOR
CAPHS12,
CAPP12
CAPL12
17, 14
CAP
Decoupling capacitor connection for on-chip regulator. Requires a 4.7uF to GND at each
CAP pin.
7
CAP
Decoupling capacitor connection for on-chip regulator. Requires two 4.7uF to GND at this
CAP pin.
16
NC
18, 15
GND
OTHERS
NC
RES[1:0]
(1)
Do not connect.
Reserved. Tie to Ground.
The VDD (VDD33 and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise.
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6 Specifications
6.1 Absolute Maximum Ratings
(1) (2)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
Supply Voltage – VDD33
-0.3
4.0
V
Supply Voltage – VDDIO
-0.3
4.0
V
LVCMOS I/O Voltage (3)
-0.3
VDDIO + 0.3
V
Serializer Output Voltage
-0.3
2.75
V
150
°C
Junction Temperature
(1)
(2)
(3)
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
The maximum limit (VDDIO +0.3V) does not apply to the PDB pin during the transition to the power down state (PDB transitioning from
HIGH to LOW).
6.2 Handling Ratings
Tstg
MIN
MAX
UNIT
-65
+150
°C
±8
±8
Charged device model (CDM), per AEC Q100-011
±1.25
±1.25
Machine Model (MM)
Storage temperature range
Human body model (HBM), per AEC Q100-002 (1)
V(ESD)
Electrostatic discharge
ESD Rating (IEC 61000-4-2,
powered-up only)
RD= 330Ω, CS = 150pF
ESD Rating (ISO 10605)
RD= 330Ω, CS = 150pF/330pF
RD= 2KΩ, CS = 150pF/330pF
(1)
±250
±250
Air Discharge
(DOUT+, DOUT-)
±15
±15
Contact Discharge
(DOUT+, DOUT-)
±8
±8
Air Discharge
(DOUT+, DOUT-)
±15
±15
Contact Discharge
(DOUT+, DOUT-)
±8
±8
kV
V
kV
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
Supply Voltage (VDD33)
3.0
3.3
3.6
UNIT
V
LVCMOS Supply Voltage (VDDIO)
3.0
3.3
3.6
V
LVCMOS Supply Voltage (VDDIO)
1.71
1.8
1.89
V
Operating Free Air Temperature (TA)
−40
25
105
°C
OR
PCLK Frequency
5
Supply Noise
6
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85
MHz
100
mVP-P
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6.4 Thermal Information
RHS
THERMAL METRIC (1)
RθJA
Junction-to-ambient thermal resistance
35
RθJC(top)
Junction-to-case (top) thermal resistance
5.2
RθJB
Junction-to-board thermal resistance
5.5
ψJT
Junction-to-top characterization parameter
0.1
ψJB
Junction-to-board characterization parameter
5.5
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.3
(1)
UNIT
48 PINS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 DC Electrical Characteristics (1)
(2) (3)
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
PIN/FREQ.
MIN
PDB
TYP
MAX
UNIT
2.0
VDDIO
V
GND
0.8
V
LVCMOS I/O DC SPECIFICATIONS
VIH
High Level Input Voltage
VDDIO = 3.0 to 3.6V
VIL
Low Level Input Voltage
VDDIO = 3.0 to 3.6V
IIN
Input Current
VIN = 0V or VDDIO = 3.0 to 3.6V
−10
VDDIO = 3.0 to 3.6V
VIH
High Level Input Voltage
VDDIO = 1.71 to 1.89V
VDDIO = 3.0 to 3.6V
VIL
IIN
VOH
VOL
Low Level Input Voltage
Input Current
High Level Output Voltage
Low Level Output Voltage
VDDIO = 1.71 to 1.89V
VIN = 0V or VDDIO
IOH = −4mA
IOL = +4mA
IOS
Output Short Circuit Current VOUT = 0V
IOZ
TRI-STATE® Output
Current
(1)
(2)
(3)
VDDIO = 3.0
to 3.6V
R[7:0], G[7:0],
B[7:0], HS, VS,
DE, PCLK,
I2S_CLK,
I2S_WC,
I2S_DA, I2S_DB
10
μA
2.0
VDDIO
V
0.65*
VDDIO
VDDIO
V
GND
0.8
V
GND
0.35*
VDDIO
V
±1
−10
±1
10
μA
VDDIO = 1.71
to 1.89V
−10
±1
10
μA
VDDIO = 3.0 to
3.6V
2.4
VDDIO
V
VDDIO = 1.71
to 1.89V
VDDIO 0.45
VDDIO
V
GND
0.4
V
GND
0.35
V
VDDIO = 3.0 to
3.6V
VDDIO = 1.71
to 1.89V
GPIO[3:0],
GPO_REG[8:4]
VOUT = 0V or VDDIO, PDB = L,
−50
−10
mA
10
μA
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Typical values represent most likely parametric norms at VDD = 3.3 V, TA = +25 °C, and at the Recommended Operating Conditions at
the time of product characterization and are not ensured.
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD and ΔVOD, which are differential voltages.
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DC Electrical Characteristics(1) (2)
(3)
www.ti.com
(continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
PIN/FREQ.
MIN
TYP
MAX
UNIT
1160
1250
1340 mVp-p
FPD-LINK III CML DRIVER DC SPECIFICATIONS
VODp-p
Differential Output Voltage
(DOUT+) – (DOUT-)
ΔVOD
Output Voltage Unbalance
VOS
Offset Voltage – Singleended
RL = 100Ω, Figure 1
1
50
2.50.25*VO
RL = 100Ω, Figure 1
Offset Voltage Unbalance
Single-ended
IOS
Output Short Circuit Current DOUT+/- = 0V, PDB = L or H
RT
Internal Termination
Resistor - Single ended
V
Dp-p
(TYP)
DOUT+, DOUT-
ΔVOS
mV
1
50
−38
40
mV
mA
52
62
Ω
148
170
mA
90
180
μA
1
1.6
mA
1.2
2.4
mA
65
150
μA
55
150
μA
SUPPLY CURRENT
IDD1
VDD33= 3.6V
IDDIO1
Supply Current
(includes load current)
RL = 100Ω, f = 85 MHz
Checker Board Pattern,
Figure 2
Supply Current Remote
Auto Power Down Mode
0x01[7] = 1, deserializer
is powered down
IDDS1
IDDIOS1
IDDS2
IDDIOS2
Supply Current Power
Down
PDB = L, All LVCMOS
inputs are floating or tied
to GND
VDD33
VDDIO = 3.6V
VDDIO =
1.89V
VDDIO
VDD33 = 3.6V
VDD33
VDDIO = 3.6V
VDDIO =
1.89V
VDDIO
VDD33 = 3.6V
VDD33
VDDIO = 3.6V
VDDIO =
1.89V
VDDIO
1
2
mA
65
150
μA
50
150
μA
6.6 AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (1)
PARAMETER
TEST CONDITIONS
PIN/FREQ.
(2) (3)
MIN
TYP
MAX
UNIT
GPIO BIT RATE
Forward Channel Bit Rate
BR
Back Channel Bit Rate
See (4)
(5)
See (4)
(5)
f = 5 – 85
MHz
GPIO[3:0]
0.25* f
Mbps
75
kbps
RECOMMENDED TIMING for PCLK
tTCP
PCLK Period
tCIH
PCLK Input High Time
tCIL
PCLK Input Low Time
tCLKT
PCLK Input Transition Time
Figure 3 (4) (5)
tIJIT
PCLK Input Jitter Tolerance,
Bit Error Rate ≤10–10
(1)
(2)
(3)
(4)
(5)
(6)
8
f / 40 < Jitter Freq < f / 20 (5)
PCLK
(6)
11.76
T
200
ns
0.4*T
0.5*T
0.6*T
ns
0.4*T
0.5*T
0.6*T
ns
f = 5 MHz
4.0
ns
f = 85 MHz
0.5
ns
f=5–
78MHz
0.4
0.6
UI
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Typical values represent most likely parametric norms at VDD = 3.3 V, TA = +25 °C, and at the Recommended Operating Conditions at
the time of product characterization and are not ensured.
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD and ΔVOD, which are differential voltages.
Specification is ensured by design and is not tested in production.
Specification is ensured by characterization and is not tested in production.
Jitter Frequency is specified in conjunction with DS90UH926 PLL bandwidth.
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6.7 DC and AC Serial Control Bus Characteristics
Over 3.3V supply and temperature ranges unless otherwise specified. (1)
PARAMETER
(2) (3)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIH
Input High Level
SDA and SCL
0.7*
VDD33
VDD33
V
VIL
Input Low Level Voltage
SDA and SCL
GND
0.3*
VDD33
V
VHY
Input Hysteresis
>50
VOL
SDA, IOL = 1.25 mA
Iin
SDA or SCL, VIN = VDD33 or GND
tR
SDA RiseTime – READ
tF
SDA Fall Time – READ
tSU;DAT
Set Up Time — READ
tHD;DAT
Hold Up Time — READ
tSP
Input Filter
Cin
Input Capacitance
(1)
(2)
(3)
mV
0
0.36
V
-10
10
µA
430
ns
20
ns
See Figure 8
560
ns
See Figure 8
615
ns
50
ns
SDA or SCL
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