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DS90UR910-Q1
SNLS414E – JUNE 2012 – REVISED OCTOBER 2016
DS90UR910-Q1 10 to 75 MHz 24-bit Color FPD-Link II to CSI-2 Converter
1 Features
2 Applications
•
•
1
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•
•
•
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•
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Automotive Grade Product: AEC-Q100 Grade 2
Qualified
10- to 75-MHz PCLK Support
(280-Mbps to 2.1-Gbps FPD-Link II Linerate)
Compatible to DC Balanced, AC-Coupled for
FPD-Link II Serial Bit Stream
Capable to Recover Data up to 10 Meters STP
Cable
MIPI D-PHY Modules Conform to v1.00.00
Compatible With MIPI CSI-2 Version 1.01
Supports Data Rate up to 900 Mbps per Data
Lane With Two Lanes
Video Stream Packet Formats: RGB888
Continuous and Non-Continuous Clocking Mode
Ultra Low Power, Escape, High Speed, and
Control Modes Support
Integrated Input Terminations and Adjustable
Receive Equalization
Fast Random Lock (No Reference Clock
Required)
CCI (Camera Control Interface) and I2C
Compatible Control Bus
@Speed BIST and Reporting Pin
Single 1.8-V Power Supply
1.8-V or 3.3-V Compatible LVCMOS I/O Interface
8-kV ISO 10605 ESD Rating
Leadless 40-Pin WQFN Package (6 mm × 6 mm)
Automotive Infotainment:
– Central Information Displays
– Rear Seat Entertainment Systems
– Digital Instrument Clusters
3 Description
The DS90UR910-Q1 is an interface bridge chip that
recovers data from the FPD-Link II serial bit stream
and converts into a Camera Serial Interface (CSI-2)
format compatible with Mobile Industry Processor
Interface (MIPI) specifications. It recovers the 24- or
18-bit RGB data and 3 video sync-signals from the
serial bit stream compatible to FPD-Link II serializers.
The recovered data is packetized and serialized over
two data lanes strobed by a half-rate serial clock
compliant with the MIPI DPHY and CSI-2
specifications, each running up to 900 Mbps. The
FPD-Link II receiver supports pixel clocks of up to
75 MHz. The CSI-2 output serial bus greatly reduces
the interconnect and signal count to a graphic
processing unit (GPU) and eases system designs for
video streams from multiple automotive driver assist
cameras.
The DS90UR910-Q1 is available in a 40-pin WQFN
package. Electrical performance is qualified for
automotive AEC-Q100 grade 2 temperature range
–40°C to 105°C.
Device Information (1)
PART NUMBER
DS90UR910-Q1
(1)
PACKAGE
WQFN (40)
BODY SIZE
6.00 mm x 6.00 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
Applications Diagram
VDD
1.8V
VDDIO
VDD
(1.8V or 3.3V) 1.8V
VDDIO
(1.8V or 3.3V)
CSI-2
R[7:0]
G[7:0]
0.1 µF
0.1 µF
0.1 µF
0.1 µF
DOUT+
DATA1±
RIN+
B[7:0]
Video
sources
DATA0±
HS
Graphic
Processor
DOUT-
VS
DE
PCLK
RIN-
FPD-Link II
1 pair 100Ÿ 673
DS90UR905Q-Q1
Serializer
CLK±
DS90UR910-Q1
Converter
Application
Processor
Display
SCL
SDA
PDB
LOCK
CONFIG[1:0]
BISTEN
CONFIG[1:0]
RFB
SCL
SDA
EQ[3:1]
PDB
ID[1:0]
VODSEL
DeEmph
ID[x]
DAP
Control
pins
BISTEN
PASS
DAP GND
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DS90UR910-Q1
SNLS414E – JUNE 2012 – REVISED OCTOBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
Electrical Characteristics: DC ................................... 6
Switching Characteristics: AC................................... 8
Timing Requirements: Serial Control Bus (CCI and
I2C) .......................................................................... 10
6.8 Timing Requirements: DC and AC Serial Control Bus
(CCI and I2C)........................................................... 10
6.9 Typical Characteristics ............................................ 13
7
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 15
7.3 Feature Description................................................. 15
7.4 Device Functional Modes........................................ 19
7.5 Programming........................................................... 20
8
Application and Implementation ........................ 25
8.1 Application Information............................................ 25
8.2 Typical Application .................................................. 25
9
Power Supply Recommendations...................... 27
9.1 Power Up Requirements and PDB Pin ................... 27
10 Layout................................................................... 27
10.1 Layout Guidelines ................................................. 27
10.2 Layout Example .................................................... 28
11 Device and Documentation Support ................. 30
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
30
30
30
30
30
30
12 Mechanical, Packaging, and Orderable
Information ........................................................... 30
4 Revision History
Changes from Revision D (July 2015) to Revision E
Page
•
Added Device Functional Modes and Application Information sections................................................................................. 1
•
Added Thermal Information table ........................................................................................................................................... 6
Changes from Revision C (May 2013) to Revision D
Page
•
Changed device status from Product Preview to Production Data ........................................................................................ 1
•
Added new section titles to update to new TI format. ............................................................................................................ 1
Changes from Revision B (October 2012) to Revision C
Page
•
Changed layout of National Semiconductor Data Sheet to TI format .................................................................................... 1
•
Changed Pin # for VDDL and VDDA Power pins for clarification .......................................................................................... 4
Changes from Revision A (September 2012) to Revision B
•
Changed Pin Diagram ............................................................................................................................................................ 3
Changes from Original (June 2012) to Revision A
•
2
Page
Page
DS90UR910-Q1 DATASHEET – Initial Release .................................................................................................................... 1
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SNLS414E – JUNE 2012 – REVISED OCTOBER 2016
5 Pin Configuration and Functions
PDB
BISTEN
RES
GND
VDDL
PASS
LOCK
VDDIO
GND
GPIO
30
29
28
27
26
25
24
23
22
21
RTA Package
40-Pin WQFN
Top View
VDDA
31
20
VDDCSI
GND
32
19
DATA1+
RIN+
33
18
DATA1–
RIN–
34
17
GND
CMF
35
16
DATA0+
GND
36
15
DATA0–
CMLOUT+
37
14
GND
CMLOUT–
38
13
CLK+
VDDA
39
12
CLK–
VDDP
40
11
CONFIG[0]
5
6
7
8
SDA
SCL
VDDL
ID[1]
10
4
GND
9
3
EQ[1]
ID[0]
2
EQ[2]
CONFIG[1]
1
EQ[3]
DAP
Not to scale
Pin Functions
PIN
NAME (2)
NO.
TYPE (1)
DESCRIPTION
FPD-LINK II SERIAL INTERFACE
RIN+
33
I
CML, inverting and noninverting differential inputs. The inputs must be AC-coupled with a 100-nF
capacitor.
RIN–
34
I
CML, inverting and noninverting differential inputs. The inputs must be AC-coupled with a 100-nF
capacitor.
CMF
35
I
Analog, common mode filter pin for the differential inputs. CMP is the virtual ground of the
differential input stage. A bypass capacitor is connected from CMP to ground to increase the
receiver’s common mode noise immunity. TI recommends a 4.7-µF ceramic capacitor.
CMLOUT+
37
O
CML, inverting and noninverting differential outputs. Single 100-Ω (1%) termination resistor must
be placed across the CMLOUT± pins. Optional loop-through output to monitor post equalizer and
requires use of the Serial Control Bus to enable.
CMLOUT–
38
O
CML, inverting and noninverting differential outputs. Single 100-Ω (1%) termination resistor must
be placed across the CMLOUT± pins. Optional loop-through output to monitor post equalizer and
requires use of the Serial Control Bus to enable.
DATA1+
19
O
DPHY, inverting and noninverting data output of DPHY Lane 1.
DATA1–
18
O
DPHY, inverting and noninverting data output of DPHY Lane 1.
DATA0+
16
O
DPHY, inverting and noninverting data output of DPHY Lane 0.
DATA0–
15
O
DPHY, inverting and noninverting data output of DPHY Lane 0.
CLK+
13
O
DPHY, inverting and noninverting half-rate DPHY clock lane.
CLK–
12
O
DPHY, inverting and noninverting half-rate DPHY clock lane.
MIPI INTERFACE
(1)
(2)
G = Ground, I = Input, O = Output, P = Power
1 = HIGH, 0 = LOW
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Pin Functions (continued)
PIN
NAME (2)
NO.
TYPE (1)
DESCRIPTION
CONTROL AND CONFIGURATION
30
I
LVCMOS with pulldown, power down mode input;
PDB = 1, Device is enabled (normal operation),
PDB = 0, Device is in power-down,
When the device is in the power-down, outputs are TRI-STATE, control registers are RESET.
CONFIG[1:0]
10, 11
I
LVCMOS with pulldown, operating mode select;
CONFIG[1:0] selects compatibility to FPD-Link II serializers. See Table 1.
EQ[3:1]
1, 2, 3
I
LVCMOS with pulldown, receive equalization control;
EQ[3:1] provides 8 combinations of the receive equalization gain settings. See Table 2. EQ[3:1]
optimizes the input equalizer’s ability to reduce inter-symbol interference from the loss
characteristics of different cable lengths.
BISTEN
29
I
LVCMOS with pulldown, BIST enable input;
BISTEN = 1, BIST is enabled,
BISTEN = 0, BIST is disabled.
LOCK
24
O
LVCMOS, LOCK status output;
LOCK = 1, PLL acquired lock to the reference clock input; DPHY outputs are active
LOCK = 0, PLL is unlocked
O
LVCMOS, normal mode status output pin (BISTEN = 0);
PASS = 1: No fault detected on input display timing,
PASS = 0: Indicates an error condition or corruption in display timing. Fault condition occurs if:
1) DE length value mismatch measured once in succession,
2) VSync length value mismatch measured twice in succession,
BIST mode status output pin (BISTEN = 1);
PASS = 1: No error detected,
PASS = 0: Error detected.
PDB
PASS
25
CCI AND I2C SERIAL CONTROL BUS
LVCMOS open drain, serial control bus clock input,
SCL requires an external pullup resistor to VDDIO.
SCL
6
I
SDA
5
I/O
8, 9
I
GPIO
21
I/O
RES
28
I
LVCMOS with pulldown, reserved pin (must tie low)
ID[1:0]
LVCMOS open drain, serial control bus data input and output,
SDA requires an external pullup resistor to VDDIO.
LVCMOS with pulldown, serial control bus device ID address select,
see Table 6.
RESERVED PINS
General purpose I/O;
Pin must be left floating during initial power-up.
POWER AND GROUND
VDDL
7, 26
P
Power to logic circuitry, 1.8 V ±5%
VDDA
31, 39
P
Power to analog circuitry, 1.8 V ±5%
VDDP
40
P
Power to PLL, 1.8 V ±5%
VDDCSI
20
P
Power to DPHY CSI-2 drivers, 1.8 V ±5%
VDDIO
23
P
Power to LVCMOS I/O circuitry, 1.8 V ±5% or 3.3 V ±10% (VDDIO)
GND
4, 14, 17,
22, 27, 32,
36
G
Ground return
GND
DAP
G
DAP is the metal contact at the bottom side, located at the center of the WQFN package. It must
be connected to the GND plane with multiple via to lower the ground impedance and improve the
thermal performance of the package. Connected to the ground plane (GND) with at least 9 vias.
4
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SNLS414E – JUNE 2012 – REVISED OCTOBER 2016
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
MAX
VDDA, VDDP, VDDL, VDDCSI (1.8 V)
−0.3
2.5
VDDIO (1.8-V I/O)
−0.3
2.5
VDDIO (3.3-V I/O)
–0.3
4
LVCMOS I/O voltage
−0.3
VDDIO + 0.3
V
Receiver input voltage
−0.3
VDDA + 0.3
V
CSI-2 output voltage
−0.3
VDDCSI + 0.3
V
1/RθJA
mW/°C
150
°C
150
°C
Supply voltage
40L WQFN package, maximum power dissipation capacity at 25°C (derate above 25°C)
Junction temperature, TJ
−65
Storage temperature, Tstg
(1)
(2)
UNIT
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
For soldering specifications, see product folder at www.ti.com and Absolute Maximum Ratings for Soldering (SNOA549).
6.2 ESD Ratings
VALUE
Human body model (HBM), per AEC Q100-002, all pins (1)
±8000
Charged device model (CDM), per AEC Q100-011, all pins
±1000
Machine model (MM)
V(ESD)
(1)
Electrostatic
discharge
UNIT
±250
IEC, powered-up only,
RD = 330 Ω, CS = 150 pF
Air discharge (RIN+, RIN–)
±30000
Contact discharge (RIN+, RIN–)
±10000
ISO10605,
RD = 330 Ω, CS = 150 pF
Air discharge (RIN+, RIN–)
±30000
Contact discharge (RIN+, RIN–)
±10000
ISO10605,
RD = 2 kΩ, CS = 150 pF or 330 pF
Air discharge (RIN+, RIN–)
±30000
Contact discharge (RIN+, RIN–)
±10000
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VDDA, VDDP,
VDDL, VDDCSI
Supply voltage
VDDIO
LVCMOS supply voltage
PCLK
Clock frequency
VDDn
Supply noise (1.8 V)
VDDIO
Supply noise
TA
Operating free-air temperature
MIN
NOM
MAX
UNIT
1.71
1.8
1.89
V
1.8-V I/O
1.71
1.8
1.89
3.3-V I/O
3
3.3
3.6
10
75
MHz
25
mVP-P
1.8-V I/O
25
3.3-V I/O
50
–40
25
V
mVP-P
105
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5
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6.4 Thermal Information
DS90UB921Q-1
THERMAL METRIC (1)
RTA (WQFN)
UNIT
48 PINS
RθJA
Junction-to-ambient thermal resistance
30.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
16.4
°C/W
RθJB
Junction-to-board thermal resistance
6.3
°C/W
ψJT
Junction-to-top characterization parameter
0.2
°C/W
ψJB
Junction-to-board characterization parameter
6.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.2
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics: DC
over operating free-air temperature range (unless otherwise noted) (1) (2) (3)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
3.3-V I/O LVCMOS, VDDIO = 3 to 3.6 V (BISTEN, LOCK, PASS, PDB, EQ[3:1], ID[1:0], CONFIG[1:0], GPIO)
VIH
High-level input voltage
VIN = 3 V to 3.6 V
2.2
VDDIO
VIL
Low-level input voltage
VIN = 3 V to 3.6 V
GND
0.8
V
IIN
Input current
VIN = 0 V or VDDIO
–15
15
µa
VOH
High-level output voltage
IOH = −2 mA
2.4
VDDIO
V
VOL
Low-level output voltage
IOL = 2 mA
GND
0.4
V
IOZ
TRI-STATE® output current
PDB = 0 V
–15
15
µa
V
1.8-V I/O LVCMOS, VDDIO = 1.71 to 1.89 V (BISTEN, LOCK, PASS, PDB, EQ[3:1], ID[1:0], CONFIG[1:0], GPIO)
VIH
High-level input voltage
VIN = 1.71 V to 1.89 V
0.65 × VDDIO
VDDIO
VIL
Low-level input voltage
VIN = 1.71 V to 1.89 V
GND
0.35 × VDDIO
V
IIN
Input current
VIN = 0 V or VDDIO
–15
15
µa
VOH
High-level output voltage
IOH = –2 mA
VDDIO – 0.45
VDDIO
V
VOL
Low-level output voltage
IOL = 2 mA
GND
0.45
V
IOZ
TRI-STATE output current
PDB = 0 V
–15
15
µa
SUPPLY CURRENT
IDD1
Supply current
IDDTX1
IDDIO1
(1)
(2)
(3)
6
Supply current
Supply current
Supply current drawn from
1.8-V rail (VDDL, VDDP, VDDA),
checker board pattern
Supply current drawn at
VDDCSI, checker board
pattern
Supply current drawn at
VDDIO, checker board pattern
VDDL, VDDP,
VDDA = 1.89 V,
f = 75 MHz
(900 Mbps)
88
VDDL, VDDP,
VDDA = 1.89 V,
f = 10 MHz
(120 Mbps)
38
VDDCSI = 1.89 V,
f = 75 MHz
(900 Mbps)
50
VDDCSI = 1.89 V,
f = 10 MHz
(120 Mbps)
22
95
mA
65
mA
VDDIO = 1.89 V,
f = 75 MHz
(900 Mbps)
10
VDDIO = 3.6 V,
f = 75 MHz
(900 Mbps)
15
mA
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
Typical values represent most likely parametric norms at VDD = 3.3 V, TA = 25°C, and at the recommended operation conditions at the
time of product characterization and are not ensured.
The Electrical Characteristics tables list ensured specifications in Recommended Operating Conditions except as otherwise modified or
specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured.
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Electrical Characteristics: DC (continued)
over operating free-air temperature range (unless otherwise noted)(1)(2)(3)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IDDZ
Supply current at power down
mode
Supply current drawn from 1.8-V rail (VDDL, VDDP,
VDDA), PDB = 0 V, VDDL, VDDP, VDDA = 1.89 V
(all other LVCMOS inputs low)
IDDTXZ
Supply current at power down
mode
Supply current drawn at VDDCSI, PDB = 0 V,
VDDCSI = 1.89 V (all other LVCMOS inputs low)
IDDIOZ
Supply current at power down
mode
Supply current drawn at
VDDIO, PDB = 0 V (all other
LVCMOS inputs low)
Ultra-low power state current
Supply current drawn from 1.8 V at (VDDL, VDDP,
VDDA, VDDCSI and VDDIO), VDD = 1.89 V,
VDDIO = 3.6 V, PLL off, no change in all input
signals,
Register:
0x19h = 0x03h
0x01h = 0x02h
20
mA
50
mV
IDDUPLS
5
mA
5
mA
VDDIO = 1.89 V
3
VDDIO = 3.6 V
3
mA
FPD-LINK II RECEIVER (RIN±)
VTH
Differential input threshold high
voltage
VCM = 1.2 V (internal VBIAS)
VTL
Differential input threshold low
voltage
VCM = 1.2 V (internal VBIAS)
VCM
Common mode voltage, internal
VBIAS
IIN
Input current
VIN = 0 V or VDD
RT
Internal termination resistor
Differential across RIN+ and RIN–
–50
mV
1.2
−15
80
100
V
15
µa
120
Ω
CMLOUT± DRIVER OUTPUT (CMLOUT±)
VOD
Differential output voltage (4)
RL = 100 Ω
500
VOS
Offset voltage, single-ended
RL = 100 Ω
1.3
RT
Internal termination resistor
Differential across CMLOUT+ and CMLOUT–
mV
V
80
100
120
Ω
150
200
250
mV
5
mV
270
mV
10
mV
360
mV
62.5
Ω
HSTX DRIVER (DATA0±, DATA1±, CLK±)
VCMTX
HS transmit static common-mode
voltage
|ΔVCMTX(1,0)|
VCMTX mismatch when output is
1 or 0 state
|VOD|
HS transmit differential voltage
|ΔVOD|
VOD mismatch when output is 1
or 0 state
VOHHS
HS output high voltage
ZOS
Single ended output impedance
ΔZOS
Mismatch in single ended output
impedance
140
40
200
50
10%
LPTX DRIVER (DATA0±, DATA1±, CLK±)
VOH
Output high level (5)
VOL
Output low level
−50
ZOLP
Output impedance
110
(4)
(5)
1.1
1.2
1.3
V
50
mV
Ω
Voltage difference compared to the DC average common mode potential.
Specification is ensured by characterization.
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6.6 Switching Characteristics: AC
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FPD-LINK II RECEIVER (RIN±)
tIJT
Input jitter tolerance,
see Figure 1
EQ = OFF,
PCLK = 65 MHz
tDDLT
Deserializer lock time
see Figure 2
PCLK = 75 MHz
jitter freq < 2 MHz
0.9
UI (1)
jitter freq > 6 MHz
0.5
UI
10
ms
HSTX DRIVER (DATA0±, DATA1±, CLK±)
HSTXDBR
Data bit rate
DATA0±, DATA1±, PCLK = 10 to 75
MHz (2)
fCLK
DDR Clock frequency
CLK±, PCLK = 10 to 75 MHz (2)
ΔVCMTX(HF)
Common mode voltage variations HF
Common-level variations above 450
MHz (2)
ΔVCMTX(LF)
Common mode voltage variations LF
Common-level variations between 50 to
450 MHz (2)
tRHS
Rise time HS
20% to 80% rise time (3)
tFHS
Fall time HS
TX common mode return loss (2)
SCCTX
PCLK ×
12
900
Mbps
60
PCLK × 6
450
MHz
15
mVRMS
25
mVPEAK
0.3
UIINST
0.3
UIINST
fLPMAX
–18
dB
fH
20% to 80% rise time
TX differential return loss (2)
SDDTX
120
150
(3)
ps
150
ps
–12
dB
fMAX
–6
dB
fLPMAX to fMAX
–6
dB
LPTX DRIVER (DATA0±, DATA1±, CLK±) (4)
tRLP
Rise time
LP 15% to 85% rise time
CLOAD = 70 pF lumped capacitance
25
ns
tFLP
Fall time
LP 15% to 85% fall time
CLOAD = 70 pF lumped capacitance
25
ns
35
ns
tREOT
Post-EoT rise and fall time
tLP-PULSE-TX
Pulse width of the LP exclusive-OR
clock
30% to 85% rise time and fall time
(2)
First LP exclusive-OR clock pulse after
Stop state or last pulse before Stop state
All other pulses (2)
tLP-PER-TX
σV/σtSR
CLOAD
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
8
Period of the LP exclusive-OR
clock (2)
Slew rate
Load capacitance
40
ns
20
ns
90
ns
(2)
CLOAD = 0 pF (5) (4) (6)
500
mV/ns
CLOAD = 5 pF (5) (4) (6)
300
mV/ns
CLOAD = 20 pF (5) (4) (6)
250
mV/ns
CLOAD = 70 pF (3) (4) (6)
150
mV/ns
CLOAD = 0 to 70 pF (falling edge
only) (3) (4) (6) (7)
30
mV/ns
CLOAD = 0 to 70 pF (rising edge
only) (3) (4) (6)
30
mV/ns
CLOAD = 0 to 70 pF (rising edge
only) (3) (4) (8) (9)
30 – 0.075 ×
(VO,INST – 700)
mV/ns
(4)
0
70
pF
UI is equivalent to one serialized data bit width (1UI = 1 / 28 × PCLK). The UI scales with PCLK frequency.
Specification is ensured by design and is not tested in production.
Specification is ensured by characterization.
CLOAD includes the low-frequency equivalent transmission line capacitance. The capacitance of TX and RX are assumed to always be
0
100
kHz
Fast mode
>0
400
kHz
Standard mode
4.7
µs
Fast mode
1.3
µs
Standard mode
Fast mode
4
µs
0.6
µs
4
µs
tHD;STA
Hold time for a start or a repeated start
condition
Standard mode
Fast mode
0.6
µs
tSU;STA
Set-up time for a start or a repeated start
condition
Standard mode
4.7
µs
Fast mode
0.6
µs
tHD;DAT
Data hold time
tSU;DAT
Data set-up time
tSU;STO
Set-up time for STOP condition
tr
SCL and SDA rise time
tf
SCL and SDA fall time
(1)
0
3.45
µs
Fast mode
0
0.9
µs
Standard mode
250
ns
Fast mode
100
ns
Standard mode
Bus Free Time
between STOP and START
tBµF
Standard mode
4
µs
Fast mode
0.6
µs
Standard mode
4.7
µs
Fast mode
1.3
µs
Standard mode
1000
ns
Fast mode
300
ns
Standard mode
300
ns
Fast mode
300
ns
Recommended Input Timing Requirements are input specifications and not tested in production.
6.8 Timing Requirements: DC and AC Serial Control Bus (CCI and I2C)
over operating free-air temperature range (unless otherwise noted; see Figure 7)
MAX
UNIT
VIH
Input high level voltage
SDA and SCL
0.65 × VDDIO
MIN
VDDIO
V
VIL
Input low level voltage
SDA and SCL
GND
0.35 × VDDIO
V
Fast mode, 3.3-V I/O
(1)
VHY
Input hysteresis
VOL
Output low level voltage
SDA, IOL = 1.5 mA
tR
SDA rise time – READ
Total capacitance of one bus line,
Cb ≤ 400 pF
tF
SDA fall time – READ
mV
0.1 × VDDIO
0
Standard mode
Fast mode
mV
0.4
V
300
ns
1000
ns
300
ns
Standard mode
250
ns
Fast mode
100
ns
Set-up time – READ
tHD;DAT
Hold-up time – READ
tSP
Input filter
Fast mode
Cin
Input capacitance
SDA and SCL
10
0.05 × VDDIO
Fast mode, 1.8 V I/O
tSU;DAT
(1)
NOM
0
ns
50
ns
5
pF
Specification is ensured by characterization.
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Ideal Data
Bit End
Sampling
Window
Ideal Data Bit
Beginning
RxIN_TOL
Left
VTH
0V
VTL
RxIN_TOL
Right
Ideal Center Position (tBIT/2)
tBIT (1 UI)
tIJT
= RxIN_TOL (Left + Right)
Sampling Window = 1 UI - tIJT
Figure 1. Receiver Input Jitter Tolerance
PDB
(3.3V I/O)
2.2V
0.8V
RIN
(Diff.)
tDDLT
LOCK
TRI-STATE
TRI-STATE
DATA0+/DATA1+/-
CLK+/-
OFF
IN LOCK TIME
ACTIVE
OFF
Figure 2. Deserializer PLL Lock Time
DATA1+
DATA1-
DATA0+
DATA00.5UI +
tskew
CLK+
CLK1 UI
Figure 3. Clock and Data Timing in HS Transmission
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Clock Lane
Data Lane
Dp/Dn
TLPX
THS-ZERO
THS-SYNC
Disconnect
Terminator
THS-PREPARE
VIH(min)
VIL(max)
TREOT
Capture
1 Data Bit
TD-TERM-EN
LP-11
LP-01
st
THS-SKIP
LP-00
THS-SETTLE
LP-11
TEOT
THS-TRAIL
THS-EXIT
Figure 4. High-Speed Data Transmission Burst
Disconnect
Terminator
Clock Lane
Dp/Dn
TCLK-POST
TCLK-SETTLE
TEOT
TCLK-TERM-EN
TCLK-MISS
VIH(min)
VIL(max)
TCLK-TRAIL
THS-EXIT
TLPX
TCLK-ZERO
TCLK-PRE
TCLK-PREPARE
Data Lane
Dp/Dn
THS-PREPARE
Disconnect
Terminator
TLPX
VIH(min)
VIL(max)
THS-SKIP
TD-TERM-EN
THS-SETTLE
Figure 5. Switching the Clock Lane Between Clock Transmission and Low-Power Mode
12
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VS
(internal Node)
Vertical Blanking
DE
(internal Node)
DATA1±
or
DATA0±
FS
1st
Line
2nd
Line
Line
Packet
Line
Packet
Last
Line
Line
Packet
Line
Packet
1 to 216 tLPX
FE
LPS
LPS
PH
EoT
LPS
SoT
LPS
PF
EoT
PH
SoT
LPS
Line
Pixel
Data
LPS
LPS
FS
LPS
Frame
Sync
Packet
Line
Packet
Figure 6. Long Line Packets and Short Frame Sync Packets
SDA
tLOW
tf
tHD;STA
tr
tf
tr
tBUF
tSP
SCL
tSU;STA
tHD;STA
tHIGH
tHD;DAT
START
tSU;STO
tSU;DAT
STOP
REPEATED
START
START
Figure 7. Serial Control Bus Timing Diagram
CSI-2 Output (500 mV/DIV)
CSI-2 Output (500 mV/DIV)
6.9 Typical Characteristics
Time (50 ns/DIV)
Time (50 ns/DIV)
Figure 8. CSI-2 D0± End of Transmission
Figure 9. CSI-2 D0± Start of Transmission
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7 Detailed Description
7.1 Overview
The DS90UR910-Q1 device recovers RBG data and sync signals from a FPD-Link II AC-coupled serial bit
stream, and converts the recovered data into packetized CSI-2 data format. The CSI-2 output serial interface
greatly reduces the interconnect and signal count to a graphic processing unit and eases system designs for
video streams from multiple automotive driver assist cameras.
The DS90UR910-Q1 is based on the DS90UR906Q de-serializer core. See the DS90UR906Q data sheet,
DS90UR90Q-Q1 5- to 65-MHz, 24-bit Color FPD-Link II Serializer and Deserializer (SNLS313), for the
functionality and performance of the FPD-Link II interface can be found in the DS90UR906Q data sheet.
The DS90UR910-Q1 conforms to the MIPI CSI-2 and DPHY standards for protocol and electrical specifications.
Compliant with standards:
• Conforms with MIPI Alliance Specification for D-PHY, version 1.00.00, dated May 14, 2009
• Compatible with MIPI Alliance Standard for Camera Serial Interface 2 (CSI-2) Version 1.01, dated Nov 9,
2010
The DS90UR910-Q1 receives 24-bit (or 18-bit) RGB data and 3 low speed control signals (VS, HS, DE) over a
serial FPD-Link II transmitted through a single twisted pair. It supports a pixel clock of 10 MHz to 75 MHz,
corresponding to the serial line rate of 280 Mb/s to 2100 Mb/s. The serial bit stream contains the scrambled 24bit data, an embedded clock, encoded control signals and DC balance information which enhances signal quality
and supports AC coupling.
The DS90UR910-Q1 is compatible with FPD-Link II serializers such as DS90UR905Q, DS90UR241Q,
DS90C241Q, DS90UR907Q, DS99R421Q, and DS90Ux92x FPD-Link III serializers in backward compatibility
mode. Figure 10 shows the serial bit stream. In each pixel clock cycle, a 28-bit frame is transmitted over the
FPD-Link. The frame contains C1 and C0 representing the embedded clock information. C1 is always high and
C0 is always low. Payload bits b[23:0] contain the scrambled 24-bit RGB data. DCB is the DC balance bit and is
used to minimize the DC offset on the signal line. DCA is used to validate the data integrity in the embedded
data stream and contain the encoded control signals VS, HS and DE (DS90UR905Q, DS90UR907Q, and
DS90Ux92x in backward compatible mode).
C
1
b
0
b
1
b
2
D
C
B
b
1
2
b
3
b
1
3
b
4
b
1
4
b
5
b
1
5
b
6
b
1
6
b
7
b
1
7
b
8
b
1
8
b
9
b
1
9
b
1
0
b
2
0
b
1
1
b
2
1
D
C
A
b
2
2
b
2
3
C
0
Figure 10. FPD-Link II Serial Stream
The DS90UR910-Q1 supports compatibility to FPD-Link II serializers and FPD-Link III serializers in backward
compatible mode as defined in Table 1.
Table 1. DS90UR910-Q1 Configuration Modes
CON
FIG1
CON
FIG0
0
0
Normal mode, Control signal filter disabled
DS90UR905Q 24-bit,
DS90UR907Q 24-bit,
DS90Ux92x Serializers 24-bit
RGB888
0
1
Normal mode, Control signal filter enabled
DS90UR905Q 24-bit,
DS90UR907Q 24-bit,
DS90Ux92x Serializers 24-bit
RGB888
1
0
Backwards compatible GEN2
DS90UR241Q 18-bit,
DS99R421Q 18-bit
RGB888
1
1
Backwards compatible GEN1
DS90C241Q 18-bit
RGB888
14
MODE
FPD-LINK II COMPATIBILITY
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CSI-2 DATA
FORMAT
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7.2 Functional Block Diagram
CMF
RIN+
RINEQ[3:1]
CSI-2 Protocol
Interface
DC Balance Decoder
50:
Serial to Parallel
50:
D-PHY
Lane
Module
DATA1+
DATA1-
DATA0+
D-PHY
Lane
Module
DATA0-
CLK+
D-PHY
Lane
Module
CLK-
Error
Detector
CONFIG[1:0]
PHY
Timing and Control
Timing
and
Control
Clock/Data
Recovery
BISTEN
SCA
ID[1:0]
LOCK
SCL
PASS
PDB
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7.3 Feature Description
7.3.1 Input Receive Equalization
The input equalizer of the DS90UR910-Q1 is designed to compensate the attenuation distortion results from
cable of different length or wire gauge. The equalizer gain setting is controlled by the control pins EQ[3:1] or
through register programming. Users can optimize the equalizer’s gain setting along with the de-emphasis level
of the DS90UR90xQ to achieve the optimum jitter performance.
Note this function cannot be seen at the RIN± input but can be observed at the serial test port (CMLOUT±)
enabled through the serial bus control registers. The equalization feature may be controlled by the external pin or
by register.
Table 2. Receiver Equalization Configuration
INPUTS EQ[3:1]
(1)
EQ BOOST
EQ3
EQ2
EQ1
0
0
1
Approximately 3 dB
0
1
0
Approximately 4.5 dB
0
1
1
Approximately 6 dB
1
0
0
Approximately 7.5 dB
1
0
1
Approximately 9 dB
1
1
0
Approximately 10.5 dB
1
1
1
Approximately 12 dB
0
0
0
See (1)
Default Setting is EQ = Off
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7.3.2 CSI-2 Interface
The DS90UR910-Q1 (in default mode) takes the RGB data bits R[7:0], G[7:0] and B[7:0] defined in the 24-bit
serializer pinout and directly maps to the RGB888 color space in the data frame. The DS90UR910-Q1 follows the
general frame format (see Figure 11). Upon the end of the vertical sync pulse (VS), the DS90UR910-Q1
generates the frame end and frame start synchronization packets within the vertical blanking period. The timing
of the frame start does not reflect the timing of the VS signal.
Upon the rising edge of the DE signal, each active line is output in a long data packet with the RGB888 data
format. At the end of each packet, the data lanes DATA0± and DATA1± return to the LP-11 state, while the clock
lane CLK± continue outputting the high-speed clock.
Frame Blanking
Line Blanking
Packet Header, PH
Packet Footer, PF
FS
Line Data
FE
(1 to N) tLPX
Frame Blanking
Line Blanking
Packet Header, PH
Packet Footer, PF
FS
Line Data
FE
Frame Blanking
Figure 11. General Frame Format
7.3.3 High-Speed Clock and Data
The high-speed clock and data outputs are source synchronous interface. The half rate clock at CLK± is derived
from the pixel clock sourced by the clock or data recovery circuit of the DS90UR910-Q1. The clock frequency is
6 times the pixel clock frequency. The 24-bit recovered RGB data is serialized and output at the 2 high-speed
data lanes DATA0± and DATA1± in according to the CSI-2 protocol. The data rate of each lane is 12 times the
pixel clock. As an example, at a pixel clock of 75 MHz, the CLK± runs at 450 MHz, and the data lanes run at
900 Mb/s.
The half-rate clock maintains a quadrature phase relationship to the data signals and allows receiver to sample
data at the rising and falling edges of the clock. Figure 3 shows the timing relationship of the clock and data
lines. The DS90UR910-Q1 supports continuous high-speed clock.
High-speed data are sent out at DATA0± and DATA1± in bursts. In between data bursts, the data lanes return to
low power states in according to protocol defined in D-PHY standard. The rising edge of the differential clock
(CLK+ – CLK–) is sent during the first payload bit of a transmission burst in the data lanes.
The DS90UR910-Q1 recovers the data bits R[7:0], G[7:0], B[7:0], VS, HS and DE from the serial FPD-Link II bit
stream at RIN±. During the vertical blanking period (VS goes low), it sends the short frame end packet, followed
by a short frame start packet. User can program the time between frame end to frame start packets from 0 to
(216–1) in units of 8 × pclk_period / 3.
16
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7.3.4 Data Frame RGB Mapping
Table 3 shows the pixel data R[7:0], G[7:0 and B[7:0] defined in DS90UR90xQ and DS90Ux92x serializers
pinout, which are recovered by the DS90UR910-Q1 and output in RGB888 format (data type 0x24) at the CSI-2
interface.
Table 3. CSI-2 RGB888 Data Format With FPD-Link II
Serializer (24-bit Mode)
FPD-LINK II (24-BIT)
PIN NAME
RGB888 DATA BITS
R[0]
R[0]
R[1]
R[1]
R[2]
R[2]
R[3]
R[3]
R[4]
R[4]
R[5]
R[5]
R[6]
R[6]
R[7]
R[7]
G[0]
G[0]
G[1]
G[1]
G[2]
G[2]
G[3]
G[3]
G[4]
G[4]
G[5]
G[5]
G[6]
G[6]
G[7]
G[7]
B[0]
B[0]
B[1]
B[1]
B[2]
B[2]
B[3]
B[3]
B[4]
B[4]
B[5]
B[5]
B[6]
B[6]
B[7]
B[7]
HS
—
VS
—
DE
—
DE
LANE1
DATA0±
LPS
SoT
ID
WC_byte1
B1
R1
G2
LANE2
DATA1±
LPS
SoT
WC_byte0
ECC
G1
B2
R2
...
Rn-1
Gn
CRC_byte0
EoT
LPS
Bn
Rn
CRC_byte1
EoT
LPS
...
Figure 12. DATA0± and DATA1± Packet Format in According to CSI-2 Protocol for RGB888
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Table 4. CSI-2 Data Format With FPD-Link II Serializers (18-Bit Mode)
FPD-LINK II (18-BIT)
PIN NAME
RGB DATA BITS
CSI-2 RGB888
DATA BITS
—
—
R[0]
—
—
R[1]
DIN[0]
R[0]
R[2]
DIN[1]
R[1]
R[3]
DIN[2]
R[2]
R[4]
DIN[3]
R[3]
R[5]
DIN[4]
R[4]
R[6]
DIN[5]
R[5]
R[7]
—
—
G[0]
—
—
G[1]
DIN[6]
G[0]
G[2]
DIN[7]
G[1]
G[3]
DIN[8]
G[2]
G[4]
DIN[9]
G[3]
G[5]
DIN[10]
G[4]
G[6]
DIN[11]
G[5]
G[7]
—
—
B[0]
—
—
B[1]
DIN[12]
B[0]
B[2]
DIN[13]
B[1]
B[3]
DIN[14]
B[2]
B[4]
DIN[15]
B[3]
B[5]
DIN[16]
B[4]
B[6]
DIN[17]
B[5]
B[7]
DIN[18]
HS
—
DIN[19]
VS
—
DIN[20]
DE
—
7.3.5 Display Timing Requirements
Table 5 shows the supported display resolutions for the DS90UR910-Q1. The display timings assume an
estimated overall blanking rate of 1.2. The DS90UR910-Q1 automatically detects the incoming data rate by from
the frame rate (by measuring VS). This timing is then mapped into a look up table. The lookup table is used for
any pixel rate of PCLK from 10 MHz to 65 MHz. The limitation that it assumes the frame rate is 60 fps and
30 fps. An override option is available to set each of the parameter individually for a data rate that is not listed in
the table. Option is programmed through CCI. Operation of frequencies above 65 MHz require additional I2C or
CCI programming of CSI_TIMING registers.
Table 5. DS90UR910-Q1 Supported Resolution and Refresh Rates WITH Expected Blanking Period
RESOLUTION
HACTIVE
(PIXELS)
HBLANK
(PIXELS)
HTOTAL
(PIXELS)
VACTIVE
(LINES)
VBLANK
(LINES)
VTOTAL
(LINES)
FRAME SIZE
(PIXELS)
REFRESH
(Hz)
PCLK (MHz)
400 × 240
400
40
440
240
5
245
107800
60
6.468
640 × 240
640
40
680
240
5
245
166600
60
9.996
24.444
18
800 × 480
800
40
840
480
5
485
407400
60
1280 × 480
1280
40
1320
480
5
485
640200
60
38.412
640 × 480
640
144
784
480
29
509
399056
60
23.94336
800 × 600
800
256
1056
600
28
628
663168
60
39.79008
960 × 160
960
40
1000
160
5
165
165000
60
9.9
640 × 160
640
40
680
160
5
165
112200
60
6.732
480 × 240
480
96
576
240
24
264
152064
60
9.12384
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Table 5. DS90UR910-Q1 Supported Resolution and Refresh Rates WITH Expected Blanking
Period (continued)
HACTIVE
(PIXELS)
HBLANK
(PIXELS)
800 × 480
800
1280 × 480
1280
RESOLUTION
HTOTAL
(PIXELS)
VACTIVE
(LINES)
VBLANK
(LINES)
VTOTAL
(LINES)
FRAME SIZE
(PIXELS)
REFRESH
(Hz)
160
960
480
48
528
506880
60
30.4128
256
1536
480
48
528
811008
60
48.66048
PCLK (MHz)
960 × 540
960
192
1152
540
54
594
684288
60
41.05728
1440 × 540
1440
288
1728
540
54
594
1026432
60
61.58592
1000 × 600
1000
200
1200
600
60
660
792000
60
47.52
640 × 480
640
160
800
480
45
525
420000
60
25.2
800 × 600
800
256
1056
600
28
628
663168
60
39.79008
1024 × 768
1024
320
1344
768
38
806
1083264
60
64.99584
1440 × 550
1440
144
1584
550
55
605
958320
60
57.4992
800 × 480
800
256
1056
480
45
525
554400
60
33.264
800 × 480
800
256
1056
480
45
525
554400
30
16.632
1024 × 480
1024
52
1076
480
24
504
542304
60
32.53824
1024 × 480
1024
52
1076
480
24
504
542304
30
16.26912
1024 × 480
1024
100
1124
480
48
528
593472
60
35.60832
1024 × 480
1024
100
1124
480
48
528
593472
30
17.80416
1440 × 550
1440
154
1594
550
55
605
964370
60
57.8622
1440 × 550
1440
154
1594
550
55
605
964370
30
28.9311
7.4 Device Functional Modes
7.4.1 Ultra-Low Power State
DS90UR910-Q1 D-PHY lanes enters ULPS mode upon software standby mode through Camera Control
Interface (CCI) generated by application processor. When ULPS is entered, all lanes including the clock and data
lanes are put in ULPS according to the MIPI D-PHY protocol. D-PHY can reduce power consumption by entering
ULPS mode.
Ultra-low power state entry command is sent after an escape mode entry command through CCI, and then lane
shall enter the Ultra-Low Power State (ULPS). When ULPS is entered, all lanes including the clock and data
lanes are put in ULPS according to the MIPI DPHY protocol. Typically an ULPS entry command is used but other
sequences can be used also. ULPS is exited by means of a mark-1 state with a length TWAKEUP followed by a
stop state.
Frame
End
Stop
(LP11)
Escape
Mode
Ultra-Low-Power-State Entry Command 00011110
ULPS
(LP00)
Mark-1
(LP10)
Stop
(LP11)
Clock Lane
Dp/Dn
Data Lane
Dp/Dn
tWAKEUP
tINIT
tLPX
Figure 13. Ultra-Low Power State
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Device Functional Modes (continued)
7.4.2 Non-Continuous or Continuous Clock
DS90UR910-Q1 D-PHY supports continuous clock mode and non-continuous clock mode. Default mode is noncontinuous clock mode, where the clock lane enters in LP mode between the transmissions of data packets.
Non-continuous clock mode is only non-continuous during the vertical blanking period for lower PCLK rates. For
higher PCLK rates, the clock is non-continuous between line and frame packets. Operating modes are
configurable through CCI.
Clock lane enters LP11 during horizontal blanking if the horizontal blanking period is longer than the overhead
time to start or stop the clock lane. There is auto-detection of the length of the horizontal blank period. The
threshold is 70 PCLK cycles. Register bit available to disable off the non-continuous clock mode.
7.5 Programming
7.5.1 Serial Control Bus (CCI or I2C)
The DS90UR910-Q1 can be configured by the use of the CCI or I2C as defined by MIPI, which is a bi-directional,
half-duplex, serial control bus consists of SCL and SDA. The SDA is the bi-directional data line. The SCL is the
serial clock line. Both SCL and SDA are driven by open drain drivers and required external pullup resistors to
VDDIO. The signals are either driven low or pulled high.
The DS90UR910-Q1 is a CCI slave. ID[1:0] pins select one of the four CCI slave addresses (see Table 6).
Table 6. CCI or I2C Slave Address
8-BIT SLAVE ADDRESS
(0 APPENDED WRITE)
ID[1]
ID[0]
7-BIT SLAVE ADDRESS
0
0
011 1100 (0x3C’h)
0111 1000 (0x78’h)
0
1
011 1101 (0x3D’h)
0111 1010 (0x7A’h)
1
0
011 0110 (0x36’h)
0110 1100 (0x6C’h)
1
1
011 0111 (0x37’h)
0110 1110 (0x6E’h)
The serial bus protocol is initiated by START or START-REPEATED, and terminated by STOP condition. A
START occurs when SDA transitions low while SCL is high. A STOP occurs when SDA transitions high when
SCL is high (see Figure 14).
SDA
SCL
S
P
START condition, or
START repeat condition
STOP condition
Figure 14. START and STOP Conditions
To communicate with a remote device, the host controller (master) sends the 7-bit slave address followed by a
write-bit (0), and listens for a response from the slave. This response is referred to as an acknowledge bit. If the
slave on the bus is addressed correctly, it acknowledges the master by driving the SDA low (ACK). If the address
does not match the slave address of the device, it negative acknowledges the master by letting SDA be pulled
high (NACK). In a write operation from master to slave, the master sends the 8-bit index address of the register
that it wants to access. After the slave ACKs, the master sends the 8-bit data byte. The slave ACKs after each
data byte is successfully received and is ready to receive another byte into the next sequential index location. At
the end of the data transfer, the master ends the transaction with a STOP condition.
20
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In a read operation, the master first sends the 8-bit index address of the register that it wants to access. After
receiving an ACK from the slave, it initiates a START-REPEAT condition, sends the 7-bit slave address followed
by the read-bit (1). The slave ACKs and sends out the 8-bit data byte. The master acknowledges an ACK when
another data byte is sent to the next sequential index address. The master acknowledges an NACK when no
more data byte is sent, and ends the transaction with a STOP condition.
The CCI interface of the DS90UR910-Q1 supports standard mode (
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