DS92LX1621, DS92LX1622
www.ti.com
SNLS327I – MAY 2010 – REVISED JANUARY 2014
DS92LX1621/DS92LX1622 10 - 50 MHz DC-Balanced Channel Link III Serializer and
Deserializer with Bi-Directional Control Channel
Check for Samples: DS92LX1621, DS92LX1622
FEATURES
1
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Configurable Data Throughput
– 12–bit (min) up to 600 Mbits/sec
– 16–bit (def) up to 800 Mbits/sec
– 18–bit (max) up to 900 Mbits/sec
10 MHz to 50 MHz Input Clock Support
Embedded Clock with DC Balanced Coding to
Support AC-Coupled Interconnects
Capable to Drive up to 10 Meters Shielded
Twisted-Pair
Bi-Directional Control Interface Channel with
I2C Support
I2C Interface for Device Configuration. Singlepin ID Addressing
16–bit Data Payload with CRC (Cyclic
Redundancy Check) for Checking Data
Integrity with Programmable Data
Transmission Error Detection and Interrupt
Control
Up to 6 Programmable GPIO's
AT-SPEED BIST Diagnosis Feature to Validate
Link Integrity
Individual Power-Down Controls for Both SER
and DES
User-Selectable Clock Edge for Parallel Data
on Both SER and DES
Integrated Termination Resistors
1.8V- or 3.3V-Compatible Parallel Bus Interface
Single Power Supply at 1.8V
IEC 61000–4–2 ESD Compliant
No Reference Clock Required on Deserializer
Programmable Receive Equalization
LOCK Output Reporting Pin to Ensure Link
Status
EMI/EMC Mitigation
– DES Programmable Spread Spectrum
(SSCG) Outputs
– DES Receiver Staggered Outputs
Temperature Range −40°C to +85°C
•
•
SER Package: 32 Pin WQFN (5mm x 5mm)
DES Package: 40 Pin WQFN (6mm x 6mm)
APPLICATIONS
•
•
Industrial Displays, Touch Screens
Medical Imaging
DESCRIPTION
The DS92LX1621 / DS92LX1622 chipset offers a
Channel Link III interface with a high-speed forward
channel and a full-duplex back channel for data
transmission over a single differential pair. The
Serializer/Deserializer pair is targeted for direct
connections between automotive camera systems
and Host Controller/Electronic Control Unit (ECU).
The primary transport sends 16 bits of image data
over a single high-speed serial stream together with a
low latency bi-directional control channel transport
that supports I2C. Included with the 16-bit payload is
a selectable data integrity option for CRC (Cyclic
Redundancy Check) or parity bit to monitor
transmission link errors. Using TI’s embedded clock
technology
allows
transparent
full-duplex
communication over a single differential pair, carrying
asymmetrical bi-directional control information without
the dependency of video blanking intervals. This
single serial stream simplifies transferring a wide data
bus over PCB traces and cable by eliminating the
skew problems between parallel data and clock
paths. This significantly saves system cost by
narrowing data paths that in turn reduce PCB layers,
cable width, and connector size and pins.
In addition, the Deserializer inputs provide
equalization control to compensate for loss from the
media over longer distances. Internal DC balanced
encoding/decoding is used to support AC-Coupled
interconnects.
The sleep function provides a power-savings mode
and a remote wake up interrupt for signaling of a
remote device.
The Serializer is offered in a 32-pin WQFN package,
and Deserializer is offered in a 40-pin WQFN
package.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2014, Texas Instruments Incorporated
DS92LX1621, DS92LX1622
SNLS327I – MAY 2010 – REVISED JANUARY 2014
www.ti.com
Typical Application Diagram
Parallel
Data In
16
Image
Sensor
Parallel
Data Out
16
Channel Link III
2
2
DS92LX1622
DS92LX1621
Bidirectional
Back Ch.
Cntl Bus
Serializer
Microcontroller/
ECU
Bidirectional
Back Ch.
Cntl Bus
Bi-direction
Back Channel
Deserializer
Figure 1. Typical Application Circuit
RIN+ RT
RT
GPIO [1:0]
DOUT-
DS92LX1621 - SERIALIZER
LOCK
PASS
I C Controller
Encoder Decoder
CAD
Clock
Gen
Timing
and
Control
PDB
M/S
BISTEN
Decoder Encoder
SCL
FIFO
I2C Controller
SDA
ROUT[13:0] HS, VS
GPIO [1:0]
PCLK
CDR
Timing
and
Control
PDB
M/S
2
RIN-
Clock
Gen
FIFO
PLL
16
SDA
SCL
2
PCLK
Output Latch
DOUT+
Decoder
RT
RT
Deserializer
2
Serializer
16
Encoder
DIN[13:0] HS, VS
Input Latch
Block Diagrams
CAD
DS92LX1622 - DESERIALIZER
Figure 2. Block Diagram
DS92LX1621
Serializer
Channel Link III
High Speed
Camera Data
DOUT+
14
Image
Sensor
YUV/RGB
HSYNC
PCLK
14
YUV/RGB
DIN[13:0]
HS, VS
VSYNC
2
Camera Data
RIN+
DOUTPixel Clock
DS92LX1622
Deserializer
RIN-
ROUT[13:0]
HS, VS
VSYNC
Bi-Directional
Back Channel
PCLK
GPIO[1:0]
GPIO[1:0]
GPI/O
SDA
Camera Unit
SCL
HSYNC
Pixel Clock
2
GPI/O
SDA
SDA
SCL
SCL
ECU Module
Microcontroller
SDA
SCL
Figure 3. Application Block Diagram
2
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Copyright © 2010–2014, Texas Instruments Incorporated
Product Folder Links: DS92LX1621 DS92LX1622
DS92LX1621, DS92LX1622
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SNLS327I – MAY 2010 – REVISED JANUARY 2014
DS92LX1621 Pin Diagram
DIN[0]/GPIO[2]
16
DIN[1]/GPIO[3]
15
DIN[2]/GPIO[4]
GPIO[0]
14
DIN[3]/GPIO[5]
GPIO[1]
VDDCML
VDDD
13
DIN[4]
17
DOUT+
DIN[10]
12
DIN[5]
18
DOUT-
DIN[11]
11
DIN[6]
19
VDDT
DIN[12]
10
DIN[7]
20
VDDPLL
9
25
26
21
28
22
29
DIN[9]
23
30
DIN[8]
24
31
VDDIO
27
Top View
PDB
1
2
3
4
5
6
7
8
HSYNC
VSYNC
PCLK
SCL
SDA
CAD
RES
M/S
32
DIN[13]
DS92LX1621
Serializer
32-Pin WQFN
Figure 4. Serializer - DS92LX1621
32-Pin WQFN (RTV Package)
DS92LX1621 Serializer PIN DESCRIPTIONS
Pin Name
Pin No.
I/O, Type
Description
LVCMOS PARALLEL INTERFACE
32, 31, 30, 29,
27, 26, 24, 23,
22, 21, 20, 19,
18, 17
Inputs, LVCMOS w/
pull down
Parallel data inputs.
HSYNC
1
Inputs, LVCMOS w/
pull down
Parallel data input 14, typically used as Horizontal SYNC Input
VSYNC
2
Inputs, LVCMOS w/
pull down
Parallel data input 15, typically used as Vertical SYNC Input
PCLK
3
Input, LVCMOS w/
pull down
Pixel Clock Input Pin. Strobe edge set by TRFB control register.
DIN[13:0]
GENERAL PURPOSE INPUT OUTPUT (GPIO)
DIN[3:0]/
GPIO[5:2]
20, 19, 18, 17
Input/Output, Digital
DIN[3:0] general-purpose pins can be individually configured as either inputs
or outputs; used to control and respond to various commands.
GPIO[1:0]
16, 15
Input/Output, Digital
General-purpose pins can be individually configured as either inputs or
outputs; used to control and respond to various commands.
Copyright © 2010–2014, Texas Instruments Incorporated
Product Folder Links: DS92LX1621 DS92LX1622
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DS92LX1621, DS92LX1622
SNLS327I – MAY 2010 – REVISED JANUARY 2014
www.ti.com
DS92LX1621 Serializer PIN DESCRIPTIONS (continued)
Pin Name
Pin No.
I/O, Type
Description
SERIAL CONTROL BUS - I2C COMPATIBLE
SCL
4
Input/Output, Digital
Clock line for the serial control bus communication
SCL requires an external pull-up resistor to VDDIO.
SDA
5
Input/Output, Open
Drain
Data line for the serial control bus communication
SDA requires an external pull-up resistor to VDDIO.
M/S
8
Input, LVCMOS w/
pull down
I2C Mode Select
M/S = L, Master (default); device generates and drives the SCL clock line
M/S = H, Slave; device accepts SCL clock input
CAD
6
Input, analog
Continuous Address Decoder
Input pin to select the Slave Device Address.
Input is connect to external resistor divider to programmable Device ID
address (See Figure 29).
CONTROL AND CONFIGURATION
PDB
9
Input, LVCMOS w/
pull down
Power down Mode Input Pin.
PDB = H, Transmitter is enabled and is ON.
PDB = L, Transmitter is in Sleep (Power Down). When the transmitter is in the
SLEEP state, the PLL is shutdown, and IDD is minimized.
RES
7
Input, LVCMOS w/
pull down
Reserved. This pin MUST be tied LOW.
Channel Link III INTERFACE
DOUT+
13
Input/Output, CML
Non-inverting differential output, back-channel input.
DOUT-
12
Input/Output, CML
Inverting differential output, back-channel input.
VDDPLL
10
Power, Analog
PLL Power, 1.8V ±5%
VDDT
11
Power, Analog
Tx Analog Power, 1.8V ±5%
VDDCML
14
Power, Analog
LVDS & BC Dr Power, 1.8V ±5%
VDDD
28
Power, Digital
Digital Power, 1.8V ±5%
VDDIO
25
Power, Digital
Power for input stage, The single-ended inputs are powered from VDDIO.
DAP
Ground, DAP
DAP must be grounded. Connect to ground plane with at least 9 vias.
Power and Ground
VSS
4
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Product Folder Links: DS92LX1621 DS92LX1622
DS92LX1621, DS92LX1622
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SNLS327I – MAY 2010 – REVISED JANUARY 2014
DS92LX1622 PIN DIAGRAM
PDB
LOCK
GPIO[0]
GPIO[1]
VDDOR1
ROUT[0]/GPIO[2]
ROUT[1]/GPIO[3]
ROUT[2]/GPIO[4]
ROUT[3]/GPIO[5]
22
21
ROUT[4]
ROUT[5]
18
ROUT[6]
17
ROUT[7]
16
VDDOR2
15
ROUT[8]
14
ROUT[9]
13
VDDD
12
ROUT[10]
11
ROUT[11]
VDDCML
DS92LX1622
Deserializer
40-Pin WQFN
35
RES
34
31
23
32
24
33
25
37
26
38
27
39
28
40
29
19
RES
30
20
PASS
VDDR
Top View
1
2
3
4
5
6
7
8
9
10
VSYNC
HSYNC
VDDOR3
ROUT[13]
ROUT[12]
M/S
PCLK
RES
VDDSSCG
VDDPLL
SCL
BISTEN
SDA
RIN-
CAD
36
RIN+
Figure 5. Deserializer - DS92LX1622
40-Pin WQFN (RTA Package)
DS92LX1622 Deserializer PIN DESCRIPTIONS
Pin Name
Pin No.
I/O, Type
Description
LVCMOS PARALLEL INTERFACE
9, 10, 11, 12,
14, 15, 17, 18,
19, 20, 21, 22,
23, 24
Outputs, LVCMOS
Parallel data outputs.
HSYNC
7
Output, LVCMOS
Parallel data output 14, typically used as Horizontal SYNC output
VSYNC
6
Output, LVCMOS
Parallel data output 14, typically used as Vertical SYNC output
PCLK
5
Output, LVCMOS
Pixel Clock Output Pin.
Strobe edge set by RRFB control register
ROUT[13:0]
General Purpose Input Output (GPIO)
ROUT[3:0] /
GPIO[5:2]
GPIO[1:0]
21, 22, 23, 24
Input/Output, Digital
ROUT[3:0] general-purpose pins can be individually configured as either inputs
or outputs; used to control and respond to various commands.
26, 27
Input/Output, Digital
General-purpose pins can be individually configured as either inputs or outputs;
used to control and respond to various commands.
SERIAL CONTROL BUS - I2C COMPATIBLE
SCL
3
Input/Output, Digital
Clock line for the serial control bus communication
SCL requires an external pull-up resistor to VDDIO.
Copyright © 2010–2014, Texas Instruments Incorporated
Product Folder Links: DS92LX1621 DS92LX1622
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DS92LX1621, DS92LX1622
SNLS327I – MAY 2010 – REVISED JANUARY 2014
www.ti.com
DS92LX1622 Deserializer PIN DESCRIPTIONS (continued)
Pin Name
Pin No.
I/O, Type
2
Input/Output, Open
Drain
40
Input, LVCMOS w/
pull up
SDA
Description
Data line for serial control bus communication
SDA requires an external pull-up resistor to VDDIO.
I2C Mode Select
M/S
M/S = L, Master; device generates and drives the SCL clock line
M/S = H, Slave (default); device accepts SCL clock input
Continuous Address Decoder
CAD
1
Input, analog
Input pin to select the Slave Device Address.
Input is connect to external resistor divider to programmable Device ID address
(See Figure 29)
CONTROL AND CONFIGURATION
Power down Mode Input Pin.
PDB
29
Input, LVCMOS w/
pull down
PDB = H, Receiver is enabled and is ON.
PDB = L, Receiver is in Sleep (Power down mode). When the Receiver is in the
SLEEP state, the LVCMOS Outputs are in TRI-STATE, the PLL is shutdown
and IDD is minimized.
LOCK Status Output Pin.
LOCK
28
Output, LVCMOS
LOCK = H, PLL is Locked, outputs are active
LOCK = L, PLL is unlocked, ROUT and PCLK output states are controlled by
OSS_SEL. May be used as Link Status.
PASS
31
Output, LVCMOS
32, 33, 39
-
When BISTEN = L; Normal operation
PASS is high to indicate no errors are detected. The PASS pin asserts low to
indicate a CRC error was detected on the link.
Reserved.
RES
Pin 39: This pin MUST be tied LOW.
Pins 32, 33: Leave pin open.
BIST MODE
BIST Enable Pin.
BISTEN
37
Input, LVCMOS w/
pull down
BISTEN = H, BIST Mode is enabled.
BISTEN = L, BIST Mode is disabled.
PASS Output Pin for BIST mode.
PASS
31
Output, LVCMOS
PASS = H, ERROR FREE Transmission
PASS = L, one or more errors were detected in the received payload.
Leave Open if unused. Route to test point (pad) recommended.
Channel Link III INTERFACE
RIN+
35
Input/Output, CML
Noninverting differential input, back channel output.
RIN-
36
Input/Output, CML
Inverting differential input, back channel output.
POWER AND GROUND
4
Digital Power
SSCG Power, 1.8V ±5%
Power supply must be connect regardless if SSCG function is in operation
25, 16, 8
Digital Power
TTL Output Buffer Power, The single-ended outputs and control input are
powered from VDDIO. VDDIO can be connected to a 1.8V ±5% or 3.3V ±10%
VDDD
13
Digital Power
Digital Core Power, 1.8V ±5%
VDDR
30
Analog Power
Rx Analog Power, 1.8V ±5%
VDDCML
34
Analog Power
Bi-Directional Control Channel Driver Power, 1.8V ±5%
VDDPLL
38
Analog Power
PLL Power, 1.8V ±5%
DAP
Ground
VDDSSCG
VDDOR1/2/3
VSS
DAP must be grounded. Connect to the ground plane with at least 16 vias.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
6
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Product Folder Links: DS92LX1621 DS92LX1622
DS92LX1621, DS92LX1622
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SNLS327I – MAY 2010 – REVISED JANUARY 2014
Absolute Maximum Ratings (1) (2)
−0.3V to +2.5V
Supply Voltage ( VDD1V8)
−0.3V to +4.0V
Supply Voltage (VDD3V3)
LVCMOS Input Voltage (VDD1V8)
−0.3V to +(VDD1V8 + 0.3V)
LVCMOS Input Voltage (VDD3V3)
−0.3V to +(VDD3V3 + 0.3V)
−0.3V to +(VDD + 0.3V)
LVCMOS Output Voltage (VDD)
CML Driver I/O Voltage (VDD1V8)
−0.3V to (VDD1V8 + 0.3V)
CML Receiver I/O Voltage (VDD1V8)
−0.3V to (VDD1V8 + 0.3V)
Junction Temperature
+150°C
Storage Temperature
−65°C to +150°C
Maximum Package Power Dissipation Capacity
1/θJA °C/W above +25°
Package Derating:
DS92LX1621 32L WQFN
θJA(based on 9 thermal vias)
34.3 °C/W
θJC(based on 9 thermal vias)
6.9 °C/W
Maximum Package Power Dissipation Capacity Package
1/θJA °C/W above +25°
Package Derating:
DS92LX1622 40L WQFN
θJA(based on 16 thermal vias)
28.0 °C/W
θJC(based on 16 thermal vias)
4.4 °C/W
ESD Rating (IEC 61000–4–2)
RD = 330Ω, CS = 150pF
Air Discharge
(DOUT+, DOUT-, RIN+, RIN-)
≥±25 kV
Contact Discharge
(DOUT+, DOUT-, RIN+, RIN-)
≥±10 kV
≥±8 kV
ESD Rating (HBM)
(1)
(2)
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional; the device should not be operated beyond such conditions.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
Recommended Operating Conditions
Min
Nom
Max
Units
VDD (1.8V)
1.71
1.8
1.89
V
VDDIO (1.8V Mode)
1.71
1.8
1.89
V
VDDIO (3.3V Mode)
3
3.3
3.6
V
VDDn(1.8V)
25
mVp-p
VDDIO(1.8V)
25
mVp-p
VDD3V3
50
mVp-p
+85
°C
50
MHz
Supply Noise
Operating Free Air
Temperature (TA)
-40
Input Clock Rate
+25
10
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DS92LX1621, DS92LX1622
SNLS327I – MAY 2010 – REVISED JANUARY 2014
www.ti.com
Serializer Electrical Characteristics (1) (2) (3)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
s
LVCMOS DC SPECIFICATIONS 3.3V I/O (SER INPUTS, DES OUTPUTS, GPIO, CONTROL INPUTS AND OUTPUTS)
VIH
High Level Input Voltage
VIN = 3.0V to 3.6V
2.0
VIN
V
VIL
Low Level Input Voltage
VIN = 3.0V to 3.6V
GND
0.8
V
IIN
Input Current
VIN = 0V or 3.6V
VIN = 3.0V to 3.6V
-20
+20
µA
VOH
High Level Output Voltage VDDIO = 3.0V to 3.6V
2.4
VDDIO
V
VOL
Low Level Output Voltage
GND
0.4
V
IOS
Output Short Circuit
Current
VOUT = 0V
TRI-STATE Output
Current
PDB = 0V,
VOUT = 0V or VDD
IOZ
VDDIO = 3.0V to 3.6V
IOH = +4mA
±1
Serializer GPIO
Outputs
-24
Deserializer
LVCMOS Outputs
-39
mA
LVCMOS Outputs
-20
±1
+20
µA
LVCMOS DC SPECIFICATIONS 1.8V I/O (TX INPUTS, RX OUTPUTS, GPIO, CONTROL INPUTS AND OUTPUTS)
VIH
High Level Input Voltage
VIN = 1.71V to 1.89V
0.65 VIN
VIN +0.3
VIL
Low Level Input Voltage
VIN = 1.71V to 1.89V
GND
0.35 VIN
IIN
Input Current
VIN = 0V or 1.89V
VIN = 1.71V to 1.89V
-20
VOH
High Level Output Voltage
VDDIO = 1.71V to 1.89V
IOH = −4mA
VOL
Low Level Output Voltage
VDDIO = 1.71V to 1.89V
IOL = +4 mA
IOS
Output Short Circuit
Current
VOUT = 0V
TRI-STATE Output
Current
PDB = 0V,
VOUT = 0V or VDD
IOZ
(4)
±1
V
+20
µA
VDDIO - 0.45
VDDIO
V
GND
0.45
V
Serializer GPIO
Outputs
-11
Deserializer
LVCMOS Outputs
-20
mA
LVCMOS Outputs
-20
±1
+20
µA
268
340
412
mV
1
50
mV
VDD - VOD
VDD (MAX) VOD (MIN)
V
1
50
mV
CML DRIVER DC SPECIFICATIONS (DOUT+, DOUT-)
|VOD|
Output Differential Voltage RT = 100Ω
ΔVOD
Output Differential Voltage
RL = 100Ω
Unbalance
VOS
Output Differential Offset
Voltage
RL = 100Ω (See Figure 10)
ΔVOS
Offset Voltage Unbalance
RL = 100Ω
IOS
Output Short Circuit
Current
DOUT+/- = 0V,
PDB = L or H (4)
RT
Differential Internal
Termination Resistance
Differential across DOUT+ and DOUT-
VDD (MIN) VOD (MAX)
-27
80
100
mA
120
Ω
CML RECEIVER DC SPECIFICATIONS (RIN+, RIN-)
VTH
VTL
(1)
(2)
(3)
(4)
8
Differential Threshold
High Voltage
Differential Threshold Low
Voltage
+90
See Figure 12
mV
-90
The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not guaranteed.
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
Typical values represent most likely parametric norms at 1.8V or 3.3V, TA = +25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not guaranteed.
Specification is guaranteed by characterization and is not tested in production.
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Product Folder Links: DS92LX1621 DS92LX1622
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www.ti.com
SNLS327I – MAY 2010 – REVISED JANUARY 2014
Serializer Electrical Characteristics(1)(2)(3) (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
s
VIN
Differential Input Voltage
Range
RIN+ - RIN-
180
IIN
Input Current
VIN = VDD or 0V,
VDD = 1.89V
-20
±1
+20
µA
RT
Differential Internal
Termination Resistance
Differential across RIN+ and RIN-
80
100
120
Ω
62
90
mV
SER/DES SUPPLY CURRENT *DIGITAL, PLL, AND ANALOG VDDS
IDDT
IDDIOT
IDDTZ
Serializer (Tx)
Total Supply Current
Mode (includes load
current)
RT = 100Ω
WORST CASE pattern
(See Figure 7)
RT = 100Ω
RANDOM PRBS-7 pattern
Serializer (Tx)
VDDIO Supply Current
(includes load current)
RT = 100Ω
WORST CASE pattern
(See Figure 7)
Serializer (Tx) Supply
Current Power-down
PDB = 0V; All other
LVCMOS Inputs = 0V
IDDIOTZ
IDDR
IDDIOR
IDDRZ
Deserializer (Rx) Supply
Current (includes load
current)
Deserializer (Rx) VDDIO
Supply Current (includes
load current)
Deserializer (Rx) Supply
Current Power-down
VDDn = 1.89V
CL = 8pF
WORST CASE Pattern
(See Figure 7)
VDDn = 1.89V,
f = 50MHz
Default Registers
2
VDDn = 3.6V,
f = 50MHz
Default Registers
7
15
VDD = 1.89V
370
775
VDDIO = 1.89V
55
125
VDDIO = 3.6V
65
135
f = 50 MHz
SSCG[3:0] = ON
Default Registers
60
96
f = 50 MHz
Default Registers
VDDIO = 1.89V
CL = 8pF
WORST CASE Pattern
(See Figure 7)
f = 50 MHz
Default Registers
VDDIO = 3.6V
CL = 8pF
Worst Case Pattern
IDDIORZ
55
VDDn = 1.89V,
f = 50MHz
Default Registers
VDDn = 3.6V
CL = 8pF
WORST CASE Pattern
PDB = 0V; All other
LVCMOS Inputs = 0V
mA
5
mA
53
mA
16
25
f = 50 MHz
Default Registers
38
64
VDDn = 1.89V
42
400
VDDIO = 1.89V
8
40
VDDIO = 3.6V
350
800
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SNLS327I – MAY 2010 – REVISED JANUARY 2014
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Recommended Serializer Timing for PCLK (1) (2)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
tTCP
Transmit Clock Period
tTCIH
Transmit Clock Input High
Time
Conditions
Typ
Max
Units
20
T
100
ns
0.4T
0.5T
0.6T
ns
0.4T
0.5T
0.6T
ns
3
ns
10 MHz — 50 MHz
tTCIL
Transmit Clock Input Low
Time
tCLKT
PCLK Input Transition Time
fosc
Internal oscillator clock
source
(1)
Min
0.5
25
MHz
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
Typical values represent most likely parametric norms at 1.8V or 3.3V, TA = +25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not guaranteed.
(2)
Serializer Switching Characteristics (1) (2) (3)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
RL = 100Ω (See Figure 8)
150
330
ps
RL = 100Ω
(See Figure 8)
150
330
ps
tLHT
CML Low-to-High Transition
Time
tHLT
CML High-to-Low Transition
Time
tDIS
Data Input Setup to PCLK
tDIH
Data Input Hold from PCLK
tPLD
Serializer PLL Lock
Time (4) (5)
RL = 100Ω
tSD
Serializer Delay
RT = 100Ω
f = 10-50 MHz
Reg Address 0x03h b[0] (TRFB = 1)
(See Figure 16)
tJIND
Serializer Output
Deterministic Jitter
Serializer output intrinsic deterministic
jitter. Measure with PRBS-7 test
pattern. PCLK = 50 MHz
0.13
UI (6)
tJINR
Serializer Output Random
Jitter
Serializer output intrinsic random jitter
(cycle-cycle). Alternating – 1,0 pattern.
0.04
UI (6)
tJINT
Peak-to-peak Serializer
Output Jitter
Serializer output peak-to-peak jitter
includes deterministic jitter, random
jitter, and jitter transfer from serializer
input. Measure with PRBS-7 test
pattern.
0.396
UI (6)
λSTXBW
Serializer Jitter Transfer
Function -3 dB Bandwidth
PCLK = 50 MHz
Default Registers
1.9
MHz
δSTX
Serializer Jitter Transfer
Function
PCLK = 50 MHz
Default Registers
0.944
dB
δSTXf
Serializer Jitter Transfer
Function Peaking Frequency
PCLK = 50 MHz
Default Registers
500
kHz
(1)
(2)
(3)
(4)
(5)
(6)
10
Serializer Data Inputs (See Figure 14)
2.0
ns
2.0
ns
6.386T + 5
1
2
ms
6.386T +
12
6.386T +
19.7
ns
Typical values represent most likely parametric norms at 1.8V or 3.3V, TA = +25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not guaranteed.
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not guaranteed.
tPLD and tDDLT is the time required by the serializer and deserializer to obtain data lock when exiting power-down state with an active
PCLK.
Specification is guaranteed by design and is not tested in production.
UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency.
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Copyright © 2010–2014, Texas Instruments Incorporated
Product Folder Links: DS92LX1621 DS92LX1622
DS92LX1621, DS92LX1622
www.ti.com
SNLS327I – MAY 2010 – REVISED JANUARY 2014
Deserializer Switching Characteristics (1) (2) (3) (4)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
tRCP
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
Units
Receiver Output Clock Period
tRCP = tTCP
PCLK
20
T
100
ns
tPDC
PCLK Duty Cycle
Default Registers
SSCG[3:0] = OFF
PCLK
45
50
55
%
tCLH
LVCMOS Low-to-High Transition
Time
1.3
2.0
2.8
tCHL
LVCMOS High-to-Low Transition
Time
1.3
2.0
2.8
tCLH
LVCMOS Low-to-High Transition
Time
1.6
2.4
3.3
1.6
2.4
3.3
0.38T
0.5T
0.38T
0.5T
4.571T +
8
4.571T +
12
tCHL
LVCMOS High-to-Low Transition
Time
tROS
ROUT Setup Data to PCLK
VDDIO: 1.71V to 1.89V or
3.0V to 3.6V, CL = 8 pF
(lumped load)
Default Registers (See
Table 1) (5)
PCLK
VDDIO: 1.71V to 1.89V or
3.0V to 3.6V, CL = 8 pF
(lumped load)
Default Registers (See
Table 1) (6)
Deserializer Data
Outputs
VDDIO: 1.71V to 1.89V or
3.0V to 3.6V, CL = 8pF
(lumped load)
Default Registers ( See
Table 1)
Deserializer Data
Outputs
Default Registers
Register 0x03h b[0]
(RRFB = 1)
10 MHz-50 MHz
ns
ns
ns
tROH
ROUT Hold Data to PCLK
tDD
Deserializer Delay
tDDLT
Deserializer Data Lock Time
10 MHz-50 MHz
tRJIT
Receiver Input Jitter Tolerance (7)
50 MHz
0.53
tRDJ
Receiver Clock Jitter
PCLK
SSCG[3:0] = OFF
10 MHz
300
550
50 MHz
120
250
tDPJ
Deserializer Period Jitter (8)
PCLK
SSCG[3:0] = OFF
10 MHz
425
600
50 MHz
320
480
tDCCJ
Deserializer Cycle-to-Cycle Clock
Jitter (9)
PCLK
SSCG[3:0] = OFF
10 MHz
320
500
50 MHz
300
500
fdev
Spread Spectrum Clocking
Deviation Frequency
fmod
Spread Spectrum Clocking
Modulation Frequency
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
LVCMOS Output Bus
(See Figure 21)
4.571T
+ 16
ns
10
ms
UI
ps
ps
ps
20 MHz-50 MHz
±0.5% to
±2.0%
%
20 MHz-50 MHz
±9 kHz to
±66 kHz
kHz
The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not guaranteed.
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
Typical values represent most likely parametric norms at 1.8V or 3.3V, TA = +25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not guaranteed.
tDCJ is the maximum amount of jitter measured over 30,000 samples based on Time Interval Error (TIE).
Specification is guaranteed by characterization and is not tested in production.
Specification is guaranteed by design and is not tested in production.
tRJIT max (0.61 UI) is limited by instrumentation and actual tRJIT of in-band jitter at low frequency (0
fLOW
SCL Low Period
4.7
µs
fHIGH
SCL High Period
4.0
µs
tHD:STA
Hold time for a start or a repeated start
condition
4.0
µs
tSU:STA
Set Up time for a start or a repeated
start condition
4.7
µs
tHD:DAT
Data Hold Time
tSU:DAT
Data Set Up Time
250
ns
tSU:STO
Set Up Time for STOP Condition,
4.0
µs
tr
SCL & SDA Rise Time
1000
tf
SCL & SDA Fall Time
300
ns
Cb
Capacitive load for bus
400
pF
fSCL = 100 kHz
0
3.45
µs
ns
SWITCHING CHARACTERISTICS ( (2))
fSCL
SCL Clock Frequency
fLOW
Serializer M/S = 0 – R/W Register
0x05 = 0x40'h
100
Deserializer M/S = 0 – READ
Register 0x06 b[6:4] = 0x00'h
100
kHz
Serializer M/S = 0 – R/W Register
0x05 = 0x40'h
SCL Low Period
Deserializer M/S = 0 – READ
Register 0x06 b[6:4] = 0x00'h
Serializer M/S = 0 – R/W Register
0x05 = 0x40'h
4.7
μs
4.0
μs
μs
fHIGH
SCL High Period
tHD:STA
Hold time for a start or a repeated start
condition
Serializer M/S = 0 Register 0x05 =
0x40'h
4.0
tSU:STA
Set Up time for a start or a repeated
start condition
Serializer M/S = 0 Register 0x05 =
0x40'h
4.7
tHD:DAT
Data Hold Time
tSU:DAT
Data Set Up Time
tSU:STO
Set Up Time for STOP Condition
tf
SCL & SDA Fall Time
tBUF
Bus free time between a stop and start
condition
tTIMEOUT
NACK Time out
(1)
(2)
12
Deserializer M/S = 0 – READ
Register 0x06 b[6:4] = 0x00'h
μs
0
Serializer M/S = 0
3.45
250
ns
4.0
μs
300
Serializer M/S = 0
μs
ns
μs
4.7
Serializer M/S = 1
1
Deserializer MODE = 1
Register 0x06 b[2:0]=111'b
25
ms
Recommended Input Timing Requirements are input specifications and not tested in production.
Specification is guaranteed by design and is not tested in production.
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Copyright © 2010–2014, Texas Instruments Incorporated
Product Folder Links: DS92LX1621 DS92LX1622
DS92LX1621, DS92LX1622
www.ti.com
SNLS327I – MAY 2010 – REVISED JANUARY 2014
SDA
tLOW
tf
tHD;STA
tr
tf
tBUF
tr
tSP
SCL
tSU;STA
tHD;STA
tHIGH
tSU;STO
tSU;DAT
tHD;DAT
START
STOP
REPEATED
START
START
Figure 6. Bi-Directional Control Bus Timing
Bi-Directional Control Bus DC Characteristics (SCL, SDA) - I2C Compliant
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VIH
Input High Level
SDA and SCL
0.7 x
VDDIO
VDDIO
V
VIL
Input Low Level Voltage
SDA and SCL
GND
0.3 x
VDDIO
V
VHY
Input Hysteresis
IOZ
TRI-STATE Output Current
PDB = 0V VOUT = 0V or VDD
-20
±1
+20
µA
IIN
Input Current
SDA or SCL, Vin = VDDIO or GND
-20
±1
+20
µA
CIN
Input Pin Capacitance
VOL
>50
mV
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