DS99R124Q-EVK/NOPB

DS99R124Q-EVK FPD-Link II to FPD-Link Converter Evaluation Kit Rev 0.0 April, 2010 General Description The DS99R124Q-EVK converts FPD-link II to FPD-Link. It translates a high-speed serialized interface with an embedded clock over a single pair to three LVDS data/control streams and one LVDS clock pair. It is backward compatible for operation with older generation deserializer devices. The DS99R124Q-EVK board has a space saving 20-position wall header as the FPD-Link output, and a Rosenberger Automotive HSD Connector as the input. USB or SMA connectors can also be configured as the input, based on the type of the cable to be used. Features • • • • • • • • • • • • • • • • • 5 – 43 MHz support (140 Mbps to 1.82 Gbps Serial Link) 4-channel (3 data + 1 clock) FPD-Link driver outputs AC Coupled STP Interconnect up to 10 meters in length Integrated input termination @ Speed link BIST Mode and reporting pin Optional I2C compatible Serial Control Bus RGB666 + VS, HS, DE converted from 1 pair Power down mode minimizes power dissipation FAST random data lock; no reference clock required Adjustable input receive equalization LOCK (real time link status) reporting pin Low EMI FPD-Link output SSCG option for lower EMI 1.8V or 3.3V compatible I/O interface Automotive grade product: AEC-Q100 Grade 2 qualified >8kV HBM ESD tolerance Backward compatible mode for operation with older generation devices Applications • • Automotive Displays for Navigation Automotive Display for Entertainment Ordering Information PART: DS99R124QSQ Demo board: DS99R124Q-EVK national.com © National Semiconductor Corporation 2009 1 Printed in U.S. Typical Configuration Quick Start Guide: 1. 2. 3. 4. Connect 3.3V DC power and ground of the board to the JP1 from the power supply. Connect 1.8V DC power and ground of the board to the J4 and J5 from the power supply. Attach an applicable cable (not supplied – Rosenberger cable) to this RX board (DS99R124Q) input from a TX board (DS99R421) output. From the Video Decoder board, connect a flat cable (not supplied) to the TX board and connect another flat cable (not supplied) from this RX board to the panel. Jumpers and switches have been configured at the factory default; they should not require any changes for immediate operation of the board. See text on Configuration Settings and datasheet for more details. national.com © National Semiconductor Corporation 2009 2 Printed in U.S. Configuration Settings Component Name Function Power Connections J7 5V DC J4 1.8V DC 1.8V VDD Power. Optional 5V DC Power Jack (Not Populated) JP1 3.3V DC 3.3V VDD Power. J5 VSS Ground. JP2 VDDIO Connect to 3.3V or 1.8V. JP3 VDDA2 Always connect to 1.8V. - VDDPC Always connect to 1.8V. - VDDL Always connect to 1.8V. - VDDTXC Always connect to 3.3V. Input and Output Connections 20 position wall header J8 Automotive HSD Connector J1 J9 and J10 SMA Connector J2 USB Connector Power Wire in USB cable through J2 JP12 and JP13 Connect to FPD-Link output. Connect to FPD-Link II input (default). Connect to FPD-Link II input. (When using these connectors, R3 and R4 should be placed with 0Ω resistors, the traces from R3 and R4 to the J1 should be cut). Connect to FPD-Link II input. (When using this connector, P1 should be removed, and R24 and R25 should be placed with 0Ω resistors) Connect to VSS is recommended. Control Connections JP4 TESTEN JP5 LF_MODE JP6 OSSEL JP7 OEN JP8 VODSEL JP9 BISTM Connect it to “L” or “H” for the BIST Mode. See datasheet for detail information. JP10 BISTEN Connect it to “H” for the BIST enable mode. See datasheet for detail information. Connect it to “L” for the power down mode. Connect it to “H” for the enable mode. See datasheet for detail information. - PDB - SSC[2:0] - OS[2:0] JP24 and VR3 ID[x] J3 and JP23 I2C Interface NSC test mode. Always connect it to “L” or leave it unconnected. Connect to “L” or “H” for the PCLK frequency select. See datasheet for detail information. Connect to “L” or “H” for the Output State select. See datasheet for detail information. Connect it to “L” or “H” for the FPD Link Output Enable. See datasheet for detail information. Connect it to “L” or “H” for the FPD-Link VOD level select. See datasheet for detail information. Connect them to “L” or “H” for the SSCG selection. Over Sample Bit Outputs Connect JP24 to VSS to have the default device PHY address (h’DC). Connect JP24 to VR3; then adjust VR3 value to select desired device PHY address. See datasheet for detail information. Connect JP23 if the I2C power is not supplied on J6. Otherwise, leave it unconnected. Others LED1 PASS PASS output. “ON” when PASS is “H” LED2 LOCK LOCK output. “ON” when LOCK is “H” JP11, JP25 Other options national.com © National Semiconductor Corporation 2009 Do not connect 3 Printed in U.S. Bill of Material Item Quantity Reference Part Comments Digi-Key P/N Part Number 1 2 C3,C4 0.1uF CAP CERAMIC .1UF25V X5R 0402 445-4964-1-ND C1005X5R1E104K 2 1 C5 4.7uF PCC1731CT-ND ECJ-0EF1C104Z 3 9 C6,C18,C20,C22,C25,C26, 0.01uF CAP .1UF 16V CERAMIC Y5V 0402. CAP CERAMIC .01UF 100V X7R 0603 399-3189-1-ND C0603C103K1RACTU 0.1uF CAP .1UF ?0% 25V CERAMIC X7R 0603 PCC2277CT-ND ECJ-1VB1E104K 493-2391-1-ND F931E226MNC 399-3714-1-ND T491B225K020AT 399-1249-1-ND C1206C104K5RACTU 399-3835-1-ND T494B226M016AT A26542-ND 87220-2 A26545-ND 87224-3 H2959CT-ND UX60-MB-5ST C27,C28,C29 4 10 C7,C17,C19,C21,C23,C24, C30,C31,C32,C35 5 2 C10,C13 22uF 6 2 C11,C14 2.2uF 7 2 C12,C15 0.1uF 8 3 C16,C33,C34 22uF 9 2 JP1,JP23 2-Pin Header 10 24 JP2,JP3,JP4,JP5,JP6,JP7, 3-Pin Header CAP TANTALUM 22UF 25V 20% SMD CAPACITOR TANT 2.2UF 20V 10% SMD CAP .10UF 50V CERAMIC X7R 1206 CAPACITOR TANT 22UF 16V 20% SMD CONN HEADER VERT .100 2POS 30AU CONN HEADER VERT .100 3POS 15AU JP8,JP9,JP10,JP12, JP13,JP14,JP15,JP16,JP17, JP18,JP19,JP20,JP21,JP22, JP24 11 1 J2 mini USB 5pin 12 1 J3 IDC1X4 13 2 J4,J5 BANANA 14 1 J8 2X10-Pin Header 15 2 J9,J10 SMA 16 1 LED1 0402_orange_LED 17 1 0603_green_LED 18 12 LED2 R1, R2, R6, R20, R21, R22, R23, R26, R27, R28, R29 R30 19 1 R7 10K 20 2 R10,R11 82.5ohm 21 5 R13,R14,R15,R16,R17 100 0 Ohm,0402 22 2 R31,R32 4.7K 23 1 U1 DS90UR908 24 1 VR3 national.com © National Semiconductor Corporation 2009 SVR100K CONN RECEPT MINI USB2.0 5POS. CONN HEADER 4POS .100 VERT GOLD BANANA-female (non-insulated) CONN HEADER 20 POS STRGHT GOLD. End Launch Jack Receptacle - Tab Contact. LED ORN/CLEAR 610NM 0402 SMD LED GREEN CLEAR THIN 0603 SMD RES ZERO OHM 1/16W 5% 0402 SMD RES 10.0K OHM 1/10W 1% 0402 SMD RES 82.5 OHM 1/10W 1% 0603 SMD RES 100 OHM 0201 SMD. 1/20W .5% RES 4.7K OHM 1/10W 5% 0603 SMD WM2702-ND 22-11-2042 J147-ND 108-0740-001 MHC20K-ND N2520-6002RB J658-ND 142-0701-851 67-1879-1-ND SML-LX0402SOC-TR 160-1446-1-ND LTST-C191KGKT P0.0JTR-ND ERJ-2GEJ0R00X P10.0KHCT-ND ERJ-3EKF1002V P82.5HCT-ND RR03P100DCTND ERJ-3EKF82R5V P4.7KGCT-ND ERJ-3GEYJ472V RR0306P-101-D DS90UR908 11-Turn Trimming Potentiometer; Top Adjust 3224W-1104ECT-ND 3224W-1-104E 4 Printed in U.S. Schematics national.com © National Semiconductor Corporation 2009 5 Printed in U.S. national.com © National Semiconductor Corporation 2009 6 Printed in U.S. Reference Layout Top Layer national.com © National Semiconductor Corporation 2009 Bottom Layer 7 Printed in U.S. IMPORTANT NOTICE FOR TI REFERENCE DESIGNS Texas Instruments Incorporated ("TI") reference designs are solely intended to assist designers (“Buyers”) who are developing systems that incorporate TI semiconductor products (also referred to herein as “components”). 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