DS99R124Q
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SNLS318D – JANUARY 2010 – REVISED APRIL 2013
DS99R124Q 5 - 43 MHz 18-bit Color FPD-Link II to FPD-Link Converter
Check for Samples: DS99R124Q
FEATURES
DESCRIPTION
•
The DS99R124Q converts FPD-Link II to FPD-Link. It
translates a high-speed serialized interface with an
embedded clock over a single pair (FPD-Link II) to
three LVDS data/control streams and one LVDS clock
pair (FPD-Link). This serial bus scheme greatly eases
system design by eliminating skew problems between
clock and data, reduces the number of connector
pins, reduces the interconnect size, weight, and cost,
and overall eases PCB layout. In addition, internal
DC balanced decoding is used to support AC-coupled
interconnects.
1
2
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5 – 43 MHz Support (140 Mbps to 1.2 Gbps
Serial Link)
4-Channel (3 data + 1 Clock) FPD-Link LVDS
Outputs
3 Low-Speed Over-Sampled LVCMOS Outputs
AC Coupled STP Interconnect up to 10 Meters
in Length
Integrated Input Termination
@ Speed Link BIST Mode and Reporting Pin
Optional I2C Compatible Serial Control Bus
RGB666 + VS, HS, DE Converted from 1 Pair
Power Down Mode Minimizes Power
Dissipation
FAST Random Data Lock; no Reference Clock
Required
Adjustable Input Receive Equalization
LOCK (Real Time Link Status) Reporting Pin
Low EMI FPD-Link Output
SSCG Option for Lower EMI
1.8V or 3.3V Compatible I/O Interface
Automotive Grade Product: AEC-Q100 Grade 2
Qualified
>8 kV HBM and ISO 10605 ESD Rating
APPLICATIONS
•
•
Automotive Display for Navigation
Automotive Display for Entertainment
The DS99R124Q converter recovers the data (RGB)
and control signals and extracts the clock from a
serial stream (FPD-Link II). It is able to lock to the
incoming data stream without the use of a training
sequence or special SYNC patterns and does not
require a reference clock. A link status (LOCK) output
signal is provided.
Adjustable input equalization of the serial input
stream provides compensation for transmission
medium losses of the cable and reduces the mediuminduced deterministic jitter. EMI is minimized by the
use of low voltage differential signaling, output state
select feature, and additional output spread spectrum
generation.
With fewer wires to the physical interface of the
display, FPD-Link output with LVDS technology is
ideal for high speed, low power and low EMI data
transfer.
The DS99R124Q is offered in a 48-pin WQFN
package and is specified over the automotive AECQ100 Grade 2 temperature range of -40˚C to +105˚C.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2013, Texas Instruments Incorporated
DS99R124Q
SNLS318D – JANUARY 2010 – REVISED APRIL 2013
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Applications Diagram
FPD-Link
FPD-Link II
FPD-Link
VDDIO
1.8V 3.3V (1.8V or 3.3V)
HOST
Graphics
Processor
RGB Style Display Interface
3.3V
High-Speed Serial Link
1 Pair/AC Coupled
RxIN2+/-
TxOUT2+/-
DOUT+
RxIN1+/RxIN0+/-
RIN+
DOUT-
RxCLKIN+/-
PWDNB
TxOUT1+/TxOUT0+/-
RIN100 ohm STP Cable
DS99R421Q
Converter
DS99R124Q
Converter
CMF
SSC[2:0]
LFMODE
BISTM
BISTEN
OS[2:0]
BISTEN
DEN
PRE
VODSEL
TxCLKOUT+/-
OS[2:0]
LOCK
PASS
PDB
VODSEL
OEN
OSSEL
SCL
SDA
ID[x]
Optional
RGB Display
QVGA to WVGA
18-bit Color Depth
Figure 1.
LFMODE
OSS_SEL
OEN
VODSEL
GND
VDDL
BISTM
BISTEN
PASS/EQ
LOCK
GND
VDDIO
36
35
34
33
32
31
30
29
28
27
26
25
DS99R124Q Pin Diagram
RES[1]
37
24
VDDA
38
23
TxOUT0+
TxOUT0-
GND
39
22
TxOUT1-
RIN+
40
21
TxOUT1+
RIN-
41
20
TxOUT2-
19
TxOUT2+
18
TxCLKOUT-
CMF
42
VDDA
43
DS99R124Q
TOP VIEW
DAP = GND
12
11
OS[1]
OS[0]
10
VDDTX
OS[2]
13
9
48
GND
GND
8
GND
VDDP
14
7
47
SSC[2]
VDDP
6
RES[0]
VDDL
15
5
46
SCL
VDDP
4
ID[x]
SDA
16
3
45
SSC[0]
GND
2
TxCLKOUT+
SSC[1]
17
1
44
PDB
GND
Figure 2. FPD-Link II to FPD-Link Convertor - DS99R124Q
48 Pin WQFN Package
See Package Number RHS0048A
2
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PIN DESCRIPTIONS
Pin Name
Pin #
I/O, Type
Description
FPD-Link II Input Interface
RIN+
40
I, LVDS
True input
The input must be AC coupled with a 100 nF capacitor. Internal termination.
RIN-
41
I, LVDS
Inverting input
The input must be AC coupled with a 100 nF capacitor. Internal termination.
CMF
42
I, Analog
Common-Mode Filter
VCM center-tap is a virtual ground which maybe ac-coupled to ground to increase receiver
common mode noise immunity. Recommended value is 4.7 μF or higher.
FPD-Link Output Interface
TxOUT[2:0]+
19, 21, 23
O, LVDS
True LVDS Data Output
This pair should have a 100 Ω termination for standard LVDS levels.
TxOUT[2:0]-
20, 22, 24
O, LVDS
Inverting LVDS Data Output
This pair should have a 100 Ω termination for standard LVDS levels.
TxCLKOUT+
17
O, LVDS
True LVDS Clock Output
This pair should have a 100 Ω termination for standard LVDS levels.
TxCLKOUT-
18
O, LVDS
Inverting LVDS Clock Output
This pair should have a 100 Ω termination for standard LVDS levels.
LVCMOS Outputs
OS[2:0]
10, 11, 12
O, LVMOS
Over-Sampled Low Frequency Outputs
These bits map to the DS99R421's OS[2:0] over-sampled low-frequency inputs. Signals must
be slower the TxCLK/5. On the DS90UR241 these map to the DIN[23:21] inputs. OS0 =
DIN21, OS1 = DIN22, OS2 = DIN23.
LOCK
27
O, LVMOS
LOCK Status Output
LOCK = 1, PLL is locked, outputs are active.
LOCK = 0, PLL is unlocked, output states determined by OSS_SEL.
Maybe used as a Link Status or to flag when the Video Data is active (ON/OFF).
Control and Configuration
PDB
1
I, LVCMOS
w/ pull-down
Power Down Mode Input
PDB = 1, Device is enabled (normal operation)
PDB = 0, Device is in power-down, the output are controlled by the settings. Control registers
are RESET.
VODSEL
33
I, LVCMOS
w/ pull-down
Differential Driver Output Voltage Select
VODSEL = 1, LVDS VOD is ±400 mV, 800 mVp-p (typ) — Long Cable / De-E Applications
VODSEL = 0, LVDS VOD is ±250 mV, 500 mVp-p (typ)
See Table 2
OEN
34
I, LVCMOS
w/ pull-down
Output Enable Input
OEN = 1, FPD-Link outputs are enabled (active).
OEN = 0, FPD-Link outputs are TRI-STATE.
OSS_SEL
35
I, LVCMOS
w/ pull-down
Output Sleep State Select Input
See Table 1
LFMODE
36
I, LVCMOS
w/ pull-down
Low Frequency Mode — Pin or Register Control
LF_MODE = 1, low frequency mode (TxCLKOUT = 5-20 MHz)
LF_MODE = 0, high frequency mode (TxCLKOUT = 20-43 MHz)
SSC[2:0]
7, 2, 3
I, LVCMOS
w/ pull-down
Spread Spectrum Clock Generation (SSCG) Range Select
See Table 3 and Table 4
RES[1:0]
37, 15
I, LVCMOS
w/ pull-down
Reserved
Tie Low
Control and Configuration — STRAP PIN
For a High State, use a 10 kΩ pull up to VDDIO; for a Low State, the IO includes an internal pull down. The STRAP pin is read upon powerup and set device configuration. Pin number listed along with shared LVCMOS Output name in square bracket.
EQ
28 [PASS]
STRAP
I, LVCMOS
w/ pull-down
EQ Gain Control of FPD-Link II Input
EQ = 1, EQ gain is enabled (~13 dB)
EQ = 0, EQ gain is disabled (~1.625 dB)
I, LVCMOS
w/ pull-down
BIST Enable Input – Optional
BISTEN = 1, BIST Mode is enabled.
BISTEN = 0, normal mode.
Optional BIST Mode
BISTEN
29
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PIN DESCRIPTIONS (continued)
Pin Name
Pin #
I/O, Type
Description
BISTM
30
I, LVCMOS
w/ pull-down
BIST Mode Input – Optional
BISTM = 1, selects Payload Error Mode
BISTM = 0, selects Pass / Fail Result-Only Mode
PASS
28
O, LVCMOS
PASS Output (BIST Mode) – Optional
PASS = 1, no errors detected
PASS = 0, errors detected
Leave open if unused. Route to a test point (pad) recommended.
Optional Serial Bus Control Interface
SCL
5
I, LVCMOS
Serial Control Bus Clock Input - Optional
SCL requires an external pull-up resistor to VDDIO.
SDA
4
I/O, LVCMOS Serial Control Bus Data Input / Output - Optional
Open Drain
SDA requires an external pull-up resistor to VDDIO.
ID[x]
16
I, Analog
Serial Control Bus Device ID Address Select — Optional
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 5.
Power and Ground
VDDL
6, 31
Power
Logic Power, 1.8 V ±5%
VDDA
38, 43
Power
Analog Power, 1.8 V ±5%
VDDP
8, 46, 47
Power
SSC Generator Power, 1.8 V ±5%
VDDTX
13
Power
FPD-Link Power, 3.3 V ±10%
VDDIO
25
Power
LVCMOS I/O Power, 1.8 V ±5% OR 3.3 V ±10%
GND
9, 14, 26,
32, 39, 44,
45, 48
Ground
Ground
DAP
DAP
Ground
DAP is the large metal contact at the bottom side, located at the center of the WQFN
package. Connected to the ground plane (GND) with at least 9 vias.
Block Diagram
DS99R124Q ± CONVERTER
SSC[2:0]
OEN
VODSEL
SSCG
RIN-
PDB
SCL
SCA
ID[x]
BISTEN
BISTM
OSS_SEL
LFMODE
Serializer
RIN+
TxOUT[2]
DC Balance Decoder
Serial to Parallel
CMF
TxOUT[0]
TxCLKOUT
Error
Detector
Timing and
Control
TxOUT[1]
3
PLL
OS[2:0]
PASS
LOCK
Figure 3. FPD-Link II to FPD-Link Convertor
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
4
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SNLS318D – JANUARY 2010 – REVISED APRIL 2013
Absolute Maximum Ratings (1) (2)
Supply Voltage – VDDn (1.8V)
−0.3V to +2.5V
Supply Voltage – VDDTX (3.3V)
−0.3V to +4.0V
−0.3V to +4.0V
Supply Voltage – VDDIO
−0.3V to +(VDDIO + 0.3V)
LVCMOS I/O Voltage
−0.3V to (VDD + 0.3V)
Receiver Input Voltage
LVDS Output Voltage
−0.3V to (VDDTX + 0.3V)
Junction Temperature
+150°C
Storage Temperature
−65°C to +150°C
Lead Temperature
(Soldering, 4s)
+260°C
48L RHS Package
Maximum Power Dissipation Capacity at
25°C
1/ θJA°C/W
Derate above 25°C
θJA
27.7 °C/W
θJC
3.0 °C/W
ESD Rating (IEC, powered-up only), RD =
330Ω, CS = 150pF
Air Discharge (RIN+, RIN−)
ESD Rating (ISO10605), RD = 330Ω, CS =
150 & 330pF
Air Discharge (RIN+, RIN−)
≥±30 kV
≥±6 kV
Contact Discharge (RIN+, RIN−)
≥±15 kV
Contact Discharge (RIN+, RIN−)
≥±8 kV
ESD Rating (ISO10605), RD = 2kΩ, CS = 150 Air Discharge (RIN+, RIN−)
& 330pF
Contact Discharge (RIN+, RIN−)
≥±15 kV
≥±8 kV
ESD Rating (HBM)
≥±8 kV
ESD Rating (CDM)
≥±1.25 kV
≥±250 V
ESD Rating (MM)
(1)
(2)
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
Recommended Operating Conditions
Min
Nom
Max
Units
Supply Voltage (VDDn)
1.71
1.8
1.89
V
LVCMOS Supply Voltage (VDDIO)
1.71
1.8
1.89
V
LVCMOS Supply Voltage (VDDIO)
3.0
3.3
3.6
V
Operating Free Air Temperature (TA)
−40
+25
+105
°C
43
MHz
100
mVP-P
TxCLK Clock Frequency
5
Supply Noise (1)
(1)
Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC coupled to the VDDn (1.8V) supply with
amplitude = 100 mVp-p measured at the device VDDn pins. Bit error rate testing of input to the Ser and output of the Des with 10 meter
cable shows no error when the noise frequency on the Ser is less than 750 kHz. The Des on the other hand shows no error when the
noise frequency is less than 400 kHz.
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DC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2) (3)
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
Units
mV
FPD-Link LVDS Output
|VOD|
Differential
Output Voltage
VODSEL = L
100
250
400
VODSEL = H
200
400
600
VODSEL = L
500
mVp-p
VODp-p
Differential
Output Voltage
A-B
VODSEL = H
800
mVp-p
ΔVOD
Output Voltage RL = 100Ω
Unbalance
VOS
Offset Voltage
ΔVOS
Offset Voltage
Unbalance
IOS
Output Short
Circuit Current
Vout = GND
IOZ
Output TRISTATE
Current
OEN = GND,
Vout =VDDTX, or GND
VODSEL = L
TxCLKOUT+,
TxCLKOUT-,
TxOUT[2:0]+,
TxOUT[2:0]-
1.0
VODSEL = H
mV
1
50
mV
1.2
1.5
V
1.2
1
V
50
-5
mV
mA
-10
+10
µA
2.2
VDDIO
V
GND
0.8
V
+15
μA
3.3 V I/O LVCMOS DC SPECIFICATIONS – VDDIO = 3.0 to 3.6V
VIH
High Level
Input Voltage
PDB,
VODSEL,
OEN,
OSS_SEL,
LFMODE,
SSC[2:0],
BISTEN,
BISTM
VIL
Low Level
Input Voltage
IIN
Input Current
VOH
High Level
I = −0.5 mA
Output Voltage OH
VOL
Low Level
I = +0.5 mA
Output Voltage OL
IOS
Output Short
Circuit Current
IOZ
TRI-STATE
PDB = 0V, OSS_SEL = 0V,
Output Current VOUT = 0V or VDDIO
VIN = 0V or VDDIO
−15
±1
VDDIO- 0.2
VDDIO
GND
LOCK, PASS,
OS[2:0]
VOUT = 0V
V
0.2
-10
V
mA
−10
+10
µA
0.7
VDDIO
VDDIO
V
GND
0.35*
VDDIO
V
+10
μA
1.8 V I/O LVCMOS DC SPECIFICATIONS – VDDIO = 1.71 to 1.89V
VIH
High Level
Input Voltage
VIL
Low Level
Input Voltage
IIN
Input Current
(1)
(2)
(3)
6
VIN = 0V or VDDIO
PDB,
VODSEL,
OEN,
OSS_SEL,
LFMODE,
SSC[2:0],
BISTEN,
BISTM
−10
±1
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Typical values represent most likely parametric norms at VDDn = 1.8V, VDDTX = 3.3V, VDDIO = 1.8V or 3.3V, Ta = +25 °C, and at the
Recommended Operation Conditions at the time of product characterization and are not ensured.
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
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DC Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3)
Symbol
Parameter
Conditions
VOH
High Level
I = −0.1 mA
Output Voltage OH
VOL
Low Level
I = +0.1 mA
Output Voltage OL
IOS
Output Short
Circuit Current
IOZ
TRI-STATE
VOUT = 0V or VDDIO
Output Current
Pin/Freq.
Typ
VDDIO
- 0.2
VDDIO
GND
LOCK, PASS,
OS[2:0]
VOUT = 0V
Min
Max
Units
V
0.2
V
-3
-15
mA
+15
µA
+50
mV
FPD-Link II LVDS RECEIVER DC SPECIFICATIONS
VTH
Differential
Input
Threshold High
Voltage
VTL
Differential
Input
Threshold Low
Voltage
VCM
Common
Mode Voltage,
Internal VBIAS
RT
Input
Termination
VCM = +1.2V (Internal VBIAS)
−50
RIN+, RIN-
mV
1.2
75
V
80
92
Ω
SUPPLY CURRENT
IDD1
Checker Board
Supply Current
Pattern,
(includes load
VODSEL = H,
current)
SSCG = On
43 MHz Clock
Figure 4
IDDTX1
IDDIO1
IDDZ
PDB = 0V, All
Supply Current
other LVCMOS
Power Down
Inputs = 0V
IDDTXZ
IDDIOZ
VDDn= 1.89V
All VDD(1.8)
pins
70
80
mA
VDDTX = 3.6V
VDDTX
30
40
mA
0.35
1
mA
1
1.5
mA
VDD= 1.89V
All VDD(1.8)
pins
0.15
4
mA
VDDTX = 3.6V
VDDTX
0.01
0.05
mA
0.1
0.4
mA
0.4
0.8
mA
VDDIO=1.89V
VDDIO = 3.6V
VDDIO=1.89V
VDDIO = 3.6V
VDDIO
VDDIO
Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2)
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
Units
FPD-Link II
tDDLT
tDJIT
Lock Time (3)
Input Jitter Tolerance
SSCG = Off
5 MHz
6
ms
SSCG = On
5 MHz
14
ms
SSCG = Off
43 MHz
5
ms
SSCG = On
43 MHz
8
ms
>0.45
UI
EQ = Off
Jitter Frequency > 10 MHz
Figure 14
FPD-Link Output
(1)
(2)
(3)
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Typical values represent most likely parametric norms at VDDn = 1.8V, VDDTX = 3.3V, VDDIO = 1.8V or 3.3V, Ta = +25 °C, and at the
Recommended Operation Conditions at the time of product characterization and are not ensured.
tDDLT is the time required by the deserializer to obtain lock when exiting power-down state with an active PCLK.
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Switching Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)
Symbol
Parameter
Conditions
tTLHT
Low to High Transition Time
tTHLT
High to Low Transition Time
tDCCJ
Cycle-to-Cycle Output Jitter (4) (5) TxCLKOUT = 5 MHz
Pin/Freq.
RL = 100Ω
Min
Typ
Max
Units
TxCLKOUT±,
TxOUT[2:0]±
0.3
0.6
ns
0.3
0.6
ns
TxCLKOUT±
900
2100
ps
75
125
ps
TxCLKOUT = 43 MHz
tTTP1
Transmitter Pulse Position for
bit 1
tTTP0
TxOUT[2:0]±
0
UI
Transmitter Pulse Position for
bit 0
1
UI
tTPP6
Transmitter Pulse Position for
bit 6
2
UI
tTTP5
Transmitter Pulse Position for
bit 5
3
UI
tTTP4
Transmitter Pulse Position for
bit 4
4
UI
tTTP3
Transmitter Pulse Position for
bit 3
5
UI
tTTP2
Transmitter Pulse Position for
bit 2
6
UI
tTPDD
Power Down Delay active to
OFF
Figure 6
TxCLKOUT = 43 MHz
Enable Delay OFF to active
Figure 7
TxCLKOUT = 43 MHz
tTXZR
6
10
ns
40
55
ns
15
ns
LVCMOS Outputs
tCLH
Low to High Transition Time
tCHL
High to Low Transition Time
tPASS
BIST PASS Valid Time,
BISTEN = 1, Figure 12
CL = 8 pF
Figure 5
LOCK, PASS, OS[2:0]
10
10
15
ns
TxCLKOUT = 5 MHz
PASS
560
570
ns
70
75
ns
TxCLKOUT = 43 MHz
SSCG Mode
fDEV
fMOD
(4)
(5)
(6)
Spread Spectrum
Clocking Deviation
Frequency
See (6)
Spread Spectrum
Clocking Modulation
Frequency
See (6)
TxCLKOUT = 5 to 43
MHz,
SSC[3:0] = ON
±0.5
±2
%
TxCLKOUT = 5 to 43
MHz,
SSC[3:0] = ON
8
100
kHz
Max
Units
tDCCJ is the maximum amount of jitter between adjacent clock cycles.
Specification is ensured by characterization and is not tested in production.
Specification is ensured by design and is not tested in production.
Recommended Timing for the Serial Control Bus
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
fSCL
Parameter
SCL Clock Frequency
tLOW
SCL Low Period
tHIGH
SCL High Period
tHD;STA
8
Hold time for a start or a
repeated start condition,
Figure 13
Conditions
Min
Typ
Standard Mode
0
100
kHz
Fast Mode
0
400
kHz
Standard Mode
4.7
us
Fast Mode
1.3
us
Standard Mode
4.0
us
Fast Mode
0.6
us
Standard Mode
4.0
us
Fast Mode
0.6
us
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Recommended Timing for the Serial Control Bus (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
tSU:STA
Parameter
Conditions
Min
Typ
Max
Units
Set Up time for a start or a
repeated start condition,
Figure 13
Standard Mode
4.7
us
Fast Mode
0.6
us
tHD;DAT
Data Hold Time,
Figure 13
Standard Mode
tSU;DAT
Data Set Up Time,
Figure 13
Standard Mode
250
ns
Fast Mode
100
ns
Set Up Time for STOP
Condition, Figure 13
Standard Mode
4.0
us
Fast Mode
0.6
us
Bus Free Time
Between STOP and START,
Figure 13
Standard Mode
4.7
us
Fast Mode
1.3
us
SCL & SDA Rise Time,
Figure 13
Standard Mode
1000
ns
Fast Mode
300
ns
SCL & SDA Fall Time,
Figure 13
Standard Mode
300
ns
Fast mode
300
ns
Max
Units
0.7*
VDDIO
VDDIO
V
GND
0.3*
VDDIO
V
tSU;STO
tBUF
tr
tf
Fast Mode
0
3.45
us
0
0.9
us
DC and AC Serial Control Bus Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
VIH
Input High Level
SDA and SCL
VIL
Input Low Level Voltage
SDA and SCL
VHY
Input Hysteresis
Min
Typ
>50
VOL
SDA, IOL = +0.5 mA
Iin
SDA or SCL, Vin = VDDIO or GND
mV
0
0.36
V
-10
+10
µA
850
ns
120
ns
SDA, RPU = X, Cb ≤ 400pF
tR
SDA RiseTime – READ
tF
SDA Fall Time – READ
tSU;DAT
Set Up Time — READ
500
tHD;DAT
Hold Up Time — READ
580
tSP
Input Filter
Cin
Input Capacitance
ns
ns
SDA or SCL
50
ns
10 PF
R = 10 k:
FB1 - FB5: Impedance = 1 k:
Low DC resistance (< 1:)
SCL
SDA
ID[X]
2
8
LOCK
PASS
VODSEL
OSS_SEL
LFMODE
SSC[2]
SSC[1]
SSC[0]
Tie to
desired
setting
NC
GND
DAP (GND)
Figure 26. DS99R124Q Typical Connection Diagram — Pin Control
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DS99R124Q
SNLS318D – JANUARY 2010 – REVISED APRIL 2013
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POWER UP REQUIREMENTS AND PDB PIN
The VDD (VDDn), VDDTX and VDDIO supply ramps should be faster than 1.5 ms with a monotonic rise. Supplies
may power up in any order, however device operation should be initiated only after all supplies are in their valid
operating ranges. The optional serial bus address selection is done upon power up also. Thus, if using this
optional feature, the PDB signal must be delayed to allow time for the ID setting to occur. The delay maybe done
by simply holding the PDB pin at a Low, or with an external RC delay based off the VDDIO rail which would then
need to lag the others in time. If the PDB pin is pulled to VDDIO, it is recommended to use a 10 kΩ pull-up and a
10 uF cap to GND to delay the PDB input signal.
TRANSMISSION MEDIA
The Ser/Des chipset is intended to be used in a point-to-point configuration, through a PCB trace, or through
twisted pair cable. The Ser and Des provide internal terminations providing a clean signaling environment. The
interconnect for LVDS should present a differential impedance of 100 Ohms. Use cables and connectors that
have matched differential impedance to minimize impedance discontinuities. Shielded or un-shielded cables may
be used depending upon the noise environment and application requirements.
LIVE LINK INSERTION
The Ser and Des devices support live pluggable applications. The automatic receiver lock to random data “plug &
go” hot insertion capability allows the DS99R124Q to attain lock to the active data stream during a live insertion
event.
PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS
Circuit board layout and stack-up for the LVDS Ser/Des devices should be designed to provide low-noise power
feed to the device. Good layout practice will also separate high frequency or high-level inputs and outputs to
minimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatly
improved by using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane
capacitance for the PCB power system with low-inductance parasitics, which has proven especially effective at
high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass
capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the
range of 0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF to 10 uF range. Voltage rating of the
tantalum capacitors should be at least 5X the power supply voltage being used.
Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per
supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power
entry. This is typically in the 50uF to 100uF range and will smooth low frequency switching noise. It is
recommended to connect power and ground pins directly to the power and ground planes with bypass capacitors
connected to the plane with via on both ends of the capacitor. Connecting power or ground pins to an external
bypass capacitor will increase the inductance of the path.
A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size
reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of
these external bypass capacitors, usually in the range of 20-30 MHz. To provide effective bypassing, multiple
capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At
high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing
the impedance at high frequency.
Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate
switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not
required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power
pin pairs. In some cases, an external filter many be used to provide clean power to sensitive circuits such as
PLLs.
Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the LVDS
lines to prevent coupling from the LVCMOS lines to the LVDS lines. Closely-coupled differential lines of 100
Ohms are typically recommended for LVDS interconnect. The closely coupled lines help to ensure that coupled
noise will appear as common-mode and thus is rejected by the receivers. The tightly coupled lines will also
radiate less.
Information on the WQFN style package is provided in Texas Instruments Note: AN-1187 (SNOA401).
24
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DS99R124Q
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SNLS318D – JANUARY 2010 – REVISED APRIL 2013
LVDS INTERCONNECT GUIDELINES
See AN-1108 (SNLA008) and AN-905 (SNLA035) for full details.
• Use 100Ω coupled differential pairs
• Use the S/2S/3S rule in spacings
– S = space between the pair
– 2S = space between pairs
– 3S = space to LVCMOS signal
• Minimize the number of Vias
• Use differential connectors when operating above 500Mbps line speed
• Maintain balance of the traces
• Minimize skew within the pair
• Terminate as close to the TX outputs and RX inputs as possible
Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the TI
web site at: http://www.ti.com/ww/en/analog/interface/lvds.shtml
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DS99R124Q
SNLS318D – JANUARY 2010 – REVISED APRIL 2013
www.ti.com
REVISION HISTORY
Changes from Revision C (April 2013) to Revision D
•
26
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 25
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
(4/5)
(6)
DS99R124QSQ/NOPB
ACTIVE
WQFN
RHS
48
1000
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 105
DS99R124Q
DS99R124QSQE/NOPB
ACTIVE
WQFN
RHS
48
250
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 105
DS99R124Q
DS99R124QSQX/NOPB
ACTIVE
WQFN
RHS
48
2500
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 105
DS99R124Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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