HD3SS215, HD3SS215I
HD3SS215I
SLAS971E – MAY 2014HD3SS215,
– REVISED DECEMBER
2020
SLAS971E – MAY 2014 – REVISED DECEMBER 2020
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HD3SS215 6.0 Gbps HDMI DisplayPort 2:1/1:2 Differential Switch
1 Features
3 Description
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HD3SS215 is a high-speed wide common mode
passive switch capable of supporting DisplayPort
HBR2 and high definition multimedia interface (HDMI)
applications requiring 4k2k 60Hz refresh rates. The
HD3SS215 can be configured to support two sources
to one sink or one source to two sinks. To support
these video standards the HD3SS215 also switches
the display data channel (DDC) and hot plug detect
(HPD) signals for HDMI or digital video interface (DVI)
applications. It also switches the auxiliary (AUX) and
hot plug detect (HPD) signals for DisplayPort
applications. The flexibility the HD3SS215 provides by
supporting both wide common mode and AC or DC
coupled links makes it ideal for many applications.
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General purpose 2:1/1:2 differential switch
Compatible with displayport electrical standard
Compatible with hdmi electrical standards
2:1 and 1:2 switching supporting data rates up to 6
Gbps
Supports HPD switching
Supports AUX and DDC switching
Wide –3-dB differential bandwidth of 7 GHz
Excellent dynamic characteristics (at 3 GHz)
– Crosstalk = –35 dB
– Isolation = –21 dB
– Insertion Loss = –1.6 dB
– Return Loss = –12 dB
– Max Bit-Bit Skew = 5 ps
VDD operating range 3.3 V ±10%
Commercial temperature range: 0°C to 70°C
(HD3SS215)
Industrial temperature range: –40°C to 85°C
(HD3SS215I)
Package options:
– 5 mm x 5 mm, 50-ball ZXH
– 8 mm × 8 mm, 56-pin RTQ
Output enable (OE) pin disables switch to save
power
Power consumption:
– Active < 9 mW typical
– Standby < 30 µW maximum (when OE = L)
Device Information (1)
PART NUMBER
HD3SS215,
HD3SS215I
(1)
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Desktop and Notebook Applications:
– PCI Express Gen 1, Gen 2 Switching
– DP Switching
– HDMI Switching
– LVDS Switching
Connected peripherals & printers
Home theater & entertainment
TV
Gaming
Pro audio, video & signage
BODY SIZE (NOM)
5.00 mm x 5.00 mm
QFN (56)
8.00 mm × 8.00 mm
For all available packages, see the orderable addendum at
the end of the datasheet.
Source A
4
DAx(p)
4
DAx(n)
4
DCx(p)
4
DCx(n)
2
DDCC
2
AUXCx
AUXAx
2
DDCA 2
HPDA
DP/DP++
HDMI sink
HPDC
AUXBx
2
DDCB 2
HPDB
OE
Source B
Dx_SEL
Control
2 Applications
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PACKAGE
nFBGA (50)
4
DBx(p)
4
DBx(n)
AUX_SEL
HD3SS215 2:1
DP/DP++
HDMI Sink A
4
DAx(p)
4
DAx(n)
4
DCx(p)
4
DCx(n)
2
DDCC
2
AUXCx
AUXAx
2
DDCA 2
HPDA
AUXBx
2
Source
HPDC
DDCB 2
DP/DP++
HDMI Sink B
HPDB
OE
Control
4
DBx(p)
4
DBx(n)
Dx_SEL
AUX_SEL
HD3SS215 1:2
Application Schematic
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
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2020 Texas Instruments
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SLAS971E – MAY 2014 – REVISED DECEMBER 2020
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Description (continued).................................................. 4
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 9
7.1 Absolute Maximum Ratings (1) (2) ...............................9
7.2 ESD Ratings............................................................... 9
7.3 Recommended Operating Conditions.........................9
7.4 Thermal Information....................................................9
7.5 Electrical Characteristics...........................................10
7.6 Electrical Characteristics, Device Parameters (1) ..... 11
7.7 Switching Characteristics.......................................... 11
7.8 Timing Diagrams....................................................... 11
8 Detailed Description......................................................13
8.1 Overview................................................................... 13
8.2 Functional Block Diagram......................................... 14
8.3 Feature Description...................................................15
8.4 Device Functional Modes..........................................15
9 Applications and Implementation................................ 16
9.1 Application Information............................................. 16
9.2 Typical Applications.................................................. 16
10 Layout...........................................................................21
10.1 Layout Guidelines................................................... 21
10.2 Layout Example...................................................... 22
11 Device and Documentation Support..........................24
11.1 Community Resources............................................24
11.2 Trademarks............................................................. 24
12 Mechanical, Packaging, and Orderable
Information.................................................................... 24
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (September 2015) to Revision E (December 2020)
Page
• NOTE: The device in the MicroStar Jr. BGA packaging were redesigned using a laminate nFBGA package.
This nFBGA package offers datasheet-equivalent electrical performance. It is also footprint equivalent to the
MicroStar Jr. BGA. The new package designator in place of the discontinued package designator will be
updated throughout the datasheet......................................................................................................................1
• Changed u*jr ZQE to nFBGA ZXH..................................................................................................................... 1
• Changed u*jr ZQE to nFBGA ZXH..................................................................................................................... 4
• Changed u*jr ZQE to nFBGA ZXH..................................................................................................................... 4
• Changed u*jr ZQE to nFBGA ZXH..................................................................................................................... 4
• Changed u*jr ZQE to nFBGA ZXH..................................................................................................................... 7
• Changed u*jr ZQE to nFBGA ZXH. Updated thermal data.................................................................................9
• Changed u*jr ZQE to nFBGA ZXH....................................................................................................................11
• Changed u*jr ZQE to nFBGA ZXH................................................................................................................... 16
Changes from Revision C (August 2015) to Revision D (September 2015)
Page
• Changed Section 3 text string from "....DisplayPort 1.2a..." to "...DisplayPort HBR2..." and from "..HDMI2.0.."
to "...HDMI..." ..................................................................................................................................................... 1
• Deleted RθJC(bot) spec from Thermal Information table as N/A...........................................................................9
• Deleted "Operating free air temperature" spec from Electrical Characteristics table....................................... 10
• Changed Figure 9-5 .........................................................................................................................................20
• Changed Section Power Supply Recommendations text string from "Decoupling capacitors may be used to
reduce noise and improve power supply integrity" to "Decoupling capacitors must be used to reduce power
supply noise"...................................................................................................................................................0
Changes from Revision B (July 2015) to Revision C (July 2015)
Page
• Added ton(OE_L-H), toff(OE_H-L), and tSWITCH_OVER to the Section 7.7 ..................................................................11
Changes from Revision A (May 2014) to Revision B (July 2015)
Page
• Changed the title From: "2.0/DisplayPort 1.2A" To: "DisplayPort"...................................................................... 1
2
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HD3SS215, HD3SS215I
SLAS971E – MAY 2014 – REVISED DECEMBER 2020
Changed Section 1 list item From: Compatible With DisplayPort 1.2a Electrical Standard To: Compatible With
DisplayPort Electrical Standard.......................................................................................................................... 1
Changed Section 1 list item From: Compatible With HDMI 1.4b and HDMI 2.0 Electrical Standards To:
Compatible With HDMI Electrical Standards...................................................................................................... 1
Added Section 1 item: Commercial Temperature Range: –40°C to 70°C (HD3SS215)..................................... 1
Added Section 1 item: Inductrial Temperature Range: –40°C to 85°C (HD3SS215I).........................................1
Added Section 1, Package Options: 8 mm × 8 mm, 56-Pin RTQ....................................................................... 1
Changed the Section 2 list item From: TV and Monitors To: UHDTV, HDTV and Monitors................................1
Added Section 5 paragraph. .............................................................................................................................. 4
Added the 56-Pin QFN image.............................................................................................................................4
Added RTQ column to the Pin Functions table ..................................................................................................4
Added RTQ column to the Pin Functions table ..................................................................................................7
Moved Tstg From: Section 7.2 To: Section 7.1 ................................................................................................... 9
Changed the Handling Ratings table to Section 7.2 table ................................................................................. 9
Added HD3SS2151I, Operating free-air temperature Section 7.3 .....................................................................9
Added RTQ 56 PIN values to the Section 7.4 ....................................................................................................9
Added table Note " This pin can be driven.." to the Section 7.5 table.............................................................. 10
Changed the Section 7.6 table to include ZQE and RTQ package values....................................................... 11
Added the Section 7.7 table .............................................................................................................................11
Added section: Section 9.2.4 ........................................................................................................................... 20
Added Figure 10-3 ........................................................................................................................................... 22
Changes from Revision * (May 2014) to Revision A (May 2014)
Page
• Changed Section 3 section ................................................................................................................................1
• Changed Figure 9-1 .........................................................................................................................................16
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SLAS971E – MAY 2014 – REVISED DECEMBER 2020
5 Description (continued)
One typical application would be a mother board that includes two GPUs that need to drive one DisplayPort sink.
The GPU is selected by the Dx_SEL pin. Another application is when one source needs to switch between one
of two sinks, such as a side connector an a docking station connector. The switching is controlled using the
Dx_SEL and AUX_SEL pins. The HD3SS215I operates from a single supply voltage of 3.3 V, over full industrial
temperature range –40°C to 85°C, in the ZXH package and 56 pin RTQ package.
6 Pin Configuration and Functions
1
2
A
Dx_SEL
VDD
B
DC0(n)
DC0(p)
C
3
GND
4
5
6
DA0(n)
DA1(n)
DA2(n)
DA0(p)
DA1(p)
DA2(p)
7
OE
8
9
DA3(p)
DA3(n)
DB0(p)
DB0(n)
AUX_SEL
GND
D
DC1(n)
DC1(p)
DB1(p)
DB1(n)
E
DC2(n)
DC2(p)
DB2(p)
DB2(n)
F
DC3(n)
DC3(p)
DB3(p)
DB3(n)
GND
GND
G
H
AUXC(n)
AUXC(p)
HPDB
GND
DDCCLK_B
AUXB(p)
J
HPDC
HPDA
DDCCLK_C
VDD
DDCDAT_B
AUXB(n)
GND
DDCCLK_A
AUXA(p)
DDCDAT_C DDCDAT_A
AUXA(n)
Figure 6-1. 50-Pin µBGA ZXH Package (Top View)
4
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DX_SEL
VDD
DA0(P)
DA0(N)
GND
DA1(P)
DA1(N)
GND
DA2(P)
DA2(N)
GND
DA3(P)
DA3(N)
OE
56
55
54
53
52
51
50
49
48
47
46
45
44
43
SLAS971E – MAY 2014 – REVISED DECEMBER 2020
AUX_SEL
1
42
NC
DC0(P)
2
41
DB0(P)
DC0(N)
3
40
DB0(N)
GND
4
39
GND
DC1(P)
5
38
DB1(P)
DC1(N)
6
37
DB1(N)
GND
7
36
GND
DC2(P)
8
35
DB2(P)
DC2(N)
9
34
DB2(N)
GND
10
33
GND
DC3(P)
11
32
DB3(P)
DC3(N)
12
31
DB3(N)
AUXC(P)
13
30
AUXA(P)
AUXC(N)
14
29
AUXA(N)
HD3SS215 RTQ
28
24
AUXB(P)
DDCDAT_A
23
DDCDAT_B
27
22
DDCCLK_B
DDCCLK_A
21
NC
26
20
NC
DDCDAT_C
19
VDD
25
18
DDCCLK_C
AUXB(N)
17
16
HPDA
HPDB
15
HPDC
GND
Figure 6-2. 56-Pin QFN RTQ Package (Top View)
Table 6-1. Pin Functions
PIN
NAME
NO.
DESCRIPTION(1)
I/O
ZXH
RTQ
Dx_SEL
A1
56
2 Level Control I
AUX_SEL
C2
1
3 Level Control I
DA0(p)
B4
54
DA0(n)
A4
53
DA1(p)
B5
51
DA1(n)
A5
50
DA2(p)
B6
48
DA2(n)
A6
47
I/O
I/O
I/O
High Speed Port Selection Control Pins
AUX/DDC Selection Control Pin in Conjunction with Dx_SEL Pin
Port A, Channel 0, High Speed Positive Signal
Port A, Channel 0, High Speed Negative Signal
Port A, Channel 1, High Speed Positive Signal
Port A, Channel 1, High Speed Negative Signal
Port A, Channel 2, High Speed Positive Signal
Port A, Channel 2, High Speed Negative Signal
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SLAS971E – MAY 2014 – REVISED DECEMBER 2020
Table 6-1. Pin Functions (continued)
PIN
NAME
NO.
ZXH
RTQ
DA3(p)
A8
45
DA3(n)
A9
44
DB0(p)
B8
41
DB0(n)
B9
40
DB1(p)
D8
38
DB1(n)
D9
37
DB2(p)
E8
35
DB2(n)
E9
34
DB3(p)
F8
32
DB3(n)
F9
31
DC0(p)
B2
2
DC0(n)
B1
3
DC1(p)
D2
5
DC1(n)
D1
6
DC2(p)
E2
8
DC2(n)
E1
9
DC3(p)
F2
11
DC3(n)
F1
12
AUXA(p)
H9
30
AUXA(n)
J9
29
AUXB(p)
H6
24
AUXB(n)
J6
25
AUXC(p)
H2
13
AUXC(n)
H1
14
DDCCLK_A
H8
27
DDCDAT_A
J8
28
DDCCLK_B
H5
22
DDCDAT_B
J5
23
DDCCLK_C
J3
18
DDCDAT_C
J7
26
HPDA/B/C
J2, H3, J1
16, 17, 15
I/O
OE
B7
43
I
VDD
A2, J4
19, 55
Supply
3.3 V Positive power supply voltage
B3, C8, G2,
G8 H4, H7
4, 7, 10, 33,
36, 39, 46,
49, 52
Supply
Ground
GND
NC
Thermal Pad
(1)
6
DESCRIPTION(1)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
20, 21, 42
–
–
Port A, Channel 3, High Speed Positive Signal
Port A, Channel 3, High Speed Negative Signal
Port B, Channel 0, High Speed Positive Signal
Port B, Channel 0, High Speed Negative Signal
Port B, Channel 1, High Speed Positive Signal
Port B, Channel 1, High Speed Negative Signal
Port B, Channel 2, High Speed Positive Signal
Port B, Channel 2, High Speed Negative Signal
Port B, Channel 3, High Speed Positive Signal
Port B, Channel 3, High Speed Negative Signal
Port C, Channel 0, High Speed Positive Signal
Port C, Channel 0, High Speed Negative Signal
Port C, Channel 1, High Speed Positive Signal
Port C, Channel 1, High Speed Negative Signal
Port C, Channel 2, High Speed Positive Signal
Port C, Channel 2, High Speed Negative Signal
Port C, Channel 3, High Speed Positive Signal
Port C, Channel 3, High Speed Negative Signal
Port A AUX Positive Signal
Port A AUX Negative Signal
Port B AUX Positive Signal
Port B AUX Negative Signal
Port C AUX Positive Signal
Port C AUX Negative Signal
Port A DDC Clock Signal
Port A DDC Data Signal
Port B DDC Clock Signal
Port B DDC Data Signal
Port C DDC Clock Signal
Port C DDC Data Signal
Port A/B/C Hot Plug Detect
Output Enable:
OE = VIH: Normal Operation
OE = VIL: Standby Mode
Not connected
GND
Supply Ground
Only the high speed data DAz/DBz ports incorporate 20kΩ pull down resistors that are switched in when a port is not selected and
switched out when the port is selected.
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SLAS971E – MAY 2014 – REVISED DECEMBER 2020
Pin Functions
PIN
NAME
NO.
DESCRIPTION(1)
I/O
ZXH
RTQ
Dx_SEL
A1
56
2 Level Control I
AUX_SEL
C2
1
3 Level Control I
DA0(p)
B4
54
DA0(n)
A4
53
DA1(p)
B5
51
DA1(n)
A5
50
DA2(p)
B6
48
DA2(n)
A6
47
DA3(p)
A8
45
DA3(n)
A9
44
DB0(p)
B8
41
DB0(n)
B9
40
DB1(p)
D8
38
DB1(n)
D9
37
DB2(p)
E8
35
DB2(n)
E9
34
DB3(p)
F8
32
DB3(n)
F9
31
DC0(p)
B2
2
DC0(n)
B1
3
DC1(p)
D2
5
DC1(n)
D1
6
DC2(p)
E2
8
DC2(n)
E1
9
DC3(p)
F2
11
DC3(n)
F1
12
AUXA(p)
H9
30
AUXA(n)
J9
29
AUXB(p)
H6
24
AUXB(n)
J6
25
AUXC(p)
H2
13
AUXC(n)
H1
14
DDCCLK_A
H8
27
DDCDAT_A
J8
28
DDCCLK_B
H5
22
DDCDAT_B
J5
23
DDCCLK_C
J3
18
DDCDAT_C
J7
26
HPDA/B/C
J2, H3, J1
16, 17, 15
I/O
OE
B7
43
I
VDD
A2, J4
19, 55
Supply
3.3 V Positive power supply voltage
B3, C8, G2,
G8 H4, H7
4, 7, 10, 33,
36, 39, 46,
49, 52
Supply
Ground
GND
NC
20, 21, 42
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
High Speed Port Selection Control Pins
AUX/DDC Selection Control Pin in Conjunction with Dx_SEL Pin
Port A, Channel 0, High Speed Positive Signal
Port A, Channel 0, High Speed Negative Signal
Port A, Channel 1, High Speed Positive Signal
Port A, Channel 1, High Speed Negative Signal
Port A, Channel 2, High Speed Positive Signal
Port A, Channel 2, High Speed Negative Signal
Port A, Channel 3, High Speed Positive Signal
Port A, Channel 3, High Speed Negative Signal
Port B, Channel 0, High Speed Positive Signal
Port B, Channel 0, High Speed Negative Signal
Port B, Channel 1, High Speed Positive Signal
Port B, Channel 1, High Speed Negative Signal
Port B, Channel 2, High Speed Positive Signal
Port B, Channel 2, High Speed Negative Signal
Port B, Channel 3, High Speed Positive Signal
Port B, Channel 3, High Speed Negative Signal
Port C, Channel 0, High Speed Positive Signal
Port C, Channel 0, High Speed Negative Signal
Port C, Channel 1, High Speed Positive Signal
Port C, Channel 1, High Speed Negative Signal
Port C, Channel 2, High Speed Positive Signal
Port C, Channel 2, High Speed Negative Signal
Port C, Channel 3, High Speed Positive Signal
Port C, Channel 3, High Speed Negative Signal
Port A AUX Positive Signal
Port A AUX Negative Signal
Port B AUX Positive Signal
Port B AUX Negative Signal
Port C AUX Positive Signal
Port C AUX Negative Signal
Port A DDC Clock Signal
Port A DDC Data Signal
Port B DDC Clock Signal
Port B DDC Data Signal
Port C DDC Clock Signal
Port C DDC Data Signal
Port A/B/C Hot Plug Detect
Output Enable:
OE = VIH: Normal Operation
OE = VIL: Standby Mode
Not connected
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SLAS971E – MAY 2014 – REVISED DECEMBER 2020
PIN
NAME
Thermal Pad
(1)
8
NO.
DESCRIPTION(1)
I/O
ZXH
RTQ
–
–
GND
Supply Ground
Only the high speed data DAz/DBz ports incorporate 20kΩ pull down resistors that are switched in when a port is not selected and
switched out when the port is selected.
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SLAS971E – MAY 2014 – REVISED DECEMBER 2020
7 Specifications
7.1 Absolute Maximum Ratings (1) (2)
over operating free-air temperature range (unless otherwise noted)
VALUE
Supply voltage
Voltage
Tstg
(1)
(2)
MIN
MAX
VDD
–0.5
4
Differential I/O
–0.5
4
AUX_SEL, Dx_SEL
–0.5
4
HPDx, DDCCLK_X, DDCDAT_X
–0.5
6
Storage temperature
–65
150
UNIT
V
V
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential voltages, are with respect to network ground pin.
7.2 ESD Ratings
V(ESD)
(1)
(2)
Electrostatic discharge
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
±1500
V
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins(2)
±1250
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VDD
Main power supply
TA
Operating free-air temperature
CAC
AC coupling capacitor
MIN
NOM
MAX
3
3.3
3.6
UNIT
V
HD3SS215
0
70
°C
HD3SS215I
–40
85
°C
200
nF
75
100
7.4 Thermal Information
THERMAL METRIC(1)
HD3SS215
RTQ (56 PIN)
ZXH (50 PIN)
UNIT
RθJA
Junction-to-ambient thermal resistance
90.5
69.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
41.9
35.1
°C/W
RθJB
Junction-to-board thermal resistance
53.9
40.4
°C/W
ψJT
Junction-to-top characterization parameter
1.8
1.6
°C/W
ψJB
Junction-to-board characterization parameter
53.4
40.2
°C/W
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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SLAS971E – MAY 2014 – REVISED DECEMBER 2020
7.5 Electrical Characteristics
Typical values for all parameters are at VDD = 3.3 V and TA = 25°C. All temperature limits are specified by design.
PARAMETER
VDD
TEST CONDITIONS
Supply voltage
VIH
Input high voltage
MIN
TYP
MAX
3
3.3
3.6
Control Pins, Signal Pins
(Dx_SEL, AUX_SEL, OE)
2
VDD
HPD and DDC
2
5.5
V
V
VDD/2
+ 300mV
V
–0.1
0.8
V
Switch I/O diff voltage
0
1.8
Vpp
Common voltage (Dx, AUXx)
Switch common mode voltage
0
3.3
V
IIH
Input high current (Dx_SEL,
AUX_SEL)
VDD = 3.6 V, VIN = VDD
1
IIM
Input mid current (AUX_SEL)
VDD = 3.6 V, VIN = VDD/2
1
IIL
Input low current (Dx_SEL,
AUX_SEL)
VDD = 3.6 V, VIN = GND
0.01
1
VDD = 3.6 V, VIN = 2 V, OE = 3.3 V
0.01
2
VDD = 3.6 V, VIN = 2 V, OE = 0 V
0.01
2
VDD = 3.6 V, VIN = 2 V, OE = 0 V;
Dx_SEL = 3.3 V
0.01
5
VDD = 3.6 V, VIN = 2 V, OE = 3.3 V;
Dx_SEL = GND
0.01
5
VIM
Input mid level voltage
AUX_SEL Pin (1)
VIL
Input low voltage
Control Pins, Signal Pins
(Dx_SEL, AUX_SEL, OE)
VI/O_Diff
Differential voltage (Dx, AUXx)
VCM
Leakage current
(Dx_SEL, AUX_SEL)
ILK
Leakage current (HPDx/DDCx)
IOFF
Device shut down current
VDD = 3.6 V, OE = GND
IDD
Supply current
VDD = 3.6 V,
Dx_SEL= VDD; AUX_SEL = GND;
Outputs Floating
VDD/2
– 300mV
UNIT
VDD/2
µA
8
2.5
3.2
mA
8
14
Ω
1.5
Ω
DA, DB, DC HIGH SPEED SIGNAL PATH
VCM = 0 V–3.3 V,
IO = –1mA
RON
ON resistance
ΔRON
On resistance match between pairs of VCM = 0 V–3. 3V,
the same channel
IO = –1 mA
RFLAT_ON
On resistance flatness (RON(MAX) –
RON(MAIN))
VCM = 0 V–3.3 V
1.3
Ω
5
8
Ω
30
40
Ω
AUXx, DDC, SIGNAL PATH
RON(AUX)
ON resistance on AUX channel
VCM = 0 V–3.3 V,
IO = –8 mA
RON(DDC)
ON resistance on DDC channel
VCM = 0.4 V, IO = -3 mA
(1)
10
This pin can be driven to the specified level or 10 kΩ. Pull up and pull downs can be used. It cannot be left floating.
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7.6 Electrical Characteristics, Device Parameters (1)
Under recommended operating conditions; RLOAD, RSC = 50 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ZXH package
RL
Dx Differential return loss
RTQ package
XTALK
Dx Differential crosstalk
OIRR
Dx Differential off-isolation
ZXH package
ZXH package
BWAUX
AUX –3-dB bandwidth
(1)
–15
3 GHz
–12
1.35 GHz
–17
3 GHz
–13
MAX UNIT
dB
–35
dB
–35
–21
dB
–16
f = 1.35 GHz
–1.2
f = 3 GHz
–1.6
f = 1.35 GHz
RTQ package
Dx Differential -3-dB bandwidth
1.35 GHz
3 GHz
RTQ package
Dx Differential insertion loss
BWDx
TYP
2.7 GHz
RTQ package
ZXH package
IL
MIN
dB
–2
f = 3 GHz
dB
–2.4
ZXH package
7
RTQ package
5
GHz
720
MHz
For Return Loss, Crosstalk, Off-Isolation, and Insertion Loss values the data was collected on a Rogers material board with minimum
length traces on the input and output of the device under test.
7.7 Switching Characteristics
Under recommended operating conditions; RLOAD, RSC = 50 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MAX
UNIT
200
ps
1
2
µs
15
50
RSC and RLOAD = 50 Ω,
See Figure 7-1
0.7
1
µs
RLOAD = 125k Ω, See Figure 7-1
0.7
1
µs
0.7
20
tPD
Switch propagation delay
RSC and RLOAD = 50 Ω,
See Figure 7-2
ton(OE_L-H)
Time from OE toggling High and valid data at the
outputs
RSC and RLOAD = 50 Ω,
VCM = 3 V - 3.3 V
toff(OE_H-L)
Time from OE toggling Low and outputs are in Zstate
tSWITCH_OVER
Time to switch between ports when DX_SEL or
AUX_SEL state is changed for Data, AUX, DDC
signals
ton
Dx_SEL/AUX_SEL-to-Switch ton (HPD)
toff
Dx_SEL/AUX_SEL-to-Switch toff (HPD)
tSK(O)
Inter-Pair output skew (CH-CH)
tSK(b-b)
Intra-Pair output skew (bit-bit)
MIN
RSC and RLOAD = 50 Ω,
See Figure 7-2
TYP
30
1
ps
5
7.8 Timing Diagrams
Dx_SEL
50%
90%
10%
VOUT
Ton
Toff
Figure 7-1. Select to Switch ton and toff
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Vcc
Rsc = 50 Ω
DAx/DBx(p)
DCx(p)
HD3SS215
RLoad = 50 Ω
Rsc = 50 Ω
DAx/DBx(n)
DCx(n)
RLoad = 50 Ω
SEL
DAx/DBx(p)
50%
50%
DAx/DBx(n)
DCx(p)
50%
50%
DCx(n)
t P1
t1
t P2
t3
t2
t4
DCx(p)
50%
DCx(n)
DCy(p)
t SK(O)
DCy(n)
tPD = Max(tp1, tp2)
tSK(O) = Difference between tPD for any
two pairs of outputs
tSK(b-b) = 0.5 X |(t4 – t3) + (t1 – t2)|
Figure 7-2. Propagation Delay and Skew
12
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8 Detailed Description
8.1 Overview
The HD3SS215 is a generic analog, differential passive switch that can work for any high speed interface
applications, as long as it is biased at a common mode voltage range of 0 V to 3.3 V and has differential
signaling with differential amplitude up to 1800 mV pp. It employs adaptive tracking that maintains the high speed
channel impedance over the entire common mode voltage range. In high-speed applications and data paths,
signal integrity is an important concern. The switch offers excellent dynamic performance such as high isolation,
crosstalk immunity, and minimal bit-bit skew. These characteristics allow the device to function seamlessly in the
system without compromising signal integrity. The 2:1/1:2, mux/de-mux device operates with ports A or B
switched to port C, or port C switched to either port A or B. This flexibility allows an application to select between
one of two Sources on ports A and B and send the output to the sink on port C. Similarly, a Source on port C can
select between one of two Sink devices on ports A and B to send the data. To comply with DisplayPort, DP++
and HDMI applications, the HD3SS215 also switches AUX, HPD, and DDC along with the high-speed differential
signals. The HPD and data signals are both switched through the Dx_SEL pin. AUX and DDC are controlled with
AUX_SEL and Dx_SEL. The Functional Modes section contains information on how to set the control pins.
With an OE control pin, the HD3SS215 is operational, with low active current, when this pin is high. When OE is
pulled lowed, the device goes into standby mode and draws very little current in order to save power
consumption in the application.
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8.2 Functional Block Diagram
VDD
DAz(p)
4
DAz(n)
4
SEL=0
4
(z = 0, 1, 2 or 3)
4
DBz(p)
4
DBz(n)
4
DCz(p)
DCz(n)
SEL=1
SEL
Dx_SEL
SEL
HPDA
SEL=0
HPDB
SEL=1
HPDC
AUX_SEL
AUXA(p)
AUXA(n)
AUXB(p)
AUXB(n)
SEL2
SEL
AUXx(P) or DDCCLK_x
AUXx(n) or DDCDAT_ x
AUXC(p)
AUXC(n)
DDCCLK_C
DDCDAT_C
DDCCLK_A
DDCDAT_A
DDCCLK_B
DDCDAT_B
OE
HD3SS215
GND
The high speed data ports incorporate 20kΩ pull down resistors that are switched in when a port is not selected and switched out when
the port is selected.
Figure 8-1. Functional Block Diagram
14
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8.3 Feature Description
8.3.1 High Speed Switching
The HD3SS215 supports switching of 6 Gbps data rates. The wide common mode of the device enables it to
support TMDS signal levels and DisplayPort signals. The high speed muxing is designed with a wide –3dB
differential bandwidth of 7 GHz and industry leading dynamic characteristics. All of these attributes help maintain
signal integrity in the application. Each high speed port incorporates 20kΩ pull down resistors that are switched
in when the port is not selected and switched out when the port is selected.
8.3.2 HPD, AUX, and DDC Switching
HPD, AUX and DDC switching is supported through the HD3SS215. This enables the device to work in multiple
application scenarios within multiple electrical standards. The AUXA/B and DDCA/B lines can both be switched
to the AUXC port. This feature supports DP++ or AUX only adapters. For HDMI applications, the DDC channels
are switched to the DDC_C port only and the AUX channel can remain active or the end user can make it float.
8.3.3 Output Enable and Power Savings
The HD3SS215 has two power modes, active/normal operating mode, and standby mode. During standby mode,
the device consumes very little current to save the maximum power. To enter standby mode, the OE control pin
is pulled low and must remain low. For active/normal operation, the OE control pin should be pulled high to VDD
through a resistor.
8.4 Device Functional Modes
8.4.1 Switch Control Modes
Refer to the Section 8.2.
The HD3SS215 behaves as a two to one or one to two differential switch using high bandwidth pass gates. The
input ports are selected using the AUX_SEL pin and Dx_SEL pin which are shown in Table 8-1.
Table 8-1. Switch Control Logic (1) (2) (3)
CONTROL
LINES(4)
SWITCHED I/O PINS
AUX_SEL
Dx_SEL
DCz(p) Pin
z = 0, 1, 2 or 3
L
L
DAz(p)
DAz(n)
HPDA
To/From
AUXC
Z
L
H
DBz(p)
DBz(n)
HPDB
Z
H
L
DAz(p)
DAz(n)
HPDA
H
H
DBz(p)
DBz(n)
M(4)
L
DAz(p)
M(4)
H
DBz(p)
(1)
(2)
(3)
(4)
DCz(n) Pin
z = 0, 1, 2 or 3
HPDC Pin
AUXA
AUXB
AUXC
DDCA
DDCB
DDCC
To/From
AUXA
Z
Z
Z
To/From
AUXC
To/From
AUXB
Z
Z
Z
Z
Z
To/From
DDCA
To/From
AUXC
Z
Z
HPDB
Z
Z
To/From
DDCB
Z
To/From
AUXC
Z
DAz(n)
HPDA
To/From
AUXC
Z
To/From
AUXA
To/From
DDCC
Z
To/From
DDCA
DBz(n)
HPDB
Z
To/From
AUXC
To/From
AUXB
Z
To/From
DDCC
To/From
DDCB
Z = High Impedance
OE pin - For normal operation, drive OE high. Driving the OE pin low will disable the switch.
The ports which are not selected by the control lines will be in high impedance status.
For HDMI application, keep the AUX_SEL at middle level voltage. The AUX channel is still active, and the end user can make the lines
float.
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9 Applications and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The HD3SS215 can be used in a variety of applications. This section shows the typical applications for
DisplayPort , DP++, and HDMI. The example diagrams illustrate using the HD3SS215 in a two source to one
sink application and a one source to two sinks application. All schematics are using the ZXH pin-out.
9.2 Typical Applications
9.2.1 DisplayPort and Dual Mode Adapter with Two Sources
The application schematic below shows the HD3SS215 in the 2:1 configuration for DisplayPort switching. The
HD3SS215 receives inputs from DP Source A and DP Source B. The control pins of the device can be set to
select Source A/B inputs and transfer them to port C through the Dx_SEL control pin. The schematic also shows
the CONFIG1 and AUX_SEL settings to configure the HD3SS215 to work with DP++ Type 2 and Type1
adapters. For this specific schematic, the AC capacitors needed on the MainLink signal lines are shown on the
Sink side of the HD3SS215. This is done to decrease the BOM. If desired the AC capacitors maybe placed in the
signal path on the Source A/B side of HD3SS215. Additional diagrams are provided to show the configuration of
the AUX channel for 2:1 and 1:2 DisplayPort only applications.
Figure 9-1. HD3SS215 Application Diagram for DisplayPort or Dual Mode Adapter Configuration
16
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Figure 9-2. HD3SS215 AUX Channel in 2:1 DisplayPort Application
Figure 9-3. HD3SS215 AUX Channel in 1:2 DisplayPort Application
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9.2.1.1 Design Requirements
Table 9-1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
VDD
3.3 V
Decoupling Capacitors
0.1 µF
AC Capacitors
75 nF to 200 nF (100 nF shown)
AUX Pull-Up/Pull-Down Resistors
10 kΩ to105 kΩ (100 kΩ shown)
Pull-Up/Pull-Down Resistors for Control Pins
10 kΩ
CONFIG1/CONFIG2 Pull-Down Resistors
1 MΩ and 5 MΩ
9.2.1.2 Detailed Design Procedure
The HD3SS215 is designed to operate with a 3.3 V power supply. Levels above those listed in the Absolute
Ratings table should not be used. If using a higher voltage system power supply, a voltage regulator can be used
to step down to 3.3 V. Decoupling capacitors may be used to reduce noise and improve power supply integrity.
AC capacitors must be placed on the MainLink lines. Additionally, AC capacitors are placed on the AUXC lines.
After the blocking capacitors, the AUXCp line must be pulled down weakly through a resistor to ground, and the
AUXCn line must be pulled up weakly through a resistor to VDD. The voltage level of the control pins, AUX_SEL
and Dx_SEL should be set according to the application and muxing desired. For a DisplayPort connector, the
CONFIG1 and CONFIG2 pins should be pulled to ground through resistors. For Dual Mode adapter
implementation, the CONFIG1 line may be used to perform cable adapter detection. The CONFIG2 line can be
configured for an HDMI adaptor or left as a no connect for a DVI adapter. The CONFIG2 pin on the connector
should be pulled up or left floating accordingly for Dual Mode adapter configuration.
18
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9.2.2 HDMI Application with Two Sinks
The HD3SS215 can be placed in applications needing to switch between two sinks. In this example, the HDMI
source selects between Sink A or Sink B in the 1:2 configuration.
Figure 9-4. Application Diagram for a 1:2 Configuration with HDMI Source and Connectors
9.2.2.1 Design Requirements
Table 9-2. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
VDD
3.3 V
Decoupling Capacitors
0.1 µF
DDC Pull-Up Resistors
1.5 kΩ to 2 kΩ to 5 V (2 kΩ shown)
Pull-Up/Pull-Down Resistors for Control Pins
10 kΩ
HPD Pull-Down Resistor
100 kΩ
9.2.2.2 Detailed Design Procedure
The HD3SS215 is designed to operate with a 3.3 V power supply. Levels above those listed in the Absolute
Ratings table should not be used. If using a higher voltage system power supply, a voltage regulator can be used
to step down to 3.3 V. Decoupling capacitors may be used to reduce noise and improve power supply integrity.
Pull-up resistors to 5 V must be placed on the source side DDC clock and data lines according to the HDMI2.0
Standard. A weak pull down resistor should be placed on the source side HPD line. This is to ensure the source
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can differentiate between when HPD is disconnected or at a high voltage level. The AUX_SEL and Dx_SEL
control pins should be set according to the application and desired muxing.
9.2.3
9.2.4 HDMI 2:1 Sink Application Using the RTQ Package
The HD3SS215 can be placed in applications needing to switch between two HDMI connectors and one Generic
HDMI sink.
3.3V
0.1uF
0.1uF
GND2
GND3
GND4
Utility
DDC_GND
D0p
D0n
DA0p
DA0n
D1p
D1n
DA1p
DA1n
D2p
D2n
DA2p
DA2n
D3p
D3n
DA3p
DA3n
DC0p
DC0n
D0p
D0n
AUXAp
AUXAn
DC1p
DC1n
D1p
D1n
DDCCLK_A
DDCDAT_A
DC2p
DC2n
D2p
D2n
HPDA
DC3p
DC3n
D3p
D3n
DDC_SCL
DDC_SDA
HPD
HDMI Connector
GND2
GND3
GND4
Utility
DDC_GND
47kΩ
DB0p
DB0n
D1p
D1n
DB1p
DB1n
D2p
D2n
DB2p
DB2n
D3p
D3n
DB3p
DB3n
HPDB
HDMI Connector
100kΩ
GND4
Utility
DDC_GND
HPDC
HDMI SINK Device
5V
3.3V
10kΩ
OE
AUX_SEL
Dx_SEL
10kΩ
DDCCLK_B
DDCDAT_B
HPD
GND3
HPD
DDCCLK_C
DDCDAT_C
AUXBp
AUXBn
DDC_SCL
DDC_SDA
GND1
GND2
DDC_SCL
DDC_SDA
AUXCp
AUXCn
D0p
D0n
Sink
47kΩ
5V
100kΩ
Source B
GND1
5V
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND1
VDD1
VDD2
5V
Source A
10kΩ
HD3SS215
AUX_SEL and Dx_SEL configured for A to C
Figure 9-5. HDMI 2:1 Sink Application Using the RTQ Package
Note
According to the HDMI specification the DDC 2-kΩ pullup resistors can be replaced by
47-kΩ pullups. Figure 9-5 schematic and Figure 10-3 PCB layout example shows 47-kΩ pullup
resistors.
Power Supply Recommendations
The HD3SS215 is designed to operate with a 3.3-V power supply. Levels above those listed in the Absolute
Ratings table should not be used. If using a higher voltage system power supply, a voltage regulator can be used
to step down to 3.3 V. Decoupling capacitors must be used to reduce power supply noise.
20
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10 Layout
10.1 Layout Guidelines
•
•
•
•
•
•
•
•
•
The ESD and EMI protection devices (if used) should be placed as close as possible to the connector.
Place voltage regulators as far away as possible from the high-speed differential pairs.
It is recommended that small decoupling capacitors for the HD3SS215 power rail be placed close to the
device.
The high-speed differential signal traces should be routed on the top layer to avoid the use of vias and allow
clean interconnects to the mux.
The high speed differential signal traces should be routed parallel to each other as much as possible. It is
recommended the traces be symmetrical.
In order to control impedance for transmission lines, a solid ground plane should be placed next to the highspeed signal layer. This also provides an excellent low-inductance path for the return current flow.
The power plane should be placed next to the ground plane to create additional high-frequency bypass
capacitance.
Adding test points will cause impedance discontinuity and will therefore negatively impact signal
performance. If test points are used, they should be placed in series and symmetrically. They must not be
placed in a manner that causes stubs on the differential pair.
Avoid 90 degree turns in traces. The use of bends in differential traces should be kept to a minimum. When
bends are used, the number of left and right bends should be as equal as possible and the angle of the bend
should be ≥135 degrees. This will minimize any length mismatch caused by the bends and therefore
minimize the impact bends have on EMI.
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10.2 Layout Example
An example layout for the HD3SS215 shows the device implemented on a 4-layer board. The layout figures
follow the DisplayPort application schematic above. The top layer layout view shows the signal routing for two
sources and one sink. The bottom layer layout view shows the remaining signal routing and a copper pour
implemented for the decoupling capacitors.
Figure 10-1. Top Layer Layout View
Figure 10-2. Bottom Layer Layout View
22
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Figure 10-3. RTQ Layout for 2:1 HDMI Sink Application
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11 Device and Documentation Support
11.1 Community Resources
11.2 Trademarks
All trademarks are the property of their respective owners.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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26-Mar-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
HD3SS215IRTQR
ACTIVE
QFN
RTQ
56
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
HD3SS215I
HD3SS215IRTQT
ACTIVE
QFN
RTQ
56
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
HD3SS215I
HD3SS215IZXHR
ACTIVE
NFBGA
ZXH
50
2500
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 85
HD3SS215I
HD3SS215IZXHT
ACTIVE
NFBGA
ZXH
50
250
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 85
HD3SS215I
HD3SS215RTQR
ACTIVE
QFN
RTQ
56
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
0 to 70
HD3SS215
HD3SS215RTQT
ACTIVE
QFN
RTQ
56
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
0 to 70
HD3SS215
HD3SS215ZXHR
ACTIVE
NFBGA
ZXH
50
2500
RoHS & Green
SNAGCU
Level-3-260C-168 HR
0 to 70
HD3SS215
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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