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HD3SS460
SLLSEM7D – JANUARY 2015 – REVISED JANUARY 2017
HD3SS460 4 x 6 Channels USB Type-C™ Alternate Mode MUX
1 Features
•
1
•
•
•
•
•
•
•
•
•
3 Description
TM
Provides MUX Solution for USB Type-C
Ecosystem Including Alternate Mode (AM)
Provides Wide Channel Selection Choices
Including USBSS and 2 Ch AM, 4 Ch AM
Compatible with 5 Gbps USB3.1 Gen 1 and AM
Including 5.4 Gbps DisplayPort 1.2a
Compatible for Source/Host and Sink/Device
Applications
Provides Cross-point MUX for Low Speed SBU
Pins
Bidirectional "Mux/De-Mux" Differential Switch
Supports Common Mode Voltage 0-2 V
Low Power with 1-μA Shutdown and 0.6 mA
Active
Single Supply Voltage VCC of 3.3 V ±10%
Industrial Temperature Range of –40 to 85°C
2 Applications
•
•
•
•
Flippable USB Type-CTM Ecosystem
Tablets, Laptops, Monitors, Phones
USB Host and Devices
Docking Stations
The HD3SS460 is a high-speed bi-directional passive
switch in mux or demux configurations. Based on
control pin POL the device provides switching to
accommodate connector flipping. The device also
provides muxing between 2Ch Data / 2Ch Video and
all 4Ch Video based on control pin AMSEL.
The device also provides cross points MUX for low
speed pins as needed in flippable connector
implementation.
The HD3SS460 is a generic analog differential
passive switch that can work for any high speed
interface applications as long as it is biased at a
common mode voltage range of 0-2V and has
differential signaling with differential amplitude up to
1800mVpp. It employs an adaptive tracking that
ensures the channel remains unchanged for entire
common mode voltage range.
Excellent dynamic characteristics of the device allow
high speed switching with minimum attenuation to the
signal eye diagram with very little added jitter. It
consumes
0.1 µF
TX2+
TX2>
0.1 µF
Type C
Connector
RX1+
RX1>
No AC
Coupling Caps
DP Source
ML0+
ML0>
RX2+
RX2>
Copyright © 2016, Texas Instruments Incorporated
Figure 3. Block Diagram for a Type C Interface Using DP as Alternate Mode – Source/Host
14
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SLLSEM7D – JANUARY 2015 – REVISED JANUARY 2017
USB SS and DP as Alternate Mode (continued)
USB3 Upstream Port
No AC Coupling Caps
SSRX
Type C
Connector
0.1 µF
0.1 µF
SSTX
RX1+
RX1>
ML0+
ML0>
TX1+
TX1>
ML1+
ML1>
HD3SS460
TX2+
TX2>
DP Sink
ML2+
ML2>
RX2+
RX2>
ML3+
ML3>
Copyright © 2016, Texas Instruments Incorporated
Figure 4. Diagram for a Type C Interface Using DP as Alternate Mode – Sink/Device/Dock
Figure 5 and Figure 6 depict the AC coupling capacitor recommendations in case the upstream or downstream
port connected internally to the HD3SS460 presents Vcm greater than 2 V.
Vcm > 2.0 V
500 nF
100 lQ
500 nF
100 lQ
100 lQ
SSTX
DP Source
RX1+
RX1>
0.1 µF
ML1+
ML1>
HD3SS460
ML2+
ML2>
ML3+
ML3>
TX1+
TX1>
0.1 µF
TX2+
TX2>
0.1 µF
RX2+
RX2>
0.1 µF
Type C
Connector
ML0+
ML0>
100 lQ
SSRX
Copyright © 2016, Texas Instruments Incorporated
Figure 5. HD3SS460 USB Host (DP Source with SS USB Vcm)
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SLLSEM7D – JANUARY 2015 – REVISED JANUARY 2017
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USB SS and DP as Alternate Mode (continued)
Vcm > 2.0 V
500 nF
100 lQ
100 lQ
RX1+
RX1>
Type C
Connector
0.1 µF
100 lQ
SSTX
SSRX
100 lQ
ML0+
ML0>
TX1+
TX1>
TX2+
TX2>
0.1 µF
500 nF
ML1+
ML1>
HD3SS460
DP Sink
ML2+
ML2>
RX2+
RX2>
ML3+
ML3>
Copyright © 2016, Texas Instruments Incorporated
Figure 6. HD3SS460 USB Upstream (DP Sink Implementation Example)
9.2.1 Design Requirements
DESIGN PARAMETERS
16
EXAMPLE VALUES
VCC
3.3 V
Decoupling capacitors
0.1 µF
AC Capacitors
75-200nF (100nF shown) USBSS TX p and n lines require AC capacotprs. Alternate
mode signals may or may not require AC capacitors
Control pins
Controls pins can be dynamically controlled or pin-strapped. The POL signal is
controlled by CC logic in the Type-C ecosystem.
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SLLSEM7D – JANUARY 2015 – REVISED JANUARY 2017
9.2.2 Detailed Design Procedure
The reference schematics shown in this document are based upon the pin assignment defined in the Alternate
mode over Type C specification as shown in Figure 7 below.
Figure 7. Pin Assignment – Alternate Mode Over Type C
Table 2 represents the example pin mapping to HD3SS460 for the DP Source pin assignments C, D, E and F,
DP Sink pin assignments C and D.
Table 2. SOURCE Pin Assignment Option C and E (AMSEL = H, EN = H)
RECEPTACLE PIN
NUMBER
460 PIN MAPPING TO DP SOURCE (GPU)
460 PIN MAPPING TO
TYPE C CONNECTOR
POL = L
POL = H
A11/10
CRX2
LnA(ML0)
LnD(ML3)
A2/3
CTX1
LnC(ML2)
LnB(ML1)
B11/10
CRX1
LnD(ML3)
LnA(ML0)
B2/3
CTX2
LnB(ML1)
LnC(ML2)
A8
CSBU1
SBU1(AUXP)
SBU2(AUXN)
B8
CSBU2
SBU2(AUXN)
SBU1(AUXP)
HD3SS460
A11 / A10
Video Source (GPU)
CRX2
LnA/LnD
ML0/ML3
A2 / A3
CTX1
LnC/LnB
ML2/ML1
B11 / B10
CRX1
LnD/LnA
ML3/ML0
B2 / B3
CTX2
LnB/LnC
ML1/ML2
A8 / B8
CSBU1/2
0.1 PF
0.1 PF
AUXN/N
AUXP/P
SSRX
SSTX
Type-C
Connector
SBU1/2
SBU2/1
Red text indicates POL = H
SSRX
SSTX
USB SS lines are internally
unconnected under this mode
xHCI Host
Copyright © 2016, Texas Instruments Incorporated
Figure 8. SOURCE Pin Assignment Option C and E (AMSEL = H, EN = H)
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Table 3. SOURCE Pin Assignment Option D and F (AMSEL = L, EN = H)
RECEPTACLE PIN
NUMBER
460 PIN MAPPING TO DP SOURCE (GPU)
460 PIN MAPPING TO
TYPE C CONNECTOR
POL = L
POL = H
A11/10
CRX2
LnA(ML0)
SSRX
A2/3
CTX1
SSTX
LnB(ML1)
B11/10
CRX1
SSRX
LnA(ML0)
B2/3
CTX2
LnB(ML1)
SSTX
A8
CSBU1
SBU1(AUXP)
SBU2(AUXN)
B8
CSBU2
SBU2(AUXN)
SBU1(AUXP)
Space
HD3SS460
A11 / A10
HD3SS460
Video Source (GPU)
CRX2
LnA
ML1
A11 / A10
A2 / A3
CTX1
LnC
ML3
B11 / B10
CRX1
LnD
B2 / B3
CTX2
LnB
A8 / B8
CSBU1/2
SBU1
SBU2
Video Source (GPU)
CRX2
LnA
ML0
A2 / A3
CTX1
LnC
ML2
ML2
B11 / B10
CRX1
LnD
ML3
ML0
B2 / B3
CTX2
LnB
ML1
AUXN
AUXP
A8 / B8
CSBU1/2
SBU2
SBU1
0.1 PF
0.1 PF
0.1 PF
0.1 PF
SSRX
Type-C
Connector
xHCI Host
LnC and LnD lines are internally
unconnected under this mode
SSTX
SSRX
SSTX
SSRX
LnC and LnD lines are internally
unconnected under this mode
SSTX
SSRX
SSTX
Type-C
Connector
AUXN
AUXP
xHCI Host
Copyright © 2016, Texas Instruments Incorporated
Copyright © 2016, Texas Instruments Incorporated
Figure 9. SOURCE Pin Assignment Option D and F
(AMSEL = L, EN = H, POL = L)
Figure 10. SOURCE Pin Assignment Option D and
F (AMSEL = L, EN = H, POL = H)
Table 4. SINK Pin Assignment Option C (AMSEL = H, EN = H)
RECEPTACLE PIN
NUMBER
460 PIN MAPPING TO DP SOURCE (GPU)
460 PIN MAPPING TO
TYPE C CONNECTOR
POL = L
POL = H
A11/10
CRX2
LnA(ML1)
LnD(ML2)
A2/3
CTX1
LnC(ML3)
LnB(ML0)
B11/10
CRX1
LnD(ML2)
LnA(ML1)
B2/3
CTX2
LnB(ML0)
LnC(ML3)
A8
CSBU1
SBU1(AUXN)
SBU2(AUXP)
B8
CSBU2
SBU2(AUXP)
SBU1(AUXN)
HD3SS460
A11 / A10
Video Sink
CRX2
LnA/LnD
ML1/ML2
A2 / A3
CTX1
LnC/LnB
ML3/ML0
B11 / B10
CRX1
LnD/LnA
ML2/ML1
B2 / B3
CTX2
LnB/LnC
ML0/ML3
A8 / B8
CSBU1/2
0.1 PF
0.1 PF
AUXN/P
AUXP/N
SSRX
SSTX
Type-C
Connector
SBU1/2
SBU2/1
Red text indicates POL = H
SSRX
SSTX
USB SS lines are internally
unconnected under this mode
SS HUB/Device
Copyright © 2016, Texas Instruments Incorporated
Figure 11. SINK Pin Assignment Option C (AMSEL = H, EN = H)
18
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Table 5. SINK Pin Assignment Option D (AMSEL = L, EN = H)
RECEPTACLE PIN
NUMBER
460 PIN MAPPING TO
TYPE C CONNECTOR
460 PIN MAPPING TO DP SOURCE (GPU)
POL = L
POL = H
A11/10
CRX2
LnA(ML1)
SSRX
A2/3
CTX1
SSTX
LnB(ML0)
B11/10
CRX1
SSRX
LnA(ML1)
B2/3
CTX2
LnB(ML0)
SSTX
A8
CSBU1
SBU1(AUXN)
SBU2(AUXP)
B8
CSBU2
SBU2(AUXP)
SBU1(AUXN)
Space
HD3SS460
A11 / A10
HD3SS460
Video Source (GPU)
CRX2
LnA
ML1
A11 / A10
A2 / A3
CTX1
LnC
ML3
B11 / B10
CRX1
LnD
B2 / B3
CTX2
LnB
A8 / B8
CSBU1/2
SBU1
SBU2
LnA
ML0
A2 / A3
CTX1
LnC
ML2
ML2
B11 / B10
CRX1
LnD
ML3
ML0
B2 / B3
CTX2
LnB
ML1
AUXN
AUXP
A8 / B8
CSBU1/2
SBU2
SBU1
0.1 PF
0.1 PF
0.1 PF
0.1 PF
xHCI Host
SSTX
SSRX
SSTX
SSRX
LnC and LnD lines are internally
unconnected under this mode
SSRX
Type-C
Connector
AUXN
AUXP
SSTX
SSRX
SSTX
Type-C
Connector
Video Source (GPU)
CRX2
LnC and LnD lines are internally
unconnected under this mode
xHCI Host
Copyright © 2016, Texas Instruments Incorporated
Figure 12. SINK Pin Assignment Option D
(AMSEL = L, EN = H, POL=L)
Copyright © 2016, Texas Instruments Incorporated
Figure 13. SINK Pin Assignment Option D
(AMSEL = L, EN = H, POL=H)
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Schematic diagrams Figure 14, Figure 15, and Figure 16 show the DP Source/USB Host implementation; and,
Figure 17, Figure 18, and Figure 19 show the DP Sink/USB Device/HUSB Hub/Dock implementation,
respectively.
VBUS
TypeC Connector and Source Pin Mapping
J2
GND
A1
B12
GND
VBUS1
VBUS2
VBUS3
VBUS4
A4
A9
B4
B9
CC1
CC2
A5
B5
CC1
CC2
SBU1
SBU2
A8
B8
CSBU1
CSBU2
DN1
DP1
A7
A6
USB2_N0
USB2_P0
DP2
DN2
B6
B7
C8
10uF
ML2P
ML1P
SSTXP1
SSTXP2
A2
B11
SSRXP1
SSRXP2
ML3P
ML0P
ML2N
ML1N
SSTXN1
SSTXN2
A3
B10
SSRXN1
SSRXN1
ML3N
ML0N
VBUS
A4
B9
VBUS
CC1
A5
B8
SBU2
DP1
A6
B7
DN2
SSTXP1
SSTXN1
A2
A3
CTX1P
CTX1N
DN1
A7
B6
DP2
SSRXP2
SSRXN2
A11
A10
CRX2P
CRX2N
SBU1
A8
B5
CC2
SSTXP2
SSTXN2
B2
B3
CTX2P
CTX2N
VBUS
A9
B4
VBUS
B11
B10
CRX1P
CRX1N
AUXP
AUXN
AUXN
AUXP
ML0N
ML3N
SSRXN2
SSRXN1
A10
B3
SSTXN2
SSTXN1
ML1N
ML2N
ML0P
ML3P
SSRXP2
SSRXP1
A11
B2
SSTXP2
SSTXP1
ML1P
ML2P
GND
A12
B1
GND
g6
g5
g4
g3
g2
g1
SSRXP1
Shield6 SSRXN1
Shield5
Shield4 GND0
Shield3 GND1
Shield2 GND2
Shield1 GND3
Note: It is
recommended to
add isolation
circuit if
voltage is to be
present on any
of the I/Os
while the
HD3SS460
device is off.
A1
A12
B1
B12
USB_TypeC_Receptacle_
CSBU1
CSBU2
R156
2MΩ
R158
2MΩ
pull-down
resistor
between 1MΩ-2MΩ
is recommended
on SBU1 and
SBU2.
Copyright © 2016, Texas Instruments Incorporated
Figure 14. Schematic Implementations for DP Source/ USB Host (1 of 3)
20
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SLLSEM7D – JANUARY 2015 – REVISED JANUARY 2017
ESD Components
Place in pass through manner with no stub
U8
1
2
3
4
5
CTX1N
CTX1P
CRX1N
CRX1P
NC10
D1
NC9
D1GND GND
D2+ NC7
NC6
D2TPD4E05U06
10
9
8
7
6
U9
1
2
3
4
5
CTX2P
CTX2N
CRX2P
CRX2N
10
NC10
D1
NC9 9
D18
GND GND 7
D2+ NC7 6
NC6
D2TPD4E05U06
U12
1
2
3
4
5
6
7
NC1
NC2
NC3
NC4
GND
NC5
NC6
D1+
D1D2+
D2GND
D3+
D3-
CC1
CC2
USB2_P0
USB2_N0
14
13
12
11
10
9
8
CSBU1
CSBU2
TPD6E05U06
Copyright © 2016, Texas Instruments Incorporated
Figure 15. Schematic Implementations for DP Source/ USB Host (2 of 3)
3P3V
3P3V
C3
0.1uF
R188
10K
R6
10K
VCC
U2
Connect to
Type C SSTX/RX
pins
AC Coupling caps to
accomodate higher Vcm
on some USB devices
CRX1N
CRX1P
CTX1N
CTX1P
C51
C49
0.1uF
CRX1P
CRX1N
0.1uF C48
0.1uF
CTX1P
CTX1N
CTX2N
CTX2P
C50 0.1uF
CRX2N
CRX2P
POL
AMSEL
EN
SSTXN
SSTXP
SSRXN
SSRXP
LNAN
LNAP
CTX2P
CTX2N
LNBN
LNBP
CRX2P
CRX2N
LNCN
LNCP
CSBU1
CSBU2
CSBU1
CSBU2
PAD
LNDN
LNDP
Connect to
Type C SBU
pins
SBU1
SBU2
Connect to control
logic to select
swtich
configuration(i.e. CC
control logic)
POL
AMSEL
EN
USB3_TX0N
USB3_TX0P
Connect to USB
Host/Hub SS TX/RX
pairs
USB3_RX0N
USB3_RX0P
ML0P
ML0N
ML1P
ML1N
ML0..ML3:
Connect to
DP Source
MainLink
lanes
ML2P
ML2N
ML3P
ML3N
SBU1
SBU2
Connect to
DP Source
AUX
Channels
HD3SS460
NOTE: ALL DIFF PAIRS ARE
ROUTED 85 TO 90 OHMS
DIFFERENTIAL AND 50 OHMS
COMMON MODE. ALL OTHER
TRACES ARE 50 OHM.
Copyright © 2017, Texas Instruments Incorporated
Figure 16. Schematic Implementations for DP Source/ USB Host (3 of 3)
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VBUS
TypeC Connector and Pin Mapping
J2
GND
A1
B12
GND
ML3P
ML0P
SSTXP1
SSTXP2
A2
B11
SSRXP1
SSRXP2
ML2P
ML1P
ML3N
ML0N
SSTXN1
SSTXN2
A3
B10
SSRXN1
SSRXN1
ML2N
ML1N
A4
B9
VBUS
AUXN
AUXP
A5
B8
SBU2
DP1
A6
B7
DN1
DN1
A7
B6
DP1
SBU1
A8
B5
CC2
VBUS
A9
B4
VBUS
SBU1
SBU2
DN1
DP1
AUXP
AUXN
SSRXP2
SSRXN2
SSTXP2
SSTXN2
SSRXN2
SSRXN1
A10
B3
SSTXN2
SSTXN1
ML0N
ML3N
ML1P
ML2P
SSRXP2
SSRXP1
A11
B2
SSTXP2
SSTXP1
ML0P
ML3P
A12
B1
GND
SSRXP1
Shield6 SSRXN1
Shield5
Shield4
GND0
Shield3
GND1
Shield2
GND2
Shield1
GND3
g6
g5
g4
g3
g2
g1
C8
10uF
A5
B5
CC1
CC2
A8
B8
CSBU1
CSBU2
A7
A6
USB2_N0
USB2_P0
B6
B7
DP2
DN2
SSTXP1
SSTXN1
ML1N
ML2N
GND
CC1
CC2
VBUS
CC1
A4
A9
B4
B9
VBUS1
VBUS2
VBUS3
VBUS4
A2
A3
CTX1P
CTX1N
A11
A10
CRX2P
CRX2N
B2
B3
CTX2P
CTX2N
B11
B10
CRX1P
CRX1N
CC1
CC2
pg3
pg3
Note: It is
recommended to
add isolation
circuit if
voltage is to be
present on any
of the I/Os
while the
HD3SS460
device is off.
A1
A12
B1
B12
USB_TypeC_Receptacle_
CSBU1
CSBU2
R156
2M
R158
2M
pull-down
resistor
between 1M-2M
is
recommended
on SBU1 and
SBU2.
Copyright © 2016, Texas Instruments Incorporated
Figure 17. Schematic Implementations for DP Sink/ USB Device/HUB/Dock (1 of 3)
ESD Components
Place in pass through manner with no stub
U8
1
2
3
4
5
CTX1N
CTX1P
CRX1N
CRX1P
D1+ NC10
D1NC9
GND GND
D2+
NC7
D2NC6
10
9
8
7
6
TPD4E05U06
U9
1
2
3
4
5
CTX2P
CTX2N
CRX2P
CRX2N
D1+ NC10
D1NC9
GND GND
D2+
NC7
D2NC6
10
9
8
7
6
TPD4E05U06
U12
1
2
3
4
5
6
7
NC1
NC2
NC3
NC4
GND
NC5
NC6
D1+
D1D2+
D2GND
D3+
D3-
14
13
12
11
10
9
8
CC1
CC2
USB2_P0
USB2_N0
CSBU1
CSBU2
TPD6E05U06
Copyright © 2016, Texas Instruments Incorporated
Figure 18. Schematic Implementations for DP Sink/ USB Device/HUB/Dock (2 of 3)
22
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Copyright © 2017, Texas Instruments Incorporated
Figure 19. Schematic Implementations for DP Sink/ USB Device/HUB/Dock (3 of 3)
10 Power Supply Recommendations
There is no power supply sequence required for HD3SS460. However it is recommended that EN is asserted low
after device supply VCC is stable and within specification. It is also recommended that ample decoupling
capacitors are placed at the device VCC near the pin.
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11 Layout
11.1 Layout Guidelines
High performance layout practices are paramount for board layout for high speed signals to ensure good signal
integrity. Even minor imperfection can cause impedance mismatch resulting reflection. Special care is warranted
for traces, connections to device, and connectors.
11.1.1 Critical Routing
The high speed differential signals must be routed with great care to minimize signal quality degradation between
the connector and the source or sink of the high speed signals by following the guidelines provided in this
document. Depending on the configuration schemes, the speed of each differential pair can reach a maximum
speed of 5.4 Gbps. These signals are to be routed first before other signals with highest priority.
• Each differential pair should be routed together with controlled differential impedance of 85 to 90-Ω and 50-Ω
common mode impedance. Keep away from other high speed signals. The number of vias should be kept to
minimum. Each pair should be separated from adjacent pairs by at least 3 times the signal trace width. Route
all differential pairs on the same group of layers (Outer layers or inner layers) if not on the same layer. No 90
degree turns on any of the differential pairs. If bends are used on high speed differential pairs, the angle of
the bend should be greater than 135 degrees.
• Length matching:
– Keep high speed differential pairs lengths within 5 mil of each other to keep the intra-pair skew minimum.
– The inter-pair matching of the differential pairs is not as critical as intra-pair matching. The SSTX and
SSRX pairs do not have to match while they need to be routed as short as possible.
• Keep high speed differential pair traces adjacent to ground plane.
• Do not route differential pairs over any plane split
• ESD components on the high speed differential lanes should be placed nearest to the connector in a pass
through manner without stubs on the differential path. In order to control impedance for transmission lines, a
solid ground plane should be placed next to the high- speed signal layer. This also provides an excellent lowinductance path for the return current flow.
– Placement recommendation would be: Connector – ESD Components --- HD3SS460
• For ease of routing, the P and N connection of the USB3.1 differential pairs to the HD3SS460 pins can be
swapped as long as the corresponding pairs are swapped on the other end of the switch The example is
shown in the reference EVM schematics section of this document. The P/N can be swapped on USB 3.1
connection of the switch for ease of routing purposes.
11.1.2 General Routing/Placement Rules
• Route all high-speed signals first on un-routed PCB: SSTXP/N, SSRXT/N, LNAP/N, LNB P/N, LNC P/N, LND
P/N, CTX*P/N. The stub on USB2 D+ and D- pairs should not exceed 3.5mm.
• Follow 20H rule (H is the distance to reference plane) for separation of the high-speed trace from the edge of
the plane
• Minimize parallelism of high speed clocks and other periodic signal traces to high speed lines
• All differential pairs should be routed on the top or bottom layer (microstrip traces) if possible or on the same
group of layers. Vias should only be used in the breakout region of the device to route from the top to bottom
layer when necessary. Avoid using vias in the main region of the board at all cost. Use a ground reference via
next to signal via. Distance between ground reference via and signal need to be calculated to have similar
impedance as traces.
• All differential signals should not be routed over plane split. Changing signal layers is preferable to crossing
plane splits.
• Use of and proper placement of stitching caps when split plane crossing is unavoidable to account for highfrequency return current path
• Route differential traces over a continuous plane with no interruptions.
• Do not route differential traces under power connectors or other interface connectors, crystals, oscillators, or
any magnetic source.
• Route traces away from etching areas like pads, vias, and other signal traces. Try to maintain a 20 mil keepout distance where possible.
24
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SLLSEM7D – JANUARY 2015 – REVISED JANUARY 2017
Layout Guidelines (continued)
•
•
•
•
•
Decoupling capacitors should be placed next to each power terminal on the HD3SS460. Care should be
taken to minimize the stub length of the trace connecting the capacitor to the power pin.
Avoid sharing vias between multiple decoupling capacitors.
Place vias as close as possible to the decoupling capacitor solder pad.
Widen VCC/GND planes to reduce effect of static and dynamic IR drop.
The VBUS traces/planes must be wide enough to carry maximum of 2 A current.
11.2 Layout Example
Figure 20, Figure 21, and Figure 22 illustrate some guidelines for layout. Actual layout should be optimized for
various factors such as board geometry, connector type, and application.
Figure 20. USB Type C Connector to HD3SS460 Signal Routing
Figure 21. Dual SMT Mid-Mount Type C Connector Layout Example Zoom-in
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Product Folder Links: HD3SS460
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HD3SS460
SLLSEM7D – JANUARY 2015 – REVISED JANUARY 2017
www.ti.com
Layout Example (continued)
Figure 22. Dual-row SMT Mid-mount Type C with ESD Components
26
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Product Folder Links: HD3SS460
HD3SS460
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SLLSEM7D – JANUARY 2015 – REVISED JANUARY 2017
12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates — go to the product folder for your device on ti.com. In the
upper right-hand corner, click the Alert me button to register and receive a weekly digest of product information
that has changed (if any). For change details, check the revision history of any revised document.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
USB Type-C is a trademark of USB-IF, Inc..
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: HD3SS460
27
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
HD3SS460IRHRR
ACTIVE
WQFN
RHR
28
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
3SS460I
HD3SS460IRHRT
ACTIVE
WQFN
RHR
28
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
3SS460I
HD3SS460IRNHR
ACTIVE
WQFN
RNH
30
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
460IRNH
HD3SS460IRNHT
ACTIVE
WQFN
RNH
30
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
460IRNH
HD3SS460RHRR
ACTIVE
WQFN
RHR
28
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
3SS460
HD3SS460RHRT
ACTIVE
WQFN
RHR
28
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
3SS460
HD3SS460RNHR
ACTIVE
WQFN
RNH
30
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
460RNH
HD3SS460RNHT
ACTIVE
WQFN
RNH
30
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
460RNH
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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