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HD3SS6126
SLAS975A – NOVEMBER 2013 – REVISED AUGUST 2015
HD3SS6126 USB 3.0 and USB 2.0 Differential Switch 2:1/1:2 MUX/DEMUX
1 Features
3 Description
•
The HD3SS6126 device is a high-speed, passive
switch that is designed for USB applications to route
both SuperSpeed USB RX and TX and USB 2.0 DP
and DM signals from a source to two destinations or
vice versa. The device can also be used for
DisplayPort, PCI-Express™, SATA, SAS, and XAUI
applications. The HD3SS6126 device can be used in
either sink-side or source-side applications.
•
•
•
•
•
•
•
Device Information(1)
PART NUMBER
PACKAGE
HD3SS6126
WQFN (42)
BODY SIZE (NOM)
9.00 mm × 3.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Diagram
NoteBook
USB 3 Rx
USB 3 Tx
USB 2
DP / DM
HD3SS6126
•
Ideal for USB Applications
– Signal Switch for USB 3.0 (SuperSpeed USB
and USB 2.0 HS/FS/LS)
Three Bidirectional Differential Pair Channel
MUX/DEMUX Switches Also Suitable for
DisplayPort, PCIe Gen1/2/3, SATA 1.5/3/6G, SAS
1.5/3/6G and XAUI Applications
Supports Data Rates up to 10 Gbps on HighBandwidth Path (SS)
VCC Operating Range 3.3 V ± 10%
Wide –3-dB Differential BW of More Than 10 GHz
on High-Bandwidth Path (SS)
Uses a Unique Adaptation Method to Maintain a
Constant Channel Impedance Over the Supported
Common-Mode Voltage Range
Excellent High-bandwidth Path Dynamic
Characteristics (at 2.5 GHz)
– Crosstalk = –35 dB
– Isolation = –23 dB
– Insertion Loss = –1.1 dB
– Return Loss = –11 dB
Small 3.5 mm × 9 mm, 42-Pin WQFN Package
(RUA)
Active Mode Power = 8 mW
USB HOST
1
USB
Connector
2 Applications
•
•
•
•
•
•
Desktop PCs
Notebook PCs
Tablets
Docking Stations
Telecommunications
Televisions
Connector
USB
Dock Station
Connector
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
HD3SS6126
SLAS975A – NOVEMBER 2013 – REVISED AUGUST 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
Electrical Characteristics – Device Parameters ........ 6
Electrical Characteristics – Signal Switch
Parameters................................................................. 7
6.7 Switching Characteristics .......................................... 8
6.8 Typical Characteristics ............................................ 10
7
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 11
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 12
8
Application and Implementation ........................ 13
8.1 Application Information............................................ 13
8.2 Typical Application ................................................. 13
9 Power Supply Recommendations...................... 15
10 Layout................................................................... 15
10.1 Layout Guidelines ................................................. 15
10.2 Layout Examples................................................... 15
11 Device and Documentation Support ................. 17
11.1
11.2
11.3
11.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
17
17
17
17
12 Mechanical, Packaging, and Orderable
Information ........................................................... 17
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (November 2013) to Revision A
•
2
Page
Added Pin Configuration and Functions section, ESD Ratings table, Typical Characteristics section, Feature
Description section, Device Functional Modes, Application and Implementation section, Power Supply
Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section ..................................................................................................................... 1
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SLAS975A – NOVEMBER 2013 – REVISED AUGUST 2015
5 Pin Configuration and Functions
RUA Package
42-Pin WQFN
Top View
NC
NC
NC
NC
39
40
41
42
NC
NC
NC
NC
NC
HS_OE
HSA(n)
HSA(p)
SEL
GND
SSA0(p)
SSA0(n)
VDD
GND
SSA1(p)
SSA1(n)
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
TQFN
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
NC
NC
NC
NC
HSC(n)
HSC(p)
HSB(n)
HSB(p)
VDD
SSB0(p)
SSB0(n)
SSB1(p)
SSB1(n)
SSC0(p)
SSC0(n)
SSC1(p)
SSC1(n)
21
20
19
18
GND
VDD
GND
NC
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Pin Functions
PIN
NAME
NO.
10, 14, 17,
19, 21
GND
HSA(p)
8
I/O
Supply
I/O
HSA(n)
7
HSB(p)
31
HSB(n)
32
HSC(p)
33
HSC(n)
34
HS_OE
6
I (Control)
1, 2, 3, 4, 5,
18, 35, 36,
37, 38, 39,
40, 41, 42
—
SEL
9
I (Control)
SSA0(p)
11
SSA0(n)
12
SSA1(p)
15
SSA1(n)
16
SSB0(p)
29
SSB0(n)
28
SSB1(p)
27
SSB1(n)
26
SSC0(p)
25
SSC0(n)
24
SSC1(p)
23
SSC1(n)
22
NC
VDD
4
13, 20, 30
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Supply
DESCRIPTION
Ground
Port A USB 2.0 positive signal
Port A USB 2.0 negative signal
Port B USB 2.0 positive signal
Port B USB 2.0 negative signal
Port C USB 2.0 positive signal
Port C USB 2.0 negative signal
Output Enable
H = Power Down
L = Normal Operation
Electrically No Connection
USB 3.0/2.0 Port Selection Control Pins
Port A, Channel 0, USB 3.0 Positive Signal
Port A, Channel 0, USB 3.0 Negative Signal
Port A, Channel 1, USB 3.0 Positive Signal
Port A, Channel 1, USB 3.0 Negative Signal
Port B, Channel 0, USB 3.0 Positive Signal
Port B, Channel 0, USB 3.0 Negative Signal
Port B, Channel 1, USB 3.0 Positive Signal
Port B, Channel 1, USB 3.0 Negative Signal
Port C, Channel 0, USB 3.0 Positive Signal
Port C, Channel 0, USB 3.0 Negative Signal
Port C, Channel 1, USB 3.0 Positive Signal
Port C, Channel 1, USB 3.0 Negative Signal
3.3-V power supply voltage
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
–0.3
4
V
Differential I/O, High-bandwidth signal path: SSA0/1(p/n), SSB0/1(p/n), SSC0/1(p/n)
–0.5
4
Differential I/O, Low-bandwidth signal path: HSAp/n), HSB(p/n), HSC(p/n)
-0.5
7
Control pin and single ended I/O
–0.3
VDD + 0.3
Supply Voltage, VDD (2)
Voltage
Continuous power dissipation
See Thermal Information
Storage temperature, Tstg
(1)
(2)
V
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential voltages, are with respect to network ground terminal.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
typical values for all parameters are at VCC = 3.3 V and TA = 25°C; all temperature limits are specified by design
VDD
Supply voltage
VIH
Input high voltage
Control Pins
VIL
Input low voltage
Control Pins
VI/O_Diff
Differential voltage
Switch I/O differential voltage for High-bandwidth signal
path only: SSA0/1(p/n), SSB0/1(p/n), SSC0/1(p/n)
VI/O_CM
Common voltage
Switch I/O common mode voltage for High-bandwidth signal
path only: SSA0/1(p/n), SSB0/1(p/n), SSC0/1(p/n)
TA
Operating free-air temperature
MIN
NOM
MAX
3.0
3.3
3.6
UNIT
V
2.0
VDD
V
–0.1
0.8
V
0
1.8
Vp-p
0
2.0
V
0
70
°C
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6.4 Thermal Information
HD3SS6126
THERMAL METRIC
RUA (WQFN)
UNIT
42 PINS
RθJA
Junction-to-ambient thermal resistance
53.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
38.2
°C/W
RθJB
Junction-to-board thermal resistance
27.4
°C/W
ψJT
Junction-to-top characterization parameter
5.6
°C/W
27.3
°C/W
ψJB
(1)
(1)
Junction-to-board characterization parameter
(1)
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics application report,
SPRA953. Test conditions for ΨJB and ΨJT are clarified in the application report..
6.5 Electrical Characteristics – Device Parameters
over recommended operating conditions (unless otherwise noted)
PARAMETER
ICC
TEST CONDITIONS
MIN
TYP
MAX
2.4
3
mA
VDD = 3.6 V, VIN = VDD
95
µA
VDD = 3.6 V, VIN = GND
1
µA
Input high current
VDD = 3.6 V, VIN = VDD
1
µA
Input high current
VDD = 3.6 V, VIN = GND
1
µA
Supply current
VDD = 3.6 V, SEL = VDD /GND; OE = GND; Outputs Floating
IIH
Input high current
IIL
Input high current
IIH
IIL
UNIT
SEL
HS_OE
SSA0/1, SSB0/1, SSC0/1
ILK
High-impedance leakage
current
VDD = 3.6 V, VIN = 2 V, VOUT= 2 V,
(ILK on open outputs Port B and C)
130
VDD = 3.6 V, VIN = 2 V, VOUT= 2 V,
(ILK on open outputs Port A)
4
VDD = 3.6 V, VIN = 0 V, VOUT= 0 V to 4 V,
HS_OE_IN = GND
1
µA
HSA, HSB, HSC
ILK
6
High-impedance leakage
current
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6.6 Electrical Characteristics – Signal Switch Parameters
under recommended operating conditions; RL, RSC = 50 Ω, CL = 10 pF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SSA0/1(p/n), SSB0/1(p/n), SSC0/1(p/n) Signal Path
CON
Outputs ON capacitance
VIN = 0 V, outputs open, switch ON
1.5
pF
COFF
Outputs OFF capacitance
VIN = 0 V, outputs open, switch OFF
1
pF
RON
Output ON resistance
VDD = 3.3 V, VCM = 0 V – 2 V,
IO = –8 mA
5
ΔRON
ON resistance match between pairs
of the same channel
RFLAT_ON
ON resistance flatness
(RON(MAX)– RON(MIN)
RL
Differential return loss
(VCM = 0 V)
XTALK
OIRR
IL
BW
Differential crosstalk
(VCM = 0 V)
Differential off-isolation
(VCM = 0 V)
Differential insertion loss
(VCM = 0 V)
Bandwidth
8
Ω
VDD = 3.3 V; 0 V ≤ VIN ≤ 2 V;
IO = –8 mA
0.7
Ω
VDD = 3.3 V; –0 V ≤ VIN ≤ 2 V
1.15
Ω
f = 0.3 MHz
–25
f = 2.5 GHz
–11
f = 4 GHz
–11
f = 0.3 MHz
-85
f = 2.5 GHz
–35
f = 4 GHz
–33
f = 0.3 MHz
-85
f = 2.5 GHz
-23
f = 4 GHz
–21
f = 0.3 MHz
–0.43
f = 2.5 GHz
–1.1
f = 4 GHz
–1.3
At –3 dB
dB
dB
dB
dB
10
GHz
HSA(p/n), HSB(p/n), HSC(p/n) SIGNAL PATH
CON
Outputs ON capacitance
VIN = 0 V, Outputs Open, Switch ON
COFF
Outputs OFF capacitance
VIN = 0 V, Outputs Open, Switch OFF
RON
ΔRON
RFLAT_ON
Output ON resistance
ON resistance match between pairs
of the same channel
ON resistance flatness
(RON(MAX)– RON(MIN )
6
7.5
pF
3.5
6
pF
3
6
VDD = 3 V, VIN = 2.4 V,
IO = 30 mA
3.4
6
VDD = 3 V; VIN = 0 V;
IO = 30 mA
0.2
VDD = 3 V; VIN = 1.7 V;
IO = -15 mA
0.2
VDD = 3 V, VIN = 0 V,
IO = 30 mA
Ω
Ω
VDD = 3 V; VIN = 0 V;
IO = 30 mA
1
VDD = 3 V; VIN = 1.7 V;
IO = –15 mA
1
Ω
XTALK
Differential crosstalk (VCM = 0 V)
RL = 50 Ω, f = 250 MHz
–40
OIRR
Differential off-isolation (VCM = 0 V)
RL = 50 Ω, f = 250 MHz
–41
dB
BW
Bandwidth
RL = 50 Ω
0.9
GHz
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6.7 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SSA0/1(p/n), SSB0/1(p/n), SSC0/1(p/n) Signal Path
ton
SEL-to-Switch ton
RSC and RL = 50 Ω, See Figure 1
70
250
ns
toff
SEL-to-Switch toff
RSC and RL = 50 Ω, See Figure 1
70
250
ns
tPD
Switch propagation delay
RSC and RL = 50 Ω, See Figure 3
85
ps
tSK(O)
Interpair output skew (CH-CH)
RSC and RL = 50 Ω, See Figure 3
20
ps
tSK(b-b)
Intrapair Output Skew (bit-bit)
RSC and RL = 50 Ω, See Figure 3
8
ps
HSA(p/n), HSB(p/n), HSC(p/n) SIGNAL PATH
SEL to Switch tON
See Figure 2
30
HS_OE to Switch tON
See Figure 2
17
SEL to Switch tOFF
See Figure 2
12
HS_OE to Switch tOFF
See Figure 2
10
tPD (1)
Switch propagation delay
See Figure 3
tSK(O) (1)
Interpair output skew (CH-CH)
100
200
ps
tSK(P) (1)
Intrapair Output Skew (bit-bit)
100
200
ps
tON
tOFF
(1)
250
ns
ns
ps
Specified by design
50%
SEL
90%
VOUT
10%
t off
t on
Figure 1. Select to Switch tON and tOFF
VCC
HSB or HSC VOUT1 or VOUT2
VIN
RL
CL
VCOM
tON
500 Ω
50 pF
V+
tOFF
500 Ω
50 pF
V+
HSA
CL(2)
HSB or HSC
VCTRL
TEST
RL
SEL
CL(2)
Logic
Input (1)
GND
RL
1.8 V
Logic
Input
(VI)
50%
50%
0
tON
Switch
Output
(VOUT1 or VOUT2)
(1)
(2)
tOFF
90%
90%
VOH
VOL
All input pulses are supplied by generators have the following characteristics: PRR ≤ 10 MHZ, ZO = 50 Ω, tr< 5 ns, tf < 5 ns.
CL includes probe and jig capacitance.
Figure 2. Turnon (tON) and Turnoff Time (tOFF)
8
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Vcc
50 Ω
HD3SS6126
A(p)
B/C(p)
50 Ω
50 Ω
A(n)
B/C(n)
50 Ω
B/C(p)
A(p)
B/C(n)
A(n)
SEL
C/B (p)
50%
50%
C/B (n)
A (p)
50%
50%
A (n)
tP1
tP2
Interpair skew
tPD = Max(tp1, tp2)
tSK(O) = Difference between tPD for any
two pairs of outputs
t1
t3
t2
t4
C/B/A (p)
50%
C/B/A (n)
C/B/A (p)
tSK(O)
C/B/A (n)
Intrapair skew
tSK(b-b) = 0.5 X |(t4 – t3) + (t1 – t2)|
NOTES:
1. Measurements based on an ideal input with zero intrapair skew on
the input, i.e. the input at A to B/C or the input at B/C to A
2. Interpair skew is measured from lane to lane on the same channel,
e.g. C0 to C1
3. Intrapair skew is defined as the relative difference from the p and n
signals of a single lane
Figure 3. Propagation Delay and Skew
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6.8 Typical Characteristics
0.625
0.465
0.62
0.455
0.615
0.445
0.61
SKEW (ps)
SKEW (ps)
0.475
0.435
0.425
0.415
0.605
0.6
0.595
0.405
0.59
0.395
0.585
0.385
0.58
0.375
0.575
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70
Temperature (qC)
D001
Figure 4. Intrapair Skew SSA to SSB Port
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70
Temperature (qC)
D002
Figure 5. Intrapair Skew SSA to SSC Port
7 Detailed Description
7.1 Overview
The HD3SS6126 is a USB 3.0 and USB 2.0 differential switch, it is designed to support data rates up to 10 Gbps
on high-bandwidth paths (SS), it is also suitable for DisplayPort, PCIe Gen1/2/3, SATA 1.5/3/6G, SAS 1.5/3/6G
and XAUI applications. The device uses a unique adaptation method to maintain a constant channel impedance
over the supported common-mode voltage range, resulting in an excellent high-bandwidth path dynamic
characteristics (at 2.5 GHz; Crosstalk = –35 dB, Isolation = –23 dB, Insertion Loss = –1.1 dB, Return Loss = –11
dB).
10
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7.2 Functional Block Diagram
NC
NC
NC
NC
39
40
41
42
NC
NC
NC
NC
NC
HS_OE
HSA(n)
HSA(p)
SEL
GND
SSA0(p)
SSA0(n)
VDD
GND
SSA1(p)
SSA1(n)
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
NC
NC
NC
NC
HSC(n)
HSC(p)
HSB(n)
HSB(p)
VDD
SSB0(p)
SSB0(n)
SSB1(p)
SSB1(n)
SSC0(p)
SSC0(n)
SSC1(p)
SSC1(n)
21
20
19
18
GND
VDD
GND
NC
7.3 Feature Description
The HD3SS6126 can be powered by VBUS from the USB Host, and is capable of selecting USB2 independently
from USB3. Although the main application of the HD3SS6126 is USB3.0/2.0, the device also supports common
interfaces such as PCIe Gen1 and Gen2, DP and SATA/SAS applications. The device is able to support these
additional interfaces because of its support of data rates up to 5.4 Gbps and common-mode voltages from 0 V to
2 V with a maximum signal swing of 1.8 V. All of these applications use an 8b or 10b coding technique to
achieve DC balance and facilitate terminal equipment.
NOTE
The device may need AC capacitors and additional bias voltage to support the PCIe Gen1
and Gen2 interfaces.
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7.4 Device Functional Modes
Table 1. Truth Table USB 3.0 SuperSpeed USB
USB 3.0 PORT SELECTION
SEL
SSA0/1
SSB0/1
0
To/From SSB0/1
To/From SSA0/1
SSC0/1
Off
1
To/From SSC0/1
Off
To/From SSA0/1
Table 2. Truth Table USB 2.0 High-Speed, Full-Speed, Low-Speed Path
12
USB 2.0 Port Selection
HS_OE
SEL
HSA
HSB
0
0
To/From HSB
To/From HSA
Off
0
1
To/From HSC
Off
To/From HSA
1
X
Off
Off
Off
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
A typical application for the HD3SS6126 is a USB 3.0 KVM switch, where one of two USB hosts system can be
selected for an USB device. These guidelines are also suitable for PCIe(Gen1,Gen2), SATA, XAUI and DP,
since the HD3SS6126 device is fully compatible with these protocols.
8.2 Typical Application
HD3SS6126
xN
PCIe/DP/USB/SATA
Signal Source 1
PCIe/DP/USB/SATA
Signal Sink
PCIe/DP/USB/SATA
Signal Source 2
Figure 6. Two Signal Sources to One Destination
HD3SS6126
xN
PCIe/DP/USB/SATA
Signal Sink 1
PCIe/DP/USB/SATA
Signal Source
PCIe/DP/USB/SATA
Signal Sink 2
Figure 7. One Signal Sources to Two Destination
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Typical Application (continued)
8.2.1 Design Requirements
Power supply requirements:
• VDD from 3 V to 3.6 V
Control pins requirements
• VIH from 2 V to VDD
• VIL from –0.1 V to 0.8 V
Differential pairs requirements:
• VI/O_Diff from 0 V to 1.8 Vp-p
• VI/O_CM from 0 V to 2 V
TA Operating free-air temperature from 0°C to 70°C
8.2.2 Detailed Design Procedure
8.2.2.1 Power Supply
The first step is to design the power supply and determine the VCC stability and minimum current required (see
Power Supply Recommendations).
8.2.2.2 Differential Pairs
All of the interfaces the HD3SS6126 device supports require AC coupling between the transmitter and receiver.
TI recommends using 0402-sized capacitors to provide AC coupling, but 0603-sized capacitors are also
acceptable. Both 0805-sized capacitors and C-packs should be avoided. Best practice is to place AC-coupling
capacitors symmetrically. A capacitor value of 0.1uF is best and the value should be matched for the +/-signal
pair. The placement should be along the TX pairs on the system board, which are usually routed on the top layer
of the board.
All differential pairs must have a matched impedance according to the implemented protocol: 100-Ω differential
(±10%) for PCIe and 90-Ω differential (±15%) for USB 2.0 and USB 3.0.
The control logic can be implemented by use of an external control processor or by using a simple selector
switch. TI recommends using 5-kΩ pullup and pulldown resistors on the control signals, if they are included. The
control logic must not violate the input voltage parameters outlined in the Recommended Operating Conditions
table.
8.2.3 Application Curves
Figure 8. USB 3.0 TX Eye Pattern Test With 3-Inch 5-mil
Differential PCB Trace Without HD3SS6126
14
Figure 9. USB 3.0 TX Eye Pattern Test With 3-Inch 5-mil
Differential PCB Trace With HD3SS6126
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9 Power Supply Recommendations
The power supply must provide a constant voltage with a 10% maximum variation of the nominal value, and has
to be able to provide at least 3 mA for the HD3SS6126 only (based on the maximum power consumption). It is
also possible to provide the power supply from VBUS from the Host, just by including a voltage regulator
powered through VBUS. Each VCC pin must have a 0.1-µF bypass capacitor placed as closely as possible. TI
recommends including two extra capacitors in parallel, which should be also placed as closely as possible to the
VCC pin. The suggested values for these extra capacitors are 1 µF and 0.01 µF.
10 Layout
10.1 Layout Guidelines
Generally, impedance match becomes critical in such high-speed signal applications to avoid reflection. Each
differential-signal pair must have a differential impedance of about 90 Ω ±15% (for PCIe or DP, 100 Ω ±10%)
with single-end signal impedance about 50 Ω to ground. Usually, Microstrip is used to accomplish impedance
match. Four layers are recommended for a low-EMI PCB design. shows physical geometries of differential traces
to form Microstrip. In order to better maintain signal integrity, reference the following:
1. Route high-speed differential signals on the top layer with a solid ground layer under them to accomplish
controlled impedance, while avoiding vias and stubs which may cause impedance discontinuities. If vias
must be used, make sure the space of the vias is as minimal as possible.
2. Be sure both the length of differential traces and the length of differential signal pairs are matched in order to
reduce intrapair skew and interpair skew separately which also does good to low EMI. TI recommends
keeping the space of the traces of the differential signal the same across the entire length of the trace to
keep impedance match and reduce EMI.
3. Route low-speed, but fast-edged control signals on the bottom layer to minimize the crosstalk of the highspeed signal.
4. For other adjacent signal traces on the same layer, make distance L ≥ 3 S to facilitate impedance match.
5. TI reccommends using 45° bends instead of 90° bends in order to maintain signal integrity and low EMI.
10.2 Layout Examples
W
L
Layer 1: High-Speed Diff-Signal Traces
S
t
+
-
h
0r
X
Layer 2: GND Plane
Layer 3: Power Plane
Layer 4: Low-Speed Signal Traces
Figure 10. PCB Layers Example
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Layout Examples (continued)
Figure 11. USB Signals Routing Example
16
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11 Device and Documentation Support
11.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.2 Trademarks
E2E is a trademark of Texas Instruments.
PCI-Express is a trademark of PCI-SIG.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
HD3SS6126RUAR
ACTIVE
WQFN
RUA
42
3000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
0 to 70
HD3SS6126
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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