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HVDA551-Q1, HVDA553-Q1
SLLSEC4B – JUNE 2013 – REVISED AUGUST 2016
HVDA55x-Q1 5-V CAN Transceiver
With I/O Level Adapting and Low-Power-Mode Supply Optimization
1
1 Features
•
•
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to
+125°C Ambient Operating Temperature
– Device HBM ESD Classification Level:
– Level 3B for Pins 6 and 7
– Level 3A for All Other Pins
– Device CDM ESD Classification Level C6
Meets or Exceeds the Requirements of
ISO 11898-2 and ISO 11898-5
GIFT/ICT Compliant
Data Rate Up to 1 Mbps
ESD Protection Up to ±12 kV (Human-Body
Model) on Bus Pins
I/O Voltage Level Adapting
– HVDA551: Adaptable I/O Voltage Range (VIO)
From 3 V to 5.33 V
SPLIT Voltage Source
– HVDA553: Common-Mode Bus Stabilization
Operating Modes:
– Normal Mode
– Low-Power Standby Mode With RXD Wake-Up
Request
High Electromagnetic Compliance (EMC)
Supports CAN Flexible Data-Rate (FD)
Protection
– Undervoltage Protection on VIO and VCC
– Bus-Fault Protection of –27 V to 40 V
– TXD Dominant State Time-Out
– RXD Wake-Up Request Lockout on CAN Bus
Stuck Dominant Fault (HVDA551)
– Digital Inputs Compatible With 5-V
Microprocessors (HVDA553)
– Thermal Shutdown Protection
– Power-Up and Power-Down Glitch-Free Bus
I/O
– High Bus Input Impedance When Unpowered
(No Bus Load)
2 Applications
•
•
•
•
•
SAE J2284 High-Speed CAN for Automotive
Applications
SAE J1939 Standard Data Bus Interface
GMW3122 Dual-Wire CAN Physical Layers
ISO 11783 Standard Data Bus Interface
NMEA 2000 Standard Data Bus Interface
3 Description
The HVDA55x-Q1 device is designed and qualified
for use in automotive applications and meets or
exceeds the specifications of the ISO 11898 High
Speed CAN (Controller Area Network) Physical Layer
standard (transceiver).
Device Information(1)
PART NUMBER
HVDA551-Q1
HVDA553-Q1
VCC
5
3
SOIC (8)
5
OVER TEMPERATURE
VCC
DOMINANT
TIME-OUT
VCC / 2
1
8
RXD
WAKE UP LOGIC /
MONITOR
LOGIC OUTPUT
MUX
LOGIC OUTPUT
MODE SELECT
UNDER
VOLTAGE
4
MUX
RXD
6
CANL
STB
MODE SELECT
CANH
DRIVER
VCC
UNDER
VOLTAGE
4
VCC
OVER TEMPERATURE
DOMINANT
TIME-OUT
TXD
6
CANL
8
3
7
CANH
DRIVER
VIO
STB
VCC
SPLIT
7
1
TXD
4.90 mm × 3.91 mm
HVDA553 Block Diagram
VCC
VIO
BODY SIZE (NOM)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
HVDA551 Block Diagram
VIO
PACKAGE
WAKE UP LOGIC /
MONITOR
2
2
GND
GND
Copyright © 2016, Texas Instruments Incorporated
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
HVDA551-Q1, HVDA553-Q1
SLLSEC4B – JUNE 2013 – REVISED AUGUST 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
5
5
5
8
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristic................................................
Parameter Measurement Information ................ 10
Detailed Description ............................................ 15
8.1 Overview ................................................................. 15
8.2 Functional Block Diagrams ..................................... 15
8.3 Feature Description................................................. 16
8.4 Device Functional Modes........................................ 19
9
Application and Implementation ........................ 22
9.1 Application Information............................................ 22
9.2 Typical Applications ................................................ 22
10 Power Supply Recommendations ..................... 25
11 Layout................................................................... 25
11.1 Layout Guidelines ................................................. 25
11.2 Layout Example .................................................... 26
12 Device and Documentation Support ................. 27
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
27
27
27
27
27
27
27
13 Mechanical, Packaging, and Orderable
Information ........................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (September 2013) to Revision B
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Removed Ordering Information table, see POA at the end of the data sheet........................................................................ 1
Changes from Original (June 2013) to Revision A
•
2
Page
In Electrical Characteristics rows 6.3 and 6.7, changed ® to (R)........................................................................................... 6
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SLLSEC4B – JUNE 2013 – REVISED AUGUST 2016
5 Pin Configuration and Functions
HVDA551 D Package
8-Pin SOIC
Top View
HVDA553 D Package
8-Pin SOIC
Top View
TXD
1
8
STB
GND
2
7
CANH
VCC
3
6
CANL
RXD
4
5
VIO
TXD
1
8
STB
GND
2
7
CANH
VCC
3
6
CANL
RXD
4
5
SPLIT
Not to scale
Not to scale
Pin Functions
PIN
NO.
NAME
TYPE (1)
DESCRIPTION
1
TXD
I
CAN transmit data input (low for dominant bus state, high for recessive bus state)
2
GND
G
Ground connection
3
VCC
P
Transceiver 5-V supply voltage
CAN receive data output (low in dominant bus state, high in recessive bus state)
4
RXD
O
VIO (HVDA551)
P/O
Transceiver logic level (IO) supply voltage
SPLIT
(HVDA553)
P/O
Common-mode stabilization output
6
CANL
I/O
Low level CAN bus line
7
CANH
I/O
High level CAN bus line
8
STB
I
5
(1)
Standby mode select pin (active high)
G = Ground, I = Input, O = Output, and P = Power
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SLLSEC4B – JUNE 2013 – REVISED AUGUST 2016
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
MAX
UNIT
VCC
Supply voltage
–0.3
6
V
VIO
I/O supply voltage
–0.3
6
V
Voltage at bus terminals (CANH, CANL)
–27
40
V
20
mA
IO
Receiver output current (RXD)
VI
Voltage input (TXD, STB, S)
TJ
Operating virtual-junction temperature
Tstg
Storage temperature
(1)
(2)
HVDA55x
–0.3
6 and VI ≤ VIO + 0.3
HVDA553
–0.3
6
–40
150
°C
150
°C
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to the ground terminal.
6.2 ESD Ratings
VALUE
Human-body model (HBM) (1)
Charged-device model (CDM)
V(ESD)
Electrostatic discharge
(5)
4
±4000
Pins 6 and 7 (2)
±12000
(3)
IEC 61000-4-2 according to IBEE
CAN EMC test specification (4)
ISO 7637 transients according to
IBEE CAN EMC test specification (5)
(1)
(2)
(3)
(4)
All pins except 6 and
7
UNIT
±1000
Pins 6, 7 to 2
±7000
Pulse 1
–100
Pulse 2a
75
Pulse 3a
–150
Pulse 3b
100
V
HBM tested in accordance with AEC-Q100-002.
HBM test method based on AEC-Q100-002, CANH and CANL bus pins stressed with respect to each other and GND.
CDM tested in accordance with AEC-Q100-011.
IEC 61000-4-2 is a system-level ESD test. Results given here are specific to the IBEE CAN EMC Test specification conditions. Different
system-level configurations lead to different results.
ISO 7637 is a system level transient test. Results given here are specific to the IBEE CAN EMC Test specification conditions. Different
system level configurations lead to different results.
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SLLSEC4B – JUNE 2013 – REVISED AUGUST 2016
6.3 Recommended Operating Conditions
MIN
MAX
UNIT
4.68
5.33
V
3
5.33
V
–12
12
V
0.7 × VIO
VIO
V
0
0.3 × VIO
V
Differential input voltage, bus (between CANH and CANL)
–6
6
V
IOH
High-level output current, RXD
–2
IOL
Low-level output current, RXD
TA
Operating ambient free-air temperature (see Thermal Information)
VCC
Supply voltage
VIO
I/O supply voltage
VI or VIC
Voltage at any bus terminal (separately or common mode)
VIH
High-level input voltage, TXD, STB (for HVD553, VIO = VCC)
VIL
Low-level input voltage, TXD, STB (for HVD553, VIO = VCC)
VID
mA
–40
2
mA
125
°C
6.4 Thermal Information
HVDA55x-Q1
THERMAL METRIC (1)
D (SOIC)
UNIT
8 PINS
Low-K thermal resistance
140
High-K thermal resistance
112
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
56
°C/W
RθJB
Junction-to-board thermal resistance
50
°C/W
ψJT
Junction-to-top characterization parameter
13
°C/W
ψJB
Junction-to-board characterization parameter
55
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
°C/W
(1)
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
TJ = –40°C to 150°C, HVDA553 VIO = VCC (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
HVDA551 SUPPLY
Standby mode (HVDA551 only), STB at VIO,
VCC = 5.33 V, VIO = 3 V, TXD at VIO (2)
ICC
5-V supply current
IIO
I/O supply current
UVVCC
Undervoltage detection
Normal mode (dominant), TXD at 0 V,
60-Ω load, STB at 0 V
50
70
Normal mode (recessive), TXD at VIO, no load,
STB at 0 V
6.75
10
Standby mode (HVDA551 only), STB at VIO ,
VCC = 5.33 V or 0 V, RXD floating, TXD at VIO,
TA = –40°C, 25°C, 125°C (3)
6.5
15
Normal mode (dominant), VCC = 5.33 V, RXD
floating, TXD at 0 V
85
300
Normal mode (recessive), VCC = 5.33 V, RXD
floating, TXD at VIO
70
300
3.6
4
On VCC for forced standby mode
VHYS(UVVCC) Hysteresis voltage
For undervoltage detection on UVVCC for
standby mode
UVVIO
Undervoltage detection
On VIO for forced standby mode
VHYS(UVVIO)
Hysteresis voltage
For undervoltage detection on UVVIO for forced
standby mode
(1)
(2)
(3)
5
µA
mA
3.2
200
1.9
2.45
µA
V
mV
2.95
130
V
mV
All typical values are at 25°C and supply voltages of VCC = 5 V and VIO = 3.3 V.
The VCC supply is not required during standby mode so in the application ICC in standby mode may be zero. If the VCC supply remains,
then ICC is per specification with VCC.
See IIO Quiescent Current in Standby / Silent Mode.
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SLLSEC4B – JUNE 2013 – REVISED AUGUST 2016
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Electrical Characteristics (continued)
TJ = –40°C to 150°C, HVDA553 VIO = VCC (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
HVDA553 SUPPLY
Standby mode (HVDA553 only), STB at VCC,
VCC = 5.33 V, TXD at VCC (2)
ICC
5-V supply current
12
Normal mode (dominant), TXD at 0 V, 60-Ω
load, STB at 0 V
Undervoltage detection
VHYS(UVVCC) Hysteresis voltage
70
6.75
10
3.6
4
mA
Normal mode (recessive), TXD at VCC, no load,
STB at 0 V
UVVCC
50
µA
On VCC for forced standby mode
3.2
For undervoltage detection on UVVCC for
standby mode
200
V
mV
DRIVER
Bus output voltage
(dominant)
VO(D)
CANH, VI = 0 V, STB at 0 V, RL = 60 Ω, see
Figure 2 and Figure 16
2.9
4.5
CANL, VI = 0 V, STB at 0 V, RL = 60 Ω, see
Figure 2 and Figure 16
0.8
1.75
VO(R)
Bus output voltage
(recessive)
VI = VIO, VIO = 3 V, STB at 0 V, RL = 60 Ω, see
Figure 2 and Figure 16
VO(STBY)
Bus output voltage
Standby mode (HVDA551 only), STB at VIO,
RL = 60 Ω, see Figure 2 and Figure 16
VOD(D)
Differential output
voltage (dominant)
Differential output
voltage (recessive)
VOD(R)
3
V
–0.1
0.1
V
VI = 0 V, RL = 60 Ω, STB at 0 V, see Figure 2,
Figure 16, and Figure 3
1.5
3
VI = 0 V, RL = 45 Ω, STB at 0 V, see Figure 2,
Figure 16, and Figure 3
1.4
3
VI = 3 V, STB at 0 V, RL = 60 Ω, see Figure 2
and Figure 16
–0.012
0.012
–0.5
0.05
Output symmetry
(dominant or recessive)
VO(CANH) + VO(CANL), STB at 0 V, RL = 60 Ω,
see Figure 12
VOC(SS)
Steady-state commonmode output voltage
STB at 0 V, RL = 60 Ω, see Figure 8
ΔVOC(SS)
Change in steady-state
common-mode output
voltage
STB at 0 V, RL = 60 Ω, see Figure 8
IOS(SS)_DOM
VCANH = 0 V, CANL open, TXD = low, see
Short-circuit steady-state Figure 11
output current, dominant VCANL = 32 V, CANH open, TXD = low, see
Figure 11
CO
2
See receiver input capacitance
VIT+
Positive-going input
threshold voltage
Normal mode, STB at 0 V, see Table 1
VIT–
Negative-going input
threshold voltage
Normal mode, STB at 0 V, see Table 1
Vhys
Hysteresis voltage
VIT+ – VIT–
VIT(STBY)
Input threshold voltage
HVDA551 only, standby mode, STB at VIO
II(OFF_LKG)
Power-off (unpowered)
bus input leakage
current
CANH = CANL = 5 V, VCC at 0 V, VIO at 0 V,
TXD at 0 V
V
0.9 × VCC
VCC
1.1 × VCC
V
2
2.5
3
V
50
mV
–100
mA
100
–20 V ≤ VCANH ≤ 32 V, CANL open,
Short-circuit steady-state TXD = high, see Figure 11
output current, recessive –20 V ≤ VCANL ≤ 32 V, CANH open,
TXD = high, see Figure 11
Output capacitance
2.5
V
VI = 3 V, STB at 0 V, no load
VSYM
IOS(SS)_REC
V
–10
10
–10
10
mA
RECEIVER
6
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800
500
400
900
mV
650
mV
125
mV
1150
mV
3
µA
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SLLSEC4B – JUNE 2013 – REVISED AUGUST 2016
Electrical Characteristics (continued)
TJ = –40°C to 150°C, HVDA553 VIO = VCC (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
CI
HVDA551: TXD at VIO, VIO at 3.3 V;
Input capacitance to
HVDA553: TXD at VCC, VI = 0.4 sin (4E6πt) +
ground (CANH or CANL)
2.5 V
CID
Differential input
capacitance
HVDA551: TXD at VIO, VIO at 3.3 V;
HVDA553: TXD at VCC, VI = 0.4 sin(4E6πt)
RID
Differential input
resistance
HVDA551: TXD at VIO, VIO = 3.3 V, STB at 0 V;
HVDA553: TXD at VCC, STB at 0 V
29
RIN
Input resistance (CANH
or CANL)
HVDA551: TXD at VIO, VIO = 3.3 V, STB at 0 V;
HVDA553: TXD at VCC, STB at 0 V
14.5
RI(M)
Input resistance
matching
[1 – RIN(CANH) / RIN(CANL))] × 100%,
V(CANH) = V(CANL)
–3%
VIH
High-level input voltage
HVD553: VIO = VCC
VIL
Low-level input voltage
HVD553: VIO = VCC
IIH
High-level input current
HVDA551: TXD at VIO; HVDA553: TXD at VCC
IIL
Low-level input current
TXD at 0 V
TYP (1)
MAX
UNIT
13
pF
5
pF
80
kΩ
25
40
kΩ
0%
3%
TXD PIN
0.7 × VIO
V
0.3 × VIO
V
–2
2
µA
–100
–7
µA
RXD PIN
VOH
High-level output voltage HVD553: VIO = VCC, IO = –2 mA, see Figure 6
VOL
Low-level output voltage
HVD553: VIO = VCC, IO = 2 mA, see Figure 6
VIH
High-level input voltage
HVD553: VIO = VCC
VIL
Low-level input voltage
HVD553: VIO = VCC
IIH
High-level input current
HVDA551: STB at VIO; HVDA553: STB at VCC
IIL
Low-level input current
STB at 0 V
0.8 × VIO
V
0.2 × VIO
V
STB PIN
0.7 × VIO
V
–2
0.3 × VIO
V
2
µA
–20
µA
SPLIT PIN (HVDA553 ONLY)
VO
Output voltage
–500 µA < IO < 500 µA
IO(STB)
Leakage current
Standby mode, STB at VCC, –12 V ≤ IO ≤ 12 V
0.3 × VCC
0.5 × VCC
–5
0.7 × VCC
V
5
µA
POWER DISSIPATION AND THERMAL SHUTDOWN
PD
Average power
dissipation
VCC = 5 V, VIO = VCC, TJ = 27°C, RL = 60 Ω,
STB at 0 V, Input to TXD at 500 kHz, 50% duty
cycle square wave, CL at
RXD = 15 pF
140
mW
VCC = 5.33 V, VIO = VCC, TJ = 130°C,
RL = 60 Ω , STB at 0 V, Input to TXD at 500
kHz, 50% duty cycle square wave, CL at RXD =
15 pF
Thermal shutdown
temperature
215
185
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°C
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6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
ns
PROPAGATION TIME (LOOP TIME TXD to RXD)
tPROP(LOOP1)
Total loop delay 1
Driver input (TXD) to receiver output
(RXD), recessive to dominant, see
Figure 9, STB at 0 V
70
230
tPROP(LOOP2)
Total loop delay 2
Driver input (TXD) to receiver output
(RXD), dominant to recessive, see
Figure 9, STB at 0 V
70
230
tPLH
Propagation delay time,
low-to-high level output
STB at 0 V, see Figure 4
65
ns
tPHL
Propagation delay time,
high-to-low level output
STB at 0 V, see Figure 4
50
ns
tR
Differential output signal rise time
STB at 0 V, see Figure 4
25
ns
tF
Differential output signal fall time
STB at 0 V, see Figure 4
55
ns
tEN
Enable time from standby or
silent mode to normal mode,
dominant
See Figure 7
t(DOM) (2)
Dominant time-out
See Figure 10
tPLH
Propagation delay time,
low-to-high-level output
STB at 0 V , see Figure 6
95
ns
tPHL
Propagation delay time,
high-to-low-level output
STB at 0 V , see Figure 6
60
ns
tR
Output signal rise time
STB at 0 V , see Figure 6
13
ns
tF
Output signal fall time
STB at 0 V , see Figure 6
10
ns
tBUS
Dominant time
HVDA551 only, required on bus for
wake-up from standby, STB at VIO,
see Figure 18 and Figure 19
1.5
5
µs
Recessive time
HVDA551 only, on the bus to clear
the standby mode receiver output
(RXD) if standby mode is entered
while bus is dominant, STB at VIO,
see Figure 18 and Figure 19
1.5
5
µs
DRIVER
1200
2000
30
µs
2800
µs
RECEIVER
tCLEAR
(1)
(2)
8
All typical values are at 25°C and supply voltages of VCC = 5 V and VIO = 3.3 V.
The TXD dominant time out (t(DOM)) disables the driver of the transceiver once the TXD has been dominant longer than t(DOM), which
releases the bus lines to recessive, preventing a local failure from locking the bus dominant. The driver may only transmit dominant
again after TXD has been returned HIGH (recessive). While this protects the bus from local faults, locking the bus dominant, it limits the
minimum data rate possible. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD) for the worst case,
where five successive dominant bits are followed immediately by an error frame. This, along with the t(DOM) minimum, limits the
minimum bit rate. The minimum bit rate may be calculated by: Minimum Bit Rate = 11 / t(DOM) = 11 bits / 300 µs = 37 kbps
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SLLSEC4B – JUNE 2013 – REVISED AUGUST 2016
6.7 Typical Characteristic
VIO = 5 V, STB = 0 V, Rl = 60 Ω, CL= open, RCM = open, TJ = 25°C (unless otherwise noted)
3.00E+00
2.50E+00
Vod
2.00E+00
1.50E+00
1.00E+00
5.00E-01
0.00E+00
4.4
4.6
4.8
5.0
5.2
5.4
VCC
5.6
C002
Figure 1. Vod vs VCC for HVDA55x
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7 Parameter Measurement Information
Figure 2. Driver Voltage, Current, and Test Definition
Figure 3. Driver VOD Test Circuit
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle,
tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
B.
CL includes instrumentation and fixture capacitance within ±20%.
C.
For HVDA553 device versions, VIO = VCC.
Figure 4. Driver Test Circuit and Voltage Waveforms
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Parameter Measurement Information (continued)
Figure 5. Receiver Voltage and Current Definitions
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle,
tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
B.
CL includes instrumentation and fixture capacitance within ±20%.
C.
For HVDA553 device versions VIO = VCC.
Figure 6. Receiver Test Circuit and Voltage Waveforms
Table 1. Differential Input Voltage Threshold Test
INPUT
OUTPUT
VCANH
VCANL
|VID|
–11.1 V
–12 V
900 mV
L
12 V
11.1 V
900 mV
L
–6 V
–12 V
6V
L
12 V
6V
6V
L
–11.5 V
–12 V
500 mV
H
12 V
11.5 V
500 mV
H
–12 V
–6 V
6V
H
6V
12 V
6V
H
Open
Open
X
H
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VOL
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A.
CL = 100 pF includes instrumentation and fixture capacitance within ±20%.
B.
All VI input pulses are from 0 V to VIO and supplied by a generator having the following characteristics: tr or tf ≤ 6 ns.
Pulse repetition rate (PRR) = 25 kHz, 50% duty cycle.
C.
For HVDA553 device versions, VIO = VCC.
Figure 7. tEN Test Circuit and Waveforms
A.
All VI input pulses are from 0 V to VIO and supplied by a generator having the following characteristics: tr or tf ≤ 6 ns.
Pulse repetition rate (PRR) = 125 kHz, 50% duty cycle.
Figure 8. Common-Mode Output Voltage Test and Waveforms
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A.
CL = 100 pF includes instrumentation and fixture capacitance within ±20%.
B.
All VI input pulses are from 0 V to VIO and supplied by a generator having the following characteristics: tr or tf ≤ 6 ns.
Pulse repetition rate (PRR) = 125 kHz, 50% duty cycle.
C.
For HVDA553 device versions, VIO = VCC.
Figure 9. tPROP(LOOP) Test Circuit and Waveform
A.
CL = 100 pF includes instrumentation and fixture capacitance within ±20%.
B.
All VI input pulses are from 0 V to VIO and supplied by a generator having the following characteristics: tr or tf ≤ 6 ns.
Pulse repetition rate (PRR) = 500 Hz, 50% duty cycle.
C.
For HVDA553 device versions, VIO = VCC.
Figure 10. TXD Dominant Time-Out Test Circuit and Waveforms
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A.
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For HVDA553 device versions VIO = VCC.
Figure 11. Driver Short-Circuit Current Test and Waveforms
A.
All VI input pulses are from 0 V to VIO and supplied by a generator having the following characteristics: tr and
tf ≤ 6 ns, pulse repetition rate (PRR) = 250 kHz, 50% duty cycle.
Figure 12. Driver Output Symmetry Test Circuit
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8 Detailed Description
8.1 Overview
The device meets or exceeds the specifications of the ISO 11898 High-Speed CAN (Controller Area Network)
Physical Layer standard (transceiver). This device provides CAN transceiver functions: differential transmit
capability to the bus and differential receive capability at data rates up to 1 megabit per second (Mbps). The
device includes many protection features providing device and CAN network robustness.
8.2 Functional Block Diagrams
VIO
VCC
5
3
VCC
VIO
OVER TEMPERATURE
7
1
DOMINANT
TIME-OUT
TXD
CANH
DRIVER
6
CANL
VIO
8
MODE SELECT
STB
4
RXD
LOGIC OUTPUT
MUX
UNDER
VOLTAGE
WAKE UP LOGIC /
MONITOR
2
GND
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Figure 13. HVDA551 Block Diagram
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Functional Block Diagrams (continued)
SPLIT
VCC
5
3
VCC / 2
VCC
OVER TEMPERATURE
VCC
7
1
DOMINANT
TIME-OUT
TXD
CANH
DRIVER
6
CANL
VCC
8
MODE SELECT
STB
4
RXD
LOGIC OUTPUT
MUX
UNDER
VOLTAGE
WAKE UP LOGIC /
MONITOR
2
GND
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Figure 14. HVDA553 Block Diagram
8.3 Feature Description
8.3.1 Digital Inputs and Outputs
The HVDA551 device has an I/O supply voltage input pin (VIO) to ratiometrically level shift the digital logic input
and output levels with respect to VIO for compatibility with protocol controllers having I/O supply voltages between
3 V and 5.33 V.
The HVDA553 devices have a single VCC supply (5 V). The digital logic input and output levels for these devices
are with respect to VCC for compatibility with protocol controllers having I/O supply voltages between 4.68 V and
5.33 V.
8.3.2 Using the HVDA553 With Split Termination
The SPLIT pin voltage output provides 0.5 × VCC in normal mode. The circuit may be used by the application to
stabilize the common-mode voltage of the bus by connecting it to the center tap of split termination for the CAN
network (see Figure 15 and Figure 23). This pin provides a stabilizing recessive voltage drive to offset leakage
currents of unpowered transceivers or other bias imbalances that might bring the network common-mode voltage
away from 0.5 × VCC. Using this feature in a CAN network improves electromagnetic emissions behavior of the
network by eliminating fluctuations in the bus common-mode voltage levels at the start of message
transmissions.
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Feature Description (continued)
Figure 15. SPLIT Pin Circuitry and Application
8.3.3 Protection Features
8.3.3.1 TXD Dominant State Time Out
During normal mode, the only mode where the CAN driver is active, the TXD dominant time-out circuit prevents
the transceiver from blocking network communication in the event of a hardware or software failure where TXD is
held dominant longer than the time-out period t(DOM). The dominant time-out circuit is triggered by a falling edge
on TXD. If no rising edge is seen before the time-out constant of the circuit expires (t(DOM)) the CAN bus driver is
disabled, freeing the bus for communication between other network nodes. The CAN driver is re-activated when
a recessive signal is seen on the TXD pin, thus clearing the dominant-state time-out. The CAN bus pins are
biased to the recessive level during a TXD dominant-state time-out.
NOTE
The maximum dominant TXD time allowed by the TXD dominant-state time-out limits the
minimum possible data rate of the devices.
The CAN protocol allows a maximum of eleven successive dominant bits (on TXD) for the worst case, where five
successive dominant bits are followed immediately by an error frame. This, along with the t(DOM) minimum, limits
the minimum bit rate. The minimum bit rate may be calculated by Equation 1:
Minimum Bit Rate = 11 / t(DOM)
(1)
8.3.3.2 Thermal Shutdown
If the junction temperature of the device exceeds the thermal shutdown threshold, the device turns off the CAN
driver circuits. This condition is cleared once the temperature drops below the thermal shutdown temperature of
the device. The CAN bus pins are biased to the recessive level during a thermal shutdown.
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Feature Description (continued)
8.3.3.3 Undervoltage Lockout or Unpowered Device
Both of the supply pins have undervoltage detection, which places the device in forced standby mode to protect
the bus during an undervoltage event on either the VCC or VIO supply pins. If VIO is undervoltage, the RXD pin is
forced to the high-impedance state and the device does not pass any wake-up signals from the bus to the RXD
pin. Because the device is placed into forced standby mode, the CAN bus pins have a common-mode bias to
ground, protecting the CAN network; see Figure 16 and Figure 17.
The device is designed to be an ideal passive load to the CAN bus if it is unpowered. The bus pins (CANH,
CANL) have extremely low leakage currents when the device is unpowered, so they do not load down the bus
but rather be a no-load. This is critical, especially if some nodes of the network are unpowered while the rest of
the network remains in operation.
NOTE
Once an undervoltage condition is cleared and VCC and VIO have returned to valid levels,
the device typically requires 300 µs to transition to normal operation.
Table 2. Undervoltage Protection
DEVICE
Both devices
VCC
VIO
(3)
BUS
RXD
Mirrors bus state through wakeup filter (2)
Bad
Good
Forced standby mode
Common mode bias to
GND (1)
Good
Bad
Forced standby mode (3)
Common mode bias to
GND (1)
High Z
Unpowered
No load
High Z
Unpowered
(1)
(2)
DEVICE STATE
See Figure 16 and Figure 17 for common-mode bias information.
See Figure 18 and Figure 19 for operation of the low-power wake-up receiver and bus monitor for RXD wake-up request behavior and
Table 5 for the wake-up receiver threshold levels.
When VIO is undervoltage, the device is forced into standby mode with respect to the CAN bus, because there is not a valid digital
reference to determine the digital I/O states or power the wake-up receiver.
8.3.3.4 Floating Pins
The device has integrated pullups and pulldowns on critical pins to place the device into known states if the pins
float. The TXD and STB pins on the HVDA551 are pulled up to VIO. This forces a recessive input level on TXD in
the case of a floating TXD pin and prevents the device from entering into the low-power standby mode if the STB
pin floats. In the case of the HVDA553 both the TXD and STB pins are pulled up to VCC, which has the same
effect.
8.3.3.5 CAN Bus Short-Circuit Current Limiting
The device has several protection features that limit the short-circuit current when a CAN bus line is shorted.
These include CAN driver-current limiting (dominant and recessive) and TXD dominant-state time-out to prevent
continuously driving dominant. During CAN communication, the bus switches between dominant and recessive
states; thus, the short-circuit current may be viewed either as the current during each bus state or as a DC
average current. For system current and power considerations in termination resistance and common-mode
choke ratings, the average short-circuit current must be used. The device has TXD dominant-state time-out,
which prevents permanently having the higher short-circuit current of dominant state. The CAN protocol also has
forced state changes and recessive bits such as bit stuffing, control fields, and interframe space. These ensure
there is a minimum recessive amount of time on the bus even if the data field contains a high percentage of
dominant bits.
NOTE
The short-circuit current of the bus depends on the ratio of recessive to dominant bits and
their respective short-circuit currents.
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The average short-circuit current may be calculated with Equation 2:
IOS(AVG) = %Transmit × [(%REC_Bits × IOS(SS)_REC) + (%DOM_Bits × IOS(SS)_DOM)] + [%Receive × IOS(SS)_REC]
where
•
•
•
•
•
•
•
IOS(AVG) is the average short-circuit current
%Transmit is the percentage the node is transmitting CAN messages
%Receive is the percentage the node is receiving CAN messages
%REC_Bits is the percentage of recessive bits in the transmitted CAN messages
%DOM_Bits is the percentage of dominant bits in the transmitted CAN messages
IOS(SS)_REC is the recessive steady-state, short-circuit current
IOS(SS)_DOM is the dominant steady-state, short-circuit current
(2)
8.4 Device Functional Modes
These devices have two main operating modes: normal mode and standby mode. Table 3 lists these modes in
detail. Operating mode selection is made through the STB input pin.
Table 3. Operating Modes
DEVICE
All devices
(1)
(2)
STB
MODE
DRIVER
RECEIVER
RXD Pin
LOW
Normal mode
Enabled (On)
Enabled (On)
Mirrors bus state (1)
HIGH
Standby mode (RXD
wake-up request)
Disabled (Off)
Low-power wake-up receiver
and bus monitor enabled
Mirrors bus state through wakeup filter (2)
Mirrors bus state: LOW if CAN bus is dominant, HIGH if CAN bus is recessive.
See Figure 18 and Figure 19 for operation of the low-power wake-up receiver and bus monitor for RXD wake-up request behavior and
Table 5 for the wake-up receiver threshold levels.
8.4.1 Bus States by Mode
The CAN bus has three valid states during powered operation, depending on the mode of the device. In normal
mode, the bus may be dominant (logic LOW) where the bus lines are driven differentially apart, or or the bus
may be recessive (logic HIGH) where the bus lines are biased to VCC / 2 through the high-ohmic internal input
resistors RIN of the receiver. The third state is low-power standby mode where the bus lines are biased to GND
through the high-ohmic internal input resistors RIN of the receiver.
Low Power
Standby Mode
Typical Bus Voltage
Normal & Silent Mode
CANH
Vdiff
Vdiff
CANL
Recessive
Dominant
Recessive
Time, t
Figure 16. Bus States (Physical Bit Representation)
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CANH
VCC/2
A
RXD
B
CANL
A: Normal Mode
B: Low Power Standby Mode
Figure 17. Simplified Common-Mode Bias and Receiver Implementation
8.4.2 Normal Mode
This is the normal operating mode of the device. Normal mode is selected by setting STB low. The CAN driver
and receiver are fully operational and CAN communication is bidirectional. The driver is translating a digital input
on TXD to a differential output on CANH and CANL. The receiver is translating the differential signal from CANH
and CANL to a digital output on RXD. In recessive state, the CAN bus pins (CANH and CANL) are biased to 0.5
× VCC. In dominant state, the bus pins are driven differentially apart. Logic high is equivalent to recessive on the
bus, and logic low is equivalent to a dominant (differential) signal on the bus.
8.4.3 Standby Mode With RXD Wake-Up Request
This is the low-power mode of the device. Standby mode is selected by setting STB high. The CAN driver and
main receiver are turned off and bidirectional CAN communication is not possible. The low-power receiver and
bus monitor, both supplied through the VIO supply, are enabled to allow for RXD wake-up requests through the
CAN bus. The VCC (5-V) supply may be turned off for additional power savings at the system level. A wake-up
request is output to RXD (driven low) for any dominant bus transmissions longer than the filter time tBUS. The
local protocol controller (MCU) must monitor RXD for transitions and then reactivate the device to normal mode
based on the wake-up request. The 5-V (VCC) supply must be reactivated by the local protocol controller to
resume normal mode if it has been turned off for low-power standby operation. The CAN bus pins are weakly
pulled to GND, see Figure 16 and Figure 17.
8.4.3.1 RXD Wake-Up Request Lockout for Bus-Stuck Dominant Fault (HVDA551)
If the bus has a fault condition where it is stuck dominant while the HVDA551 is placed into standby mode
through the STB pin, the device locks out the RXD wake-up request until the fault has been removed to prevent
false wake-up signals in the system.
STB
Standby Mode, STB = High
Bus VDiff
tBUS
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