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INA826
SBOS562G – AUGUST 2011 – REVISED JUNE 2020
INA826 Precision, 200-µA Supply Current, 3-V to 36-V Supply
Instrumentation Amplifier With Rail-to-Rail Output
1 Features
3 Description
•
•
The INA826 is a cost-effective instrumentation
amplifier that offers extremely low power consumption
and operates over a very wide single-supply or dualsupply range. A single external resistor sets any gain
from 1 to 1000. The device offers excellent stability
over temperature, even at G > 1, as a result of the
low gain drift of only 35 ppm/°C (maximum).
1
•
•
•
•
•
•
•
•
•
•
•
Input common-mode range: Includes V–
Common-mode rejection:
– 104 dB, min (G = 10)
– 100 dB, min at 5 kHz (G = 10)
Power-supply rejection: 100 dB, min (G = 1)
Low offset voltage: 150 µV, max
Gain drift: 1 ppm/°C (G = 1), 35 ppm/°C (G > 1)
Noise: 18 nV/√Hz, G ≥ 100
Bandwidth: 1 MHz (G = 1), 60 kHz (G = 100)
Inputs protected up to ±40 V
Rail-to-rail output
Supply current: 200 µA
Supply range:
– Single supply: 3 V to 36 V
– Dual supply: ±1.5 V to ±18 V
Specified temperature range:
–40°C to +125°C
Packages: 8-pin VSSOP, SOIC, and WSON
The INA826 is optimized to provide excellent
common-mode rejection ratio of over 100 dB (G = 10)
over frequencies up to 5 kHz. At G = 1, the commonmode rejection ratio exceeds 84 dB across the full
input common-mode range, from the negative supply
all the way up to 1 V of the positive supply. Using a
rail-to-rail output, the INA826 is a great choice for
low-voltage operation from a 3-V single supply, as
well as dual supplies up to ±18 V.
Additional circuitry protects the inputs against
overvoltage of up to ±40 V beyond the power
supplies by limiting the input currents to less than
8 mA.
The INA826 is available in 8-pin SOIC, VSSOP, and
tiny 3-mm × 3-mm WSON surface-mount packages.
All versions are specified for the –40°C to +125°C
temperature range.
2 Applications
•
•
•
•
•
•
•
•
Analog input module
Flow transmitter
Battery test
LCD test
Electrocardiogram (ECG)
Surgical equipment
Process analytics (pH, gas, concentration, force
and humidity)
Circuit breaker (ACB, MCCB, VCB)
Device Information(1)
PART NUMBER
INA826
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.91 mm
WSON (8)
3.00 mm × 3.00 mm
VSSOP (8)
3.00 mm × 3.00 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
General-Purpose Instrumentation Amplifier
V+
0.1 mF
8
(1)
RS
-IN
1
RFI Filter
50 kW
50 kW
A1
VO = G ´ (VIN+ - VIN-)
2
24.7 kW
RG
G=1+
24.7 kW
+
3
Load VO
50 kW
(1)
RS
+IN
4
49.4 kW
RG
7
A3
50 kW
A2
6
REF
RFI Filter
Device
5
0.1 mF
V-
(1)
This resistor is optional if the input voltage stays above [(V–) – 2 V] or if the signal source current drive capability is
limited to less than 3.5 mA; see the Input Protection section for more details.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
INA826
SBOS562G – AUGUST 2011 – REVISED JUNE 2020
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
4
5
7.1
7.2
7.3
7.4
7.5
7.6
5
5
5
5
6
8
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 18
8.1 Overview ................................................................. 18
8.2 Functional Block Diagram ....................................... 18
8.3 Feature Description................................................. 19
8.4 Device Functional Modes........................................ 25
9
Application and Implementation ........................ 26
9.1 Application Information............................................ 26
9.2 Typical Application .................................................. 26
9.3 System Examples ................................................... 28
10 Power Supply Recommendations ..................... 33
11 Layout................................................................... 33
11.1 Layout Guidelines ................................................. 33
11.2 Layout Example .................................................... 34
12 Device and Documentation Support ................. 35
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Support Resources ...............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
35
35
35
35
35
35
13 Mechanical, Packaging, and Orderable
Information ........................................................... 35
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (July 2016) to Revision G
Page
•
Changed Figure 58, INA826 Simplified Circuit Diagram ...................................................................................................... 19
•
Added last bullet regarding new DRG package to Layout Guidelines section..................................................................... 33
•
Changed Figure 73, INA826 Example Layout...................................................................................................................... 34
Changes from Revision E (April 2013) to Revision F
Page
•
Added Device Information, ESD Ratings, Recommended Operating Conditions tables, and Feature Description,
Device Functional Modes, Application and Implementation, Power Supply Recommendations, Layout, Device and
Documentation Support, and Mechanical, Packaging, and Orderable Information sections ................................................. 1
•
Added TI Design .................................................................................................................................................................... 1
•
Changed 2.7-V to 3-V in document title ................................................................................................................................ 1
•
Changed MSOP to VSSOP, SO to SOIC, and DRG to WSON throughout document .......................................................... 1
•
Changed Supply Range Features bullet minimum voltage levels ......................................................................................... 1
•
Changed Packages Features bullet ...................................................................................................................................... 1
•
Changed page 1 graphic ....................................................................................................................................................... 1
•
Changed Description section for minor rewording, renaming of packages , and changing single supply voltage value
from 2.7 V to 3 V .................................................................................................................................................................... 1
•
Deleted DGK PackagePackage/Ordering Information table ................................................................................................. 4
•
Changed Temperature parameter symbols in Absolute Maximum Ratings table ................................................................. 5
•
Changed Input, Differential impedance and Common-mode impedance parameter symbols in Electrical
Characteristics table ............................................................................................................................................................... 6
•
Changed Input, VCM parameter test conditions in Electrical Characteristics table ................................................................ 6
•
Deleted Gain, Range of gain parameter symbol from Electrical Characteristics table ......................................................... 7
•
Changed Power Supply, VS parameter minimum specifications, and moved to Recommended Operating Conditions
table ....................................................................................................................................................................................... 7
•
Changed VS voltage to 3.0 V and red VREF trace to 1.5 V in Figure 9 and Figure 10............................................................ 9
2
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INA826
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SBOS562G – AUGUST 2011 – REVISED JUNE 2020
•
Changed VS voltage level to 3.0 V in Figure 29 .................................................................................................................. 12
•
Changed blue VS trace value to 3.0 V in Figure 36 ............................................................................................................. 13
•
Changed 2.7 V to 3 V and 1.35 V to 1.5 V in Operating Voltage section ........................................................................... 24
•
Changed TINA-TI simulation circuit links in Using TINA-TI SPICE-Based Analog Simulation Program with the
INA826 section ..................................................................................................................................................................... 29
Changes from Revision D (March 2013) to Revision E
•
Page
Deleted package marking column from Package/Ordering Information table ....................................................................... 4
Changes from Revision C (March 2012) to Revision D
•
Page
Changed Input voltage range parameter specification value in Absolute Maximum Ratings table ....................................... 5
Changes from Revision B (December 2011) to Revision C
Page
•
Changed product status from Mixed Status to Production Data ............................................................................................ 1
•
Deleted gray shading and footnote 2 from Package/Ordering Information table .................................................................. 4
•
Changed DFN-8 package to production data ........................................................................................................................ 4
Changes from Revision A (September 2011) to Revision B
•
Page
Deleted gray from SO-8 row in Package/Ordering Information ............................................................................................. 4
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INA826
SBOS562G – AUGUST 2011 – REVISED JUNE 2020
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5 Device Comparison Table
DEVICE
DESCRIPTION
INA333
25-µV VOS, 0.1 µV/°C VOS drift, 1.8-V to 5-V, RRO, 50-µA IQ, chopper-stabilized INA
PGA280
20-mV to ±10-V programmable gain IA with 3-V or 5-V differential output; analog supply up to ±18 V
INA159
G = 0.2 V differential amplifier for ±10-V to 3-V and 5-V conversion
PGA112
Precision programmable gain op amp with SPI
6 Pin Configuration and Functions
DGK and D Package
8-Pin SOIC, VSSOP
Top View
DRG Package
8-Pin WSON
Top View
-IN
1
8
+VS
RG
2
7
VOUT
RG
3
6
REF
+IN
4
5
-VS
-IN
1
RG
2
RG
3
+IN
4
Exposed
Thermal
Die Pad
on
Underside
8
+VS
7
VOUT
6
REF
5
-VS
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
SOIC,
VSSOP
WSON
–IN
1
1
I
Negative (inverting) input
+IN
4
4
I
Positive (noninverting) input
REF
6
6
I
Reference input. This pin must be driven by low impedance.
2
2
3
3
VOUT
7
–VS
5
+VS
Thermal
pad
RG
4
—
Gain setting pin. Place a gain resistor between pin 2 and pin 3.
7
O
Output
5
—
Negative supply
8
8
—
Positive supply
—
—
—
Exposed thermal die pad is internally connected to –VS. Connect externally to –VS
or leave floating.
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SBOS562G – AUGUST 2011 – REVISED JUNE 2020
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
–20
20
Voltage
(–VS) – 40
(+VS) + 40
REF pin
–20
+20
Supply voltage
Signal input pins
Output short-circuit (2)
Operating, TA
–50
V
150
Junction, TJ
175
Storage, Tstg
(2)
V
Continuous
Temperature
(1)
UNIT
–65
°C
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Short-circuit to VS / 2.
7.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±2500
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1500
Machine model (MM)
±150
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Single-supply
Supply voltage
Dual-supply
NOM
MAX
3
36
±1.5
±18
–40
125
Specified temperature, TA
UNIT
V
°C
7.4 Thermal Information
INA826
THERMAL METRIC (1)
D (SOIC)
DGK (VSSOP)
DRG (WSON)
UNIT
8 PINS
8 PINS
8 PINS
RθJA
Junction-to-ambient thermal resistance
141.4
215.4
50.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
75.4
66.3
60.0
°C/W
RθJB
Junction-to-board thermal resistance
59.6
97.8
25.4
°C/W
ψJT
Junction-to-top characterization parameter
27.4
10.5
1.2
°C/W
ψJB
Junction-to-board characterization parameter
59.1
96.1
25.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
7.2
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SBOS562G – AUGUST 2011 – REVISED JUNE 2020
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7.5 Electrical Characteristics
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RTI
40
150
vs temperature, TA = –40°C to +125°C
0.4
2
RTI
200
700
µV
2
10
µV/°C
INPUT
VOSI
Input stage offset voltage (1)
VOSO
Output stage offset
voltage (1)
vs temperature, TA = –40°C to +125°C
G = 1, RTI
100
124
G = 10, RTI
115
130
G = 100, RTI
120
140
G = 1000, RTI
120
µV
µV/°C
PSRR
Powersupply rejection ratio
zid
Differential impedance
20 || 1
GΩ || pF
zic
Common-mode impedance
10 || 5
GΩ || pF
RFI filter, –3-dB frequency
140
20
V–
VCM
Operating input range (2)
VS = ±1.5 V to ±18 V
TA = –40°C to +125°C
Input overvoltage range
TA = –40°C to +125°C
At dc to
60 Hz, RTI
CMRR
dB
Common-mode rejection
ratio
At 5 kHz,
RTI
V
See Figure 41 to Figure 44
±40
G = 1, VCM = (V–) to (V+) – 1 V
84
95
G = 10, VCM = (V–) to (V+) – 1 V
104
115
G = 100, VCM = (V–) to (V+) – 1 V
120
130
G = 1000, VCM = (V–) to (V+) – 1 V
120
130
G = 1, VCM = (V–) to (V+) – 1 V,
TA = –40°C to +125°C
MHz
(V+) – 1
80
G = 1, VCM = (V–) to (V+) – 1 V
84
G = 10, VCM = (V–) to (V+) – 1 V
100
G = 100, VCM = (V–) to (V+) – 1 V
105
G = 1000, VCM = (V–) to (V+) – 1 V
105
V
dB
BIAS CURRENT
IB
Input bias current
IOS
Input offset current
VCM = VS / 2
35
TA = –40°C to +125°C
VCM = VS / 2
65
95
0.7
TA = –40°C to +125°C
5
10
nA
nA
NOISE VOLTAGE
eNI
eNO
In
(1)
(2)
f = 1 kHz, G = 100, RS = 0 Ω
Input stage voltage noise (3)
Output stage voltage noise
Noise current
(3)
18
fB = 0.1 Hz to 10 Hz, G = 100, RS = 0 Ω
0.52
f = 1 kHz, G = 1, RS = 0 Ω
110
20
nV/√Hz
115
nV/√Hz
µVPP
fB = 0.1 Hz to 10 Hz, G = 1, RS = 0 Ω
3.3
µVPP
f = 1 kHz
100
fA/√Hz
fB = 0.1 Hz to 10 Hz
5
pAPP
Total offset, referred-to-input (RTI): VOS = (VOSI) + (VOSO / G).
Input voltage range of the INA826 input stage. The input range depends on the common-mode voltage, differential voltage, gain, and
reference voltage. See Typical Characteristic curves Figure 9 through Figure 16 and Figure 41 through Figure 44 for more information.
(3)
(eNI)2 +
Total RTI voltage noise =
6
eNO
G
2
.
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SBOS562G – AUGUST 2011 – REVISED JUNE 2020
Electrical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
GAIN
49.4 kW
G
1+
Gain equation
Range of gain
GE
Gain error
Gain vs temperature (4)
Gain nonlinearity
V/V
RG
1
1000
G = 1, VO = ±10 V
±0.003%
±0.015%
G = 10, VO = ±10 V
±0.03%
±0.15%
G = 100, VO = ±10 V
±0.04%
±0.15%
G = 1000, VO = ±10 V
±0.04%
±0.15%
G = 1, TA = –40°C to +125°C
±0.1
±1
G > 1, TA = –40°C to +125°C
±10
±35
G = 1 to 100, VO = –10 V to +10 V
1
5
G = 1000, VO = –10 V to +10 V
5
20
V/V
ppm/°C
ppm
OUTPUT
Voltage swing
RL = 10 kΩ
(V–) + 0.1
Load capacitance stability
ZO
Open-loop output impedance
ISC
Short-circuit current
(V+) – 0.15
V
1000
pF
See Figure 56
Continuous to VS / 2
±16
mA
1
MHz
FREQUENCY RESPONSE
G=1
BW
SR
Bandwidth, –3 dB
Slew rate
G = 10
500
G = 100
60
G = 1000
6
G = 1, VO = ±14.5 V
1
G = 100, VO = ±14.5 V
1
0.01%
tS
Settling time
0.001%
G = 1, VSTEP = 10 V
12
G = 10, VSTEP = 10 V
12
G = 100, VSTEP = 10 V
24
G = 1000, VSTEP = 10 V
224
G = 1, VSTEP = 10 V
14
G = 10, VSTEP = 10 V
14
G = 100, VSTEP = 10 V
31
G = 1000, VSTEP = 10 V
278
kHz
V/µs
µs
REFERENCE INPUT
RIN
Input impedance
100
Voltage range
(V–)
Gain to output
kΩ
(V+)
1
Reference gain error
V
V/V
0.01%
POWER SUPPLY
IQ
(4)
Quiescent current
VIN = 0 V
200
250
vs temperature, TA = –40°C to +125°C
250
300
µA
The values specified for G > 1 do not include the effects of the external gain-setting resistor, RG.
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7.6 Typical Characteristics
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
1600
25
1400
20
1200
Count
Count
1000
800
15
10
600
400
5
200
0
−200
−180
−160
−140
−120
−100
−80
−60
−40
−20
0
20
40
60
80
100
120
140
160
180
200
−2
−1.8
−1.6
−1.4
−1.2
−1
−0.8
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
0
Input Offset Voltage (µV)
Input Offset Voltage Drift (µV/°C)
G026
Figure 1. Typical Distribution of Input Offset Voltage
G029
Figure 2. Typical Distribution of Input Offset Voltage Drift
25
1600
1400
20
1200
Count
Count
1000
800
15
10
600
400
5
200
0
−1000
−900
−800
−700
−600
−500
−400
−300
−200
−100
0
100
200
300
400
500
600
700
800
900
1000
−10
−9
−8
−7
−6
−5
−4
−3
−2
−1
0
1
2
3
4
5
6
7
8
9
10
0
Output Offset Voltage (µV)
Output Offset Voltage Drift (mV/°C)
G025
Figure 3. Typical Distribution of Output Offset Voltage
G030
Figure 4. Typical Distribution of Output Offset Voltage Drift
2000
3000
2500
1500
Count
Count
2000
1000
1500
1000
500
500
0
Input Bias Current (nA)
Input Offset Current (nA)
G027
Figure 5. Typical Distribution of Input Bias Current
8
−5
−4.5
−4
−3.5
−3
−2.5
−2
−1.5
−1
−0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
0
G028
Figure 6. Typical Distribution of Input Offset Current
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SBOS562G – AUGUST 2011 – REVISED JUNE 2020
Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
32000
16000
Wafer Probe Data
14000
24000
12000
20000
10000
Count
28000
16000
8000
12000
6000
8000
4000
4000
2000
0
0
Gain Error Drift (ppm/°C)
−20
−19
−18
−17
−16
−15
−14
−13
−12
−11
−10
−9
−8
−7
−6
−5
−4
−3
−2
−1
0
−1
−0.9
−0.8
−0.7
−0.6
−0.5
−0.4
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Count
Wafer Probe Data
Gain Error Drift (ppm/°C)
G052
G=1
Figure 7. Typical Gain Error Drift Distribution
Figure 8. Typical Gain Error Drift Distribution
Single supply
Single supply
Figure 9. Input Common-Mode Voltage vs Output Voltage
Figure 10. Input Common-Mode Voltage vs Output Voltage
5
5
VREF = 0 V
VREF = 2.5 V
4
3.5
3
2.5
2
1.5
1
0.5
0
0
0.5
1
1.5
2
2.5
3
3.5
Output Voltage (V)
4
4.5
VREF = 0 V
VREF = 2.5 V
4.5
Common−Mode Voltage (V)
Common−Mode Voltage (V)
4.5
−0.5
−1
G051
G>1
5
4
3.5
3
2.5
2
1.5
1
0.5
0
−0.5
−1
0
G034
Single supply
0.5
1
1.5
2
2.5
3
3.5
Output Voltage (V)
4
4.5
5
G037
Single supply
Figure 11. Input Common-Mode Voltage vs Output Voltage
Figure 12. Input Common-Mode Voltage vs Output Voltage
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Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
5
3
G=1
G = 100
1
0
−1
−2
−3
3
2
1
0
−1
−2
−3
−4
−5
−4
−3
−2
−1
0
1
Output Voltage (V)
2
3
−6
4
−6
−5
G039
Dual supply
Common−Mode Voltage (V)
Common−Mode Voltage (V)
VS= ±15 V
VS= ±12 V
8 10 12 14 16
G040
3
4
5
6
G038
16
14
12
10
8
6
4
2
0
−2
−4
−6
−8
−10
−12
−14
−16
−16−14−12−10 −8 −6 −4 −2 0 2 4 6
Output Voltage (V)
VS= ±15 V
VS= ±12 V
8 10 12 14 16
G040
Dual supply
Figure 15. Input Common-Mode Voltage vs Output Voltage
Figure 16. Input Common-Mode Voltage vs Output Voltage
12m
16
8m
16
9m
12
6m
12
6m
8
4m
8
3m
4
2m
4
0
0
0
0
−4
−6m
−8
IIN
VOUT
−9m
Input Current (A)
−3m
Output Voltage (V)
Input Current (A)
−2 −1 0
1
2
Output Voltage (V)
Figure 14. Input Common-Mode Voltage vs Output Voltage
Dual supply
−2m
−4
−4m
−8
IIN
VOUT
−6m
−12
−12m
−16
−40−35−30−25−20−15−10 −5 0 5 10 15 20 25 30 35 40
Input Voltage (V)
G065
−12
−8m
−16
−40−35−30−25−20−15−10 −5 0 5 10 15 20 25 30 35 40
Input Voltage (V)
G064
G=1
G=1
Figure 17. Input Overvoltage vs Input Current
10
−3
Dual supply
Figure 13. Input Common-Mode Voltage vs Output Voltage
16
14
12
10
8
6
4
2
0
−2
−4
−6
−8
−10
−12
−14
−16
−16−14−12−10 −8 −6 −4 −2 0 2 4 6
Output Voltage (V)
−4
Output Voltage (V)
−4
G=1
G = 100
4
Common−Mode Voltage (V)
Common−Mode Voltage (V)
2
Figure 18. Input Overvoltage vs Input Current
With 10-kΩ Resistance
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Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
140
Common−Mode Rejection Ratio (dB)
Common−Mode Rejection Ratio (dB)
160
140
120
100
80
60
G=1
G = 10
G = 100
G = 1000
40
20
0
10
100
1k
Frequency (Hz)
10k
120
100
80
60
40
G=1
G = 10
G = 100
G = 1000
20
0
100k
10
160
160
140
140
120
100
80
60
G=1
G = 10
G = 100
G = 1000
20
0
10
1k
Frequency (Hz)
10k
100k
G002
100
80
60
G=1
G = 10
G = 100
G = 1000
40
0
100k
10
100
G003
Figure 21. Positive PSRR vs Frequency (RTI)
1k
Frequency (Hz)
10k
100k
G004
Figure 22. Negative PSRR vs Frequency (RTI)
1k
70
50
40
Voltage Noise (nV/ Hz)
G=1
G = 10
G = 100
G = 1000
60
Gain (dB)
10k
120
20
100
1k
Frequency (Hz)
Figure 20. CMRR vs Frequency
(RTI, 1-kΩ Source Imbalance)
Negative Power−Supply
Rejection Ratio (dB)
Positive Power−Supply
Rejection Ratio (dB)
Figure 19. CMRR vs Frequency (RTI)
40
100
G001
30
20
10
0
−10
G=1
G = 10
G = 100
G = 1000
100
−20
−30
10
100
1k
10k
100k
Frequency (Hz)
1M
10M
10
1
G005
Figure 23. Gain vs Frequency
10
100
1k
Frequency (Hz)
10k
100k
G019
Figure 24. Voltage Noise Spectral Density
vs Frequency (RTI)
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Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
1k
3
Noise (µV/div)
Current Noise (fA/ Hz)
2
100
1
0
−1
−2
10
1
10
100
Frequency (Hz)
1k
−3
10k
0
1
2
3
G020
4
5
6
Time (s/div)
7
8
9
10
G007
G=1
Figure 25. Current Noise Spectral Density vs Frequency
(RTI)
Figure 26. 0.1-Hz to 10-Hz RTI Voltage Noise
400
15
300
10
Noise (pA/div)
Noise (nV/div)
200
100
0
−100
5
0
−5
−200
−10
−300
−400
0
1
2
3
4
5
6
Time (s/div)
7
8
9
−15
10
0
1
2
3
G006
4
5
6
Time (s/div)
7
8
9
10
G008
G = 1000
Figure 27. 0.1-Hz to 10-Hz RTI Voltage Noise
Figure 28. 0.1-Hz to 10-Hz RTI Current Noise
0
0
−40°C
+25°C
+125°C
−20
−10
Input Bias Current (nA)
Input Bias Current (nA)
−10
−30
−40
−50
−60
−70
−80
−20
−40°C
+25°C
+125°C
−30
−40
−50
−60
−70
−1
−0.5
0
0.5
1
1.5
2
Common Mode Voltage (V)
2.5
3
−80
−16
G056
−12
−8
−4
0
4
8
Common Mode Voltage (V)
12
16
G055
VS = 3.0 V
Figure 29. Input Bias Current vs Common-Mode Voltage
12
Figure 30. Input Bias Current vs Common-Mode Voltage
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Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
100
10
Representative Data
Input Offset Current − IOS (nA)
Input Bias Current − IB (nA)
90
80
70
60
50
40
30
20
10
6
4
2
0
−2
−4
−6
−8
0
−50
−25
0
25
50
75
Temperature (°C)
100
125
−10
−50
150
2000
30
1500
20
25
50
75
Temperature (°C)
100
125
150
G053
1000
Gain Error (ppm)
10
0
−10
−20
−30
500
0
−500
−1000
−40
−60
−50
0
Figure 32. Input Offset Current vs Temperature
40
−50
−25
G033
Figure 31. Input Bias Current vs Temperature
Gain Error (ppm)
Max Data
Min Data
Unit 1
Unit 2
Unit 3
8
Representative Data
Normalized at +25°C
−25
0
25
50
75
Temperature (°C)
−1500
100
125
150
−2000
−50
G031
G=1
Representative Data
Normalized at +25°C
−25
0
25
50
75
Temperature (°C)
100
125
150
G054
G>1
Figure 33. Gain Error vs Temperature
Figure 34. Gain Error vs Temperature
10
8
CMRR (µV/V)
6
4
2
0
−2
−4
−6
−8
−10
−50
Representative Data
Normalized at +25°C
−25
0
25
50
75
Temperature (°C)
100
125
150
G032
G=1
Figure 35. CMRR vs Temperature
Figure 36. Supply Current vs Temperature
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Typical Characteristics (continued)
4
4
3
3
Nonlinearity (ppm)
Nonlinearity (ppm)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
2
1
2
1
0
−10
−8
−6
−4
−2
0
2
4
Output Voltage (V)
6
8
0
−10
10
−8
−6
−4
G021
G=1
−11
−2
−12
−4
−13
−14
−15
−16
−17
−8
−12
−14
−16
−18
−2
0
2
4
Output Voltage (V)
6
8
−20
−10
10
−8
−6
G023
G = 100
Figure 39. Gain Nonlinearity
6
8
10
G024
Figure 40. Gain Nonlinearity
VS = ±15 V
−50°C
−40°C
+25°C
+85°C
+125°C
+150°C
250
200
50
150
100
50
−50
−100
−150
−200
−250
0
−300
−50
−350
−100
−15.5
−15.3
−15.1
−14.9
−14.7
Common Mode Voltage (V)
VS = ±15 V
0
Offset Voltage (µV)
Offset Voltage (µV)
−2
0
2
4
Output Voltage (V)
100
300
−14.5
−400
13.8
G057
Figure 41. Offset Voltage vs Negative Common-Mode
Voltage
14
−4
G = 1000
400
350
G022
−10
−19
−4
10
−6
−18
−6
8
Figure 38. Gain Nonlinearity
0
Nonlinearity (ppm)
Nonlinearity (ppm)
Figure 37. Gain Nonlinearity
−8
6
G = 10
−10
−20
−10
−2
0
2
4
Output Voltage (V)
−50°C
−40°C
+25°C
+85°C
+125°C
+150°C
13.9
14
14.1
14.2
Common Mode Voltage (V)
14.3
14.4
G058
Figure 42. Offset Voltage vs Positive Common-Mode
Voltage
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Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
Figure 43. Offset Voltage vs Negative Common-Mode
Voltage
Figure 44. Offset Voltage vs Positive Common-Mode
Voltage
15
−14
−14.2
Output Voltage (V)
Output Voltage (V)
14.8
14.6
−50°C
−40°C
+25°C
+85°C
+125°C
+150°C
14.4
14.2
14
−50°C
−40°C
+25°C
+85°C
+125°C
+150°C
0
2
4
−14.4
−14.6
−14.8
6
8
10
Output Current (mA)
12
14
16
−15
0
G045
2
4
6
8
10
Output Current (mA)
12
14
16
G046
Figure 45. Positive Output Voltage Swing vs Output Current
Figure 46. Negative Output Voltage Swing vs Output Current
Figure 47. Positive Output Voltage Swing vs Output Current
Figure 48. Negative Output Voltage Swing vs Output Current
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Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
25
30
VS = ±15 V
VS = +5 V
27
0.01%
0.001%
21
21
Settling Time (µs)
Output Voltage (V)
24
18
15
12
9
17
13
9
6
3
0
1k
10k
100k
Frequency (Hz)
5
1M
2
80
80
60
60
40
0 pF
0
100 pF
−20
220 pF
500 pF
−40
1 nF
−60
16
18
20
G061
20
0
−20
−40
−80
0
8
16
24
Time (ps)
32
40
−100
48
0
5
10
15
G013
20
25
time (us)
30
35
40
G009
G = 1, RL = 1 kΩ, CL = 100 pF
Figure 51. Small-Signal Response Over Capacitive Loads
Figure 52. Small-Signal Response
100
100
80
80
60
60
40
40
Amplitude (mV)
Amplitude (mV)
10
12
14
Step Size (V)
40
G=1
20
0
−20
−40
−60
20
0
−20
−40
−60
−80
−80
−100
−100
0
5
10
15
20
25
time (us)
30
35
40
0
G010
G = 10, RL = 10 kΩ, CL = 100 pF
20
40
60
80
100 120 140 160 180 200
time (us)
G011
G = 100, RL = 10 kΩ, CL = 100 pF
Figure 53. Small-Signal Response
16
8
−60
−80
−100
6
Figure 50. Settling Time vs Step Size
100
Amplitude (mV)
Amplitude (mV)
Figure 49. Large-Signal Frequency Response
100
20
4
G014
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Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
100
100k
80
40
10k
20
ZO (Ω)
Amplitude (mV)
60
0
−20
1k
−40
−60
−80
−100
0
100 200 300 400 500 600 700 800 900 1000
time (us)
G012
100
1
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
G062
G = 1000, RL = 10 kΩ, CL = 100 pF
Figure 55. Small-Signal Response
Figure 56. Open-Loop Output Impedance
Change in Input Offset Voltage (µV)
15
10
5
0
−5
−10
−15
0
2
4
6
8
10
Warm−up Time (s)
12
14
16
G063
Figure 57. Change in Input Offset Voltage vs Warm-Up Time
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8 Detailed Description
8.1 Overview
The Functional Block Diagram section shows the basic connections required for operation of the INA826. Good
layout practice mandates the use of bypass capacitors placed as close to the device pins as possible.
The output of the INA826 is referred to the output reference (REF) terminal, which is normally grounded. This
connection must be low-impedance to maintain good common-mode rejection. Although 5 Ω or less of stray
resistance can be tolerated when maintaining specified CMRR, small stray resistances of tens of ohms in series
with the REF pin can cause noticeable degradation in CMRR.
8.2 Functional Block Diagram
V+
0.1 mF
8
(1)
RS
-IN
1
RFI Filter
50 kW
50 kW
A1
VO = G ´ (VIN+ - VIN-)
2
24.7 kW
RG
G=1+
7
A3
24.7 kW
+
3
Load VO
50 kW
(1)
RS
+IN
49.4 kW
RG
-
50 kW
6
A2
4
REF
RFI Filter
Device
5
0.1 mF
V-
Also drawn in simplified form:
-IN
RG
+IN
Device
VO
REF
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(1)
18
This resistor is optional if the input voltage stays above [(V–) – 2 V] or if the signal source current drive capability is
limited to less than 3.5 mA; see the Input Protection section for more details.
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8.3 Feature Description
8.3.1 Inside the INA826
See the Functional Block Diagram section for a simplified representation of the INA826. A more detailed
diagram, shown in Figure 58, provides additional insight into the INA826 operation.
Each input is protected by two field-effect transistors (FETs) that provide a low series resistance under normal
signal conditions, and preserve excellent noise performance. When excessive voltage is applied, these
transistors limit input current to approximately 8 mA.
The differential input voltage is buffered by Q1 and Q2 and is impressed across RG, causing a signal current to
flow through RG, R1, and R2. The output difference amplifier, A3, removes the common-mode component of the
input signal and refers the output signal to the REF terminal.
The equations shown in Figure 58 describe the output voltages of A1 and A2. The VBE and voltage drop across
R1 and R2 produce output voltages on A1 and A2 that are approximately 0.8 V higher than the input voltages.
+VS
VB
RB
IB Cancellation
RB
IB Cancellation
±VS +VS
50 k
±
±
+
±
+
50 k
A1
A2
A3
OUT
+
50 k
REF
50 k
+VS
+VS
±VS +VS
Q1
±IN
Overvoltage
Protection
SuperNPN
+VS
R1
24.7 k
+VS
RG
±VS
Q2
+IN
Overvoltage
Protection
R2
24.7 k
RG
(External)
±VS
SuperNPN
±VS
RG
±VS
Figure 58. INA826 Simplified Circuit Diagram
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Feature Description (continued)
8.3.2 Setting the Gain
Gain of the INA826 is set by a single external resistor, RG, connected between pins 2 and 3. The value of RG is
selected according to Equation 1:
G=1+
49.4 kW
RG
(1)
Table 1 lists several commonly-used gains and resistor values. The 49.4-kΩ term in Equation 1 comes from the
sum of the two internal 24.7-kΩ feedback resistors. These on-chip resistors are laser-trimmed to accurate
absolute values. The accuracy and temperature coefficients of these resistors are included in the gain accuracy
and drift specifications of the INA826.
Table 1. Commonly-Used Gains and Resistor Values
DESIRED GAIN (V/V)
RG (Ω)
1
—
NEAREST 1% RG (Ω)
—
2
49.4 k
49.9 k
5
12.35 k
12.4 k
10
5.489 k
5.49 k
20
2.600 k
2.61 k
50
1.008 k
1k
100
499
499
200
248
249
500
99
100
1000
49.5
49.9
8.3.2.1 Gain Drift
The stability and temperature drift of the external gain setting resistor, RG, also affects gain. The contribution of
RG to gain accuracy and drift is directly inferred from the gain of Equation 1.
The best gain drift of 1 ppm/℃ is achieved when the INA826 uses G = 1 without RG connected. In this case, the
gain drift is limited only by the slight mismatch of the temperature coefficient of the integrated 50-kΩ resistors in
the differential amplifier (A3). At G greater than 1, the gain drift increases as a result of the individual drift of the
24.7-kΩ resistors in the feedback of A1 and A2, relative to the drift of the external gain resistor RG. Process
improvements of the temperature coefficient of the feedback resistors now make possible specifying a maximum
gain drift of the feedback resistors of 35 ppm/℃, thus significantly improving the overall temperature stability of
applications using gains greater than 1.
Low resistor values required for high gain can make wiring resistance important. Sockets add to the wiring
resistance and contribute additional gain error (such as a possible unstable gain error) at gains of approximately
100 or greater. To maintain stability, avoid parasitic capacitance of more than a few picofarads at RG
connections. Careful matching of any parasitics on both RG pins maintains optimal CMRR over frequency; see
Figure 19 and Figure 20.
20
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8.3.3 Offset Trimming
Most applications require no external offset adjustment; however, if necessary, adjustments can be made by
applying a voltage to the REF terminal. Figure 59 shows an optional circuit for trimming the output offset voltage.
The voltage applied to the REF terminal is summed at the output. The op amp buffer provides low impedance at
the REF terminal to preserve good common-mode rejection.
VIN-
V+
RG
VIN+
VO
INA826
100 mA
1/2 REF200
REF
OPA333
±10 mV
Adjustment Range
100 Ω
10 kΩ
100 Ω
100 mA
1/2 REF200
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Figure 59. Optional Trimming of the Output Offset Voltage
8.3.4 Input Common-Mode Range
The linear input voltage range of the INA826 input circuitry extends from the negative supply voltage to 1 V
below the positive supply and maintains 84-dB (minimum) common-mode rejection throughout this range. The
common-mode range for most common operating conditions is described in the input common-mode voltage
versus output voltage Typical Characteristics curves (Figure 9 through Figure 15) and the offset voltage versus
common-mode voltage curves (Figure 41 through Figure 43). The INA826 operates over a wide range of power
supplies and VREF configurations, thus providing a comprehensive guide to common-mode range limits for all
possible conditions is impractical.
The most commonly overlooked overload condition occurs when a circuit exceeds the output swing of A1 and A2,
which are internal circuit nodes that cannot be measured. Calculating the expected voltages at the output of A1
and A2 (see Figure 58) provides a check for the most common overload conditions. The designs of A1 and A2 are
identical and the outputs can swing to within approximately 100 mV of the power-supply rails. For example, when
the A2 output is saturated, A1 can still be in linear operation, responding to changes in the noninverting input
voltage. This difference can give the appearance of linear operation but the output voltage is invalid.
A single-supply instrumentation amplifier has special design considerations. To achieve a common-mode range
that extends to single-supply ground, the INA826 employs a current-feedback topology with PNP input
transistors; see Figure 58. The matched PNP transistors Q1 and Q2 shift the input voltages of both inputs up by a
diode drop, and (through the feedback network) shift the output of A1 and A2 by approximately 0.8 V. With both
inputs and VREF at single-supply ground (negative power supply), the output of A1 and A2 is well within the linear
range, allowing differential measurements to be made at the GND level. As a result of this input level-shifting, the
voltages at pin 2 and pin 3 are not equal to the respective input terminal voltages (pin 1 and pin 4). For most
applications, this inequality is not important because only the gain-setting resistor connects to these pins.
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8.3.5 Input Protection
The inputs of the INA826 are individually protected for voltages up to ±40 V. For example, a condition of –40 V
on one input and +40 V on the other input does not cause damage. However, if the input voltage exceeds (V–) –
2 V and the signal source current drive capability exceeds 3.5 mA, the output voltage switches to the opposite
polarity; see Figure 17. This polarity reversal can easily be avoided by adding resistance of 10 kΩ in series with
both inputs.
Internal circuitry on each input provides low series impedance under normal signal conditions. If the input is
overloaded, the protection circuitry limits the input current to a safe value of approximately 8 mA. Figure 17 and
Figure 18 illustrate this input current limit behavior. The inputs are protected even if the power supplies are
disconnected or turned off.
8.3.6 Input Bias Current Return Path
The input impedance of the INA826 is extremely high (approximately 20 GΩ). However, a path must be provided
for the input bias current of both inputs. This input bias current is typically 35 nA. High input impedance means
that this input bias current changes very little with varying input voltage.
Input circuitry must provide a path for this input bias current for proper operation. Figure 60 shows various
provisions for an input bias current path. Without a bias current path, the inputs float to a potential that exceeds
the common-mode range of the INA826 and the input amplifiers saturate. If the differential source resistance is
low, the bias current return path can be connected to one input (as shown in the thermocouple example in
Figure 60). With higher source impedance, using two equal resistors provides a balanced input with possible
advantages of lower input offset voltage as a result of bias current and better high-frequency common-mode
rejection.
Microphone,
Hydrophone,
etc.
Device
47 kW
47 kW
Thermocouple
Device
10 kW
Device
Center tap provides
bias current return.
Figure 60. Providing an Input Common-Mode Current Path
22
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8.3.7 Reference Terminal
The output voltage of the INA826 is developed with respect to the voltage on the reference pin. Often in dualsupply operation, the reference pin (pin 6) is connected to the low-impedance system ground. In single-supply
operation, offsetting the output signal to a precise midsupply level can be useful (for example, 2.5 V in a 5-V
supply environment). To accomplish this level shift, tie a voltage source to the REF pin to level-shift the output so
that the INA826 can drive a single-supply ADC, for example.
For best performance, keep the source impedance to the REF pin less than 5 Ω. As illustrated in the Functional
Block Diagram section, the reference resistor is at one end of a 50-kΩ resistor. Additional impedance at the REF
pin adds to this 50-kΩ resistor. The imbalance in the resistor ratios results in degraded common-mode rejection
ratio (CMRR).
Figure 61 shows two different methods of driving the reference pin with low impedance. The OPA330 is a lowpower, chopper-stabilized amplifier, and therefore offers excellent stability over temperature. The OPA330 is
available in the space-saving SC70 and even smaller chip-scale package. The REF3225 is a precision reference
in the small SOT23-6 package.
+5 V
VIN-
+5 V
RG
VOUT
INA826
VIN-
REF
VIN+
+5 V
RG
VOUT
INA826
REF
+5 V
VIN+
+2.5 V
OPA330
a) Level shifting using the OPA330 as a low-impedance buffer
REF3225
+5 V
b) Level shifting using the low-impedance output of the REF3225
Figure 61. Options for Low-Impedance Level Shifting
8.3.8 Dynamic Performance
Figure 23 illustrates that, despite its low quiescent current of only 200 µA, the INA826 achieves much wider
bandwidth than other INAs in its class. This achievement is a result of using TI’s proprietary high-speed precision
bipolar process technology. The current-feedback topology provides the INA826 with wide bandwidth even at
high gains. Settling time also remains excellent at high gain because of a high slew rate of 1 V/µs.
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8.3.9 Operating Voltage
The INA826 operates over a power-supply range of 3 V to 36 V (±1.5 V to ±18 V). Supply voltages higher than
40 V (±20 V) can permanently damage the device. Parameters that vary over supply voltage or temperature are
shown in the Typical Characteristics section of this data sheet.
8.3.9.1 Low-Voltage Operation
The INA826 can operate on power supplies as low as ±1.5 V. Most parameters vary only slightly throughout this
supply voltage range; see the Typical Characteristics section. Operation at very-low supply voltage requires
careful attention to make sure that the input voltages remain within the linear range. Voltage swing requirements
of internal nodes limit the input common-mode range with low power-supply voltage. Figure 9 through Figure 15
and Figure 41 through Figure 43 describe the range of linear operation for various supply voltages, reference
connections, and gains.
8.3.10 Error Sources
Most modern signal-conditioning systems calibrate errors at room temperature. However, calibration of errors
that result from a change in temperature is normally difficult and costly. Therefore, minimizing these errors is
important. Make sure to choose high-precision components, such as the INA826, that have improved
specifications in critical areas that impact the precision of the overall system. Figure 62 shows an example
application.
RS+ = 10 kW
VDIFF = 1 V
5.49 kW
+15 V
VOUT
Device
REF
VCM = 10 V
RS- = 9.9 kW
Signal Bandwidth: 5 kHz
- 15 V
Figure 62. Example Application With G = 10 V/V and 1-V Differential Voltage
Resistor-adjustable INAs, such as the INA826, show the lowest gain error in G = 1 because of the inherently
well-matched drift of the internal resistors of the differential amplifier. At gains greater than 1 (for instance, G =
10 V/V or G = 100 V/V), the gain error becomes a significant error source because of the contribution of the
resistor drift of the 24.7-kΩ feedback resistors in conjunction with the external gain resistor. Except for very high
gain applications, the gain drift is by far the largest error contributor compared to other drift errors, such as offset
drift.
24
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The INA826 offers excellent gain error over temperature for both G > 1 and G = 1 (no external gain resistor).
Table 2 summarizes the major error sources in common INA applications and compares the two cases of G = 1
(no external resistor) and G = 10 (5.49-kΩ external resistor). As can be seen in Table 2, although the static errors
(absolute accuracy errors) in G = 1 are almost twice as great as compared to G = 10, there are much fewer drift
errors because of the much lower gain error drift. In most applications, these static errors can readily be removed
during calibration in production. All calculations refer the error to the input for easy comparison and system
evaluation.
Table 2. Error Calculations
INA826
ERROR SOURCE
ERROR CALCULATION
SPECIFICATION
G = 10 ERROR
(ppm)
G = 1 ERROR
(ppm)
ABSOLUTE ACCURACY AT 25°C
Input offset voltage (µV)
VOSI / VDIFF
150
150
150
Output offset voltage (µV)
VOSO / (G × VDIFF)
700
70
700
Input offset current (nA)
IOS × maximum (RS+, RS–) / VDIFF
5
50
50
104 (G = 10),
84 (G = 1)
63
631
333
1531
35 (G = 10),
1 (G = 1)
2800
80
CMRR (dB)
VCM / (10CMRR/20 × VDIFF)
Total absolute accuracy error (ppm)
DRIFT TO 105°C
Gain drift (ppm/°C)
GTC × (TA – 25)
Input offset voltage drift (µV/°C)
(VOSI_TC / VDIFF) × (TA – 25)
2
160
160
Output offset voltage drift (µV/°C)
[VOSO_TC / ( G × VDIFF)] × (TA – 25)
10
80
800
Offset current drift (pA/°C)
IOS_TC × maximum (RS+, RS–) ×
(TA – 25) / VDIFF
60
48
48
3088
1088
5
5
5
eNI = 18,
eNO = 110
10
10
15
15
3436
2634
Total drift error (ppm)
RESOLUTION
Gain nonlinearity (ppm of FS)
Voltage noise (1 kHz)
BW ´
(eNI2 +
eNO
G
2
6
´
VDIFF
Total resolution error (ppm)
TOTAL ERROR
Total error
Total error = sum of all error sources
8.4 Device Functional Modes
The INA826 has a single functional mode and is operational when the power-supply voltage is greater than 3 V
(±1.5 V). The maximum power-supply voltage for the INA826 is 36 V (±18 V).
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The low power consumption and high performance of the INA826 make the device an excellent instrumentation
amplifier for many applications. The INA826 can be used in many low-power, portable applications because the
device has a low quiescent current (200 µA, typical) and comes in a small 8-pin WSON package. The input
protection circuitry, low maximum gain drift, low offset voltage, and 36-V maximum supply voltage also make the
INA826 an excellent choice for industrial applications as well.
9.2 Typical Application
Figure 63 shows a three-terminal programmable-logic controller (PLC) design for the INA826. This PLC
reference design accepts inputs of ±10 V or ±20 mA. The output is a single-ended voltage of 2.5 V ±2.3 V (or
200 mV to 4.8 V). Many PLCs typically have these input and output ranges.
±10 V
R1 = 100 NŸ
5V
15 V
R2 = 4.12 NŸ
±20 mA
REF3225
v
R3 =
V+
INA826
RG = 10.4 NŸ
VREF
RO = 100 Ÿ
VOUT
2.5 V ± 2.3 V
20 Ÿ
+
V
RL = 10 NŸ
CO = 1.59 nF
15 V
Copyright © 2016, Texas Instruments Incorporated
Figure 63. Three-Terminal PLC Design
9.2.1 Design Requirements
This design has the following requirements:
•
•
•
26
Supply voltage: ±15 V, 5 V
Inputs: ±10 V, ±20 mA
Output: 2.5 V, ±2.3 V
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Typical Application (continued)
9.2.2 Detailed Design Procedure
There are two modes of operation for the circuit shown in Figure 63: current input and voltage input. This design
requires R1 >> R2 >> R3. Given this relationship, the current input mode transfer function is given by Equation 2.
VOUT-I = VD ´ G + VREF = -(IIN ´ R3) ´ G + VREF
where
•
G represents the gain of the instrumentation amplifier
(2)
The transfer function for the voltage input mode is shown by Equation 3.
R2
VOUT-V = VD ´ G + VREF = - VIN ´
´ G + VREF
R 1 + R2
(3)
R1 sets the input impedance of the voltage input mode. The minimum typical input impedance is 100 kΩ. This
value is selected for R1 because increasing the R1 value also increases noise. The value of R3 must be
extremely small compared to R1 and R2. 20 Ω for R3 is selected because that resistance value is much smaller
than R1 and yields an input voltage of ±400 mV when operated in current mode (±20 mA).
Equation 4 can be used to calculate R2 given VD = ±400 mV, VIN = ±10 V, and R1 = 100 kΩ.
R2
R ´ VD
VD = VIN ´
® R2 = 1
= 4.167 kW
R 1 + R2
VIN - VD
(4)
The value obtained from Equation 4 is not a standard 0.1% value, so 4.12 kΩ is selected. R1 and R2 also use
0.1% tolerance resistors to minimize error.
The ideal gain of the instrumentation amplifier is calculated with Equation 5.
V
- VREF 4.8 V - 2.5 V
V
= 5.75 V
G = OUT
=
VD
400 mV
(5)
Using the INA826 gain equation, Equation 1, the gain-setting resistor value is calculated as shown by Equation 6.
49.4 kW
49.4 kW
49.4 kW
GINA826 = 1 + R
® RG =
=
= 10.4 kW
5.75
-1
G
1
G
INA826
(6)
10.4 kΩ is a standard 0.1% resistor value that can be used in this design. Finally, the output RC filter
components are selected to have a –3-dB cutoff frequency of 1 MHz.
9.2.3 Application Curves
5
5
4
4
Output Voltage (V)
Output Voltage (V)
Figure 64 and Figure 65 illustrate typical characteristic curves for Figure 63.
3
2
1
3
2
1
0
−10
−5
0
Input Voltage (V)
5
10
0
−0.02
G071
Figure 64. PLC Output Voltage vs Input Voltage
−0.01
0
Input Current (A)
0.01
0.02
G070
Figure 65. PLC Output Voltage vs Input Current
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9.3 System Examples
9.3.1 Circuit Breaker
Figure 66 shows the INA826 used in a circuit breaker application.
3V
AVDD
DVDD
SCLK
Serial
Interface
(SPI)
Passive
Integrator
100 kW
RG
DIO
MSP430
Microcontroller
CS
INA826
IP
Ch 1
Mux
ADC
REF
G=1
Rogowski
Coil
100 kW
PGA112
PGA113
3V
GND
REF3312
REF
1.2 V
Copyright © 2017, Texas Instruments Incorporated
Figure 66. Circuit Breaker Example
9.3.2 Programmable Logic Controller (PLC) Input
The INA826 used in an example programmable logic controller (PLC) input application is shown in Figure 67.
±10 V
100 kW
15 V
4.87 kW
4 mA to 20 mA
±20 mA
20 W
12.4 kW
VOUT = 2.5 V ± 2.3 V
TI Device
REF
-15 V
2.5 V
REF3225
5V
Copyright © 2017, Texas Instruments Incorporated
Figure 67. ±10-V, 4-mA to 20-mA PLC Input
Additional application ideas are illustrated in Figure 68 to Figure 72.
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System Examples (continued)
9.3.3 Using TINA-TI SPICE-Based Analog Simulation Program With the INA826
TINA is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a
free, fully-functional version of the TINA software, preloaded with a library of macromodels in addition to a range
of both passive and active models. TINA provides all the conventional dc, transient, and frequency domain
analysis of SPICE as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer users the ability to
select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
Figure 68 and Figure 70 illustrate example TINA-TI circuits for the INA826 that can be used to develop, modify,
and assess the circuit design for specific applications. Links to download these simulation files are provided in
this section.
NOTE
These files require that either the TINA software (from DesignSoft) or TINA-TI software be
installed. Download the free TINA-TI software from the TINA-TI folder.
The circuit in Figure 68 is used to convert inputs of ±10 V, ±5 V, or ±20 mA to an output voltage range from 0.5 V
to 4.5 V. The input selection depends on the settings of SW1 and SW2. Further explanation as well as the TINATI simulation circuit is provided in the compressed file that can be downloaded at the following link: PLC Circuit.
+Vs
V1 15
CurrentInput
V2 15
Source_Switch
Vin
Iin
+ Terminal
Iin
Vin
+Vs
Ref
RG 49.9 k
VoltageInput
R4 250
SW2
Rg
±
Amp Out
INA Out
+
+
Rg
SW1
+
+
Ref 1
U2 INA826
Vs 5
- Terminal
-Vs
Sense
±
U1 INA159 +
Ref 2
ADC_Diff
±
Vref 2.5
-Vs
Copyright © 2017, Texas Instruments Incorporated
Figure 68. Two-Terminal Programmable Logic Controller (PLC) Input
Figure 69 is an example of a LEAD I ECG circuit. The input signals come from leads attached to the right arm
(RA) and left arm (LA). These signals are simulated with the circuitry in the corresponding boxes. Protection
resistors (RPROT1 and RPROT2) and filtering are also provided. The OPA333 is used as an integrator to remove the
gained-up dc offsets and servo the INA826 outputs to VREF. Finally, the right leg drive is biased to a potential
(+VS / 2), and inverts and amplifies the average common-mode signal back into the patient's right leg. This
architecture reduces the 50-Hz and 60-Hz noise pickup.
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System Examples (continued)
+Vs
U1 OPA333
LA Electrode
+
R4 52k
+
Vref
-
ECGp
C2 47n
+Vs
Rprot1 100k
+
C10 1u
+
ECG_LA
C5 33p
RG1 6.1k
RG2 6.1k
C6 1n
C4 47n
+
U4 INA826
Rg
Vout
Rg
+
-
C7 33p
Rprot2 100k
ECG_RA
+Vs
R7 52k
ECGn
R1 1M
R_RLD 52k
C_RLD 47n
RA Electrode
RL Electrode
R12 500k
Ref
Vref
V1 5
R6 10k
C11 1n
R9 1M
U3 OPA2314
-
Rprot3 100k
U2 OPA2314
-
R3 10k
R5 10M
+
+
+Vs
++
Vref
Copyright © 2016, Texas Instruments Incorporated
+Vs
Figure 69. ECG Circuit
Figure 70 shows an example of how the INA826 can be used for low-side current sensing. The load current
(ILOAD) creates a voltage drop across the shunt resistor (RSHUNT). This voltage is amplified by the INA826 with
gain set to 100. The output swing of the INA826 is set by the common-mode voltage (which is 0 V in low-side
current sensing) and power supplies. Therefore, a dual-supply circuit is implemented. The load current is set
from 1 A to 10 A, corresponding to an output voltage range from 350 mV to 3.5 V. The output range can be
adjusted by changing the shunt resistor and the gain of the INA826. Click the following link to download the
TINA-TI file: Current Sensing Circuit.
+Vs
+Vs
Iload 10
V1 5
Vbus 10
+
U2 INA826
+
Rg
Rshunt 3.5m
Ref
RG 499
Vout
Rg
V2 5
Rout 10k
-
-Vs
-Vs
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Figure 70. Low-Side Current Sensing
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System Examples (continued)
Figure 71 shows an example of how the INA826 can be used for RTD signal conditioning. This circuit creates an
excitation current (ISET) by forcing 2.5 V from the REF5025 across RSET. The zero-drift, low-noise OPA188
creates the virtual ground that maintains a constant differential voltage across RSET with changing common-mode
voltage. This voltage is necessary because the voltage on the positive input of the INA826 fluctuates over
temperature as a result of the changing RTD resistance. Click the following link to download the TINA-TI file:
RTD Circuit.
+Vs
Vref5025
U2 REF5025
NC
Vout
Vin
Temp
Trim GND
R2 1.5M
+
Vset
Rset 2.5k
-
VirtualGND
-Vs
+Vs
++
V1 15
U1 OPA188
+
+Vs
A
Iset
V2 15
+Vs
+
Rg
-Vs
U4 INA826
+
Ref
RTD 100
Rg 5k
Rg
-
Rparasitic 5
+
-
Vout
-Vs
Copyright © 2017, Texas Instruments Incorporated
Figure 71. RTD Signal Conditioning
The circuit in Figure 72 creates a precision current ISET by forcing the INA826 VDIFF across RSET. The input
voltage VIN is amplified to the output of the INA826 and then divided down by the gain of the INA826 to create
VDIFF. ISET can be controlled either by changing the value of the gain-set resistor RG, the set resistor RSET, or by
changing VOUT through the gain of the composite loop. Make sure that the changing load resistance RL does not
create a voltage on the negative input of the INA826 that violates the compliance of the common-mode input
range. Likewise, the voltage on the output of the OPA170 must remain compliant throughout the changing load
resistance for this circuit to function properly.
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System Examples (continued)
R1 10k
R2 10k
C1 100p
-Vs
+
+
+
Rg
+
Vdiff
+
Vin
+Vs
U2 OPA170
-
Ref
Vout
RG 1k
Rset 10k
-
+Vs
U4 INA826
+
Rg
-
+Vs
-Vs
+
A
V1 15
Iset
RL 1k
V2 15
-Vs
Copyright © 2017, Texas Instruments Incorporated
Figure 72. Precision Current Source
32
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10 Power Supply Recommendations
The nominal performance of the INA826 is specified with a supply voltage of ±15 V and mid-supply reference
voltage. The device can also be operated using power supplies from ±1.5 V (3 V) to ±18 V (36 V) and non midsupply reference voltages with excellent performance. Parameters that can vary significantly with operating
voltage and reference voltage are illustrated in the Typical Characteristics section.
11 Layout
11.1 Layout Guidelines
Attention to good layout practices is always recommended. Keep traces short and, when possible, use a printed
circuit board (PCB) ground plane with surface-mount components placed as close to the device pins as possible.
Place 0.1-μF bypass capacitors close to the supply pins. Apply these guidelines throughout the analog circuit to
improve performance and provide benefits such as reducing the electromagnetic-interference (EMI) susceptibility.
The INA826EVM is intended to provide basic functional evaluation of the INA826. An image of the INA826EVM is
provided in Figure 73. The INA826EVM is also available for purchase through the TI eStore.
Attention to good layout practices is always recommended. For best operational performance of the device, use
good PCB layout practices, including:
• Make sure to match both input paths to avoid converting common-mode signals into differential signals.
• Connect a bypass capacitor of 0.1-µF between each supply pin and ground, placed close to the device as
possible.
• Route the input traces as far away from the supply or output traces as possible. This reduces parasitic
coupling.
• Place the external components as close to the device as possible.
• Keep traces as short as possible.
• For the DRG package: Connect the exposed thermal pad to the lowest voltage potential on the circuit that is
the negative power supply (–V).
11.1.1 CMRR vs Frequency
The INA826 pinout is optimized for achieving maximum CMRR performance over a wide range of frequencies.
However, make sure that both input paths are well-matched for source impedance and capacitance to avoid
converting common-mode signals into differential signals. In addition, parasitic capacitance at the gain-setting
pins can also affect CMRR over frequency. For example, in applications that implement gain switching using
switches or PhotoMOS® relays to change the value of RG, choose the component so that the switch capacitance
is as small as possible.
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11.2 Layout Example
+V
C2
RG
INA826
RG
-IN
OUT
±VS
R3
REF
+IN
+VS
R2
R1
DRG Package:
Connect Thermal
Pad to negative
supply íV or left
floating
C1
íV
+V
Use ground pours for
shielding the input
signal pairs
Place bypass
capacitors as close to
IC as possible
GND
C2
R1
±IN
1
±IN
+VS
8
2
RG
OUT
7
3
RG
REF
6
4
+IN
-VS
5
OUT
R3
+IN
Low-impedance
connection for
reference terminal
R2
GND
C1
REF
íV
Copyright © 2017, Texas Instruments Incorporated
Figure 73. INA826 Example Layout
The INA826EVM provides the following features:
• Intuitive evaluation with silkscreen schematic
• Easy access to nodes with surface-mount test points
• Advanced evaluation with two prototype areas
• Reference voltage source flexibility
• Convenient input and output filtering
34
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, OPAx330 50-μV VOS, 0.25-μV/°C, 35-μA CMOS Operational Amplifiers Zerø-Drift Series
data sheet
• Texas Instruments, REF32xx 4ppm/°C, 100μA, SOT23-6 Series Voltage Reference data sheet
• Texas Instruments, REF50xx Low-Noise, Very Low Drift, Precision Voltage Reference data sheet
• Texas Instruments, INA333 Micro-Power (50μA), Zerø-Drift, Rail-to-Rail Out Instrumentation Amplifier data
sheet
• Texas Instruments, PGA280 Zerø-Drift, High-Voltage, Programmable Gain Instrumentation Amplifier data
sheet
• Texas Instruments, INA159 Precision, Gain of 0.2 Level Translation Difference Amplifier data sheet
• Texas Instruments, PGA11x Zerø-Drift Programmable Gain Amplifier With Mux data sheet
• Texas Instruments, INA826EVM User's Guide
• Texas Instruments, TINA-TI software folder
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
PhotoMOS is a registered trademark of Panasonic Electric Works Europe AG.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Copyright © 2011–2020, Texas Instruments Incorporated
Product Folder Links: INA826
35
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
INA826AID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
INA826
INA826AIDGK
ACTIVE
VSSOP
DGK
8
80
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
IPDI
INA826AIDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
IPDI
INA826AIDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
INA826
INA826AIDRGR
ACTIVE
SON
DRG
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
IPEI
INA826AIDRGT
ACTIVE
SON
DRG
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
IPEI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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