Product
Folder
Sample &
Buy
Support &
Community
Tools &
Software
Technical
Documents
ISO5452-Q1
SLLSEQ5A – SEPTEMBER 2016 – REVISED DECEMBER 2016
ISO5452-Q1 High-CMTI 2.5-A and 5-A Isolated IGBT, MOSFET Gate Driver
With Split Outputs and Active Protection Features
1 Features
2 Applications
•
•
•
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to
+125°C Ambient Operating Temperature
Range
– Device HBM Classification Level 3A
– Device CDM Classification Level C6
50-kV/μs Minimum and 100-kV/μs Typical
Common-Mode Transient Immunity (CMTI)
at VCM = 1500 V
Split Outputs to provide 2.5-A Peak Source and
5-A Peak Sink Currents
Short Propagation Delay: 76 ns (Typ),
110 ns (Max)
2-A Active Miller Clamp
Output Short-Circuit Clamp
Soft Turn-Off (STO) during Short Circuit
Fault Alarm upon Desaturation Detection is
Signaled on FLT and Reset Through RST
Input and Output Undervoltage Lockout (UVLO)
With Ready (RDY) Pin Indication
Active Output Pulldown and Default Low Outputs
With Low Supply or Floating Inputs
2.25-V to 5.5-V Input Supply Voltage
15-V to 30-V Output Driver Supply Voltage
CMOS Compatible Inputs
Rejects Input Pulses and Noise Transients
Shorter Than 20 ns
Isolation Surge Withstand Voltage 10000-VPK
Safety-Related Certifications:
– 8000-VPK VIOTM and 1420-VPK VIORM
Reinforced Isolation per DIN V VDE V 0884-10
(VDE V 0884-10):2006-12
– 5700-VRMS Isolation for 1 Minute per UL 1577
– CSA Component Acceptance Notice 5A, IEC
60950–1 and IEC 60601–1 End Equipment
Standards
– TUV Certification per EN 61010-1 and EN
60950-1
– GB4943.1-2011 CQC Certification
– All Certifications Complete
Isolated IGBT and MOSFET Drives in:
– HEV and EV Power Modules
– Industrial Motor Control Drives
– Industrial Power Supplies
– Solar Inverters
– Induction Heating
3 Description
The ISO5452-Q1 is a 5.7-kVRMS, reinforced isolated
gate driver for IGBTs and MOSFETs with split
outputs, OUTH and OUTL, providing 2.5-A source
and 5-A sink current. The input side operates from a
single 2.25-V to 5.5-V supply. The output side allows
for a supply range from minimum 15 V to maximum
30 V. Two complementary CMOS inputs control the
output state of the gate driver. The short propagation
time of 76 ns assures accurate control of the output
stage.
An internal desaturation (DESAT) fault detection
recognizes when the IGBT is in an overcurrent
condition. Upon a DESAT detect, a Mute logic
immediately blocks the output of the isolator and
initiates a soft-turn-off procedure which disables
OUTH, and pulls OUTL to low over a time span of
2 μs. When OUTL reaches 2 V with respect to the
most negative supply potential, VEE2, the gate driver
output is pulled hard to VEE2 potential, turning the
IGBT immediately off.
Device Information(1)
PART NUMBER
ISO5452-Q1
PACKAGE
BODY SIZE (NOM)
SOIC (16)
10.30 mm × 7.50 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Functional Block Diagram
VCC2
VCC1
VCC1
UVLO1
UVLO2
500 µA
DESAT
IN±
Mute
9V
IN+
GND2
VCC2
VCC1
RDY
Gate Drive
Ready
OUTH
and
Encoder
Logic
STO
VCC1
FLT
Q
S
Q
R
VCC1
OUTL
Decoder
2V
Fault
CLAMP
RST
GND1
VEE2
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ISO5452-Q1
SLLSEQ5A – SEPTEMBER 2016 – REVISED DECEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Function ...........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
8
9
1
1
1
2
3
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings ............................................................ 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 5
Power Ratings........................................................... 5
Insulation Specifications............................................ 6
Safety-Related Certifications..................................... 7
Safety Limiting Values .............................................. 7
Electrical Characteristics........................................... 8
Switching Characteristics ...................................... 10
Insulation Characteristics Curves ......................... 11
Typical Characteristics .......................................... 12
Parameter Measurement Information ................ 19
Detailed Description ............................................ 21
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
21
21
22
23
10 Application and Implementation........................ 24
10.1 Application Information.......................................... 24
10.2 Typical Applications .............................................. 24
11 Power Supply Recommendations ..................... 34
12 Layout................................................................... 34
12.1 Layout Guidelines ................................................. 34
12.2 PCB Material ......................................................... 34
12.3 Layout Example .................................................... 34
13 Device and Documentation Support ................. 35
13.1
13.2
13.3
13.4
13.5
13.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
35
35
35
35
35
35
14 Mechanical, Packaging, and Orderable
Information ........................................................... 35
4 Revision History
Changes from Original (September 2015) to Revision A
Page
•
Changed the Title From: "Active Safety Features" To: Active Protection Features" ............................................................. 1
•
Changed the status of all certifications to complete .............................................................................................................. 1
•
Changed the Electrostatic Discharge Caution...................................................................................................................... 35
2
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: ISO5452-Q1
ISO5452-Q1
www.ti.com
SLLSEQ5A – SEPTEMBER 2016 – REVISED DECEMBER 2016
5 Description (continued)
When desaturation is active, a fault signal is sent across the isolation barrier, pulling the FLT output at the input
side low and blocking the isolator input. Mute logic is activated through the soft-turn-off period. The FLT output
condition is latched and can be reset only after RDY goes high, through a low-active pulse at the RST input.
When the IGBT is turned off during normal operation with bipolar output supply, the output is hard clamp to VEE2.
If the output supply is unipolar, an active Miller clamp can be used, allowing Miller current to sink across a low
impedance path, preventing IGBT to be dynamically turned on during high voltage transient conditions.
The readiness for the gate driver to be operated is under the control of two undervoltage-lockout circuits
monitoring the input side and output side supplies. If either side has insufficient supply the RDY output goes low,
otherwise this output is high.
The ISO5452-Q1 is available in a 16-pin SOIC package. Device operation is specified over a temperature range
from –40°C to +125°C ambient.
6 Pin Configuration and Function
DW Package
16-Pin SOIC
Top View
VEE2
1
16
GND1
DESAT
2
15
VCC1
GND2
3
14
RST
OUTH
4
13
FLT
VCC2
5
12
RDY
OUTL
6
11
IN±
CLAMP
7
10
IN+
VEE2
8
9
GND1
Not to scale
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
1
VEE2
—
2
DESAT
I
Output negative supply. Connect to GND2 for Unipolar supply application.
3
GND2
—
Gate drive common. Connect to IGBT emitter.
4
OUTH
O
Positive gate drive voltage output
5
VCC2
—
Most positive output supply potential.
6
OUTL
O
Negative gate drive voltage output
7
CLAMP
O
Miller clamp output
8
VEE2
—
Output negative supply. Connect to GND2 for Unipolar supply application.
9
GND1
—
Input ground
10
IN+
I
Non-inverting gate drive voltage control input
Desaturation voltage input
11
IN–
I
Inverting gate drive voltage control input
12
RDY
O
Power-good output, active high when both supplies are good.
13
FLT
O
Fault output, low-active during DESAT condition
Reset input, apply a low pulse to reset fault latch.
14
RST
I
15
VCC1
—
Positive input supply (2.25 V to 5.5 V)
16
GND1
—
Input ground
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: ISO5452-Q1
3
ISO5452-Q1
SLLSEQ5A – SEPTEMBER 2016 – REVISED DECEMBER 2016
www.ti.com
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
GND1 – 0.3
6
V
–0.3
35
V
–17.5
0.3
V
–0.3
35
V
Positive gate driver output voltage
VEE2 – 0.3
VCC2 + 0.3
V
Negative gate driver output voltage
VEE2 – 0.3
VCC2 + 0.3
V
2.7
A
5.5
A
VCC1
Supply voltage input side
VCC2
Positive supply voltage output side
(VCC2 – GND2)
VEE2
Negative supply voltage output side
(VEE2 – GND2)
V(SUP2)
Total supply output voltage
(VCC2 – VEE2)
V(OUTH)
V(OUTL)
I(OUTH)
Gate driver high output current
Gate driver high output current
(maximum pulse width = 10 μs,
maximum duty cycle = 0.2%)
I(OUTL)
Gate driver low output current
Gate driver high output current
(maximum pulse width = 10 μs,
maximum duty cycle = 0.2%)
V(LIP)
Voltage at IN+, IN–, FLT, RDY, RST
I(LOP)
Output current of FLT, RDY
V(DESAT)
Voltage at DESAT
V(CLAMP)
Clamp voltage
TJ
TSTG
(1)
GND1 - 0.3
VCC1 + 0.3
V
10
mA
GND2 - 0.3
VCC2 + 0.3
V
VEE2 – 0.3
VCC2 + 0.3
V
Junction temperature
–40
150
°C
Storage temperature
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic
discharge
Human-body model (HBM), per AEC Q100-002 (1)
±4000
Charged-device model (CDM), per AEC Q100-011
±1500
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VCC1
Supply voltage input side
VCC2
NOM
MAX
UNIT
2.25
5.5
V
Positive supply voltage output side (VCC2 – GND2)
15
30
V
VEE2
Negative supply voltage output side (VEE2 – GND2)
–15
0
V
V(SUP2)
Total supply voltage output side (VCC2 – VEE2)
15
30
V
VIH
High-level input voltage (IN+, IN–, RST)
0.7 × VCC1
VCC1
V
VIL
Low-level input voltage (IN+, IN–, RST)
0
0.3 × VCC1
V
tUI
Pulse width at IN+, IN– for full output (CLOAD = 1 nF)
tRST
Pulse width at RST for resetting fault latch
800
TA
Ambient temperature
–40
4
Submit Documentation Feedback
40
ns
ns
125
°C
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: ISO5452-Q1
ISO5452-Q1
www.ti.com
SLLSEQ5A – SEPTEMBER 2016 – REVISED DECEMBER 2016
7.4 Thermal Information
ISO5452-Q1
THERMAL METRIC (1)
DW (SOIC)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
99.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
48.5
°C/W
RθJB
Junction-to-board thermal resistance
56.5
°C/W
ψJT
Junction-to-top characterization parameter
29.2
°C/W
ψJB
Junction-to-board characterization parameter
56.5
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
7.5 Power Ratings
VCC1 = 5.5 V, VCC2 = 30 V, TA = 25°C
PARAMETER
PD
Maximum power dissipation (1)
PID
Maximum input power dissipation
POD
Maximum output power dissipation
(1)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1255
mW
175
mW
1080
mW
Full chip power dissipation is derated 10.04 mW/°C beyond 25°C ambient temperature. At 125°C ambient temperature, a maximum of
251 mW total power dissipation is allowed. Power dissipation can be optimized depending on ambient temperature and board design,
while ensuring that Junction temperature does not exceed 150°C.
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: ISO5452-Q1
5
ISO5452-Q1
SLLSEQ5A – SEPTEMBER 2016 – REVISED DECEMBER 2016
www.ti.com
7.6 Insulation Specifications
PARAMETER
TEST CONDITIONS
VALUE
UNIT
GENERAL
CLR
External clearance (1)
Shortest terminal-to-terminal distance through air
>8
mm
CPG
External creepage (1)
Shortest terminal-to-terminal distance across the package surface
>8
mm
DTI
Distance through the insulation
Minimum internal gap (internal clearance)
>21
μm
CTI
Tracking resistance (comparative tracking
DIN EN 60112 (VDE 0303-11); IEC 60112;
index)
>600
V
Material Group
According to IEC 60664-1; UL 746A
Overvoltage category (according to IEC
60664-1)
I
Rated Mains Voltage ≤ 300 VRMS
I-IV
Rated Mains Voltage ≤ 600 VRMS
I-III
Rated Mains Voltage ≤ 1000 VRMS
I-II
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 (2)
VIORM
Maximum repetitive peak isolation
voltage
VIOWM Maximum isolation working voltage
VIOTM
VIOSM
qpd
Maximum transient isolation voltage
Maximum surge isolation voltage
(3)
Apparent charge (4)
AC voltage (bipolar)
1420
VPK
AC voltage. Time dependent dielectric breakdown (TDDB) Test, see Figure 1
1000
VRMS
DC voltage
1420
VDC
VTEST = VIOTM, t = 60 s (qualification), t = 1 s (100% production)
8000
VPK
Test method per IEC 60065, 1.2/50 μs waveform, VTEST = 1.6 × VIOSM = 10000 VPK
(qualification) (3)
6250
VPK
Method a: After I/O safety test subgroup 2/3, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 ×
VIORM = 1704 VPK, tm = 10 s
≤5
Method a: After environmental tests subgroup 1, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.6 ×
VIORM = 2272 VPK, tm = 10 s
≤5
Method b1: At routine test (100% production) and preconditioning (type test), Vini =
VIOTM, tini = 60 s; Vpd(m) = 1.875× VIORM = 2663 VPK, tm = 10 s
≤5
VIO = 500 V, TA = 25°C
RIO
CIO
Isolation resistance, input to output
(5)
Barrier capacitance, input to output (5)
pC
> 1012
Ω
11
Ω
VIO = 500 V, 100°C ≤ TA ≤ 125°C
> 10
VIO = 500 V at TS = 150°C
> 109
Ω
1
pF
VIO = 0.4 x sin (2πft), f = 1 MHz
Pollution degree
2
UL 1577
VISO
(1)
(2)
(3)
(4)
(5)
6
Withstanding Isolation voltage
VTEST = VISO, t = 60 s (qualification),
VTEST = 1.2 × VISO = 6840 VRMS,
t = 1 s (100% production)
5700
VRMS
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
This coupler is suitable for basic electrical insulation only within the maximum operating ratings. Compliance with the safety ratings shall
be ensured by means of suitable protective circuits.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier tied together creating a two-terminal device
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: ISO5452-Q1
ISO5452-Q1
www.ti.com
SLLSEQ5A – SEPTEMBER 2016 – REVISED DECEMBER 2016
7.7 Safety-Related Certifications
VDE
CSA
UL
CQC
TUV
Certified according to GB
4943.1-2011
Certified according to
EN 61010-1:2010 (3rd Ed)
and
EN 609501:2006/A11:2009/A1:2010/
A12:2011/A2:2013
Reinforced Insulation
Maximum Transient isolation
voltage, 8000 VPK;
Maximum surge isolation
voltage, 6250 VPK,
Maximum repetitive peak
isolation voltage, 1420 VPK
Isolation Rating of 5700 VRMS;
Reinforced insulation per CSA
60950- 1- 07+A1+A2 and IEC
60950-1 (2nd Ed.), 800 VRMS
max working voltage (pollution
Single Protection, 5700 VRMS
degree 2, material group I) ;
(1)
2 MOPP (Means of Patient
Protection) per CSA 606011:14 and IEC 60601-1 Ed.
3.1, 250 VRMS (354 VPK) max
working voltage
Reinforced Insulation, Altitude
≤ 5000m, Tropical climate,
400 VRMS maximum working
voltage
5700 VRMS Reinforced
insulation per
EN 61010-1:2010 (3rd Ed) up
to working voltage of 600
VRMS
5700 VRMS Reinforced
insulation per
EN 609501:2006/A11:2009/A1:2010/
A12:2011/A2:2013 up to
working voltage of 800 VRMS
Certification completed
Certificate number: 40040142
Master contract number:
220991
Certification completed
Certificate number:
CQC16001141761
Certification completed
Client ID number: 77311
Certified according to DIN V
VDE V 0884-10
(VDE V 0884-10):2006-12
and DIN EN 60950-1
(VDE 0805 Teil 1):2011-01
Certified according to CSA
Component Acceptance
Notice 5A, IEC 60950-1 and
IEC 60601-1
(1)
Certified according to UL
1577 Component Recognition
Program
Certification completed
File number: E181974
Production tested ≥ 6840 VRMS for 1 second in accordance with UL 1577.
7.8 Safety Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure of
the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier, potentially leading to secondary system failures.
PARAMETER
IS
Safety input, output or supply
current
TEST CONDITIONS
Safety input, output, or total power
TS
Safety temperature
(1)
TYP
MAX
456
RθJA = 99.6°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C, see Figure 2
346
RθJA = 99.6°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C, see Figure 2
228
RθJA = 99.6°C/W, VI = 15 V, TJ = 150°C, TA = 25°C, see Figure 2
484
RθJA = 99.6°C/W, VI = 30 V, TJ = 150°C, TA = 25°C, see Figure 2
PS
MIN
RθJA = 99.6°C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C, see Figure 2
RθJA = 99.6°C/W, TJ = 150°C, TA = 25°C, see Figure 3
UNIT
mA
42
1255 (1)
150
mW
°C
Input, output, or the sum of input and output power should not exceed this value
The safety-limiting constraint is the maximum junction temperature specified in the data sheet. The power
dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines
the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that
of a device installed on a high-K test board for leaded surface-mount packages. The power is the recommended
maximum input voltage times the current. The junction temperature is then the ambient temperature plus the
power times the junction-to-air thermal resistance.
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: ISO5452-Q1
7
ISO5452-Q1
SLLSEQ5A – SEPTEMBER 2016 – REVISED DECEMBER 2016
www.ti.com
7.9 Electrical Characteristics
Over recommended operating conditions unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2.25
V
VOLTAGE SUPPLY
VIT+(UVLO1)
Positive-going UVLO1 threshold
voltage input side (VCC1 – GND1)
VIT-(UVLO1)
Negative-going UVLO1 threshold
voltage input side (VCC1 – GND1)
VHYS(UVLO1)
UVLO1 Hysteresis voltage (VIT+ – TA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V,
VIT–) input side
GND2 – VEE2 = 8 V
VIT+(UVLO2)
Positive-going UVLO2 threshold
voltage output side (VCC2 –
GND2)
TA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V,
GND2 – VEE2 = 8 V
VIT-(UVLO2)
Negative-going UVLO2 threshold
voltage output side (VCC2 –
GND2)
TA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V,
GND2 – VEE2 = 8 V
11
VHYS(UVLO2)
UVLO2 Hysteresis voltage (VIT+ – TA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V,
VIT–) output side
GND2 – VEE2 = 8 V
1
IQ1
Input supply quiescent current
TA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V,
GND2 – VEE2 = 8 V
IQ2
Output supply quiescent current
TA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V,
GND2 – VEE2 = 8 V
1.7
V
0.2
V
13
V
12
9.5
V
V
4.5
mA
2.8
6
mA
3.6
LOGIC I/O
VIT+(IN,RST)
Positive-going input threshold
voltage (IN+, IN–, RST)
VIT-(IN,RST)
Negative-going input threshold
voltage (IN+, IN–, RST)
VHYS(IN,RST)
Input hysteresis voltage (IN+,
IN–, RST)
TA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V,
GND2 – VEE2 = 8 V
IIH
High-level input leakage at
(IN+) (1)
IN+ = VCC1, TA = 25°C, VCC1 = 5 V,
VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V
IIL
Low-level input leakage at (IN–,
RST) (2)
IN– = GND1, RST = GND1, TA = 25°C, VCC1 = 5 V,
VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V
IPU
Pullup current of FLT, RDY
V(RDY) = GND1, V(FLT) = GND1, TA = 25°C,
VCC1 = 5 V, VCC2 – GND2 = 15 V,
GND2 – VEE2 = 8 V
VOL
Low-level output voltage at FLT,
RDY
I(FLT) = 5 mA
0.7 × VCC1
0.3 × VCC1
V
V
0.15 × VCC1
V
100
µA
–100
µA
100
µA
0.2
V
2
V
GATE DRIVER STAGE
V(OUTPD)
Active output pulldown voltage
I(OUTH/L) = 200 mA, VCC2 = open
I(OUTH) = –20 mA
V(OUTH)
High-level output voltage
V(OUTL)
Low-level output voltage
VCC2 – 0.5
I(OUTH) = –20 mA, TA = 25°C, VCC1 = 5 V, VCC2 –
GND2 = 15 V, GND2 – VEE2 = 8 V
I(OUTL) = 20 mA
VEE2 + 50
I(OUTL) = 20 mA, TA = 25°C, VCC1 = 5 V, VCC2 –
GND2 = 15 V, GND2 – VEE2 = 8 V
IN+ = high, IN– = low, V(OUTH) = VCC2 – 15 V
VEE2 + 13
I(OUTH)
High-level output peak current
I(OUTL)
Low-level output peak current
IN+ = low, IN– = high, V(OUTL) = VEE2 + 15 V,
TA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V,
GND2 – VEE2 = 8 V
5
I(OLF)
Low level output current during
fault condition
TA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V,
GND2 – VEE2 = 8 V
130
(1)
(2)
8
mV
1.5
IN+ = high, IN– = low, V(OUTH) = VCC2 – 15 V,
TA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V,
GND2 – VEE2 = 8 V
IN+ = low, IN– = high, V(OUTL) = VEE2 + 15 V
V
VCC2 – 0.24
2.5
A
3.4
A
mA
IIH for IN–, RST pin is zero as they are pulled high internally.
IIL for IN+ is zero, as it is pulled low internally.
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: ISO5452-Q1
ISO5452-Q1
www.ti.com
SLLSEQ5A – SEPTEMBER 2016 – REVISED DECEMBER 2016
Electrical Characteristics (continued)
Over recommended operating conditions unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ACTIVE MILLER CLAMP
I(CLP) = 20 mA
VEE2 + 0.08
V(CLP)
Low-level clamp voltage
I(CLP)
Low-level clamp current
V(CLAMP) = VEE2 + 2.5 V, TA = 25°C, VCC1 = 5 V,
VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V
V(CLTH)
Clamp threshold voltage
TA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V,
GND2 – VEE2 = 8 V
2.1
IN+ = high, IN– = low, tCLP = 10 µs,
I(OUTH) = 500 mA
1.1
I(CLP) = 20 mA, TA = 25°C, VCC1 = 5 V,
VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V
V(CLAMP) = VEE2 + 2.5 V
V
VEE2 + 0.015
1.6
3.3
A
2.5
1.6
2.5
V
SHORT CIRCUIT CLAMPING
V(CLP_OUTH)
V(CLP_OUTL)
Clamping voltage
(VOUTH – VCC2)
Clamping voltage
(VOUTL – VCC2)
Clamping voltage
(VCLP – VCC2)
V
IN+ = high, IN– = low, tCLP = 10 µs, I(OUTH) = 500
mA, TA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V,
GND2 – VEE2 = 8 V
IN+ = high, IN– = low, tCLP = 10 µs,
I(OUTL) = 500 mA
1.3
Clamping voltage at CLAMP
V
IN+ = high, IN– = low, tCLP = 10 µs, I(CLP) = 500
mA, TA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V,
GND2 – VEE2 = 8 V
1.3
V(CLP_OUTL)
V
1.1
IN+ = High, IN– = Low, I(CLP) = 20 mA, TA = 25°C,
VCC1 = 5 V, VCC2 – GND2 = 15 V,
GND2 – VEE2 = 8 V
V
0.7
IN+ = High, IN– = Low, I(OUTL) = 20 mA
Clamping voltage at OUTL
(VCLP - VCC2)
1.5
IN+ = high, IN– = low, tCLP = 10 µs, I(OUTL) = 500
mA, TA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V,
GND2 – VEE2 = 8 V
IN+ = High, IN– = Low, I(CLP) = 20 mA
V(CLP_CLAMP)
1.3
1.1
IN+ = High, IN– = Low, I(OUTL) = 20 mA, TA = 25°C,
VCC1 = 5 V, VCC2 – GND2 = 15 V,
GND2 – VEE2 = 8 V
V
0.7
DESAT PROTECTION
I(CHG)
V(DESAT) – GND2 = 2 V
Blanking capacitor charge current V(DESAT) – GND2 = 2 V, TA = 25°C, VCC1 = 5 V,
VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V
I(DCHG)
Blanking capacitor discharge
current
V(DSTH)
DESAT threshold voltage with
respect to GND2
V(DSL)
DESAT voltage with respect to
GND2, when OUTH/L is driven
low
V(DESAT) – GND2 = 6 V
0.42
0.58
mA
0.5
9
V(DESAT) – GND2 = 6 V, TA = 25°C, VCC1 = 5 V,
VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V
mA
14
8.3
TA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V,
GND2 – VEE2 = 8 V
9.5
V
9
0.4
1
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: ISO5452-Q1
V
9
ISO5452-Q1
SLLSEQ5A – SEPTEMBER 2016 – REVISED DECEMBER 2016
www.ti.com
7.10 Switching Characteristics
Over recommended operating conditions unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
CLOAD = 1 nF
Output signal rise time, see
Figure 44, Figure 45 and Figure 46 CLOAD = 1 nF, TA = 25°C, VCC1 = 5 V,
VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V
12
tr
CLOAD = 1 nF
Output signal fall time, see
Figure 44, Figure 45 and Figure 46 CLOAD = 1 nF, TA = 25°C, VCC1 = 5 V,
VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V
12
tf
tPLH, tPHL
Propagation delay, see Figure 44,
Figure 45 and Figure 46
tsk-p
Pulse skew |tPHL – tPLH|, see
CLOAD = 1 nF
Figure 44, Figure 45 and Figure 46
tsk-pp
Part-to-part skew, see Figure 44,
Figure 45 and Figure 46
tGF
CLOAD = 1 nF
Glitch filter on IN+, IN–, RST, see
Figure 44, Figure 45 and Figure 46 CLOAD = 1 nF, TA = 25°C, VCC1 = 5 V,
VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V
ns
37
ns
20
76
110
ns
CLOAD = 1 nF
DESAT sense to 90% VOUTH/L
delay, see Figure 44, Figure 45
and Figure 46
CLOAD = 10 nF
(10%)
DESAT sense to 10% VOUTH/L
delay, see Figure 44, Figure 45
and Figure 46
CLOAD = 10 nF
tDS
tDS
(GF)
DESAT glitch filter delay
tDS
(FLT)
DESAT sense to FLT-low delay,
see Figure 46
20
20
ns
30 (1)
ns
40
ns
30
760
CLOAD = 10 nF, TA = 25°C, VCC1 = 5 V,
VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V
ns
553
3.5
CLOAD = 10 nF, TA = 25°C, VCC1 = 5 V,
VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V
2
CLOAD = 1 nF, TA = 25°C, VCC1 = 5 V,
VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V
330
μs
ns
1.4
310
tLEB
Leading edge blanking time, see
Figure 44 and Figure 45
tGF(RSTFLT)
Glitch filter on RST for resetting
FLT
CI
Input capacitance (2)
CMTI
VCM = 1500 V
Common-mode transient immunity,
VCM = 1500 V, TA = 25°C, VCC1 = 5 V,
see Figure 47
VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V
UNIT
35
CLOAD = 1 nF, TA = 25°C, VCC1 = 5 V,
VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V
(90%)
10
MAX
18
CLOAD = 1 nF
tDS
(1)
(2)
TYP
TA = 25°C, VCC1 = 5 V,
VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V
480
ns
400
300
VI = VCC1 / 2 + 0.4 × sin (2πft), f = 1 MHz,
VCC1 = 5 V, TA = 25°C, VCC1 = 5 V,
VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V
μs
800
2
ns
pF
50
100
kV/μs
Measured at same supply voltage and temperature condition
Measured from input pin to ground.
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: ISO5452-Q1
ISO5452-Q1
www.ti.com
SLLSEQ5A – SEPTEMBER 2016 – REVISED DECEMBER 2016
7.11 Insulation Characteristics Curves
1.E+12
Safety Margin Zone: 1200 VRMS,1268 Years
Operating Zone: 1000 VRMS, 676 Years
TDDB Line (