ISO5851QDWRQ1

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents ISO5851-Q1 SLLSEQ1A – SEPTEMBER 2016 – REVISED DECEMBER 2016 ISO5851-Q1 High-CMTI 2.5-A and 5-A Isolated IGBT, MOSFET Gate Driver With Active Protection Features 1 Features 2 Applications • • • 1 • • • • • • • • • • • • • • Qualified for Automotive Applications AEC-Q100 Qualified With the Following Results: – Device Temperature Grade 1: –40°C to +125°C Ambient Operating Temperature Range – Device HBM Classification Level 3A – Device CDM Classification Level C6 100-kV/μs Minimum Common-Mode Transient Immunity (CMTI) at VCM = 1500 V 2.5-A Peak Source and 5-A Peak Sink Currents Short Propagation Delay: 76 ns (Typ), 110 ns (Max) 2-A Active Miller Clamp Output Short-Circuit Clamp Fault Alarm upon Desaturation Detection is Signaled on FLT and Reset Through RST Input and Output Undervoltage Lockout (UVLO) with Ready (RDY) Pin Indication Active Output Pull-down and Default Low Outputs with Low Supply or Floating Inputs 3-V to 5.5-V Input Supply Voltage 15-V to 30-V Output Driver Supply Voltage CMOS Compatible Inputs Rejects Input Pulses and Noise Transients Shorter Than 20 ns Isolation Surge Withstand Voltage 12800-VPK Safety-Related Certifications: – 8000-VPK VIOTM and 2121-VPK VIORM Reinforced Isolation per DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 – 5700-VRMS Isolation for 1 Minute per UL 1577 – CSA Component Acceptance Notice 5A, IEC 60950–1 and IEC 60601–1 End Equipment Standards – TUV Certification per EN 61010-1 and EN 60950-1 – GB4943.1-2011 CQC Certification – All Certifications Complete Isolated IGBT and MOSFET Drives in: – HEV and EV Power Modules – Industrial Motor Control Drives – Industrial Power Supplies – Solar Inverters – Induction Heating 3 Description The ISO5851-Q1 is a 5.7-kVRMS, reinforced isolated gate driver for IGBTs and MOSFETs with 2.5-A source and 5-A sink current. The input side operates from a single 3-V to 5.5-V supply. The output side allows for a supply range from minimum 15 V to maximum 30 V. Two complementary CMOS inputs control the output state of the gate driver. The short propagation time of 76 ns assures accurate control of the output stage. An internal desaturation (DESAT) fault detection recognizes when the IGBT is in an overload condition. Upon a DESAT detect, the gate driver output is driven low to VEE2 potential, turning the IGBT immediately off. When desaturation is active, a fault signal is sent across the isolation barrier, pulling the FLT output at the input side low and blocking the isolator input. The FLT output condition is latched and can be reset through a low-active pulse at the RST input. Device Information(1) PART NUMBER ISO5851-Q1 PACKAGE BODY SIZE (NOM) SOIC (16) 10.30 mm × 7.50 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Functional Block Diagram VCC2 VCC1 VCC1 UVLO1 UVLO2 500 µA DESAT IN± Mute 9V IN+ GND2 VCC1 VCC2 RDY Gate Drive and Encoder Logic Ready OUT VCC1 FLT Q S Q R VCC1 Decoder 2V Fault CLAMP RST GND1 VEE2 Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ISO5851-Q1 SLLSEQ1A – SEPTEMBER 2016 – REVISED DECEMBER 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Description (continued)......................................... Pin Configuration and Function ........................... Specifications......................................................... 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 8 9 1 1 1 2 3 4 5 Absolute Maximum Ratings ...................................... 5 ESD Ratings ............................................................ 5 Recommended Operating Conditions....................... 5 Thermal Information .................................................. 5 Power Ratings........................................................... 6 Insulation Characteristics .......................................... 6 Safety-Related Certifications..................................... 7 Safety Limiting Values .............................................. 7 Electrical Characteristics........................................... 8 Switching Characteristics ........................................ 9 Insulation Characteristics Curves ......................... 10 Typical Characteristics .......................................... 11 Parameter Measurement Information ................ 17 Detailed Description ............................................ 19 9.1 9.2 9.3 9.4 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 19 19 20 21 10 Application and Implementation........................ 22 10.1 Application Information.......................................... 22 10.2 Typical Applications .............................................. 22 11 Power Supply Recommendations ..................... 32 12 Layout................................................................... 32 12.1 Layout Guidelines ................................................. 32 12.2 PCB Material ......................................................... 32 12.3 Layout Example .................................................... 32 13 Device and Documentation Support ................. 33 13.1 13.2 13.3 13.4 13.5 13.6 Documentation Support ........................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 33 33 33 33 33 33 14 Mechanical, Packaging, and Orderable Information ........................................................... 33 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (September 2015) to Revision A Page • Changed the data sheet title from Active Safety Features to Active Protection Features .................................................... 1 • Changed the status of all certifications to complete............................................................................................................... 1 • Changed the Electrostatic Discharge Caution...................................................................................................................... 33 2 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ISO5851-Q1 ISO5851-Q1 www.ti.com SLLSEQ1A – SEPTEMBER 2016 – REVISED DECEMBER 2016 5 Description (continued) When the IGBT is turned off during normal operation with bipolar output supply, the output is hard clamp to VEE2. If the output supply is unipolar, an active Miller clamp can be used, allowing Miller current to sink across a low impedance path preventing IGBT to be dynamically turned on during high voltage transient conditions. When desaturation is active, a fault signal is sent across the isolation barrier pulling the FLT output at the input side low and blocking the isolator input. The FLT output condition is latched and can be reset through a lowactive pulse at the RST input. When the IGBT is turned off during normal operation with bipolar output supply, the output is hard clamp to VEE2. If the output supply is unipolar, an active Miller clamp can be used, allowing Miller current to sink across a low impedance path preventing IGBT to be dynamically turned on during high voltage transient conditions. The readiness for the gate driver to be operated is under the control of two undervoltage-lockout circuits monitoring the input side and output side supplies. If either side has insufficient supply the RDY output goes low; otherwise, this output is high. The ISO5851-Q1 is available in a 16-pin SOIC package. Device operation is specified over a temperature range from –40°C to +125°C ambient. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ISO5851-Q1 3 ISO5851-Q1 SLLSEQ1A – SEPTEMBER 2016 – REVISED DECEMBER 2016 www.ti.com 6 Pin Configuration and Function DW Package 16-Pin SOIC Top View 1 16 GND1 DESAT 2 15 VCC1 GND2 3 14 RST NC 4 13 FLT VCC2 5 12 RDY OUT 6 11 IN- CLAMP 7 10 IN+ VEE2 8 9 ISOLATION VEE2 GND1 Pin Functions PIN I/O DESCRIPTION NAME NO. CLAMP 7 O Miller clamp output DESAT 2 I Desaturation voltage input FLT 13 O Fault output, low-active during DESAT condition GND1 9, 16 — Input ground GND2 3 — Gate drive common. Connect to IGBT emitter. IN+ 10 I Non-inverting gate drive voltage control input IN– 11 I Inverting gate drive voltage control input NC 4 — Not connected OUT 6 O Gate drive voltage output RDY 12 O Power-good output, active high when both supplies are good. RST 14 I Reset input, apply a low pulse to reset fault latch. VCC1 15 — Positive input supply (3 V to 5.5 V) VCC2 5 — Most positive output supply potential. VEE2 1, 8 — Output negative supply. Connect to GND2 for Unipolar supply application. 4 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ISO5851-Q1 ISO5851-Q1 www.ti.com SLLSEQ1A – SEPTEMBER 2016 – REVISED DECEMBER 2016 7 Specifications 7.1 Absolute Maximum Ratings Over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT GND1 - 0.3 6 V VCC2 – GND2 –0.3 35 V Negative supply voltage output side VEE2 – GND2 –17.5 0.3 V V(SUP2) Total supply output voltage VCC2 – VEE2 –0.3 35 V VOUT Gate driver output voltage VEE2 – 0.3 VCC2 + 0.3 V VCC1 Supply voltage input side VCC2 Positive supply voltage output side VEE2 I(OUTH) Gate driver high output current Gate driver high output current max pulse width = 10 μs, max duty cycle = 0.2% I(OUTL) Gate driver low output current Gate driver high output current max pulse width = 10 μs, max duty cycle = 0.2% V(LIP) Voltage at IN+, IN–,FLT, RDY, RST I(LOP) Output current of FLT, RDY V(DESAT) Voltage at DESAT V(CLAMP) Clamp voltage TJ TSTG (1) GND1 – 0.3 2.7 5.5 A A VCC1 + 0.3 V 10 mA GND2 – 0.3 VCC2 + 0.3 V VEE2 – 0.3 VCC2 + 0.3 V Junction temperature –40 150 °C Storage temperature –65 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7.2 ESD Ratings VALUE V(ESD) (1) Electrostatic discharge Human-body model (HBM), per AEC Q100-002 (1) ±4000 Charged-device model (CDM), per AEC Q100-011 ±1500 UNIT V AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN VCC1 Supply voltage input side VCC2 NOM MAX UNIT 3 5.5 V Positive supply voltage output side (VCC2 – GND2) 15 30 V VEE2 Negative supply voltage output side (VEE2 – GND2) –15 0 V V(SUP2) Total supply voltage output side (VCC2 – VEE2) 15 30 V VIH High-level input voltage (IN+, IN–, RST) 0.7 × VCC1 VCC1 V VIL Low-level input voltage (IN+, IN–, RST) 0 0.3 × VCC1 tUI Pulse width at IN+, IN– for full output (CLOAD = 1 nF) tRST Pulse width at RST for resetting fault latch 800 TA Ambient temperature –40 V 40 ns ns 25 125 °C 7.4 Thermal Information ISO5851-Q1 THERMAL METRIC (1) DW (SOIC) UNIT 16 PINS RθJA Junction-to-ambient thermal resistance 99.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.5 °C/W RθJB Junction-to-board thermal resistance 56.5 °C/W ψJT Junction-to-top characterization parameter 29.2 °C/W ψJB Junction-to-board characterization parameter 56.5 °C/W (1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics (SPRA953). Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ISO5851-Q1 5 ISO5851-Q1 SLLSEQ1A – SEPTEMBER 2016 – REVISED DECEMBER 2016 www.ti.com 7.5 Power Ratings PARAMETER PD Maximum power dissipation (1) PID Maximum input power dissipation POD Maximum output power dissipation (1) TEST CONDITIONS MIN TYP MAX UNIT 1255 mW 175 mW 1080 mW Full chip power dissipation is de-rated 10.04 mW/°C beyond 25°C ambient temperature. At 125°C ambient temperature, a maximum of 251 mW total power dissipation is allowed. Power dissipation can be optimized depending on ambient temperature and board design, while ensuring that Junction temperature does not exceed 150°C. 7.6 Insulation Characteristics PARAMETER SPECIFICATION UNIT Shortest terminal-to-terminal distance through air TEST CONDITIONS 8 mm Shortest terminal-to-terminal distance across the package surface 8 mm Minimum internal gap (internal clearance) 21 μm DIN EN 60112 (VDE 0303-11); IEC 60112 >600 V CLR External clearance (1) CPG External creepage (1) DTI Distance through the insulation CTI Comparative tracking index Material group According to IEC 60664-1 Overvoltage category per IEC 60664-1 I Rated mains voltage ≤ 600 VRMS I-IV Rated mains voltage ≤ 1000 VRMS I-III DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 (2) VIORM VIOWM Maximum repetitive peak isolation voltage AC voltage (bipolar) 2121 VPK Maximum isolation working voltage AC voltage. Time dependent dielectric breakdown (TDDB) Test, see Figure 1 1500 VRMS DC voltage 2121 VDC 8000 8000 VIOTM Maximum Transient isolation voltage VTEST = VIOTM, t = 60 sec (qualification), t = 1 sec (100% production) VIOSM Maximum surge isolation voltage (3) Test method per IEC 60065, 1.2/50 μs waveform, VTEST = 1.6 x VIOSM = 12800 VPK (qualification) qpd Apparent charge RIO (4) Isolation resistance, input to output (5) Method a: After I/O safety test subgroup 2/3, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM = 2545 VPK, tm = 10 s ≤5 Method a: After environmental tests subgroup 1, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.6 × VIORM = 3394 VPK, tm = 10 s ≤5 Method b1: At routine test (100% production) and preconditioning (type test) Vini = VIOTM, tini = 60 s; Vpd(m) = 1.875× VIORM = 3977 VPK, tm = 10 s ≤5 CIO Barrier capacitance, input to output pC VIO = 500 V at TS > 109 Ω VIO = 500 V, TA = 25°C >1012 Ω 11 >10 Ω 1 pF VIO = 500 V, 100°C ≤ TA ≤ 125°C (5) VPK VIO = 0.4 x sin (2πft), f = 1 MHz Pollution degree 2 UL 1577 VISO (1) (2) (3) (4) (5) 6 Withstanding Isolation voltage VTEST = VISO, t = 60 sec (qualification), VTEST = 1.2 × VISO = 6840 VRMS, t = 1 sec (100% production) 5700 VRMS Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications. This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits. Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier. Apparent charge is electrical discharge caused by a partial discharge (pd). All pins on each side of the barrier tied together creating a two-terminal device. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ISO5851-Q1 ISO5851-Q1 www.ti.com SLLSEQ1A – SEPTEMBER 2016 – REVISED DECEMBER 2016 7.7 Safety-Related Certifications VDE CSA UL CQC TUV Certified according to GB 4943.1-2011 Certified according to EN 61010-1:2010 (3rd Ed) and EN 609501:2006/A11:2009/A1:2010/ A12:2011/A2:2013 Reinforced Insulation Maximum Transient isolation voltage, 8000 VPK; Maximum surge isolation voltage, 8000 VPK, Maximum repetitive peak isolation voltage, 2121 VPK Isolation Rating of 5700 VRMS; Reinforced insulation per CSA 60950-1- 07+A1+A2 and IEC 60950-1 (2nd Ed.), 800 VRMS max working voltage (pollution Single Protection, 5700 VRMS degree 2, material group I) ; (1) 2 MOPP (Means of Patient Protection) per CSA 606011:14 and IEC 60601-1 Ed. 3.1, 250 VRMS (354 VPK) max working voltage Reinforced Insulation, Altitude ≤ 5000m, Tropical climate, 400 VRMS maximum working voltage 5700 VRMS Reinforced insulation per EN 61010-1:2010 (3rd Ed) up to working voltage of 600 VRMS 5700 VRMS Reinforced insulation per EN 609501:2006/A11:2009/A1:2010/ A12:2011/A2:2013 up to working voltage of 800 VRMS Certification completed Certificate number: 40040142 Master contract number: 220991 Certification completed Certificate number: CQC16001141761 Certification completed Client ID number: 77311 Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 and DIN EN 60950-1 (VDE 0805 Teil 1):2011-01 Certified according to CSA Component Acceptance Notice 5A, IEC 60950-1, and IEC 60601-1 (1) Certified according to UL 1577 Component Recognition Program Certification completed File number: E181974 Production tested ≥6840 VRMS for 1 second in accordance with UL 1577. 7.8 Safety Limiting Values Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures. PARAMETER IS Safety input, output or supply current PS Safety input, output, or total power TS Maximum ambient safety temperature TEST CONDITIONS TYP MAX 349 RθJA = 99.6°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C 228 RθJA = 99.6°C/W, VI = 15 V, TJ = 150°C, TA = 25°C 84 RθJA = 99.6°C/W, VI = 30 V, TJ = 150°C, TA = 25°C (1) MIN RθJA = 99.6°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C RθJA = 99.6°C/W, TJ = 150°C, TA = 25°C UNIT mA 42 1255 (1) 150 mW °C Input, output, or the sum of input and output power should not exceed this value The safety-limiting constraint is the maximum junction temperature specified in the data sheet. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of a device installed on a high-K test board for leaded surface-mount packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ISO5851-Q1 7 ISO5851-Q1 SLLSEQ1A – SEPTEMBER 2016 – REVISED DECEMBER 2016 www.ti.com 7.9 Electrical Characteristics Over recommended operating conditions unless otherwise noted. All typical values are at TA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 2.25 V VOLTAGE SUPPLY VIT+(UVLO1) Positive-going UVLO1 threshold voltage input side (VCC1 – GND1) VIT-(UVLO1) Negative-going UVLO1 threshold voltage input side (VCC1 – GND1) VHYS(UVLO1) UVLO1 Hysteresis voltage (VIT+ – VIT–) input side VIT+(UVLO2) Positive-going UVLO2 threshold voltage output side (VCC2 – GND2) VIT-(UVLO2) Negative-going UVLO2 threshold voltage output side (VCC2 – GND2) VHYS(UVLO2) UVLO2 Hysteresis voltage (VIT+ – VIT–) output side IQ1 Input supply quiescent current 2.8 4.5 mA IQ2 Output supply quiescent current 3.6 6 mA 1.7 V 0.24 12 9.5 V 13 V 11 V 1 V LOGIC I/O VIT+(IN,RST) Positive-going input threshold voltage (IN+, IN–, RST) VIT-(IN,RST) Negative-going input threshold voltage (IN+, IN–, RST) VHYS(IN,RST) Input hysteresis voltage (IN+, IN–, RST) IIH High-level input leakage at (IN+) IN+ = VCC1 IIL Low-level input leakage at (IN–, RST) IN– = GND1, RST = GND1 IPU Pull-up current of FLT, RDY V(RDY) = GND1, V(FLT) = GND1 VOL Low-level output voltage at FLT, RDY I(FLT) = 5 mA 0.7 × VCC1 0.3 × VCC1 V V 0.15 × VCC1 V 100 µA –100 µA 100 µA 0.2 V 2 V GATE DRIVER STAGE V(OUTPD) Active output pulldown voltage IOUT = 200 mA, VCC2 = open V(OUTH) High-level output voltage IOUT = –20 mA V(OUTL) Low-level output voltage IOUT = 20 mA I(OUTH) High-level output peak current IN+ = high, IN– = low, VOUT = VCC2 - 15 V 1.5 2.5 A I(OUTL) Low-level output peak current IN+ = low, IN– = high, VOUT = VEE2 + 15 V 3.4 5 A VCC2 – 0.5 VCC2 – 0.24 VEE2 + 13 V VEE2 + 50 mV ACTIVE MILLER CLAMP V(CLP) Low-level clamp voltage I(CLP) = 20 mA I(CLP) Low-level clamp current V(CLAMP) = VEE2 + 2.5 V V(CLTH) Clamp threshold voltage VEE2 + 0.015 VEE2 + 0.08 V 1.6 2.5 1.6 2.1 2.5 A V 1.3 V SHORT CIRCUIT CLAMPING V(CLP_OUT) Clamping voltage (VOUT - VCC2) IN+ = high, IN– = low, tCLP = 10 µs, I(OUTH) = 500 mA 0.8 V(CLP_CLAMP) Clamping voltage (VCLP - VCC2) IN+ = high, IN– = low, tCLP = 10 µs, I(CLP) = 500 mA 1.3 V(CLP_CLAMP) Clamping voltage at CLAMP IN+ = High, IN– = Low, I(CLP) = 20 mA 0.7 1.1 V 0.58 mA V DESAT PROTECTION I(CHG) Blanking capacitor charge current V(DESAT) - GND2 = 2 V 0.42 0.5 I(DCHG) Blanking capacitor discharge current V(DESAT) - GND2 = 6 V 9 14 V(DSTH) DESAT threshold voltage with respect to GND2 8.3 9 V(DSL) DESAT voltage with respect to GND2, when OUT is driven low 0.4 8 Submit Documentation Feedback mA 9.5 V 1 V Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ISO5851-Q1 ISO5851-Q1 www.ti.com SLLSEQ1A – SEPTEMBER 2016 – REVISED DECEMBER 2016 7.10 Switching Characteristics Over recommended operating conditions unless otherwise noted. All typical values are at TA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V MIN TYP MAX tr Output signal rise time PARAMETER 12 20 35 ns tf Output signal fall time 12 20 37 ns tPLH, tPHL Propagation Delay 76 110 ns tsk-p Pulse Skew |tPHL – tPLH| 20 ns tsk-pp Part-to-part skew 30 (1) ns tGF TEST CONDITIONS CLOAD = 1 nF, see Figure 38, Figure 39, and Figure 40 Glitch filter on IN+, IN–, RST tDESAT (10%) DESAT sense to 10% OUT delay tDESAT (GF) DESAT glitch filter delay tDESAT (FLT) DESAT sense to FLT-low delay see Figure 40 Leading edge blanking time see Figure 38 and Figure 39 tGF(RSTFLT) Glitch filter on RST for resetting FLT CI Input capacitance (2) VI = VCC1 /2 + 0.4 x sin (2πft), f = 1 MHz, VCC1 = 5 V CMTI Common-mode transient immunity VCM = 1500 V, see Figure 41 (1) (2) 20 30 40 ns 300 415 500 ns 330 tLEB UNIT 330 ns 2000 2420 ns 400 500 ns 800 ns 300 2 100 120 pF kV/μs Measured at same supply voltage and temperature condition Measured from input pin to ground. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: ISO5851-Q1 9 ISO5851-Q1 SLLSEQ1A – SEPTEMBER 2016 – REVISED DECEMBER 2016 www.ti.com 7.11 Insulation Characteristics Curves 1.E+11 1.E+10 Safety Margin Zone: 1800 VRMS, 254 Years Operating Zone: 1500 VRMS, 135 Years TDDB Line (