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LDC1000-Q1
SLOS886B – SEPTEMBER 2014 – REVISED OCTOBER 2014
LDC1000-Q1 Inductance to Digital Converter
1 Features
3 Description
•
•
Inductive sensing is a contactless, short-range
sensing technology that enables low-cost, highresolution sensing of conductive targets in the
presence of dust, dirt, oil, and moisture, making this
technology extremely reliable in harsh environments.
Using a coil that can be created for example on a
PCB as a sensing element, the LDC1000-Q1 device
enables ultra-low cost system solutions.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 0: –40°C to 150°C
Ambient Operating Temperature Range E
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature Range Q
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level C6
Magnet-Free Operation
Sub-Micron Precision
Adjustable Sensing Range (through Coil Design)
Lower System Cost
Remote Sensor Placement (Decoupling the LDC
from Harsh Environments)
High Durability (by Virtue of Contact-Less
Operation)
Insensitivity to Environmental Interference (such
as Dirt, Dust, Water, Oil)
Supply Voltage, Analog: 4.75 to 5.25 V
Supply Voltage, IO: 1.8 to 5.25 V
Supply Current (Without LC Tank): 1.7 mA
RP Resolution: 16-bit
L Resolution: 24-bit
LC Frequency Range: 5 kHz to 5 MHz
2 Applications
The LDC1000-Q1 device is the first automotivequalified LDC, offering the benefits of inductive
sensing in a low-power, small-footprint solution. The
product is available in a 16-pin TSSOP package and
offers several modes of operation. An SPI interface
simplifies connection to an MCU.
Device Information(1)
PART NUMBER
LDC1000-Q1
PACKAGE
TSSOP (16)
BODY SIZE (NOM)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application — Axial Distance Sensing
Drive-by-Wire Systems
Gear-Tooth Counting
Flow Meters
Push-Button Switches
Rotational Position Sensor
Linear Position Sensor
Pedal Position Sensor
Throttle Position Sensor
LDC Output (Rp)
•
•
•
•
•
•
•
•
Inductive sensing technology enables precise
measurement of linear or angular position,
displacement, motion, compression, vibration, metal
composition, and many other applications in markets
including automotive, consumer, computer, industrial,
medical, and communications. Inductive sensing
offers better performance and reliability at lower cost
than other competitive solutions.
0.25
0.5
0.75
Distance
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LDC1000-Q1
SLOS886B – SEPTEMBER 2014 – REVISED OCTOBER 2014
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
6
7
Absolute Maximum Ratings ......................................
Handling Ratings.......................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3
7.4
7.5
7.6
8
Feature Description................................................... 8
Device Functional Modes........................................ 12
Programming........................................................... 14
Register Map........................................................... 16
Application and Implementation ........................ 26
8.1 Application Information............................................ 26
8.2 Typical Application ................................................. 28
9 Power Supply Recommendations...................... 32
10 Layout................................................................... 32
10.1 Layout Guidelines ................................................. 32
10.2 Layout Example .................................................... 33
11 Device and Documentation Support ................. 34
11.1 Trademarks ........................................................... 34
11.2 Electrostatic Discharge Caution ............................ 34
11.3 Glossary ................................................................ 34
12 Mechanical, Packaging, and Orderable
Information ........................................................... 34
4 Revision History
Changes from Revision A (September 2014) to Revision B
•
Changed pin configuration image and removed DAP from Pin Functions table .................................................................... 3
Changes from Original (September 2014) to Revision A
•
2
Page
Page
Changed the device status from Product Preview to Production Data ................................................................................. 1
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5 Pin Configuration and Functions
PW Package
16-Pin TSSOP
Top View
SCLK
1
16
INTB
CSB
2
15
XOUT
SDI
3
14
TBCLK/XIN
VIO
4
13
CLDO
SDO
5
12
VDD
DGND
6
11
GND
CFB
7
10
INB
CFA
8
9
INA
Pin Functions
PIN
TYPE (1)
DESCRIPTION
NO.
NAME
1
SCLK
DI
SPI clock input. The SCLK pin is used to clock-out and clock-in the data from or into the chip
2
CSB
DI
SPI CSB. Multiple devices can be connected on the same SPI bus and the CSB pin can be used to
select which device is communicated with.
3
SDI
DI
SPI Slave Data In (Master Out Slave In). This pin should be connected to the Master Out Slave In of
the master device.
4
VIO
P
Digital IO Supply
5
SDO
DO
6
DGND
P
Digital ground
7
CFB
A
LDC filter capacitor
8
CFA
A
LDC filter capacitor
9
INA
A
External LC Tank. Connect this pin to an external LC tank.
10
INB
A
External LC Tank. Connect this pin to an external LC tank.
11
GND
P
Analog ground
12
VDD
P
Analog supply
13
CLDO
A
LDO bypass capacitor. Connect a 56-nF capacitor from this pin to GND.
14
TBCLK/XIN
DI/A
External time-base clock and XTAL. This pin is either an external clock or is connected to a crystal.
15
XOUT
A
XTAL. Crystal out. Connecting an 8-Mhz crystal between the TBCLK/XIN pin and the XOUT pin with
20-pF capacitor from each pin to ground is recommended. This pin should be floating when an
external clock is used.
16
INTB
DO
(1)
SPI Slave Data Out (Master In Slave Out). This pin is high-Z when the CSB pin is high.
Configurable interrupt. This pin can be configured to function in three different ways (threshold detect,
wakeup, or DRDYB) by programing the INT pin mode register.
DO: Digital Output, DI: Digital Input, P: Power, A: Analog
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
5.5
V
5.5
V
VDD + 0.3
V
Analog supply voltage
VDD – GND
IO supply voltage
VIO – GND
Voltage
On any pin
–0.3
On any digital pin
–0.3
VIO + 0.3
V
8
mA
150
°C
Input Current
INA and INB
Junction Temperature, TJ
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 Handling Ratings
Tstg
V(ESD)
(1)
MIN
MAX
UNIT
–65
150
°C
Human body model (HBM), per AEC Q100-002 (1)
–2000
2000
Charged device model (CDM), per AEC Q100-011, all pins
–1000
1000
Storage temperature range
Electrostatic discharge
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VDD
Analog supply voltage (VDD – GND)
4.75
5.25
V
VIO
IO supply voltage (VIO – GND)
1.8
5.25
V
VDD – VIO
≥0
Operating temperature (see the Mechanical,
Packaging, and Orderable Information section for
package options)
TA
V
Grade 0 (temperature range E)
–40
150
Grade 1 (temperature range Q)
–40
125
°C
6.4 Thermal Information
THERMAL METRIC (1)
PW
16 PINS
RθJA
Junction-to-ambient thermal resistance
106.3
RθJC(top)
Junction-to-case (top) thermal resistance
40.8
RθJB
Junction-to-board thermal resistance
51.3
ψJT
Junction-to-top characterization parameter
3.6
ψJB
Junction-to-board characterization parameter
50.8
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
(1)
4
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
Unless otherwise specified, all limits ensured for TA = 25°C, VDD = 5 V, VIO = 3.3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
4.75
5
5.25
V
1.8
3.3
5.25
V
1.7
2.3
mA
14
µA
POWER
VDD
Analog supply voltage
VIO
IO supply voltage
VIO ≤ VDD
IDD
Supply current
Does not include the LC
tank current
IIO
IO supply current
Static current
IDD(LP)
Low-power mode supply current
Without LC tank
t(start)
Start-up time
From POR to ready-toconvert. Crystal not used
for frequency counter
250
µA
2
ms
LDC
fsensor_min
Minimum sensor frequency
5
kHz
fsensor_max
Maximum sensor frequency
5
MHz
Asensor_min
Minimum sensor amplitude
1
VPP
Asensor_max
Maximum sensor amplitude
4
VPP
10
1 / fsensor
Oscillation start-up time
after RP under-range
condition
trec
Recovery time
ZRP_min
Minimum sensor RP range
798
Ω
RRP_max
Maximum sensor RP range
3.93
MΩ
RRP_res
RP measurement resolution
16
Bits
tres(min)
Minimum response time
Minimum programmable
settling time of digital filter
192 × 1 / fsensor
s
tres(max)
Maximum response time
Maximum programmable
settling time of digital filter
6144 × 1 / fsensor
s
EXTERNAL CLOCK AND CRYSTAL FOR FREQUENCY COUNTER
fref
Crystal frequency
txtalst
Crystal startup time
8
MHz
30
ms
External clock frequency
8
External clock input high voltage
MHz
VIO
V
DIGITAL I/O CHARACTERISTICS
0.8 ×
VIO
VIH
Logic 1 input voltage
VIL
Logic 0 input voltage
VOH
Logic 1 output voltage
I(SOURCE) = 400 µA
VOL
Logic 0 output voltage
I(SINK) = 400 µA
IlkgIO
Digital IO leakage current
V
0.2 × VIO
VIO– 0.3
–500
V
0.3
V
500
nA
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5
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6.6 Timing Requirements
Unless otherwise noted, all limits specified at TA = 25°C, VDD = 5 V, VIO = 3.3 V, 10-pF capacitive load in parallel with a 10-kΩ
load on the SDO. Specified by design; not production tested. See Figure 1
MIN
NOM
MAX
UNIT
4
MHz
fSCLK
Serial clock frequency
See Figure 1
twH
SCLK pulse-width high
fSCLK = 4 Mhz, See Figure 1
0.4 / fSCLK
twL
SCLK pulse-width low
fSCLK = 4 Mhz, See Figure 1
0.4 / fSCLK
s
tsu
SDI setup time
10
ns
th
SDI hold time
10
ns
tODZ
SDO driven-to-tristate
time
Measured at 10% / 90% point, See
Figure 2
20
ns
tOZD
SDO tristate-to-driven
time
Measured at 10% / 90% point, See
Figure 2
20
ns
td(OUTPUT)
SDO output delay time
20
ns
tsu(CS)
CSB setup time
th(CS)
CSB hold time
tIAG
inter-access gap
See Figure 16
Data ready pulse width
Data ready pulse at every 1 / ODR if no
data is read
tw(DRDY)
See Figure 1
See Figure 2
ttwLt
s
20
ns
20
ns
100
ns
1 / fsensor
ttwHt
s
16th Clock
SCLK
ttsut
ttht
Valid Data
SDI
Valid Data
Figure 1. Write Timing Diagram
1st Clock
8th Clock
16th Clock
SCLK
th(CS)
tsu(CS)
th(CS)
tsu(CS)
CSB
tOZD
SDI
tODZ
D7
D1
ttht
D0
Figure 2. Read Timing Diagram
6
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6.7 Typical Characteristics
14
60
12
50
Code (decimal)
Rp (k
10
8
6
4
40
30
20
10
2
0
0
0
1
2
3
4
5
6
Distance (mm)
Sensor Details: Table 21
Target Material: Stainless Steel
7
8
0
Rp_MIN: 1.347 kΩ
Rp_MAX: 38.785 kΩ
1
2
3
4
5
6
7
Distance (mm)
C002
Sensor Details: Table 21
Target Material: Stainless Steel
Figure 3. RP vs Distance
8
C003
Rp_MIN: 1.347 kΩ
Rp_MAX: 38.785 kΩ
Figure 4. Proximity Data vs Distance
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7 Detailed Description
7.1 Overview
The LDC1000-Q1 device is an inductance-to-digital converter that simultaneously measures the impedance and
resonant frequency of an LC resonator. The device accomplishes this task by regulating the oscillation amplitude
in a closed-loop configuration to a constant level, while monitoring the energy dissipated by the resonator. By
monitoring the amount of power injected into the resonator, the LDC1000-Q1 device can determine the value of
RP. When the value is determined, the device returns this as a digital value which is inversely proportional to RP.
In addition, the LDC1000-Q1 device also measure the oscillation frequency of the LC circuit. This frequency is
used to determine the inductance of the LC circuit. The device outputs a digital value that is inversely
proportional to frequency.
The threshold detector block provides a comparator with hysteresis. With the threshold registers programed and
comparator enabled, the proximity data register is compared with threshold registers and INTB pin indicates the
output.
The device has a simple 4-wire SPI interface. The INTB pin provides multiple functions which are programmable
with SPI.
The device has separate analog and I/O supplies. The analog supply operates at 5 V and the I/O operates at 1.8
to 5 V. The integrated LDO requires a 56-nF capacitor connected from the CLDO pin to GND.
7.2 Functional Block Diagram
CFA
CFB
Threshold
Detector
L
INA
Proximity Data
Register
LDC
C
INB
SCLK
4-Wire
Serial
Interface
Frequency
Counter Data
Register
SDI
SDO
CSB
INTB
rs
Power
VDD
GND
VIO
Frequency Counter
DGND
CLDO
TBCLK/XIN
XOUT
7.3 Feature Description
7.3.1 Inductive Sensing
An alternating current (AC) flowing through a coil generates an AC magnetic field. If a conductive material, such
as a metal target, is brought into the vicinity of the coil, this magnetic field induces circulating currents (eddy
currents) on the surface of the target. These eddy currents are a function of the distance, size, and composition
of the target. These eddy currents then generate a magnetic field that opposes the original field generated by the
coil. This mechanism is best compared to a transformer, where the coil is the primary core and the eddy current
is the secondary core. The inductive coupling between both cores depends on distance and shape. Hence the
resistance and inductance of the secondary core (eddy current), shows up as a distant dependent resistive and
inductive component on the primary side (coil). Figure 5 through Figure 8 show a simplified circuit model.
8
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Feature Description (continued)
d
Metal
Target
Figure 5. Inductor with a Metal Target
Eddy currents generated on the surface of the target can be modeled as a transformer as shown in Figure 6. The
coupling between the primary and secondary coils is a function of the distance and characteristics of the
conductor. In Figure 6, the inductance Ls is the inductance of the coil, and rs is the parasitic series resistance of
the coil. The inductance L(d), which is a function of distance, d, is the coupled inductance of the metal target.
Likewise, R(d) is the parasitic resistance of the eddy currents.
Eddy
Currents
Ls + L(d)
Conductance
of Metal
Target Metal
Surface
Distance d
rs + R(d)
Figure 6. Metal Target Modeled as L and R With Circulating Eddy Currents
Generating an alternating magnetic field with just an inductor consumes a large amount of power. This power
consumption can be reduced by adding a parallel capacitor, turning the right part of Figure 6 into a resonator as
shown in Figure 7 . In this manner the power consumption is reduced to the eddy and inductor losses rs + R(d)
only.
L(d)
C
Oscillator
rs(d)
Figure 7. LC Tank Connected to Oscillator
The LDC1000-Q1 device does not directly measure the series resistance. Instead, the device measures the
equivalent parallel resonance impedance RP (see Figure 8). This representation is equivalent to the
representation shown in Figure 8 , where the parallel resonance impedance RP(d) is given by Equation 1.
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Feature Description (continued)
L(d)
C
RP(d)
Oscillator
Figure 8. Equivalent Resistance of rs in Parallel With LC Tank
RP(d) = (1 ⁄ ([rs + R(d)]) × ([Ls + L(d)]) / C
RP = (1 / rs) × (L / C)
(1)
(2)
Figure 9 shows the variation in RP as a function of distance for a 14-mm diameter PCB coil (23 turns, 4-mil trace
width, 4-mil spacing between trace,1-oz copper thickness, FR4). The target metal used is a stainless steel 2-mm
thick.
20
Equivalent Parallel
Resonance Impedance (kΩ)
18
16
14
12
10
8
6
4
2
0
0
1
2
3
4
5
Distance (mm)
6
7
8
C001
Figure 9. Typical RP versus Distance With a 14-mm PCB Coil
7.3.2 Measuring Parallel Resonance Impedance and Inductance with LDC1000-Q1
The LDC1000-Q1 device is an inductance-to-digital converter that simultaneously measures the impedance and
resonant frequency of an LC resonator. The device accomplishes this task by regulating the oscillation amplitude
in a closed-loop configuration to a constant level, while monitoring the energy dissipated by the resonator. By
monitoring the amount of power injected into the resonator, the LDC1000-Q1 device can determine the value of
RP. The device returns this value as a digital value which is inversely proportional to RP. In addition, the
LDC1000-Q1 device can also measure the oscillation frequency of the LC circuit. This frequency is used to
determine the inductance of the LC circuit. The oscillation frequency is returned as a digital value.
The LDC1000-Q1 device supports a wide range of LC combinations with oscillation frequencies ranging from 5
kHz to 5 MHz and RP ranging from 798 Ω to 3.93 MΩ. This range of RP can be viewed as the maximum input
range of an ADC. As shown in Figure 9, the range of RP is typically much smaller than maximum input range
supported by the LDC1000-Q1 device. To achieve better resolution in the desired sensing range, the LDC1000Q1 device offers a programmable input range through the Rp_MIN and Rp_MAX registers. See the Calculation
of Rp_Min and Rp_Max section for how to set these registers.
When the resonance impedance of the sensor, RP, drops below the programed Rp_MIN, the RP output of the
LDC will clip at the full scale output. An example occurrence of this situation is when a target comes too close to
the coil.
10
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Feature Description (continued)
30000
Code (decimal)
25000
20000
15000
10000
5000
0
12
17
22
27
32
37
Equivalent Parallel Resonance Impedance (kΩ)
42
47
C001
Figure 10. Transfer Characteristics of LDC1000-Q1 With Rp_MIN = 16.160 kΩ and Rp_MAX = 48.481 kΩ
Use Equation 3 to calculate the resonance impedance from the digital output code.
RP = (Rp_MAX × Rp_MIN ) / (Rp_MIN × (1 – Y) + Rp_MAX × Y), in Ω.
Where:
•
•
Y = Proximity Data / 215
Proximity data is the LDC output, register address 0x21 and 0x22.
(3)
Example: If Proximity data (address 0x22 to 0x21) is 5000, Rp_MIN is 2.394 kΩ, and Rp_MAX is 38.785 kΩ, the
resonance impedance is given by:
Y = 5000 / 215 = 0.1526
RP = (38785 × 2394) / (2394 × (1 – 0.1526) + 38785 × 0.1526) =(92851290) / (2028.675 + 5918.591)
RP = 11.683 kΩ
(4)
(5)
(6)
0.6
140
0.5
120
100
0.4
Count
0.3
0.2
80
60
40
0.1
Distance (mm)
1.2
1.00
1.0
0.75
0.8
0.50
0.6
0.25
0.4
0.00
0.2
±0.25
0
0.0
±0.50
0.0
±0.75
20
±1.00
RMS Noise (µm)
Figure 11 and Figure 12 show the change in RMS noise versus distance and a histogram of noise, with the
target at an 0.8-mm distance from the sensor coil. Data was collected with a 14-mm PCB coil (23 turns, 4-mil
trace width, 4-mil spacing between trace,1-oz copper thickness, FR4) with a sensing range of 0.125 mm to 1.125
mm. At a distance of 0.8 mm, the RMS noise is approximately 250 nm.
C001
Figure 11. Typical RMS Noise versus Distance With PCB
Coil
Deviation (µm)
C001
Figure 12. Histogram of Output Codes at 0.8-mm Distance
NOTE
Although the LDC1000-Q1 device has high resolution, the absolute accuracy depends on
offset and gain correction which can be achieved by two-point calibration.
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Feature Description (continued)
7.3.2.1 Measuring Inductance
The LDC1000-Q1 device measures the frequency of the oscillation of the sensor by a frequency counter. The
frequency counter timing is set by an external clock or crystal. Either the external clock (8 MHz typical) from a
microcontroller can be provided on the TBCLK/XIN pin or a crystal can be connected on the TBCLK/XIN and
XOUT pins. The clock mode is controlled through clock configuration register (address 0x05). The sensor
resonance frequency is derived from the frequency-counter register value (see the Frequency Counter LSB
(offset = 0x23) [reset = NA] section through the Frequency Counter MSB (offset = 0x25) [reset = NA] section) as
shown in Equation 7.
fsensor = (1/3) × (fext / fcount) × tres
where
•
•
•
•
fsensor is the sensor frequency
fext is the frequency of the external clock or crystal
fcount is the value obtained from the Frequency Counter Data register (see the Frequency Counter LSB (offset =
0x23) [reset = NA] section through the Frequency Counter MSB (offset = 0x25) [reset = NA] section)
tres is the programmed response time (see the LDC Configuration (offset = 0x04) [reset = 0x1B] section)
(7)
The inductance in H can be calculated with Equation 8.
L=1 / [C × (2 × π × fsensor)2]
where
•
C is the parallel capacitance of the resonator
(8)
7.3.2.1.1 Example
If the following values are selected, fext = 6 Mhz, tres = 6144, C = 10 0pF, and measured fcount = 3000 (decimal)
(see the Frequency Counter LSB (offset = 0x23) [reset = NA] section through the Frequency Counter MSB (offset
= 0x25) [reset = NA] section) then:
fsensor = 1/3 × (6000000 / 3000) × (6144) = 4.096 MHz
(9)
Now use Equation 10.
L = 1 / [C × (2 × π × fsensor)2]
where
•
L = 15.098 µH
(10)
The accuracy of measurement largely depends upon the choice of the external time-base clock (TBCLK) or the
crystal oscillator (XIN and XOUT).
7.4 Device Functional Modes
7.4.1 INTB Pin Modes
The INTB pin is a configurable output pin which can be used to drive an interrupt on an MCU. The LDC1000-Q1
device provides three different modes on the INTB pin which include:
1. Comparator mode
2. Wake-up mode
3. DRDY mode
The LDC1000-Q1 device has a built-in high trigger and low trigger threshold registers that can be a comparator
with programmable hysteresis or a special mode that is used to wake-up an MCU. The following sections
describe these modes in detail.
7.4.1.1 Comparator Mode
In the comparator mode, the INTB pin is asserted or de-asserted when the proximity register value increases
above the threshold high registers or decreases below the threshold low registers respectively. In this mode, the
function of the LDC1000-Q1 device is a proximity switch with programmable hysteresis.
12
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Device Functional Modes (continued)
Threshold High
RP Data
Threshold Low
INTB
t
Figure 13. Behavior of the INTB Pin in Comparator Mode
7.4.1.2 Wake-Up Mode
In wake-up mode, the INTB pin is asserted when proximity register value increases above the threshold high
registers and is deasserted when wake-up mode is disabled in the INTB pin mode register.
This mode can wake-up an MCU that is in sleep mode to conserve power.
Threshold High
RP Data
Threshold Low
INTB
CSB
SPI
SPI: INTB pin mode changed to DRDYB
t
Figure 14. Behavior of the INTB Pin in Wake-Up Mode
7.4.1.3 DRDYB Mode
In DRDY mode (default), the INTB pin is asserted every time the conversion data is available and is deasserted
when the read command on register 0x21 is registered internally. If the read command is in progress, the pin is
pulsed instead.
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Device Functional Modes (continued)
ODRt
t
INTB
CSB
CMD:
Read 0x21
SPI
Data
Read
t
Figure 15. Behavior of the INTB Pin in DRDYB Mode
7.5 Programming
7.5.1 Digital Interface
The LDC1000-Q1 device uses a 4-wire SPI interface to access control and data registers. The LDC1000-Q1
device is an SPI slave device and does not initiate any transactions.
7.5.1.1 SPI Description
A typical serial interface transaction begins with an 8-bit instruction that is comprised of a read-write (R/W) bit
(MSB, R = 1) and a 7-bit address of the register followed by a data field that is typically 8 bits. However, the data
field can be extended to a multiple of 8 bits by providing sufficient SPI clocks. See the Extended SPI
Transactions section.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
SCLK
tIAG
CSB
tCOMMAND FIELDt
SDI
tDATA FIELDt
C7
C6
C5
C4
C3
C2
C1
C0
R/Wb
A6
A5
A4
A3
A2
A1
A0
R/Wb = Read/Write
0: Write Data
1: Read Data
SDO
Address (7-bits)
D7
D6
(MSB)
D5
D4
D3
D2
D1
D0
(LSB)
D2
D1
D0
(LSB)
Write DATA
D7
D6
(MSB)
D5
High-Z
D4
D3
Read DATA
Data (8-bits)
tSingle Access Cyclet
Figure 16. Serial Interface Protocol
14
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Programming (continued)
Each assertion of the chip select bar (CSB) begins a new register access. The R/W bit in the command field
configures the direction of the access. A value of 0 indicates a write operation and a value of 1 indicates a read
operation. All output data is driven on the falling edge of the serial clock SCLK, and all input data is sampled on
the rising edge of the serial clock SCLK. Data is written into the register on the rising edge of the 16th clock.
Deasserting the CSB pin after the 16th clock is required. No data write occurs if the CSB pin is deasserted
before the 16th clock.
7.5.1.2 Extended SPI Transactions
A transaction can be extended to multiple registers by keeping the CSB pin asserted beyond the stated 16
clocks. In this mode, the register addresses increment automatically. The CSB pin must be asserted during 8 ×
(1+ N) clock cycles of SCLK, where N is the amount of bytes to write or read during the transaction.
During an extended read access, the SDO pin outputs register contents every 8 clock cycles after the initial 8
clocks of the command field. During an extended write access, the data is written to the registers every 8 clock
cycles after the initial 8 clocks of the command field.
Extended transactions can be used to read 16-bits of proximity data and 24-bits of frequency data all in one SPI
transaction by initiating a read from register 0x21.
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7.6 Register Map
Table 1. Register Map (1) (2)
REGISTER NAME
ADDRESS
TYPE (3)
DEFAULT
Device ID
0x00
R
0x80
Device ID
Rp_MAX
0x01
R/W
0x0E
Rp Maximum
Rp_MIN
0x02
R/W
0x14
Rp Minimum
Sensor Frequency
0x03
R/W
0x45
Min Resonating Frequency
LDC Configuration
0x04
R/W
0x1B
Clock Configuration 0x05
R/W
0x01
Comparator
Threshold High
LSB
0x06
R/W
0xFF
Threshold High LSB
Comparator
Threshold High
MSB
0x07
R/W
0xFF
Threshold High MSB
Comparator
Threshold Low
LSB
0x08
R/W
0x00
Threshold Low LSB
Comparator
Threshold Low
MSB
0x09
R/W
0x00
Threshold Low MSB
INTB Pin
Configuration
0x0A
R/W
0x00
Power
Configuration
0x0B
R/W
0x00
Status
0x20
R
Proximity Data LSB 0x21
R
Proximity Data[7-0]
Proximity Data
MSB
0x22
R
Proximity Data[15-8]
Frequency Counter
0x23
Data LSB
R
ODR LSB
Frequency Counter
0x24
Data Mid-Byte
R
ODR Mid Byte
Frequency Counter
0x25
Data MSB
R
ODR MSB
(1)
(2)
(3)
16
BIT 7
BIT 6
BIT 5
BIT 4
Reserved(000)
BIT 3
Amplitude
Reserved(000000)
BIT 2
BIT 1
Response Time
CLK_SEL
Reserved(00000)
DRDYB
Wake-up
CLK_PD
INTB_MODE
Reserved(0000000)
OSC Dead
BIT 0
Comparator
PWR_MODE
Don't Care
Values of bits which are unused should be set to default values only.
LEGEND R/W = read/write. R = read only. W = write only
When the device is in active mode (the PWR_MODE bit is SET), registers 0x01 through 0x05 are read only (R).
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7.6.1 Register Description
7.6.1.1 Revision ID (offset = 0x00) [reset = 0x80]
Figure 17. Revision ID Register
7
6
5
4
3
2
1
0
Revision ID
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 2. Revision ID Field Descriptions
Bit
Field
Type
Reset
Description
7-0
Revision ID
R
0x080
Revision ID of silicon.
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7.6.1.2 Rp_MAX (offset = 0x01) [reset = 0x0E]
Figure 18. Rp_MAX Register
7
6
5
4
3
2
1
0
Rp Maximum
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 3. Rp_MAX Field Descriptions
Bit
Field
Type
Reset
Description
7-0
Rp Maximum
R/W
0x0E
Maximum RP that the LDC1000-Q1 device must measure.
Configures the input dynamic range of the LDC1000-Q1 device.
Register setting for Rp_MAX (kΩ):
0x00 = 3926.991
0x01 = 3141.593
0x02 = 2243.995
0x03 = 1745.329
0x04 = 1308.997
0x05 = 981.748
0x06 = 747.998
0x07 = 581.776
0x08 = 436.332
0x09 = 349.066
0x0A = 249.333
0x0B = 193.926
0x0C = 145.444
0x0D = 109.083
0x0E = 83.111
0x0F = 64.642
0x10 = 48.481
0x11 = 38.785
0x12 = 27.704
0x13 = 21.547
0x14 = 16.16
0x15 = 12.12
0x16 = 9.235
0x17 = 7.182
0x18 = 5.387
0x19 = 4.309
0x1A = 3.078
0x1B = 2.394
0x1C = 1.796
0x1D = 1.347
0x1E = 1.026
0x1F = 0.798
18
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7.6.1.3 Rp_MIN (offset = 0x02) [reset = 0x14]
Figure 19. Rp_MIN Register
7
6
5
4
3
2
1
0
Rp Minimum
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4. Rp_MIN Field Descriptions
Bit
Field
Type
Reset
Description
7-0
Rp Minimum
R/W
0x014
Minimum RP that the LDC1000-Q1 device must measure.
Configures the input dynamic range of the LDC1000-Q1 device.
Register setting for Rp_MIN (kΩ):
0x20 = 3926.991
0x21 = 3141.593
0x22 = 2243.995
0x23 = 1745.329
0x24 = 1308.997
0x25 = 981.748
0x26 = 747.998
0x27 = 581.776
0x28 = 436.332
0x29 = 349.066
0x2A = 249.333
0x2B = 193.926
0x2C = 145.444
0x2D = 109.083
0x2E = 83.111
0x2F = 64.642
0x30 = 48.481
0x31 = 38.785
0x32 = 27.704
0x33 = 21.547
0x34 = 16.16
0x35 = 12.12
0x36 = 9.235
0x37 = 7.182
0x38 = 5.387
0x39 = 4.309
0x3A = 3.078
0x3B = 2.394
0x3C = 1.796
0x3D = 1.347
0x3E = 1.026
0x3F = 0.798
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7.6.1.4 Sensor Frequency (offset = 0x03) [reset = 0x45]
Figure 20. Sensor Frequency Register
7
6
5
4
3
Min Resonating Frequency
R/W
2
1
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5. Sensor Frequency Field Descriptions
Bit
Field
Type
Reset
Description
7-0
Min Resonating Frequency
R/W
0x45
Sets the minimum resonating frequency to approximately 20%
below the lowest resonating frequency of the sensor with no
target in front. Use the formula below to determine the value of
register.
N = 68.94 × log10(f / 2000)
where
•
•
N = Register Value. Round to nearest
value.
f = 20% below resonating frequency,
Hz
(11)
Example: Sensor frequency (fsensor) = 1 MHz
f = 0.8 × 1 MHz = 800 KHz
(12)
N = 68.94 × log10(800 KHz / 2000) = Round to nearest
whole number (179.38) = 179 (Value to be programmed
in the sensor frequency register)
(13)
7.6.1.5 LDC Configuration (offset = 0x04) [reset = 0x1B]
Figure 21. LDC Configuration Register
7
6
Reserved
—
5
4
3
2
Amplitude
R/W
1
Response Time
R/W
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6. LDC Configuration Field Descriptions
Bit
Field
Type
Reset
Description
7-5
Reserved
—
—
Reserved to 0
4-3
Amplitude
R/W
0x1B
Sets the oscillation amplitude
00: 1 V
01: 2 V
10: 4 V
11: Reserved
2-0
Response Time
R/W
0x1B
Sets the response time
000: Reserved
001: Reserved
010: 192
011: 384
100: 768
101: 1536
110: 3072
111: 6144
20
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7.6.1.6 Clock Configuration (offset = 0x05) [reset = 0x01]
Figure 22. Clock Configuration Register
7
6
5
4
3
2
1
CLK_SEL
R/W
Reserved
R/W
0
CLK_PD
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7. Clock Configuration Field Descriptions
Bit
Field
Type
Reset
Description
7-2
Resrved
—
—
Reserved to 0
CLK_SEL
R/W
0x01
1
1:External crystal used for frequency counter (XIN or
XOUT).
0:External time-base clock used for frequency counter
(TBCLK).
0
CLK_PD
R/W
0x01
1:Disable external time base clock. Crystal oscillator
power down.
0:Enable External time base clock.
7.6.1.7 Comparator Threshold High LSB (offset = 0x06) [reset = 0xFF]
Figure 23. Comparator Threshold High LSB Register
7
Threshold
High[7:0]
R/W
6
Threshold
High[6]
R/W
5
Threshold
High[5]
R/W
4
Threshold
High[4]
R/W
3
Threshold
High[3]
R/W
2
Threshold
High[2]
R/W
1
Threshold
High[1]
R/W
0
Threshold
High[0]
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8. Comparator Threshold High LSB Field Descriptions
Bit
Field
Type
Reset
Description
7:0
Threshold High LSB
Threshold High[7:0]
R/W
0xFF
Least Significant byte (LSB) of the threshold high register. This
register is a buffer. A read reflects the current value of the
threshold high[7:0] register. See the Comparator Threshold High
MSB (offset = 0x07) [reset = 0xFF] section for details on
updating the threshold high register.
7.6.1.8 Comparator Threshold High MSB (offset = 0x07) [reset = 0xFF]
Figure 24. Comparator Threshold High MSB Register
7
Threshold
High[15]
R/W
6
Threshold
High[14]
R/W
5
Threshold
High[13]
R/W
4
Threshold
High[12]
R/W
3
Threshold
High[11]
R/W
2
Threshold
High[10]
R/W
1
Threshold
High[9]
R/W
0
Threshold
High[8]
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9. Comparator Threshold High MSB Field Descriptions
Bit
Field
Type
Reset
Description
7:0
Threshold High MSB
Threshold High[15:8]
R/W
0xFF
Most significant byte (MSB) of the threshold high register. A
write to this register copies the contents of the 0x06 register and
writes to the threshold high register[15:0]. A read returns the
threshold high [15:8] register. To update the threshold high
register write register 0x06 first and then 0x07.
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7.6.1.9 Comparator Threshold Low LSB (offset = 0x08) [reset = 0x00]
Figure 25. Comparator Threshold Low LSB Register
7
Threshold
Low[7:0]
R/W
6
Threshold
Low[6]
R/W
5
Threshold
Low[5]
R/W
4
Threshold
Low[4]
R/W
3
Threshold
Low[3]
R/W
2
Threshold
Low[2]
R/W
1
Threshold
Low[1]
R/W
0
Threshold
Low[0]
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10. Comparator Threshold Low LSB Field Descriptions
Bit
Field
Type
Reset
Description
7:0
Threshold Low LSB
Threshold Low[7:0]
R/W
0x00
Least significant byte of the threshold low value. This register is
a buffer. A read reflects the current value of the threshold low
[7:0] register. See the Comparator Threshold Low MSB (offset =
0x09) [reset = 0x00] section for details on updating the threshold
low register.
7.6.1.10 Comparator Threshold Low MSB (offset = 0x09) [reset = 0x00]
Figure 26. Comparator Threshold Low MSB Register
7
Threshold
Low[15]
R/W
6
Threshold
Low[14]
R/W
5
Threshold
Low[13]
R/W
4
Threshold
Low[12]
R/W
3
Threshold
Low[11]
R/W
2
Threshold
Low[10]
R/W
1
Threshold
Low[9]
R/W
0
Threshold
Low[8]
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11. Comparator Threshold Low MSB Field Descriptions
Bit
Field
Type
Reset
Description
7:0
Threshold Low MSB
Threshold Low[15:8]
R/W
0x00
Most significant byte of the threshold low register. A write to this
register copies the contents of the 0x08 register and writes to
the threshold low register[15:0]. A read returns the threshold low
[15:8] register. To update the threshold low register write register
address 0x08 first and then 0x09.
7.6.1.11 INTB Pin Configuration (offset = 0x0A) [reset = 0x00]
Figure 27. INTB Pin Configuration Register
7
6
5
Reserved
—
4
3
2
1
Mode
R/W
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12. INTB Pin Configuration Field Descriptions
Bit
Field
Type
Reset
Description
7:3
Reserved
—
—
Reserved to 0
2:0
Mode
R/W
0x00
100: DRDYB enabled on the INTB pin
010: The INTB pin indicates the status of the comparator output
001: Wake-up enabled on the INTB pin
000: All modes disabled
All other combinations are reserved
22
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7.6.1.12 Power Configuration (offset = 0x0B) [reset = 0x00]
Figure 28. Power Configuration Register
7
6
5
4
Reserved
—
3
2
1
0
PWR_MODE
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13. Power Configuration Field Descriptions
Bit
Field
Type
Reset
Description
7:1
Reserved
—
—
Reserved to 0
PWR_MODE
R/W
0x00
0: Stand-by mode
0
1: Active mode. Conversion is enabled
7.6.1.13 Status (offset = 0x20) [reset = NA]
Figure 29. Status Register
7
OSC status
R
6
Data Ready
R
5
Wake-up
R
4
Comparator
R
3
2
1
0
Don't Care
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14. Status Field Descriptions
Bit
Field
Type
Reset
Description
7
OSC status
R
NA
1: Indicates that the oscillator is overloaded and has stopped
6
Data Ready
R
NA
5
Wake-up
R
NA
0: Oscillator is working
0: Data is ready to be read
1: No new data is available
0: Wake-up triggered. Proximity data is more than the threshold
high value.
1: Wake-up is disabled
4
Comparator
R
NA
0: Proximity data is more than the threshold high value
1: Proximity data is less than the threshold low value
3:0
Don't Care
R
NA
7.6.1.14 Proximity Data LSB (offset = 0x21) [reset = NA]
Figure 30. Proximity Data LSB Register
7
Proximity
Data[7]
R
6
Proximity
Data[6]
R
5
Proximity
Data[5]
R
4
Proximity
Data[4]
R
3
Proximity
Data[3]
R
2
Proximity
Data[2]
R
1
Proximity
Data[1]
R
0
Proximity
Data[0]
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15. Proximity Data LSB Field Descriptions
Bit
Field
Type
Reset
Description
7:0
Proximity Data[7:0]
R
NA
Least significant byte of proximity data
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7.6.1.15 Proximity Data MSB (offset = 0x22) [reset = NA]
Figure 31. Proximity Data MSB Register
7
Proximity
Data[15]
R
6
Proximity
Data[14]
R
5
Proximity
Data[13]
R
4
Proximity
Data[12]
R
3
Proximity
Data[11]
R
2
Proximity
Data[10]
R
1
Proximity
Data[9]
R
0
Proximity
Data[8]
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16. Proximity Data MSB Field Descriptions
Bit
Field
Type
Reset
Description
7:0
Proximity data[15:8]
R
NA
Most significant byte of proximity data
7.6.1.16 Frequency Counter LSB (offset = 0x23) [reset = NA]
Figure 32. Frequency Counter LSB Register
7
6
5
4
3
2
1
0
ODR[7]
R
ODR[6]
R
ODR[5]
R
ODR[4]
R
ODR[3]
R
ODR[2]
R
ODR[1]
R
ODR[0]
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 17. Frequency Counter LSB Field Descriptions
Bit
Field
Type
Reset
Description
7:0
ODR LSB
ODR[7:0]
R
NA
LSB of output data rate. Sensor frequency can be calculated
using the output data rate. See the Measuring Inductance
section.
7.6.1.17 Frequency Counter Mid-Byte (offset = 0x24) [reset = NA]
Figure 33. Frequency Counter Mid-Byte Register
7
ODR[15]
R
6
ODR[14]
R
5
ODR[13]
R
4
ODR[12]
R
3
ODR[11]
R
2
ODR[10]
R
1
ODR[9]
R
0
ODR[8]
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18. Frequency Counter Mid-Byte Field Descriptions
24
Bit
Field
Type
Reset
Description
7:0
ODR Mid byte
ODR[15:8]
R
NA
Middle byte of output data rate
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7.6.1.18 Frequency Counter MSB (offset = 0x25) [reset = NA]
Figure 34. Frequency Counter MSB Register
7
ODR[23]
R
6
ODR[22]
R
5
ODR[21]
R
4
ODR[20]
R
3
ODR[19]
R
2
ODR[18]
R
1
ODR[17]
R
0
ODR[16]
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19. Frequency Counter MSB Field Descriptions (1)
(1)
Bit
Field
Type
Reset
Description
7:0
ODR MSB
ODR[23:16]
R
NA
MSB of Output data rate
Care must be taken to ensure that the proximity data[15:0] and Frequency Counter[23:0] registers are all from same conversion.
Conversion data is updated to these registers only when a read is initiated on 0x21 register. If the read is delayed between subsequent
conversions, these registers are not updated until another read is initiated on 0x21.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Calculation of Rp_Min and Rp_Max
Different sensing applications may have a different ranges of the resonance impedance RP to measure. The
LDC1000-Q1 measurement range of RP is controlled by setting two registers: Rp_MIN and Rp_MAX. For a given
application, RP must never be outside the range set by these register values, otherwise the measured value will
be clipped. For optimal sensor resolution, the range of Rp_MIN to Rp_MAX should not be unnecessarily large.
The following procedure is recommended to determine the Rp_MIN and Rp_MAX register values.
8.1.1.1 Rp_MAX
Rp_MAX sets the upper limit of the LDC1000-Q1 resonant impedance input range.
•
•
•
Configure the sensor such that the eddy-current losses are minimized. As an example, for a proximity sensing
application, set the distance between the sensor and the target to the maximum sensing distance.
Measure the resonant impedance RP using an impedance analyzer.
Multiply RP by 2 and use the next higher value from the register settings listed in Table 3.
For example, if RP is measured at 18 kΩ, 18000 × 2 = 36000. Referring to Table 3, 38.785 kΩ is the smallest
value larger than 36 kΩ; therefore Rp_MAX should be set to 0x11.
Setting Rp_MAX to a value not listed in Table 3 can result in indeterminate behavior.
8.1.1.2 Rp_MIN
Rp_MIN sets the lower limit of the LDC1000-Q1 resonant impedance input range.
•
•
•
Configure the sensor such that the eddy current losses are maximized. As an example, for a proximity
sensing application, set the distance between the sensor and the metal target to the minimum sensing
distance.
Measure the resonant impedance RP using an impedance analyzer.
Divide the RP value by 2 and then select the next lower RP value from the register settings listed in Table 4.
For example, if RP at 1 mm is measured to be 5 kΩ, 5000 / 2 = 2500. Referring to Table 4, 2.394 kΩ is the
smallest value smaller than 2.5 kΩ which corresponds to an Rp_MIN value of 0x3B.
Setting Rp_MIN to a value not listed on Table 4 can result in indeterminate behavior. In addition, Rp_MIN powers
on with a default value of 0x14 which must be set to a value from Table 4 prior to powering on the LDC.
8.1.2 Output Data Rate
The output data rate of the LDC1000-Q1 device depends on the sensor frequency, fsensor and the Response
Time[2-0] field in the LDC configuration register (address: 0x04).
Output data rate = fsensor / (Response Time[2-0] / 3) in SPS (samples per second)
(14)
8.1.2.1 Example
If the following values are selected, fsensor= 5 Mhz and Response Time[2-0] = 192, then:
Output data rate = 5 MHz / (192 / 3) = 78.125 KSPS
26
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Application Information (continued)
8.1.3 Selecting a Filter Capacitor (CFA and CFB Pins)
The filter capacitor is critical to the operation of the LDC1000-Q1 device. The capacitor should be low leakage,
temperature stable, and it must not generate any piezoelectric noise (the dielectrics of many capacitors exhibit
piezoelectric characteristics and any such noise is coupled directly through RP into the converter). The optimal
capacitance values range from 20 pF to 100 nF. The value of the capacitor is based on the time constant and
resonating frequency of the LC tank.
If a ceramic capacitor is used, then a C0G (or NP0) grade dielectric is recommended. The voltage rating should
be 10 V or higher. The traces connecting the CFA and CFB pins to the capacitor should be as short as possible
to minimize any parasitics.
For optimal performance, the selected filter capacitor, connected between the CFA and CFB pins, must be as
small as possible but large enough such that the active filter does not saturate. The size of this capacitor
depends on the time constant of the sense coil, which is given by L / rs (L = inductance, rs = series resistance of
the inductor at oscillation frequency). The larger this time constant, the larger filter capacitor is required.
Therefore the time constant reaches the maximum when there is no target present in front of the sensing coil.
Use the following procedure to find the optimal filter capacitance:
1. Use with a large filter capacitor. For a ferrite core coil, a value of 10 nF is generally large enough. For an air
coil or PCB coil, a value of 100 pF is generally large enough.
2. Power on the LDC and set the desired register values.
3. Minimize the eddy currents losses by ensuring maximum clearance between the target and the sensing coil.
4. Observe the signal on the CFB pin using a scope. Because this node is very sensitive to capacitive loading,
the use of an active probe is recommended. As an alternative, a passive probe with a 1-kΩ series resistance
between the tip and the CFB pin can be used.
5. Vary the values of the filter capacitor until the signal observed on the CFB pin has an amplitude of
approximately 1 VPP. This signal scales linearly with the reciprocal of the filter capacitance. For example, if a
100-pF filter capacitor is applied and the signal observed on the CFB pin has a peak-to-peak value of 200
mV, the desired 1-VPP value is obtained using a filter capacitor value that is calculated with Equation 16.
200 mV / 1 V × 100 pF = 20 pF
(16)
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8.2 Typical Application
5V
VIO
5V
LDO
VIO
VDD
MOSI
SDI
INA
VIO
MISO
SDO
SCLK
SCLK
GPIO
CSB
INT/GPIO
INTB
CFA
TBCLK
CFB
MCU
Timer/Aux CLK
INB
LDC1000
DGND
Sensor
GND
DGND
CLDO
DGND
DAP
AGND
DGND
(Rp)
Figure 35. Typical Application Schematic
Figure 36. Linear Position Sensing
28
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(Rp)
Typical Application (continued)
Figure 37. Angular Position Sensing
8.2.1 Design Requirements
For this design example, use the following as the input parameters.
Table 20. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Minimum sensing distance
1 mm
Maximum sensing distance
8 mm
Output data rate
78 KSPS (Max data rate with LDC10xx series)
Number of PCB layers for sensor
2 layers
8.2.2 Detailed Design Procedure
8.2.2.1 Sensor and Target
In this example, consider a sensor with the characteristics listed in Table 21.
Table 21. Sensor Characteristics
PARAMETER
VALUE
Layers
2
Thickness of copper
1 oz
Coil shape
Circular
Number of turns
23
Trace thickness
4 mil
Trace spacing
4 mil
PCB core material
FR4
RP at 1 mm
5 kΩ
RP at 8 mm
12.5 kΩ
Nominal Inductance
18 µH
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The target material used is stainless steel.
8.2.2.2 Calculating a Sensor Capacitor
Sensor frequency depends on various factors in the application. In this example, use Equation 17 to calculate the
sensor frequency in order to achieve an output data rate of 78 KSPS per the design parameter.
fsensor
Output Data Rate
§ Response time ·
¨
¸
3
©
¹
(17)
With the lowest response time (tres) of 192 and output data rate of 78 KSPS, the calculated sensor frequency
using Equation 17 is 4.99 MHz.
Use Equation 18 to calculate the sensor capacitor as 55 pF with a sensor inductance of 18 µH.
1
L
C u (2S u fsensor )2
(18)
8.2.2.3 Selecting a Filter Capacitor
Use the steps listed in the Selecting a Filter Capacitor (CFA and CFB Pins) section to calculate a filter capacitor.
For this example, the selected capacitor value is 20 pF. The following waveforms were taken on the CFB pin with
a 14-mm, 2-layer PCB coil (23 turns, 4-mil trace width, 4-mil spacing between trace, 1-o.z copper thickness,
FR4).
Figure 38. Waveform on CFB With 100 pF
Figure 39. Waveform on CFB With 20 pF
8.2.2.4 Setting Rp_MIN and Rp_MAX
To calculate the value for the Rp_MAX register, use the following value: Rp at 8 mm is 12.5 kΩ, 12500 × 2 =
25000. Then 27.704 kΩ is the nearest value larger than 25 kΩ. Referring to Table 3, this value corresponds to a
Rp_MAX value of 0x12.
To calculate the value for the Rp_MAX register, use the following value: Rp at 1 mm is 5 kΩ, 5000 / 2 = 2500.
Then 2.394 kΩ is the nearest value lower than 2.5 kΩ. Referring to Table 4, this value corresponds to Rp_MIN
value of 0x3B.
8.2.2.5 Calculating Minimum Sensor Frequency
Use Equation 19 to calculate the minimum sensor frequency.
§ F ·
N 68.94 u log10 ¨
¸
© 2500 ¹
where
•
30
N is 227.51
(19)
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For this example, round the value of N up to 228. This value must be written into the watchdog timer register,
which is used to wake up the internal circuit when the sensor is saturated.
8.2.3 Application Curves
25
14
12
20
Inductance (µH)
Rp (k
10
8
6
15
10
4
5
2
0
0
0
1
2
3
4
5
Distance (mm)
6
7
8
0
C002
1
2
3
4
5
6
7
Distance (mm)
8
C001
Figure 41. Inductance vs Distance
Figure 40. RP vs Distance
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9 Power Supply Recommendations
The LDC1000-Q1 device is designed to operate from an analog supply range of 4.75 to 5.25 V and digital I/O
supply range of 1.8 to 5.25 V. The analog supply voltage should be greater than or equal to the digital supply
voltage for proper operation of the device. The supply voltage should be well regulated. If the supply is located
more than a few inches from the LDC1000-Q1 device, additional bulk capacitance may be required in addition to
the ceramic bypass capacitors.
10 Layout
10.1 Layout Guidelines
Use the following guidelines:
• Bypass the VDD and VIO pin to ground with a low ESR ceramic bypass capacitor. A ceramic X7R dielectric
capacitor with a value of 0.1 µF is recommend.
• Place the VDD, VIO, GND, and DGND pins as close to the device as possible. Take care to minimize the
loop area formed by the bypass capacitor connection and the VDD, VIO, GND, and DGND pins of the IC. See
Figure 42 for a PCB layout example.
• Bypass the CLDO pin to the digital ground (DGND) with a ceramic bypass capacitor with a value of 56 nF.
• Connect the filter capacitor that is selected using the procedure listed in the Selecting a Filter Capacitor (CFA
and CFB Pins) section between the CFA and CFB pins. Place the capacitor close to the CFA and CFB pins.
Do not use any ground or power planes below the capacitor and the trace connecting the capacitor and the
CFx pins.
• Use two separate ground planes for the ground (GND) and digital ground (DGND) for a star connection as
recommended. See Figure 42 for a PCB layout example.
32
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10.2 Layout Example
Figure 42. LDC10xx Board Layout
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11 Device and Documentation Support
11.1 Trademarks
All trademarks are the property of their respective owners.
11.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
34
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PACKAGE OPTION ADDENDUM
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28-Jan-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LDC1000EPWRQ1
NRND
TSSOP
PW
16
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
0 to 0
LDC1000E
LDC1000QPWRQ1
NRND
TSSOP
PW
16
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 125
LDC1000Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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