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LM10504
SNVS739F – DECEMBER 2011 – REVISED OCTOBER 2016
LM10504 Triple Buck and LDO Power Management Unit
•
•
•
•
•
•
•
The LM10504 operates cooperatively with ASIC to
optimize the supply voltage for low-power conditions
and power saving modes through the SPI interface. It
also supports a 250-mA LDO and a programmable
interrupt comparator.
Device Information(1)
PART NUMBER
PACKAGE
LM10504
BODY SIZE (NOM)
DSBGA (34)
2.80 mm × 2.80 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Application Schematic
Reset
DevSLP
LM10504
CS
IO input
supply
Control
CLK
C9
2.2 F
C8
2.2 F
Power Supply
3.3/5.0V
System
DI
DO
SPI
VIN_IO
VIN
VIN_B1
C5
4.7 F
VIN_B2
C6
4.7 F
Vcomp
COMP
Interrupt
LDO
3V
LDO
C4
4.7 F
L1
3V
SW_B1
BUCK1
2.2 H
FB_B1
L2
SW_B2
BUCK2
2.2 H
FB_B2
L3
C1
10 F
3V
C2 Low = 1.8V
10 F
BUCK3
FB_B3
2.2 H
Host
Controller
Vhost
3.0V/250 mA
Host 1
Flash
Vcc
3.0V/1.6A
Host 2
Domain
Vccq
3.0V/1A
1.2V
SW_B3
VIN_B3
C7
4.7 F
Vselect3
•
The LM10504 is an advanced PMU containing three
configurable, high-efficiency buck regulators for
supplying variable voltages. The device is ideal for
supporting ASIC and SOC designs for solid-state and
flash drives.
Vselect2
•
3 Description
CONTROL LOGIC and REGISTERS
•
Solid-State Drives
GND
•
Three High-Efficiency Programmable Buck
Regulators
– Integrated FETs With Low RDSON
– Bucks Operate With Their Phases Shifted to
Reduce the Input Current Ripple and Capacitor
Size
– Programmable Output Voltage Through the
SPI Interface
– Overvoltage and Undervoltage Lockout
– Automatic Internal Soft Start With Power-On
Reset
– Current Overload and Thermal Shutdown
Protection
– PFM Mode for Low-Load, High-Efficiency
Operation
Power-Down Data Protection Enhances Data
Integrity
– Bypass Mode Available on Bucks 1 and 2
Deep Sleep Mode to Save Power During Idle
Times With DevSLP Function
Programmable Low-Dropout LDO 1.2 V to 3.1 V,
up to 250 mA
SPI-Programmable Interrupt Comparator
(2 V to 4 V)
Alternate Buck VOUTS Selectable Through VSELECT
Logic Pins
Customizable Start-Up Sequencing for Varied
Controllers
RESET Pin
Programmable Buck Regulators:
– Buck 1: 1.1 V to 3.6 V at 1.6 A
– Buck 2: 1.1 V to 3.6 V at 1 A
– Buck 3: 0.7 V to 1.335 V at 1 A
±3% Feedback Voltage Accuracy
Up to 95% Efficient Buck Regulators
2-MHz Switching Frequency for Smaller Inductor
Size
GND
•
1
2 Applications
GND
1 Features
C3 Low = 1.0V
10 F
Host 3
Domain
Vcore
1.2V/1A
Voltage Monitored
at Startup
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM10504
SNVS739F – DECEMBER 2011 – REVISED OCTOBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
7
1
1
1
2
3
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Electrical Characteristics – General.......................... 6
Electrical Characteristics – Buck 1............................ 7
Electrical Characteristics – Buck 2............................ 8
Electrical Characteristics – Buck 3............................ 9
Electrical Characteristics – LDO ............................. 10
Electrical Characteristics – Comparators.............. 10
Typical Characteristics .......................................... 11
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 14
7.3
7.4
7.5
7.6
8
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Register Maps .........................................................
14
18
22
23
Application and Implementation ........................ 28
8.1 Application Information............................................ 28
8.2 Typical Application .................................................. 28
9 Power Supply Recommendations...................... 34
10 Layout................................................................... 35
10.1 Layout Guidelines ................................................. 35
10.2 Layout Example .................................................... 35
11 Device and Documentation Support ................. 37
11.1
11.2
11.3
11.4
11.5
11.6
Device Support......................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
37
37
37
37
37
37
12 Mechanical, Packaging, and Orderable
Information ........................................................... 37
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (March 2013) to Revision F
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
•
Changed RθJA value in the Thermal Information table From: 44.5 To: 65.5........................................................................... 5
Changes from Revision D (March 2013) to Revision E
•
2
Page
Changed layout of National Semiconductor Data Sheet to TI format .................................................................................... 1
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SNVS739F – DECEMBER 2011 – REVISED OCTOBER 2016
5 Pin Configuration and Functions
YFR Package
34-Pin DSBGA
Top View
A
B
C
D
E
F
G
7
GND_B1
GND_B1
VCOMP
GND
DevSLP
RESET
GND_B3
6
SW_B1
SW_B1
SW_B3
SW_B3
5
VIN_B1
VIN_B1
FB_B3
VIN_B3
4
FB_B1
FB_B1
Vselect_B3
Vselect_B2
3
VIN
GND
FB_B2
VIN_B2
2
LDO
GND
SW_B2
SW_B2
1
Interrupt
VIN_IO
SPI_CS
GND_B2
SPI_CLK
SPI_DI
SPI_DO
Pin Functions
PIN
TYPE (1)
DESCRIPTION
NO.
NAME
A1
Interrupt
O
Digital output of comparator to signal interrupt condition.
A2
LDO
P
LDO regulator output voltage.
Power supply input voltage. Must be present for device to work; decouple closely to D7.
A3
VIN
P
A4, B4
FB_B1
I/O
A5, B5
VIN_B1
P
Buck switcher regulator 1: Power supply voltage input for power stage PFET, if Buck 1 is not
used, tie to ground to reduce leakage.
A6, B6
SW_B1
P
Buck switcher regulator 1: Power switching node, connect to inductor.
A7, B7
GND_B1
P
Buck switcher regulator 1: Power ground for buck regulator.
B1
VIN_IO
I
Supply voltage for digital interface.
B2
GND
G
Connect to system ground.
(1)
Buck switcher regulator 1: Voltage output feedback plus bypass power.
G = Ground, I = Input, O = Output, and P = Power
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SNVS739F – DECEMBER 2011 – REVISED OCTOBER 2016
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Pin Functions (continued)
PIN
NO.
NAME
TYPE (1)
DESCRIPTION
B3
GND
G
Connect to system ground.
C1
SPI_CLK
I
SPI interface: Serial clock input.
C7
VCOMP
I
Analog input for comparator.
D1
SPI_DI
I
SPI interface: Serial data input.
D7
GND
G
Connect to system ground; decouple closely to A3.
E1
SPI_DO
O
SPI interface: Serial data output.
E7
DevSLP
I
Digital input control signal for entering device sleep mode. This is an active high pin with an
internal pulldown resistor. Lowers core ASIC voltage and turns off the FLASH and I/O bucks.
F1
SPI_CS
I
SPI interface: Chip select.
F2, G2
SW_B2
P
Buck switcher regulator 2: Power switching node, connect to inductor.
F3
FB_B2
I
Buck switcher regulator 2: Voltage output feedback.
F4
Vselect_B3
I
Digital input start-up control signal to change predefined output voltage of buck 3, internally
pulled up as a default.
F5
FB_B3
I
Buck switcher regulator 3: Voltage output feedback.
F6, G6
SW_B3
P
Buck switcher regulator 3: Power switching node, connect to inductor.
F7
RESET
I
Digital input control signal to abort SPI transactions; resets the PMIC to default voltages. This is
an active low pin with an internal pullup.
G1
GND_B2
P
Buck switcher regulator 2: Power ground for buck regulator.
G3
VIN_B2
P
Buck switcher regulator 2: Power supply voltage input for power stage PFET, if buck 2 is not
used, tie to ground to reduce leakage.
G4
Vselect_B2
I
Digital input start-up control signal to change predefined output voltage of buck 2, internally
pulled down as a default.
G5
VIN_B3
P
Buck switcher regulator 3: Power supply voltage input for power stage PFET.
G7
GND_B3
P
Buck switcher regulator 3: Power ground for buck regulator.
4
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SNVS739F – DECEMBER 2011 – REVISED OCTOBER 2016
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
MAX
UNIT
VIN, VCOMP
–0.3
6
V
VIN_IO, VIN_B1, VIN_B2, VIN_B3, SPI_CS, SPI_DI, SPI_CLK, SPI_DO, Vselect_B2,Vselect_B3,
RESET, SW_1, SW_2, SW_3, FB_1, FB_2, FB_3, LDO, Interrupt, DevSLP
–0.3
6
V
150
°C
150
°C
Junction temperature, TJ-MAX
Storage temperature, Tstg
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
6.2 ESD Ratings
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
VALUE
UNIT
±2000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1) (2) (3)
VIN_B1, VIN_B2_VIN_B3, VIN
VIN_IO
All pins other than VIN_IO
MIN
MAX
3
5.5
UNIT
V
1.72
3.63
V
0
VIN
V
0.9
W
PD-MAX
Maximum continuous power dissipation
TA
Ambient temperature
–30
85
°C
TJ
Junction temperature
–30
125
°C
(1)
(2)
(3)
Internal thermal shutdown protects device from permanent damage. Thermal shutdown engages at TJ = 140°C and disengages at
TJ = 120°C (typically). Thermal shutdown is ensured by design.
In applications where high power dissipation or poor thermal resistance is present, the maximum ambient temperature may have to be
derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the
maximum power dissipation of the device in the application (PD-MAX), and the junction-to-ambient thermal resistance of the part or
package in the application (RθJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (RθJA × PD-MAX).
The amount of absolute maximum power dissipation allowed for the device depends on the ambient temperature and can be calculated
using the formula: P = (TJ – TA) / RθJA, where TJ is the junction temperature, TA is the ambient temperature, and RθJA is the junction-toambient thermal resistance. RθJA is highly application and board-layout dependent. Internal thermal shutdown circuitry protects the
device from permanent damage (see Electrical Characteristics – General).
6.4 Thermal Information
LM10504
THERMAL METRIC (1)
YFR (DSBGA)
UNIT
34 PINS
RθJA
Junction-to-ambient thermal resistance
65.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
0.2
°C/W
RθJB
Junction-to-board thermal resistance
39
°C/W
ψJT
Junction-to-top characterization parameter
1.5
°C/W
ψJB
Junction-to-board characterization parameter
38.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SNVS739F – DECEMBER 2011 – REVISED OCTOBER 2016
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6.5 Electrical Characteristics – General
TJ = 25°C and VIN = 5 V where VIN = VIN_B1 = VIN_B2 = VIN_B3 (unless otherwise noted) (1) (2)
PARAMETER
IQ(DEVSLP)
Quiescent supply current
TEST CONDITIONS
DevSLP = HIGH,
no load
MIN
TJ = 25°C
TYP
MAX
100
–30°C ≤ TJ ≤ 85°C
200
UNIT
µA
UNDERVOLTAGE OR OVERVOLTAGE LOCKOUT
TJ = 25°C
2.9
VUVLO_RISING
Undervoltage lockout, rising
VUVLO_FALLING
Undervoltage lockout, falling
VOVLO_RISING
Overvoltage lockout, rising
5.64
V
VOVLO_FALLING
Overvoltage lockout, falling
5.54
V
–30°C ≤ TJ ≤ 85°C
2.75
TJ = 25°C
–30°C ≤ TJ ≤ 85°C
3.05
2.6
2.45
2.75
V
V
DIGITAL INTERFACE
VIL
Logic input low
SPI_CS, SPI_DI, SPI_CLK, RESET,
DevSLP, –30°C ≤ TJ ≤ 85°C
VIH
Logic input high
SPI_CS, SPI_DI, SPI_CLK, RESET,
DevSLP, –30°C ≤ TJ ≤ 85°C
VIL
Logic input low
Vselect_B2, Vselect_B3,
–30°C ≤ TJ ≤ 85°C
VIH
Logic input high
Vselect_B2, Vselect_B3,
–30°C ≤ TJ ≤ 85°C
VOL
Logic output low
SPI_DO, –30°C ≤ TJ ≤ 85°C
VOH
Logic output high
SPI_DO, –30°C ≤ TJ ≤ 85°C
IIL
Input current, pin driven low
SPI_CS, SPI_DI, SPI_CLK,
Vselect_B2, DevSLP
–2
Vselect_B3, RESET
–5
IIH
Input current, pin driven high
fSPI_MAX
tRESET
tDEVSLP
(1)
(2)
(3)
6
0.7 × VIN_IO
0.3 × VIN_IO
V
0.7 × VIN
0.3 × VIN
V
0.8 × VIN_IO
0.2 × VIN_IO
V
µA
SPI_CS, SPI_DI, SPI_CLK,
Vselect_B3, RESET
2
Vselect_B2, DevSLP
5
SPI max frequency
–30°C ≤ TJ ≤ 85°C
Minimum pulse width (3)
–30°C ≤ TJ ≤ 85°C
10
2
µA
MHz
µs
All limits are ensured by design, test, or statistical analysis. All electrical characteristics having room-temperature limits are tested during
production with TJ = 25°C. All hot and cold limits are ensured by correlating the electrical characteristics to process and temperature
variations and applying statistical process control.
Capacitors: Low-ESR surface-mount ceramic capacitors (MLCCs) are used in setting electrical characteristics.
Specification ensured by design. Not tested during production.
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SNVS739F – DECEMBER 2011 – REVISED OCTOBER 2016
6.6 Electrical Characteristics – Buck 1
TJ = 25°C and VIN = 5 V where VIN=VIN_B1 = VIN_B2 = VIN_B3 (unless otherwise noted) (1) (2) (3)
PARAMETER
CONDITIONS
MIN
TJ = 25°C
TYP
MAX UNITS
15
IQ
VIN DC bias current
No load, PFM mode
IOUT_MAX
Continuous maximum load
current (4) (5)
Buck 1 enabled, switching in PWM,
–30°C ≤ TJ ≤ 85°C
IPEAK
Peak switching current limit
Buck 1 enabled,
switching in PWM
η
Peak efficiency (4)
IOUT = 0.3 A
FSW
Switching frequency
CIN
Input capacitor (4)
0 mA ≤ IOUT ≤ IOUT-MAX
Output filter capacitor (4)
0 mA ≤ IOUT ≤ IOUT-MAX
Output capacitor ESR (4)
0 mA ≤ IOUT ≤ IOUT-MAX
Output filter inductance (4)
0 mA ≤ IOUT ≤ IOUT-MAX
DC line regulation (4)
3.3 V ≤ VIN ≤ 5 V, IOUT = IOUT-MAX
0.5%
V
100 mA ≤ IOUT ≤ IOUT-MAX
0.3%
A
COUT
L
ΔVOUT
DC load regulation
(4)
IFB
Feedback pin input bias current
RDS-ON-HS
High-side switch on resistance
RDS-ON-LS
Low-side switch on resistance
RDS-ON-BYPASS
Bypass FET on resistance
–30°C ≤ TJ ≤ 85°C
50
1.6
TJ = 25°C
1.9
2.6
A
90%
TJ = 25°C
2
–30°C ≤ TJ ≤ 85°C
VFB = 3 V
A
2.1
–30°C ≤ TJ ≤ 85°C
µA
1.75
2.3
4.7
10
10
100
20
2.2
TJ = 25°C
5
135
VIN = 2.6 V
215
TJ = 25°C
85
–30°C ≤ TJ ≤ 85°C
µF
mΩ
µH
2.1
–30°C ≤ TJ ≤ 85°C
MHz
µA
mΩ
190
mΩ
Used in parallel with the high-side FET while in
bypass mode. Resistance
(DCR) of inductor = 100 mΩ
VIN = 3.3 V
85
VIN = 2.6 V
120
Start up from shutdown, VOUT = 0 V, no load,
LC = recommended circuit, using software
enable, to VOUT = 95% of final value
0.1
mΩ
START-UP
TSTART
(1)
(2)
(3)
(4)
(5)
Internal soft-start (turnon time) (4)
ms
All limits are ensured by design, test, or statistical analysis. All electrical characteristics having room-temperature limits are tested during
production with TJ = 25°C. All hot and cold limits are ensured by correlating the electrical characteristics to process and temperature
variations and applying statistical process control.
Capacitors: Low-ESR surface-mount ceramic capacitors (MLCCs) are used in setting electrical characteristics.
BUCK normal operation is ensured if VIN ≥ VOUT + 1 V.
Specification ensured by design. Not tested during production.
In applications where high power dissipation or poor thermal resistance is present, the maximum ambient temperature may have to be
derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the
maximum power dissipation of the device in the application (PD-MAX), and the junction-to-ambient thermal resistance of the part or
package in the application (RθJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (RθJA × PD-MAX).
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6.7 Electrical Characteristics – Buck 2
TJ = 25°C and VIN = 5 V where VIN=VIN_B1 = VIN_B2 = VIN_B3 (unless otherwise noted) (1) (2) (3)
PARAMETER
TEST CONDITIONS
MIN
TJ = 25°C
TYP
MAX
15
UNIT
IQ
VIN DC bias current
No load, PFM mode
IOUT_MAX
Continuous maximum load current (4) (5)
Buck 2 enabled, switching in PWM,
–30°C ≤ TJ ≤ 85°C
IPEAK
Peak switching current limit
Buck 2 enabled,
switching in PWM
η
Peak efficiency (4)
IOUT = 0.3 A
FSW
Switching frequency
CIN
Input capacitor (4)
0 mA ≤ IOUT ≤ IOUT-MAX
Output filter capacitor (4)
0 mA ≤ IOUT ≤ IOUT-MAX
Output capacitor ESR (4)
0 mA ≤ IOUT ≤ IOUT-MAX
Output filter inductance (4)
0 mA ≤ IOUT ≤ IOUT-MAX
DC line regulation (4)
3.3 V ≤ VIN ≤ 5 V, IOUT = IOUT-MAX
0.5%
V
100 mA ≤ IOUT ≤ IOUT-MAX
0.3%
A
COUT
L
ΔVOUT
DC load regulation
(4)
IFB
Feedback pin input bias current
RDS-ON-HS
High-side switch on resistance
RDS-ON-LS
Low-side switch on resistance
–30°C ≤ TJ ≤ 85°C
50
1
TJ = 25°C
1.35
1.8
A
90%
TJ = 25°C
2
–30°C ≤ TJ ≤ 85°C
VFB = 1.8 V
A
1.56
–30°C ≤ TJ ≤ 85°C
µA
1.75
2.3
4.7
10
10
100
20
2.2
TJ = 25°C
µF
mΩ
µH
1.8
–30°C ≤ TJ ≤ 85°C
MHz
5
µA
135
VIN = 2.6 V
260
TJ = 25°C
85
–30°C ≤ TJ ≤ 85°C
mΩ
190
START-UP
TSTART
(1)
(2)
(3)
(4)
(5)
8
Internal soft-start (turnon time) (4)
Start up from shutdown, VOUT = 0 V, no load,
LC = recommended circuit, using software
enable, to VOUT = 95% of final value
0.1
ms
All limits are ensured by design, test, or statistical analysis. All electrical characteristics having room-temperature limits are tested during
production with TJ = 25°C. All hot and cold limits are ensured by correlating the electrical characteristics to process and temperature
variations and applying statistical process control.
Capacitors: Low-ESR surface-mount ceramic capacitors (MLCCs) are used in setting electrical characteristics.
BUCK normal operation is ensured if VIN ≥ VOUT + 1 V.
Specification ensured by design. Not tested during production.
In applications where high power dissipation or poor thermal resistance is present, the maximum ambient temperature may have to be
derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the
maximum power dissipation of the device in the application (PD-MAX), and the junction-to-ambient thermal resistance of the part or
package in the application (RθJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (RθJA × PD-MAX).
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SNVS739F – DECEMBER 2011 – REVISED OCTOBER 2016
6.8 Electrical Characteristics – Buck 3
TJ = 25°C and VIN = 5 V where VIN = VIN_B1 = VIN_B2 = VIN_B3 (unless otherwise noted) (1) (2) (3)
PARAMETER
TEST CONDITIONS
MIN
TJ = 25°C
TYP
MAX
15
UNIT
IQ
VIN DC bias current
No load, PFM mode
IOUT_MAX
Continuous maximum load current (4) (5)
Buck 3 enabled, switching in PWM,
–30°C ≤ TJ ≤ 85°C
IPEAK
Peak switching current limit
Buck 3 enabled,
switching in PWM
η
Peak efficiency (4)
IOUT = 0.3 A
FSW
Switching frequency
CIN
Input capacitor (4)
0 mA ≤ IOUT ≤ IOUT-MAX
Output filter capacitor (4)
0 mA ≤ IOUT ≤ IOUT-MAX
Output capacitor ESR (4)
0 mA ≤ IOUT ≤ IOUT-MAX
Output filter inductance (4)
0 mA ≤ IOUT ≤ IOUT-MAX
DC line regulation (4)
3.3 V ≤ VIN ≤ 5 V, IOUT = IOUT-MAX
0.5%
V
100 mA ≤ IOUT ≤ IOUT-MAX
0.3%
A
COUT
L
ΔVOUT
DC load regulation
(4)
IFB
Feedback pin input bias current
RDS-ON-HS
High-side switch on resistance
RDS-ON-LS
Low-side switch on resistance
–30°C ≤ TJ ≤ 85°C
50
1
TJ = 25°C
1.35
1.8
A
90%
TJ = 25°C
2
–30°C ≤ TJ ≤ 85°C
VFB = 1.2 V
A
1.56
–30°C ≤ TJ ≤ 85°C
µA
1.75
2.3
4.7
10
10
100
20
2.2
TJ = 25°C
µF
mΩ
µH
0.9
–30°C ≤ TJ ≤ 85°C
MHz
5
µA
135
VIN = 2.6 V
260
TJ = 25°C
85
–30°C ≤ TJ ≤ 85°C
mΩ
190
START-UP
TSTART
(1)
(2)
(3)
(4)
(5)
Internal soft-start (turnon time) (4)
Start up from shutdown, VOUT = 0 V, no load,
LC = recommended circuit, using software
enable, to VOUT = 95% of final value
0.1
ms
All limits are ensured by design, test, or statistical analysis. All electrical characteristics having room-temperature limits are tested during
production with TJ = 25°C. All hot and cold limits are ensured by correlating the electrical characteristics to process and temperature
variations and applying statistical process control.
Capacitors: Low-ESR surface-mount ceramic capacitors (MLCCs) are used in setting electrical characteristics.
BUCK normal operation is ensured if VIN ≥ VOUT + 1 V.
Specification ensured by design. Not tested during production.
In applications where high power dissipation or poor thermal resistance is present, the maximum ambient temperature may have to be
derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the
maximum power dissipation of the device in the application (PD-MAX), and the junction-to-ambient thermal resistance of the part or
package in the application (RθJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (RθJA × PD-MAX).
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6.9 Electrical Characteristics – LDO
TJ = 25°C and VIN = 5 V where: VIN = VIN_B1 = VIN_B2 = VIN_B3 (unless otherwise noted) (1) (2)
PARAMETER
VOUT
Output voltage accuracy
IOUT
Maximum output current
ISC
Short-circuit current limit
VDO
TEST CONDITIONS
MIN
IOUT = 1 mA, –30°C ≤ TJ ≤ 85°C
TYP
–3%
3%
mA
VOUT = 0 V
0.5
TJ = 25°C
Line regulation
3.3 V ≤ VIN ≤ 5 V, IOUT = 1 mA
5
Load regulation
1 mA ≤ IOUT ≤ 250 mA, VIN = 3.3 V, 5 V
5
eN
Output noise voltage (3)
10 Hz ≤ f ≤ 100 kHz
PSRR
Power supply rejection ratio (3)
F = 10 kHz, COUT = 4.7 µF,
IOUT = 20 mA
TSTART
Start-up time from shutdown (3)
COUT = 4.7 µF, IOUT = 250 mA
(1)
(2)
(3)
A
160
IOUT = 250 mA
TTRANSIENT Start-up transient overshoot (3)
UNIT
250
Dropout voltage
ΔVOUT
MAX
–30°C ≤ TJ ≤ 85°C
220
VIN = 5 V
10
VIN = 3.3 V
35
VIN = 5 V
65
VIN = 3.3 V
40
VIN = 5 V
45
VIN = 3.3 V
60
COUT = 4.7 µF, IOUT = 250 mA, –30°C ≤ TJ ≤ 85°C
mV
µVRMS
dB
µs
30
mV
All limits are ensured by design, test, or statistical analysis. All electrical characteristics having room-temperature limits are tested during
production with TJ = 25°C. All hot and cold limits are ensured by correlating the electrical characteristics to process and temperature
variations and applying statistical process control.
Capacitors: Low-ESR surface-mount ceramic capacitors (MLCCs) are used in setting electrical characteristics.
Specification ensured by design. Not tested during production.
6.10 Electrical Characteristics – Comparators
TJ = 25°C and VIN = 5 V (unless otherwise noted) (1) (2)
PARAMETER
TEST CONDITIONS
VCOMP = 0 V
IVCOMP
VCOMP pin bias current
VCOMP = 5 V
MIN
TJ = 25°C
TYP
2
TJ = 25°C
0.1
–30°C ≤ TJ ≤ 85°C
Comparator rising edge trigger level
2.79
Comparator falling edge trigger level
2.74
TJ = 25°C
InterruptVOH
Output voltage high
–30°C ≤ TJ ≤ 85°C
InterruptVOL
Output voltage low
–30°C ≤ TJ ≤ 85°C
tCOMP
Transition time of interrupt output
(1)
(2)
10
TJ = 25°C
–30°C ≤ TJ ≤ 85°C
µA
2
VCOMP_FALL
–30°C ≤ TJ ≤ 85°C
UNIT
0.1
–30°C ≤ TJ ≤ 85°C
VCOMP_RISE
Hysteresis
MAX
V
60
30
80
0.8 × VIN_IO
0.2 × VIN_IO
6
15
mV
V
µs
All limits are ensured by design, test, or statistical analysis. All electrical characteristics having room-temperature limits are tested during
production with TJ = 25°C. All hot and cold limits are ensured by correlating the electrical characteristics to process and temperature
variations and applying statistical process control.
Capacitors: Low-ESR surface-mount ceramic capacitors (MLCCs) are used in setting electrical characteristics.
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6.11 Typical Characteristics
100
100
90
90
80
80
EFFICIENCY (%)
EFFICIENCY (%)
TA = 25°C (unless otherwise noted)
70
60
50
70
60
50
40
40
30
30
20
VOUT = 3.0V
VOUT = 1.8V
20
1
10
VIN= 5 V
100
IOUT(mA)
1k
10k
VOUT = 3 V
1
10
100
IOUT(mA)
1k
10k
VIN = 5 V
Figure 1. Efficiency of Buck 1
Figure 2. Efficiency of Buck 2
200 µs/
1 1.00V/
100
EFFICIENCY (%)
90
VIN = 3.3V
1A load
80
70
60
50
40
1
30
BUCK1
20
1
10
VIN = 5 V
100
IOUT(mA)
1k
10k
VOUT = 1 V
VIN = 3.3 V
Figure 3. Efficiency of Buck 3
1 1.00V/
VOUT = 3 V
Figure 4. Start-Up of Buck 1
200 µs/
3.20
3.16
3.12
VIN = 5V
1A load
VOUT(V)
3.08
3.04
3.00
2.96
2.92
1
BUCK1
2.88
2.84
2.80
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
IOUT(A)
VIN = 5 V
VOUT = 3 V
VIN = 5 V
Figure 5. Start-Up of Buck 1
VOUT = 3 V
Figure 6. Buck 1 VOUT vs IOUT
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1.85
3.10
1.84
3.08
1.83
3.06
1.82
3.04
VOUT(V)
VOUT(V)
Typical Characteristics (continued)
1.81
1.80
1.79
3.02
3.00
2.98
1.78
2.96
1.77
2.94
1.76
2.92
1.75
2.90
0
200
VIN = 5 V
400
600
IOUT(mA)
800
1000
VOUT = 1.8 V
0
200
400 600 800 1000 1200
IOUT(mA)
VIN = 5 V
Figure 7. Buck 2 VOUT vs IOUT
VOUT = 3 V
Figure 8. Buck 2 VOUT vs IOUT
1.02
1.210
1.208
1.01
1.206
1.204
VOUT(V)
VOUT(V)
1.00
1.202
0.99
1.200
1.198
0.98
1.196
1.194
0.97
1.192
0.96
1.190
0
200
VIN = 5 V
400 600 800 1000 1200
IOUT(mA)
VOUT = 1 V
0
VIN = 5 V
Figure 9. Buck 3 VOUT vs IOUT
VOUT = 1.2 V
1.800
2.995
1.795
2.990
VOUT(V)
VOUT(V)
3.000
1.790
2.985
1.785
2.980
1.780
2.975
1.775
2.970
3.0
3.5
4.0
VIN(V)
4.5
5.0
IOUT = 1 A
3.5
4.0
4.5
5.0
VIN(V)
VOUT = 3 V
Figure 11. Buck 2 VOUT vs VIN
12
400 600 800 1000 1200
IOUT(mA)
Figure 10. Buck 3 VOUT vs IOUT
1.805
VOUT = 1.8 V
200
IOUT= 1 A
Figure 12. Buck 2 VOUT vs VIN
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Typical Characteristics (continued)
1.215
1.010
1.210
1.005
1.205
VOUT(V)
VOUT(V)
1.015
1.000
1.200
0.995
1.195
0.990
1.190
0.985
1.185
3.0
3.5
VOUT= 1 V
4.0
VIN(V)
4.5
5.0
3.0
IOUT= 1 A
VOUT= 1.2 V
Figure 13. Buck 3 VOUT vs VIN
1 1.00V/ 2 1.00V/
1
VIN
2
LDO
4.0
VIN(V)
4.5
5.0
IOUT = 1 A
Figure 14. Buck 3 VOUT vs VIN
1 1.00V/ 2 1.00V/
5.00 ms/
Figure 15. LDO Start-Up Time from VIN Rise
1 1.00V/ 2 1.00V/
3.5
1
LDO
2
BUCK1
Figure 16. From LDO Start-Up to Buck 1 Start-Up
1.00 ms/
1 1.00V/ 2 1.00V/
1
BUCK1
1
BUCK2
2
BUCK2
2
BUCK3
Figure 17. From Buck 1 Start-Up to Buck 2 Start-Up
1.00 ms/
1.00 ms/
Figure 18. From Buck 2 Start-Up to Buck 3 Start-Up
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7 Detailed Description
7.1 Overview
LM10504 is a highly efficient and integrated power management unit for systems-on-a-chip (SoCs), ASICs, and
processors. It operates cooperatively and communicates with processors over an SPI interface with output
voltage programmability.
The device incorporates three high-efficiency synchronous buck regulators and one LDO that deliver four output
voltages from a single power source. The device also includes a SPI-programmable comparator block that
provides an interrupt output signal.
GND
GND
GND
LDO
VIN
SPI_CLK
SPI_DO
SPI_DI
VIN_IO
SPI_CS
7.2 Functional Block Diagram
SPI
RESET
REGISTERS
VIN_B2
EN
DEVSLP
LDO
CONTROL
LOGIC
SW_B2
BUCK2
GND_B2
FB_B2
EN
VSELECT_B2
LM10504
VIN_B1
SEQUENCER
TSD
EN
SW_B1
BUCK1
GND_B1
OVLO
UVLO
FB_B1
EN
VIN_B3
VCOMP
SW_B3
BUCK3
COMPARATOR
GND_B3
FB_B3
INTERRUPT
VSELECT_B3
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7.3 Feature Description
A buck converter contains a control block, a switching PFET connected between input and output, a synchronous
rectifying NFET connected between the output and ground and a feedback path. Figure 19 shows the block
diagram of each of the three buck regulators integrated in the device.
14
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Feature Description (continued)
FB
CONTROL
G
S
CIN
P
D
D
SW
N
S
L
COUT
PGND
VOUT
G
VIN
PVIN
U1
LM10504
GND
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Figure 19. Buck Functional Diagram
During the first portion of each switching cycle, the control block turns on the internal PFET switch. This allows
current to flow from the input through the inductor to the output filter capacitor and load. The inductor limits the
current to a ramp with a slope of (VIN – VOUT) / L by storing energy in a magnetic field. During the second portion
of each cycle, the control block turns the PFET switch off, blocking current flow from the input, and then turns the
NFET synchronous rectifier on. The inductor draws current from ground through the NFET to the output filter
capacitor and load, which ramps the inductor current down with a slope of (–VOUT) / L.
The output filter stores charge when the inductor current is high, and releases it when low, smoothing the voltage
across the load. The output voltage is regulated by modulating the PFET switch on time to control the average
current sent to the load. The effect is identical to sending a duty-cycle modulated rectangular wave formed by the
switch and synchronous rectifier at the SW pin to a low-pass filter formed by the inductor and output filter
capacitor. The output voltage is equal to the average voltage at the SW pin.
7.3.1 Buck Regulators Description
The LM10504 incorporates three high-efficiency synchronous switching buck regulators that deliver various
voltages from a single DC input voltage. They include many advanced features to achieve excellent voltage
regulation, high efficiency, and fast transient response time. The bucks feature voltage mode architecture with
synchronous rectification.
Each of the switching regulators is specially designed for high-efficiency operation throughout the load range.
With a 2MHz typical switching frequency, the external L-C filter can be small and still provide very low output
voltage ripple. The bucks are internally compensated to be stable with the recommended external inductors and
capacitors as detailed in the application diagram. Synchronous rectification yields high efficiency for low voltage
and high output currents.
All bucks can operate up to a 100% duty cycle allowing for the lowest possible input voltage that still maintains
the regulation of the output. The lowest input to output dropout voltage is achieved by keeping the PMOS switch
on.
Additional features include soft start, undervoltage lockout, bypass, and current and thermal overload protection.
To reduce the input current ripple, the device employs a control circuit that operates the 3 bucks at 120° phase.
These bucks are nearly identical in performance and mode of operation. They can operate in FPWM (forced
PWM) or automatic mode (PWM/PFM).
7.3.2 PWM Operation
During PWM operation the converter operates as a voltage-mode controller with input voltage feedforward. This
allows the converter to achieve excellent load and line regulation. The DC gain of the power stage is proportional
to the input voltage. To eliminate this dependence, a feedforward voltage inversely proportional to the input
voltage is introduced.
In forced PWM mode the bucks always operate in PWM mode regardless of the output current.
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Feature Description (continued)
In automatic mode, if the output current is less than 70 mA (typical), the bucks automatically transition into Pulse
Frequency Modulation (PFM) operation to reduce the current consumption. At higher than 100 mA (typical), they
operate in PWM mode. This increases the efficiency at lower output currents. The 30-mA (typical) hysteresis is
designed in for stable mode transition.
While in PWM mode, the output voltage is regulated by switching at a constant frequency and then modulating
the energy per cycle to control power to the load. At the beginning of each clock cycle the PFET switch is turned
on, and the inductor current ramps up until the comparator trips and the control logic turns off the switch. The
current limit comparator can also turn off the switch in case the current limit of the PFET is exceeded. In this
case the NFET switch is turned on and the inductor current ramps down. The next cycle is initiated by the clock
turning off the NFET and turning on the PFET.
PWM Mode at
Moderate to
Heavy Loads
VOUT
PFM Mode at Light Load
Load current
increases, draws
Vout towards Low 2
PFM Threshold
High PFM
Threshold
~1.016*VOUT
Low1 PFM
Threshold
~1.008*VOUT
PFET on
until
LPFM
limit
reached
NFET on
drains
inductor
current
until
I inductor=0
High PFM
Voltage
Threshold
reached,
go into
idle mode
Low PFM
Threshold,
turn on
PFET
Load
current
increases
Low 2 PFM
Threshold,
switch back to
PWM mode
Low2 PFM
Threshold
VOUT
Time
Figure 20. PFM vs PWM Operation
7.3.3 PFM Operation
At very light loads, Bucks 1, 2, and 3 enter PFM mode and operate with reduced switching frequency and supply
current to maintain high efficiency.
Bucks 1, 2, and 3 automatically transitions into PFM mode when either of two conditions occurs for a duration of
32 or more clock cycles:
1. The inductor current becomes discontinuous
2. The peak PMOS switch current drops below the IMODE level.
During PFM operation, the converter positions the output voltage slightly higher than the nominal output voltage
during PWM operation, allowing additional headroom for voltage drop during a load transient from light to heavy
load. The PFM comparators sense the output voltage through the feedback pin and control the switching of the
output FETs such that the output voltage ramps between 0.8% and 1.6% (typical) above the nominal PWM
output voltage. If the output voltage is below the ‘high’ PFM comparator threshold, the PMOS power switch is
turned on. It remains on until the output voltage exceeds the ‘high’ PFM threshold or the peak current exceeds
the IPFM level set for PFM mode.
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Feature Description (continued)
Once the PMOS power switch is turned off, the NMOS power switch is turned on until the inductor current ramps
to zero. When the NMOS zero-current condition is detected, the NMOS power switch is turned off. If the output
voltage is below the ‘high’ PFM comparator threshold (see Figure 20), the PMOS switch is again turned on and
the cycle is repeated until the output reaches the desired level. Once the output reaches the high PFM threshold,
the NMOS switch is turned on briefly to ramp the inductor current to zero and then both output switches are
turned off and the part enters an extremely low power mode. Quiescent supply current during this idle mode is
less than 100 µA, which allows the part to achieve high efficiencies under extremely light load conditions. When
the output drops below the ‘low’ PFM threshold, the cycle repeats to restore the output voltage to approximately
1.6% above the nominal PWM output voltage.
If the load current must increase during PFM mode causing the output voltage to fall below the ‘low2’ PFM
threshold, the part automatically transitions into fixed-frequency PWM mode.
7.3.4 Soft Start
Each of the buck converters has an internal soft-start circuit that limits the in-rush current during start-up. This
allows the converters to gradually reach the steady-state operating point, thus reducing start-up stresses and
surges. During start-up, the switch current limit is increased in steps.
For Bucks 1, 2, and 3 the soft start is implemented by increasing the switch current limit in steps that are
gradually set higher. The start-up time depends on the output capacitor size, load current, and output voltage.
Typical start-up time with the recommended output capacitor of 10 µF is 0.2 to 1ms. It is expected that in the final
application the load current condition is more likely in the lower load current range during start-up.
7.3.5 Current Limiting
A current limit feature protects the device and any external components during overload conditions. In PWM
mode the current limiting is implemented by using an internal comparator that trips at current levels according to
the buck capability. If the output is shorted to ground the device enters a timed current limit mode where the
NFET is turned on for a longer duration until the inductor current falls below a low threshold, ensuring inductor
current has more time to decay, thereby preventing runaway.
7.3.6 Internal Synchronous Rectification
While in PWM mode, the bucks use an internal NFET as a synchronous rectifier to reduce the rectifier forward
voltage drop and the associated power loss. Synchronous rectification provides a significant improvement in
efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier
diode.
7.3.7 Bypass-FET Operation on Buck 1 and Buck 2
There is an additional bypass FET used on Buck 1. The FET is connected in parallel to high-side FET and
inductor. Buck 2 has no extra bypass FET; it uses high-side FET (PFET) for bypass operation. If Buck 1 input
voltage is greater than 3.5 V (2.6 V for Buck 2), the bypass function is disabled. The determination of whether or
not the Buck regulators are in bypass mode or standard switching regulation is constantly monitored while the
regulators are enabled. If at any time the input voltage goes above 3.5 V (2.6 V for Buck 2) while in bypass
mode, the regulators transitions to normal operation.
When the bypass mode is enabled, the output voltage of the buck that is in bypass mode is not regulated, but
instead, the output voltage follows the input voltage minus the voltage drop seen across the FET and DCR of the
inductor. The voltage drop is a direct result of the current flowing across those resistive elements. When Buck 1
transitions into bypass mode, there is an extra FET used in parallel along with the high-side FET for transmission
of the current to the load. This added FET helps reduce the resistance seen by the load and decrease the
voltage drop. For Buck 2, the bypass function uses the same high-side FET.
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Feature Description (continued)
Equivalent Circuit of Bypass Operation of Buck 1
High Side FET
VIN_B1
DCR
100m Max.
Ideal Inductor,
no resistance
VOUT Buck1
SW_B1
Model of Inductor
Load
Resistance
FB_B1
Load
Capacitance
Bypass FET
Equivalent Circuit of Bypass Operation of Buck 2
High Side FET
VIN_B2
DCR
100m Max.
Ideal Inductor,
no resistance
VOUT Buck2
SW_B2
Model of Inductor
Load
Resistance
Load
Capacitance
Figure 21. Bypass Operations for Buck 1 and Buck 2
7.3.8 Low Dropout Operation
The device can operate at 100% duty cycle (no switching; PMOS switch completely on) for low dropout support.
In this way, the output voltage is controlled down to the lowest possible input voltage. When the device operates
near 100% duty cycle, output voltage ripple is approximately 25 mV.
The minimum input voltage needed to support the output voltage is calculated with Equation 1.
VIN_MIN = VOUT + ILOAD × (RDSON_PFET + RIND)
where
•
•
•
ILOAD is the load current
RDSON_PFET is the drain to source resistance of PFET (high-side)
RIND is the inductor resistance
(1)
7.3.9 Out of Regulation
When any of the Buck outputs are taken out of regulation (below 85% of the output level), the device starts a
shutdown sequence and all other outputs switch off normally. The device restarts when the forced out-ofregulation condition is removed.
7.4 Device Functional Modes
7.4.1 Start-Up Sequence
The start-up mode of the LM10504 depends on the input voltage. Once VIN reaches the UVLO threshold, there
is a 15-ms delay before the LM10504 determines how to set up the buck regulators. If VIN is below 3.6 V, then
Buck 1 and Buck 2 are in bypass mode; see Bypass-FET Operation on Buck 1 and Buck 2 for functionality
description. If the VIN voltage is greater than 3.6 V, the bucks start up as standard regulators. The 3 buck
regulators are staggered during start-up to avoid large inrush currents. There is a fixed delay of 2 ms between
the start-up of each regulator.
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Device Functional Modes (continued)
The start-up sequence is:
1. 15 msec (±30%) delay after VIN above UVLO
2. LDO → 3.2 V
3. 2-ms delay
4. Buck 1 → 3 V
5. 2-ms delay
6. Buck 2 → 3 V or if Vselect_B2 = Low → 1.8 V
7. 2-ms delay
8. Buck 3 → 1.2 V or if Vselect_B3 = Low → 1 V
5.9V
5.8V
2.76V
2.75V
2.5V
2.2V
VIN
BG / BIAS
7ms
7ms
UVLO
LDO
2ms
2ms
2ms
1.05 V PSML
Buck1
2ms
2ms
2ms
Buck2
1ms
1ms
Buck3
2ms
1.1V
1.1V
Comparator
If Vcomp=Vin
OVLO
DevSLP
UVLO
STARTUP
OVLO
STARTUP
DEVSLP
UVLO
Figure 22. Operating Modes
7.4.2 Power-On Default and Device Enable
The device is always enabled and the LDO is always on, unless outside of operating voltage range. There is no
LM10504 Enable pin. Once VIN reaches a minimum required input voltage, the power-up sequence is started
automatically and the start-up sequence is initiated. Once the device is started, the output voltage of the Bucks 1
and 2 can be individually disabled by accessing their corresponding BKEN register bits (BUCK CONTROL).
7.4.3 Reset Pin Function
The RESET pin is internally pulled high. If the RESET pin is pulled low, the device performs a complete reset of
all the registers to their default states. This means that all of the voltage settings on the regulators go back to
their default states.
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Device Functional Modes (continued)
7.4.4 DevSLP Function
The device can be placed into sleep (DevSLP) mode. There are two ways for doing that:
1. DevSLP pin
2. Programming through the SPI
Bucks 1 and 2 are ramped down when the disable signal is given. Buck 1 starts ramping 2 ms after Buck 2 has
started ramping.
To
1.
2.
3.
4.
5.
enter the DevSLP sequence:
Buck 3 → PSML (Programmable DevSLP Mode Level)
2-ms delay
Buck 2 → Disabled
2-ms delay
Buck 1 → Disabled
7.4.4.1 DevSLP Pin
When the DevSLP pin is asserted high, the LM10504 enters sleep mode. While in sleep mode, Buck 1 and Buck
2 are disabled. Buck 3’s output voltage is transitioned to the programmable sleep mode level (PSML) as set by
LM10504 register 0x09. The DevSLP pin is internally pulled down, and there is a 1-s delay during power up
before the state of the DevSLP pin is checked.
NOTE
If Buck 1 and Buck 2 are already disabled, and the DevSLP pin is asserted high, then
Buck 3 does not go to PSML. For further instructions, see DevSLP Programming Through
SPI. Bucks 1 and 2 are ramped down when the disable signal is given. Buck 1 starts
ramping 2 ms after Buck 2 has started ramping.
To
1.
2.
3.
4.
5.
enter the sleep sequence:
Buck 3 → PSML
2-ms delay
Buck 2 → Disabled
2-ms delay
Buck 1 → Disabled
An internal 22-kΩ pulldown resistor (±30%) is attached to the FB pin of Buck 1 and Buck 2. Buck 1 and 2 outputs
are pulled to ground level when they are disabled to discharge any residual charge present in the output circuitry.
When Sleep transitions to a low, Buck 1 is again enabled followed by Buck 2. Buck 3 goes back to its previous
state.
When waking up from sleep mode, the sequence is:
1. Buck 1 → Previous state
2. 2-ms delay
3. Buck 2 and Buck 3 transition together → Previous state
7.4.4.2 DevSLP Programming Through SPI
There is no bit which has the same function as DevSLP pin. There is only one requirement programming
LM10504 into DevSLP mode through SPI. Setting LDO sleep mode bit high must be the last move when entering
DevSLP mode and programming the bit low when waking from DevSLP mode must be the first move. Disabling
or programming the Bucks to new level is the user’s decision based on power consumption and other
requirements.
20
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Device Functional Modes (continued)
The following section describes how to program the chip into sleep mode corresponding to DevSLP pin function.
To program the LM10504 to sleep mode through SPI, Buck 1 and Buck 2 must be disabled by host device
(Register 0x0A bit 1 and 0). Buck 3 must be programmed to desired level using Register 0x00. After Buck 3 has
finished ramping, LDO sleep mode bit must be set high (Register 0x0E bit 1). To wake LM10504 from sleep
mode, LDO sleep mode bit must be set low (Register 0x0E bit 1). Buck 1 and 2 must be enabled. Buck 3 voltage
must be programmed to previous output level.
7.4.4.3 DevSLP Operational Constraints
In sleep mode the device is in a low power mode. All internal clocks are turned off to conserve power and Buck 3
only operates in PFM mode. While limited to PFM mode the loading on Buck 3 must be kept below 80 mA
(typical) to remain below the PFM/PWM threshold and avoid device shutdown. The device loading must be
lowered accordingly before entering sleep mode through DevSLP.
7.4.5 Vselect_B2, Vselect_B3 Function
The Vselect_B2/3 pins are digital pins which control alternate voltage selections of Buck 2 and Buck 3,
respectively. Vselect_B2 has an internal pulldown which defaults to a 1.8-V output voltage selection for Buck 2.
Alternatively, if Vselect_B2 is driven high, an output voltage of 3 V is selected. Vselect_B3 has an internal pullup
which defaults to a 1.2-V output voltage selection for Buck 3. Alternatively, if Vselect_B3 is driven low, an output
voltage of 1 V is selected. The pullup resistor is connected to the main input voltage. Transitions of the pins does
not affect the output voltage, the state is only checked during start-up.
7.4.6 Undervoltage Lockout (UVLO)
The VIN voltage is monitored for a supply under voltage condition, for which the operation of the device can not
be ensured. The part automatically disables Buck 3. To prevent unstable operation, the undervoltage lockout
(UVLO) has a hysteresis window of about 300 mV. An UVLO forces the device into the reset state, all internal
registers are reset. Once the supply voltage is above the UVLO hysteresis, the device initiates a power-up
sequence and then enter the active state.
Buck 1 and Buck 2 remain in bypass mode after VIN passes the UVLO until VIN reaches approximately 1.9 V.
When Buck 2 is set to 1.8 V, the voltage jumps from 1.8 V to VUVLO_FALLING, and then follow VIN.
The LDO and the comparator remains functional past the UVLO threshold until VIN reaches approximately
2.25 V.
7.4.7 Overvoltage Lockout (OVLO)
The VIN voltage is monitored for a supply overvoltage condition, for which the operation of the device cannot be
ensured. The purpose of overvoltage lockout (OVLO) is to protect the part and all other consumers connected to
the PMU outputs from any damage and malfunction. Once VIN rises over 5.64 V all the Bucks, and LDO is
disabled automatically. To prevent unstable operation, the OVLO has a hysteresis window of about 100 mV. An
OVLO forces the device into the reset state; all internal registers are reset. Once the supply voltage is below the
OVLO hysteresis, the device initiates a power-up sequence, and then enter the active state. Operating maximum
input voltage at which parameters are ensured is 5.5 V. Absolute maximum of the device is 6 V.
7.4.8 Device Status, Interrupt Enable
The LM10504 has 2 interrupt registers, INTERRUPT ENABLE and INTERRUPT STATUS. These registers can
be read through the serial interface. The interrupts are not latched to the register, always represents the current
state, and does not clear on read.
If interrupt condition is detected, then corresponding bit in the INTERRUPT STATUS register (0x0D) is set to '1',
and Interrupt output is asserted. There are 5 interrupt generating conditions:
• Buck 3 output is over flag level (90% when rising, 85% when falling)
• Buck 2 output is over flag level (90% when rising, 85% when falling)
• Buck 1 output is over flag level (90% when rising, 85% when falling)
• LDO is over flag level (90% when rising, 85% when falling
• Comparator input voltage crosses over selected threshold
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Device Functional Modes (continued)
Reading the interrupt register does not release interrupt output. Interrupt generation conditions can be
individually enabled or disabled by writing respective bits in INTERRUPT ENABLE register (0x0C) to 1 or 0.
7.4.9 Thermal Shutdown (TSD)
The temperature of the silicon die is monitored for an overtemperature condition, for which the operation of the
device can not be ensured. The part is automatically disabled if the temperature is too high (>140°C). The
thermal shutdown (TSD) forces the device into the reset state. In reset, all circuitry is disabled. To prevent
unstable operation, the TSD has a hysteresis window of about 20°C. Once the temperature has decreased below
the TSD hysteresis, the device initiates a power-up sequence and then enter the active state. In the active state,
the part starts up as if for the first time, all registers are in their default state.
7.4.10 Comparator
The comparator on the LM10504 takes its inputs from the VCOMP pin and an internal threshold level which is
programmed by the user. The threshold level is programmable between 2 and 4 V with a step of 31 mV and a
default comp code of 0x19. The output of the comparator is the Interrupt pin. Its polarity can be changed using
Register 0x0E bit 0. If Interrupt_polarity = 0 → Active low (default) is selected, then the output is low if VCOMP
value is greater than the threshold level. The output is high if the VCOMP value is less than the threshold level. If
Interrupt_polarity = 1 → Active high is selected then the output is high if VCOMP value is greater than the
threshold level. The output is low if the VCOMP value is less than the threshold level. There is some hysteresis
when VCOMP transitions from high to low, typically 60 mV. There is a control bit in register 0x0B, comparator
control, that can double the hysteresis value.
VTHRES
+
VCOMP
Interrupt
-
Interrupt
VCOMP
Delay due to
hysteresis
VTHRES
7.5 Programming
The device is programmable through 4-wire SPI Interface. The signals associated with this interface are CS, DI,
DO and CLK. Through this interface, the user can enable or disable the device, program the output voltages of
the individual Bucks, and of course read the status of Flag registers.
By accessing the registers in the device through this interface, the user can access and control the operation of
the buck controllers and program the reference voltage of the comparator in the device.
CS
CLK
DI
1
1
2
0
Write
Command
DO
3
A4
7
A3
A2
A1
Register Address
A0
9
0
D7
16
D6
D5
D4
D3
D2
D1
D0
Write Data
0
Figure 23. SPI Interface Write
22
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Programming (continued)
•
•
Data In (DI)
– 1 to 0 Write Command
– A4to A0 Register address to be written
– D7 to D0 Data to be written
Data Out (DO)
– All Os
CS
CLK
DI
1
1
2
1
Read
Command
3
A4
7
A3
A2
A1
A0
9
16
0
Register Address
DO
D7
D6
D5
D4
D3
D2
D1
D0
Read Data
Figure 24. SPI Interface Read
•
•
•
Data In (DI)
– 1 to 1 Read Command
– A4to A0 Register address to be read
Data Out (DO)
– D7 to D0 Data Read
Data In (DI)
– Don't Care after A0
7.6 Register Maps
Table 1. Registers Configurable Through SPI Interface
ADDR
0x00
0x07
REG NAME
Buck 3 voltage
Buck 1 voltage
BIT
R/W
7
—
DEFAULT
DESCRIPTION
NOTES
6
R/W
Buck 3 Voltage Code[6]
Vselect_B3 = 1 → 0x64 (1.2 V)
5
R/W
Buck 3 Voltage Code[5]
Vselect_B3 = 0 → 0x3C (1 V)
4
R/W
Buck 3 Voltage Code[4]
3
R/W
2
R/W
Buck 3 Voltage Code[2]
1
R/W
Buck 3 Voltage Code[1]
0
R/W
Buck 3 Voltage Code[0]
7
—
6
—
5
R/W
4
R/W
3
R/W
2
R/W
Buck 1 Voltage Code[2]
1
R/W
Buck 1 Voltage Code[1]
0
R/W
Buck 1 Voltage Code[0]
Reset default:
See Table 3
Buck 3 Voltage Code[3]
Range: 0.7 V to 1.335 V
Reset default:
0x26 (3 V)
Buck 1 Voltage Code[5]
See Table 2
Buck 1 Voltage Code[4]
Range: 1.1 V to 3.6 V
Buck 1 Voltage Code[3]
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Register Maps (continued)
Table 1. Registers Configurable Through SPI Interface (continued)
ADDR
0x08
REG NAME
Buck 2 voltage
BIT
R/W
7
—
DEFAULT
DESCRIPTION
6
—
5
R/W
Buck 2 Voltage Code[5]
4
R/W
Buck 2 Voltage Code[4]
3
R/W
2
R/W
Buck 2 Voltage Code[2]
1
R/W
Buck 2 Voltage Code[1]
0
R/W
Buck 2 Voltage Code[0]
Vselect_B2 = 1 → 0x26 (3 V)
See Table 2
Buck 2 Voltage Code[3]
7
0x09
DevSLP mode
for Buck 3
0x0B
0x0C
24
Buck control
Comparator
control
(see Table 4)
Interrupt enable
Vselect_B2 = 0 → 0x0E (1.8 V)
Range: 1.1 V to 3.6 V
Reset default:
6
Buck 3 Voltage Code[6]
Vselect_B3 = 1 → 0x53 (1.115 V)
5
Buck 3 Voltage Code[5]
Vselect_B3 = 0 → 0x0E (0.93 V)
4
3
R/W
See Table 3
Buck 3 Voltage Code[4]
Buck 3 Voltage Code[3]
2
Buck 3 Voltage Code[2]
1
Buck 3 Voltage Code[1]
0
0x0A
NOTES
Reset default:
Buck 3 Voltage Code[0]
7
R
6
—
1
BK3EN
Reads Buck 3 enable status
5
—
4
R/W
0
BK1FPWM
Buck 1 forced PWM mode when high
3
R/W
0
BK2FPWM
Buck 2 forced PWM mode when high
2
R/W
0
BK3FPWM
Buck 3 forced PWM mode when high
1
R/W
1
BK1EN
Enables Buck 1 0-disabled, 1-enabled
0
R/W
1
BK2EN
Enables Buck 2 0-disabled, 1-enabled
7
R/W
0
Comp_hyst[0]
Doubles Comparator hysteresis
6
R/W
0
Comp_thres[5]
Programmable range of 2 V to 4 V, step size
= 31.75 mV
5
R/W
1
Comp_thres[4]
4
R/W
1
Comp_thres[3]
3
R/W
0
Comp_thres[2]
Comp_hyst = 1 → min 80 mV hysteresis
2
R/W
0
Comp_thres[1]
Comp_hyst = 0 → min 40 mV hysteresis
1
R/W
1
Comp_thres[0]
0
R/W
1
COMPEN
7
—
6
—
5
—
4
R/W
0
LDO OK
3
R/W
0
Buck 3 OK
2
R/W
0
Buck 2 OK
1
R/W
0
Buck 1 OK
0
R/W
1
Comparator
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Comparator Threshold reset default: 0x19
Comparator enable
Interrupt comp event
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Register Maps (continued)
Table 1. Registers Configurable Through SPI Interface (continued)
ADDR
0x0D
0x0E
REG NAME
Interrupt status
MISC control
BIT
R/W
DEFAULT
DESCRIPTION
NOTES
7
—
6
—
5
—
4
R
LDO OK
LDO is greater than 90% of target
3
R
Buck 3 OK
Buck 3 is greater than 90% of target
2
R
Buck 2 OK
Buck 2 is greater than 90% of target
1
R
Buck 1 OK
Buck 1 is greater than 90% of target
0
R
Comparator
Comparator output is high
7
—
6
—
5
—
4
—
3
—
2
—
1
R/W
0
LDO sleep mode
LDO goes into extra power save mode
0
R/W
0
Interrupt Polarity
Interrupt_polarity= 0 → Active low Interrupt
Interrupt_polarity= 1 → Active high Interrupt
Table 2. ADDR 0x07 and 0x08 – Buck 1 and Buck 2 Voltage Code and VOUT Level Mapping
VOLTAGE CODE
VOLTAGE
VOLTAGE CODE
VOLTAGE
0x00
1.1
0x20
2.7
0x01
1.15
0x21
2.75
0x02
1.2
0x22
2.8
0x03
1.25
0x23
2.85
0x04
1.3
0x24
2.9
0x05
1.35
0x25
2.95
0x06
1.4
0x26
3
0x07
1.45
0x27
3.05
0x08
1.5
0x28
3.1
0x09
1.55
0x29
3.15
0x0A
1.6
0x2A
3.2
0x0B
1.65
0x2B
3.25
0x0C
1.7
0x2C
3.3
0x0D
1.75
0x2D
3.35
0x0E
1.8
0x2E
3.4
0x0F
1.85
0x2F
3.45
0x10
1.9
0x30
3.5
0x11
1.95
0x31
3.55
0x12
2
0x32
3.6
0x13
2.05
0x33
3.6
0x14
2.1
0x34
3.6
0x15
2.15
0x35
3.6
0x16
2.2
0x36
3.6
0x17
2.25
0x37
3.6
0x18
2.3
0x38
3.6
0x19
2.35
0x39
3.6
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Table 2. ADDR 0x07 and 0x08 – Buck 1 and Buck 2 Voltage Code and VOUT Level Mapping (continued)
VOLTAGE CODE
VOLTAGE
VOLTAGE CODE
VOLTAGE
0x1A
2.4
0x3A
3.6
0x1B
2.45
0x3B
3.6
0x1C
2.5
0x3C
3.6
0x1D
2.55
0x3D
3.6
0x1E
2.6
0x3E
3.6
0x1F
2.65
0x3F
3.6
Table 3. ADDR 0x00 and 0x09 – Buck 3 Voltage Code and VOUT Level Mapping
VOLTAGE
CODE
VOLTAGE
VOLTAGE
CODE
VOLTAGE
VOLTAGE
CODE
VOLTAGE
VOLTAGE
CODE
VOLTAGE
0x00
0.7
0x20
0.86
0x40
1.02
0x60
1.18
0x01
0.705
0x21
0.865
0x41
1.025
0x61
1.185
0x02
0.71
0x22
0.87
0x42
1.03
0x62
1.19
0x03
0.715
0x23
0.875
0x43
1.035
0x63
1.195
0x04
0.72
0x24
0.88
0x44
1.04
0x64
1.2
0x05
0.725
0x25
0.885
0x45
1.045
0x65
1.205
0x06
0.73
0x26
0.89
0x46
1.05
0x66
1.21
0x07
0.735
0x27
0.895
0x47
1.055
0x67
1.215
0x08
0.74
0x28
0.9
0x48
1.06
0x68
1.22
0x09
0.745
0x29
0.905
0x49
1.065
0x69
1.225
0x0A
0.75
0x2A
0.91
0x4A
1.07
0x6A
1.23
0x0B
0.755
0x2B
0.915
0x4B
1.075
0x6B
1.235
0x0C
0.76
0x2C
0.92
0x4C
1.08
0x6C
1.24
0x0D
0.765
0x2D
0.925
0x4D
1.085
0x6D
1.245
0x0E
0.77
0x2E
0.93
0x4E
1.09
0x6E
1.25
0x0F
0.775
0x2F
0.935
0x4F
1.095
0x6F
1.255
0x10
0.78
0x30
0.94
0x50
1.1
0x70
1.26
0x11
0.785
0x31
0.945
0x51
1.105
0x71
1.265
0x12
0.79
0x32
0.95
0x52
1.11
0x72
1.27
0x13
0.795
0x33
0.955
0x53
1.115
0x73
1.275
0x14
0.8
0x34
0.96
0x54
1.12
0x74
1.28
0x15
0.805
0x35
0.965
0x55
1.125
0x75
1.285
0x16
0.81
0x36
0.97
0x56
1.13
0x76
1.29
0x17
0.815
0x37
0.975
0x57
1.135
0x77
1.295
0x18
0.82
0x38
0.98
0x58
1.14
0x78
1.3
0x19
0.825
0x39
0.985
0x59
1.145
0x79
1.305
0x1A
0.83
0x3A
0.99
0x5A
1.15
0x7A
1.31
0x1B
0.835
0x3B
0.995
0x5B
1.155
0x7B
1.315
0x1C
0.84
0x3C
1
0x5C
1.16
0x7C
1.32
0x1D
0.845
0x3D
1.005
0x5D
1.165
0x7D
1.325
0x1E
0.85
0x3E
1.01
0x5E
1.17
0x7E
1.33
0x1F
0.855
0x3F
1.015
0x5F
1.175
0x7F
1.335
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Table 4. ADDR 0x0B – Comparator Threshold Mapping
VOLTAGE CODE
VOLTAGE
VOLTAGE CODE
VOLTAGE
0x00
2
0x20
3.016
0x01
2.032
0x21
3.048
0x02
2.064
0x22
3.08
0x03
2.095
0x23
3.111
0x04
2.127
0x24
3.143
0x05
2.159
0x25
3.175
0x06
2.191
0x26
3.207
0x07
2.222
0x27
3.238
0x08
2.254
0x28
3.27
0x09
2.286
0x29
3.302
0x0A
2.318
0x2A
3.334
0x0B
2.349
0x2B
3.365
0x0C
2.381
0x2C
3.397
0x0D
2.413
0x2D
3.429
0x0E
2.445
0x2E
3.461
0x0F
2.476
0x2F
3.492
0x10
2.508
0x30
3.524
0x11
2.54
0x31
3.556
0x12
2.572
0x32
3.588
0x13
2.603
0x33
3.619
0x14
2.635
0x34
3.651
0x15
2.667
0x35
3.683
0x16
2.699
0x36
3.715
0x17
2.73
0x37
3.746
0x18
2.762
0x38
3.778
0x19
2.794
0x39
3.81
0x1A
2.826
0x3A
3.842
0x1B
2.857
0x3B
3.873
0x1C
2.889
0x3C
3.905
0x1D
2.921
0x3D
3.937
0x1E
2.953
0x3E
3.969
0x1F
2.984
0x3F
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LM10504 contains three buck converters and one LDO.
8.2 Typical Application
Reset
DevSLP
LM10504
CS
IO input
supply
VIN_IO
Control
CLK
C8
2.2 F
CONTROL LOGIC and REGISTERS
C9
2.2 F
Power Supply
3.3/5.0V
System
DI
DO
SPI
VIN
VIN_B1
C5
4.7 F
VIN_B2
C6
4.7 F
Vcomp
COMP
Interrupt
LDO
3V
LDO
C4
4.7 F
L1
3V
SW_B1
BUCK1
2.2 H
FB_B1
C1
10 F
L2
SW_B2
BUCK2
2.2 H
FB_B2
L3
3V
C2
10 F
Low = 1.8V
Vselect3
Vselect2
GND
GND
BUCK3
GND
C7
4.7 F
2.2 H
FB_B3
Host 1
Flash
Vcc
3.0V/1.6A
Host 2
Domain
Vccq
3.0V/1A
1.2V
SW_B3
VIN_B3
Host
Controller
Vhost
3.0V/250 mA
C3 Low = 1.0V
10 F
Host 3
Domain
Vcore
1.2V/1A
Voltage Monitored
at Startup
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Figure 25. Typical Application Diagram
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Typical Application (continued)
8.2.1 Design Requirements
Table 5 lists the output characteristics of the power regulators.
Table 5. Output Voltage Configurations for LM10504
VOUT IF
Vselect=HIGH
(B2, B3)
VOUT IF
Vselect=LOW
(B2, B3)
VOUT IF
DevSLP=HIGH
(DevSLP MODE)
VOUT
MAXIMUM
OUTPUT
CURRENT
TYPICAL
APPLICATION
COMMENTS
Buck 1
3V
3V
Off
1.1 V to 3.6,
50 mV steps
1.6 A
VCC
Flash
Buck 2
3V
1.8 V
Off
1.1 V to 3.6,
50 mV steps
1A
VCCQ
Interface
Buck 3
1.2 V
1V
Vnominal –7%
0.7 V to 1.335 V,
5 mV steps
1A
VCORE
Core
3V
3V
3V
3V
250 mA
VHOST controller
Reference for
host
REGULATOR
LDO
8.2.2 Detailed Design Procedure
8.2.2.1 External Components Selection
All three switchers require an input capacitor and an output inductor-capacitor filter. These components are
critical to the performance of the device. All three switchers are internally compensated and do not require
external components to achieve stable operation. The output voltages of the bucks can be programmed through
the SPI pins.
8.2.2.1.1 Output Inductors and Capacitors Selection
There are several design considerations related to the selection of output inductors and capacitors:
• Load transient response
• Stability
• Efficiency
• Output ripple voltage
• Overcurrent ruggedness
The device has been optimized for use with nominal LC values as shown in Figure 25.
8.2.2.1.2 Inductor Selection
The recommended inductor values are shown in Figure 25. It is important to ensure the inductor core does not
saturate during any foreseeable operational situation. The inductor must be rated to handle the peak load current
plus the ripple current in Equation 2.
Care must be taken when reviewing the different saturation current ratings that are specified by different
manufacturers. Saturation current ratings are typically specified at 25°C, so ratings at maximum ambient
temperature of the application must be requested from the manufacturer.
IL(MAX) ILOAD(MAX) 'IRIPPLE
ILOAD(MAX)
| ILOAD(MAX)
D
D u (VIN VOUT )
2 u L u FS
D u (VIN VOUT )
(A typ.),
2 u 2.2 u 2.0
VOUT
, FS
VIN
2 MHz, L
2.2 PH
(2)
The two methods of selecting the inductor saturation are in Recommended Method for Inductor Selection and
Alternate Method for Inductor Selection.
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8.2.2.1.2.1 Recommended Method for Inductor Selection
The best way to ensure the inductor does not saturate is to choose an inductor that has saturation current rating
greater than the maximum device current limit, as specified in Electrical Characteristics – General. In this case,
the device prevents inductor saturation by going into current limit before the saturation level is reached.
8.2.2.1.2.2 Alternate Method for Inductor Selection
If the recommended approach cannot be used, care must be taken to ensure that the saturation current is
greater than the peak inductor current as calculated in Equation 3.
ISAT > ILPEAK
IRIPPLE
2
VOUT )
ILPEAK = IOUTMAX +
IRIPPLE
D
D u (VIN
L u FS
VOUT
VIN u EFF
•
•
•
•
•
•
•
•
•
•
ISAT is the inductor saturation current at operating temperature
ILPEAK is the peak inductor current during worst case conditions
IOUTMAX is the maximum average inductor current
IRIPPLE is the peak-to-peak inductor current
VOUT is the output voltage
VIN is the input voltage
L is the inductor value in Henries at IOUTMAX
F is the switching frequency, Hertz
D is the estimated duty factor
EFF is the estimated power supply efficiency
(3)
ISAT may not be exceeded during any operation, including transients, start-up, high temperature, worst-case
conditions, and so forth.
8.2.2.1.2.2.1 Suggested Inductors and Their Suppliers
The designer must choose the inductors that best match the system requirements. A very wide range of
inductors are available as regarding physical size, height, maximum current (thermally limited, and inductance
loss limited), series resistance, maximum operating frequency, losses, and so forth. In general, smaller physical
size inductors have higher series resistance (DCR), and implicitly lower overall efficiency is achieved. Very lowprofile inductors may have even higher series resistance. The designer must try to find the best compromise
between system performance and cost.
Table 6. Recommended Inductors
VALUE
MANUFACTURER
PART NUMBER
DCR
CURRENT
PACKAGE
2.2 µH
Murata
LQH55PN2R2NR0L
31 mΩ
2.5 A
2220
2.2 µH
TDK
NLC565050T-2R2K-PF
60 mΩ
1.3 A
2220
2.2 µH
Murata
LQM2MPN2R2NG0
110 mΩ
1.2 A
806
8.2.2.1.3 Output and Input Capacitors Characteristics
Special attention must be paid when selecting these components. As shown in Figure 26, the DC bias of these
capacitors can result in a capacitance value that falls below the minimum value given in Table 7. The graph
shows the capacitance out of spec for the 0402 case size capacitor at higher bias voltages. TI recommends that
the capacitor manufacturers’ specifications for the nominal value capacitor are consulted for all conditions, as
some capacitor sizes (for example, 0402) may not be suitable in the actual application.
30
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CAP VALUE (% of NOMINAL 1 PF)
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0603, 10V, X5R
100
80
60
0402, 6.3V, X5R
40
20
0
1.0
2.0
3.0
4.0
5.0
DC BIAS (V)
Figure 26. Typical Variation in Capacitance vs DC Bias
The ceramic capacitor’s capacitance can vary with temperature. The capacitor type X7R, which operates over a
temperature range of −55°C to 125°C, only varies the capacitance to within ±15%. The capacitor type X5R has a
similar tolerance over a reduced temperature range of −55°C to 85°C. Many large value ceramic capacitors,
larger than 1 µF are manufactured with Z5U or Y5V temperature characteristics. Their capacitance can drop by
more than 50% as the temperature varies from 25°C to 85°C. Therefore, X7R is recommended over Z5U and
Y5V in applications where the ambient temperature changes significantly above or below 25°C.
Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more
expensive when comparing equivalent capacitance and voltage ratings in the 0.47 µF to 44 µF range. Another
important consideration is that tantalum capacitors have higher ESR values than equivalent size ceramics. This
means that while it may be possible to find a tantalum capacitor with an ESR value within the stable range, it
would have to be larger in capacitance (which means bigger and more costly) than a ceramic capacitor with the
same ESR value. It must also be noted that the ESR of a typical tantalum increases about 2:1 as the
temperature goes from 25°C down to −30°C, so some guard band must be allowed.
8.2.2.1.3.1 Output Capacitor Selection
L
ESR
SW1/2/3
COUT
The output capacitor of a switching converter absorbs the AC ripple current from the inductor and provides the
initial response to a load transient. The ripple voltage at the output of the converter is the product of the ripple
current flowing through the output capacitor and the impedance of the capacitor. The impedance of the capacitor
can be dominated by capacitive, resistive, or inductive elements within the capacitor, depending on the frequency
of the ripple current. Ceramic capacitors have very low ESR and remain capacitive up to high frequencies. Their
inductive component can usually be neglected at the frequency ranges at which the switcher operates.
VOUT1/2/3
OUTPUT
CAPACITOR
Figure 27. Basic Schematic of Feedback Components
The output-filter capacitor smooths out the current flow from the inductor to the load and helps maintain a steady
output voltage during transient load changes. It also reduces output voltage ripple. These capacitors must be
selected with sufficient capacitance and low enough ESR to perform these functions.
Note that the output voltage ripple increases with the inductor current ripple and the Equivalent Series
Resistance of the output capacitor (ESRCOUT). Also note that the actual value of the capacitor’s ESRCOUT is
frequency and temperature dependent, as specified by its manufacturer. The ESR must be calculated at the
applicable switching frequency and ambient temperature with Equation 4.
VOUT-RIPPLE-PP
'IRIPPLE
where 'IRIPPLE
8 u FS u COUT
D u (VIN VOUT )
and D
2 u L u FS
VOUT
VIN
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Output ripple can be estimated from the vector sum of the reactive (capacitance) voltage component and the real
(ESR) voltage component of the output capacitor with Equation 5 and Equation 6.
VOUT-RIPPLE-PP
V 2ROUT
V 2COUT
where
(5)
VROUT
•
•
•
IRIPPLE
8 u FS u COUT
IRIPPLE u ESRCOUT and VCOUT
VOUT-RIPPLE-PP is the estimated output ripple
VROUT is the estimated real output ripple
VCOUT is the estimated reactive output ripple
(6)
The device is designed to be used with ceramic capacitors on the outputs of the buck regulators. The
recommended dielectric type of these capacitors is X5R, X7R, or of comparable material to maintain proper
tolerances over voltage and temperature. The recommended value for the output capacitors is 22 μF, 6.3 V with
an ESR of 2 mΩ or less. The output capacitors need to be mounted as close as possible to the output or ground
pins of the device.
Table 7. Recommended Output Capacitors
MODEL
TYPE VENDOR
VENDOR
VOLTAGE RATING
CASE SIZE
08056D226MAT2A
Ceramic, X5R
AVX Corporation
6.3 V
0805, (2012)
C0805L226M9PACTU
Ceramic, X5R
Kemet
6.3 V
0805, (2012)
ECJ-2FB0J226M
Ceramic, X5R
Panasonic - ECG
6.3 V
0805, (2012)
JMK212BJ226MG-T
Ceramic, X5R
Taiyo Yuden
6.3 V
0603, (1608)
C2012X5R0J226M
Ceramic, X5R
TDK Corporation
6.3 V
0603, (1608)
8.2.2.1.3.2 Input Capacitor Selection
There are 3 buck regulators in the LM10504 device. Each of these buck regulators has its own input capacitor
which must be located as close as possible to their corresponding SWx_VIN and SWx_GND pins, where x
designates Buck 1, 2, or 3. The 3 buck regulators operate at 120° out of phase, which means that they switch on
at equally spaced intervals, to reduce the input power rail ripple. TI recommends connecting all the supply and
ground pins of the buck regulators, SWx_VIN to two solid internal planes located under the device. In this way,
the 3 input capacitors work together and further reduce the input current ripple. A larger tantalum capacitor can
also be located in the proximity of the device.
The input capacitor supplies the AC switching current drawn from the switching action of the internal power
FETs. The input current of a buck converter is discontinuous, so the ripple current supplied by the input capacitor
is large. The input capacitor must be rated to handle both the RMS current and the dissipated power.
The input capacitor must be rated to handle this current with Equation 7.
IRMS _ CIN
IOUT
VOUT (VIN
VOUT )
VIN
(7)
The power dissipated in the input capacitor is given by Equation 8.
PD _ CIN
I2RMS _ CIN u RESR _ CIN
(8)
The device is designed to be used with ceramic capacitors on the inputs of the buck regulators. The
recommended dielectric type of these capacitors is X5R, X7R, or of comparable material to maintain proper
tolerances over voltage and temperature. The minimum recommended value for the input capacitor is 10 µF with
an ESR of 10 mΩ or less. The input capacitors need to be mounted as close as possible to the power and
ground input pins of the device.
The input power source supplies the average current continuously. However, during the PFET switch on-time,
the demanded di/dt is higher than can be typically supplied by the input power source. This delta is supplied by
the input capacitor.
32
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A simplified worst-case assumption is that all of the PFET current is supplied by the input capacitor. This results
in conservative estimates of input ripple voltage and capacitor RMS current.
Input ripple voltage is estimated with Equation 9.
IOUT u D
IOUT u ESRCIN
CIN u FS
VPPIN
where
•
•
•
•
VPPIN is the estimated peak-to-peak input ripple voltage
IOUT is the output current
CIN is the input capacitor value
ESRCIN is the input capacitor ESR
(9)
This capacitor is exposed to significant RMS current, so it is important to select a capacitor with an adequate
RMS current rating. Capacitor RMS current estimated with Equation 10.
IRMSCIN
§
D u ¨ I2OUT
¨
©
I2RIPPLE ·
¸
12 ¸¹
where
•
IRMSCIN is the estimated input capacitor RMS current
(10)
8.2.2.2 Recommendations For Unused Functions and Pins
If any function is not used in the end application, see Table 8 for tying off the associated pins on the circuit
boards must be used.
Table 8. Unused Pin Recommendations
FUNCTION
BUCK1
BUCK2
BUCK3
SPI
PIN
IF UNUSED
VIN_B1
Connect to GND
SW_B1
Floating
FB_B1
Connect to GND
VIN_B2
Connect to GND
SW_B2
Floating
FB_B2
Connect to GND
VIN_B3
Connect to VIN
SW_B3
Floating
FB_B3
Connect to VIN
SPI_CS
Connect to VIN_IO
SPI_DI
Connect to GND
SPI_DO
Connect to GND
SPI_CK
Connect to GND
Vselect_B2
Connect to GND or leave open
Vselect_B3
Connect to VIN or leave open
DevSLP
Connect to GND or leave open
RESET
COMPARATOR
Connect to VIN_IO
VCOMP
Connect to VIN
Interrupt
Leave open
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8.2.3 Application Curves
3.008
3.003
VIN = 5.0V
VIN = 3.3V
3.006
IOUT = 1mA
IOUT= 250mA
3.002
3.001
3.004
VOUT(V)
VOUT(V)
3.000
3.002
2.999
3.000
2.998
2.997
2.998
2.996
2.996
2.995
2.994
2.994
2.992
2.993
0
40
80
120 160 200 240 280
IOUT(mA)
Figure 28. LDO VOUT vs IOUT
3.0
3.5
4.0
4.5 5.0
VIN(V)
5.5
6.0
Figure 29. LDO VIN vs VOUT
9 Power Supply Recommendations
The device is designed to operate from a fixed input voltage supply at 3.3 V or 5 V, but is capable of operating at
input voltages from 3 V to 5.5 V.
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10 Layout
10.1 Layout Guidelines
PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance
of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss
in the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability.
Good layout can be implemented by following a few simple design rules.
1. Minimize area of switched current loops. In a buck regulator there are two loops where currents are switched
rapidly. The first loop starts from the CIN input capacitor, to the regulator SWx_VIN pin, to the regulator SW
pin, to the inductor then out to the output capacitor COUTand load. The second loop starts from the output
capacitor ground, to the regulator SWx_GND pins, to the inductor and then out to COUT and the load (see
Figure 31). To minimize both loop areas, the input capacitor must be placed as close as possible to the VIN
pin. Grounding for both the input and output capacitors must consist of a small localized top-side plane that
connects to PGND. The inductor must be placed as close as possible to the SW pin and output capacitor.
2. Minimize the copper area of the switch node. The SW pins must be directly connected with a trace that runs
on top-side directly to the inductor. To minimize IR losses this trace must be as short as possible and with a
sufficient width. However, a trace that is wider than 100 mils increases the copper area and cause too much
capacitive loading on the SW pin. The inductors must be placed as close as possible to the SW pins to
further minimize the copper area of the switch node.
3. Have a single point ground for all device analog grounds. The ground connections for the feedback
components must be connected together then routed to the GND pin of the device. This prevents any
switched or load currents from flowing in the analog ground plane. If not properly handled, poor grounding
can result in degraded load regulation or erratic switching behavior.
4. Minimize trace length to the FB pin. The feedback trace must be routed away from the SW pin and inductor
to avoid contaminating the feedback signal with switch noise.
5. Make input and output bus connections as wide as possible. This reduces any voltage drops on the input or
output of the converter and can improve efficiency. If voltage accuracy at the load is important make sure
feedback voltage sense is made at the load. Doing so corrects for voltage drops at the load and provide the
best output accuracy.
10.1.1 PCB Layout Thermal Dissipation For DSGBA Package
1. Position ground layer as close as possible to DSBGA package. Second PCB layer is usually good option.
LM10504 evaluation board is a good example.
2. Draw power traces as wide as possible. Bumps which carry high currents must be connected to wide traces.
This helps the silicon to cool down.
10.2 Layout Example
Outside 7×7 array, 0.4-mm DSBGA 34-bump with 24 peripheral and 6 inner vias = 30 individual signals
Figure 30. Possible PCB Layout Configuration
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Layout Example (continued)
S
CIN
L
G
N
COUT
PGND
LOOP2
D
VIN
CONTROL
LOOP1
VOUT
P
D
SW VIN
G
S
U1 LM10504
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Figure 31. Schematic of LM10504 Highlighting Layout Sensitive Nodes
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LM10504TME/NOPB
NRND
DSBGA
YFR
34
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
0 to 0
V039
LM10504TMX/NOPB
NRND
DSBGA
YFR
34
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
0 to 0
V039
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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