LM21215
SNVS625G – FEBRUARY 2011 – REVISED MARCH 2022
LM21215 2.95-V to 5.5-V, 12-A, Voltage-Mode Synchronous Buck Regulator
efficiency. The device is optimized to work over an
input voltage range of 2.95 V to 5.5 V, making it
suitable for a wide variety of low voltage systems.
The voltage mode control loop provides high noise
immunity, narrow duty cycle capability and can be
compensated to be stable with any type of output
capacitance, providing maximum flexibility and ease
of use.
1 Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Integrated 7-mΩ high-side and 4.3-mΩ low-side
FET switches
Adjustable current limit
Adjustable output voltage from 0.6 V to VIN (100%
duty cycle capable), ±1% reference
2.95-V to 5.5-V input voltage range
500-kHz fixed switching frequency
Start-up into prebiased loads
Output voltage tracking capability
Wide bandwidth voltage loop error amplifier
Adjustable soft start with external capacitor
Precision enable pin with hysteresis
Integrated OVP, OTP, UVLO, and power good
Thermally enhanced 20-pin HTSSOP exposed pad
package
Create a custom design using the LM21215 with
the WEBENCH® Power Designer
The LM21215 features internal overvoltage protection
(OVP) and resistor-programmable overcurrent
protection (OCP) for increased system reliability. A
precision enable pin and integrated UVLO allow
turn-on of the device to be tightly controlled and
sequenced. Start-up inrush currents are limited by
both an internally fixed and externally adjustable softstart circuit. Fault detection and supply sequencing
are possible with the integrated power good circuit.
The LM21215 is designed to work well in multi-rail
power supply architectures. The output voltage of
the device can be configured to track an external
voltage rail using the SS/TRK pin. If the output is
prebiased at start-up, it will not sink current, allowing
the output to smoothly rise past the prebiased voltage.
The regulator is offered in a 20-pin HTSSOP package
with an exposed pad that can be soldered to the PCB,
eliminating the need for bulky heat sinks.
2 Applications
•
•
•
Broadband, networking, and wireless
communications
High-performance FPGAs, ASICs, and
microprocessors
Simple-to-design, high-efficiency point-of-load
regulation from a 5-V or 3.3-V bus
3 Description
Device Information
The LM21215 is a monolithic synchronous point-ofload buck regulator that is capable of delivering up
to 15 A of continuous output current while producing
an output voltage down to 0.6 V with outstanding
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
LM21215
HTSSOP (20)
6.50 mm × 4.40 mm
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
HTSSOP-20
LOUT
5,6,7
VIN
PVIN
CIN
SW
11-16
RF
VOUT
COUT
4
CC3
AVIN
RFB1
CF
3
LM21215
FB
EN
optional
optional
COMP
18
CC1 RC1
RFB2
2 SS/
TRK
CSS
CC2
17
1
PGOOD
ILIM
RILIM
RC2
19
PGND AGND
8,9,10
20
Simplified Application Circuit
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM21215
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SNVS625G – FEBRUARY 2011 – REVISED MARCH 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Ratings..............................4
6.4 Electrical Characteristics.............................................4
6.5 Typical Characteristics................................................ 6
7 Detailed Description......................................................10
7.1 Overview................................................................... 10
7.2 Functional Block Diagram......................................... 10
7.3 Feature Description...................................................10
7.4 Device Functional Modes..........................................14
8 Application and Implementation.................................. 15
8.1 Application Information............................................. 15
8.2 Typical Application.................................................... 15
9 Layout.............................................................................29
9.1 Layout Considerations.............................................. 29
9.2 Layout Example........................................................ 29
10 Device and Documentation Support..........................32
10.1 Device Support....................................................... 32
10.2 Receiving Notification of Documentation Updates..32
10.3 Support Resources................................................. 32
10.4 Trademarks............................................................. 32
10.5 Electrostatic Discharge Caution..............................32
10.6 Glossary..................................................................32
11 Mechanical, Packaging, and Orderable
Information.................................................................... 33
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (June 2019) to Revision G (March 2022)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document. ................1
• Removed reference to adjustable frequency.................................................................................................... 10
• Removed reference to adjustable frequency.................................................................................................... 15
Changes from Revision E (March 2013) to Revision F (June 2019)
Page
• Editorial changes only, no technical revisions; add links for WEBENCH............................................................1
2
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5 Pin Configuration and Functions
Top View
20 AGND
ILIM 1
SS/TRK 2
19 FB
18 COMP
EN 3
AVIN 4
17 PGOOD
PVIN 5
16 SW
PVIN 6
EP
15 SW
PVIN 7
14 SW
PGND 8
13 SW
PGND 9
12 SW
PGND 10
11 SW
Figure 5-1. 20-Pin HTSSOP Package PWP Package (Top View)
Table 5-1. Pin Functions
PIN
NO.
NAME
DESCRIPTION
1
ILIM
Resistor-programmable current limit pin. A resistor connected to this pin and ground sets the value of the
rising current limit, ICLR. Shorting this pin to AGND programs the device to the maximum possible current
limit.
2
SS/TRK
Soft-start control pin. An internal 2-µA current source charges an external capacitor connected between
this pin and AGND to set the output voltage ramp rate during start-up. This pin can also be used to
configure the tracking feature.
3
EN
Active high enable input for the device. If not used, the EN pin can be left open, which goes high due to
an internal current source.
4
AVIN
Analog input voltage supply that generates the internal bias. It is recommended to connect PVIN to AVIN
through a low pass RC filter to minimize the influence of input rail ripple and noise on the analog control
circuitry.
5,6,7
PVIN
Input voltage to the power switches inside the device. These pins should be connected together at the
device. A low-ESR input capacitance should be located as close as possible to these pins.
8,9,10
PGND
Power ground pins for the internal power switches
11-16
SW
17
PGOOD
18
COMP
19
FB
20
AGND
EP
Exposed Pad
Switch node pins. These pins should be tied together locally and connected to the filter inductor.
Open-drain power good indicator
Compensation pin is connected to the output of the voltage loop error amplifier
Feedback pin is connected to the inverting input of the voltage loop error amplifier
Quiet analog ground for the internal reference and bias circuitry
Exposed metal pad on the underside of the package with an electrical and thermal connection to
PGND. TI recommends connecting this pad to the PC board ground plane in order to improve thermal
dissipation.
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6 Specifications
6.1 Absolute Maximum Ratings
See
PVIN(1), AVIN to GND
−0.3 V to +6 V
SW(2), EN, FB, COMP, PGOOD, SS/TRK to GND
−0.3 V to PVIN + 0.3 V
Storage temperature
−65°C to 150°C
Lead temperature (soldering, 10 s)
(1)
(2)
260°C
The PVIN pin can tolerate transient voltages up to 6.5 V for a period of up to 6 ns. These transients can occur during the normal
operation of the device.
The SW pin can tolerate transient voltages up to 9.0 V for a period of up to 6 ns, and –1 V for a duration of 4 ns. These transients can
occur during the normal operation of the device.
6.2 ESD Ratings
V(ESD)
(1)
Electrostatic discharge
VALUE
UNIT
±2000
V
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Ratings
See (1)
PVIN, AVIN to GND
+2.95 V to +5.5 V
Junction temperature
−40°C to +125°C
θJA (2)
(1)
(2)
24°C/W
Absolute Maximum Ratings indicate limits beyond witch damage to the device may occur. Recommended operating ratings indicate
conditions for which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications
and test conditions, see the Electrical Characteristics.
Thermal measurements were performed on a 2-inch × 2-inch, 4-layer, 2-oz. copper outer layer, 1-oz. copper inner layer board with
twelve 8-mil. vias under the EP of the device and an additional sixteen 8-mil. vias under the unexposed package.
6.4 Electrical Characteristics
Unless otherwise stated, the following conditions apply: VPVIN, AVIN = 5 V. Limits in standard type are for TJ = 25°C only,
limits in boldface type apply over the junction temperature (TJ) range of −40°C to +125°C. Minimum and maximum limits are
specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C,
and are provided for reference purposes only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
-1%
0.6
1%
V
SYSTEM
VFB
VIN = 2.95V to 5.5V
ΔVOUT/ΔIOUT Load Regulation
0.02
%VOUT/A
ΔVOUT/ΔVIN
0.1
%VOUT/V
Line Regulation
RDSON HS
High Side Switch On Resistance
ISW = 12A
7
9.0
mΩ
RDSON LS
Low Side Switch On Resistance
ISW = 12A
4.3
6.0
mΩ
ICLR
HS Rising Switch Current Limit
A
ICLF
VZX
4
Feedback pin voltage
LS Falling Switch Current Limit
RILIM = 16.5 kΩ
16.5
20
23.5
RILIM = 41.3 kΩ
8.5
10
11.5
RILIM = 130 kΩ
3.8
RILIM = 16.5 kΩ
14.5
RILIM = 41.3 kΩ
7.5
RILIM = 130 kΩ
3
Zero Cross Voltage
IQ
Operating Quiescent Current
ISD
Shutdown Quiescent Current
-8
VEN = 0V
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A
3
12
mV
1.5
3
mA
50
70
µA
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Unless otherwise stated, the following conditions apply: VPVIN, AVIN = 5 V. Limits in standard type are for TJ = 25°C only,
limits in boldface type apply over the junction temperature (TJ) range of −40°C to +125°C. Minimum and maximum limits are
specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C,
and are provided for reference purposes only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2.45
2.7
2.95
V
140
200
280
mV
SYSTEM
VUVLO
AVIN Under Voltage Lockout
AVIN Rising
VUVLOHYS
AVIN Under Voltage Lockout Hysteresis
VTRACKOS
SS/TRACK PIN accuracy (VSS - VFB)
ISS
0 < VTRACK < 0.55V
Soft-Start Pin Source Current
CSS = 0
-10
6
20
mV
1.3
1.9
2.5
µA
tINTSS
Internal Soft-Start Ramp to Vref
350
500
675
µs
tRESETSS
Device reset to soft-start ramp
50
110
200
µs
Switching Frequency
475
500
525
kHz
OSCILLATOR
fOSC
tHSBLANK
HS OCP blanking time
Rising edge of SW to ICLR
comparison
55
ns
tLSBLANK
LS OCP blanking time
Falling edge of SW to ICLF
comparison
400
ns
tZXBLANK
Zero Cross blanking time
Falling edge of SW to VZX
comparison
120
ns
Minimum HS on-time
140
ns
PWM Ramp p-p Voltage
0.8
V
95
dBV/V
11
MHz
tMINON
ΔVRAMP
ERROR AMPLIFIER
VOL
Error Amplifier Open Loop Voltage Gain
GBW
Error Amplifier Gain-Bandwidth Product
IFB
Feedback Pin Bias Current
ICOMP = -65µA to 1mA
1
nA
ICOMPSRC
COMP Output Source Current
VFB = 0.6V
1
mA
ICOMPSINK
COMP Output Sink Current
65
µA
POWERGOOD
VOVP
VOVPHYS
VUVP
VUVPHYS
Overvoltage Protection Rising Threshold
VFB Rising
Overvoltage Protection Hysteresis
VFB Falling
Undervoltage Protection Rising Threshold
VFB Rising
Undervoltage Protection Hysteresis
VFB Falling
105
112.5
120
2
82
90
%VFB
%VFB
97
%VFB
2.5
%VFB
tPGDGL
PGOOD Deglitch Low (OVP/UVP Condition
Duration to PGOOD Falling)
15
µs
tPGDGH
PGOOD Deglitch High (minimum low pulse)
12
µs
RPD
IPGOODLEAK
PGOOD Pulldown Resistance
10
PGOOD Leakage Current
VPGOOD = 5V
VIHENR
EN Pin Rising Threshold
VEN Rising
VENHYS
EN Pin Hysteresis
20
40
1
Ω
nA
LOGIC
IEN
EN Pin Pullup Current
VEN = 0V
1.20
1.35
1.45
V
50
110
180
mV
2
µA
165
°C
10
°C
THERMAL SHUTDOWN
TTHERMSD
Thermal Shutdown
TTHERMSDHYS Thermal Shutdown Hysteresis
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6.5 Typical Characteristics
Unless otherwise specified: VIN = 5 V, VOUT = 1.2 V, L= 0.56 µH (1.8-mΩ RDCR), CSS = 33 nF, TA = 25°C for
efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others.
100
100
VIN = 3.3V
VIN = 5.0V
98
99
98
EFFICIENCY (%)
EFFICIENCY (%)
96
94
92
90
88
86
97
96
95
94
93
84
92
82
91
80
90
0
3
6
9
12
OUTPUT CURRENT (A)
15
Figure 6-1. Efficiency
VIN = 4.0V
VIN = 5.5V
0
3
6
9
12
OUTPUT CURRENT (A)
VOUT = 3.3 V
15
Inductor P/N SER2010-02MLD
Figure 6-2. Efficiency
1.17
IAVIN(mA)
1.3
1.2
1.1
1.0
3.0
3.5
4.0
4.5
5.0
INPUT VOLTAGE (V)
0.164
1.11
0.156
1.08
0.148
1.05
0.140
1.02
0.132
0.99
0.124
0.96
0.116
0.93
0.108
Figure 6-4. Non-Switching IAVIN and IPVIN vs
Temperature
0.602
1.37
VFB(V)
VIHENR(V)
0.601
0.600
0.599
0.598
6
V IHENR
V ENHYS
160
152
1.36
144
1.35
136
1.34
128
1.33
120
1.32
112
1.31
104
1.30
96
1.29
88
1.28
80
-40 -20 0 20 40 60 80 100 120
JUNCTION TEMPERATURE (°C)
Figure 6-5. VFB vs Temperature
0.172
1.14
0.100
0.90
-40 -20 0 20 40 60 80 100 120
JUNCTION TEMPERATURE (°C)
5.5
Figure 6-3. Non-Switching IQTOTAL vs VIN
0.180
VENHYS(V)
IPVIN+ IAVIN(mA)
1.4
IAVIN
IPVIN
IPVIN(mA)
1.20
1.5
-40 -20 0 20 40 60 80 100 120
JUNCTION TEMPERATURE (°C)
Figure 6-6. Enable Threshold and Hysteresis vs
Temperature
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VUVLO(V)
300
60
285
58
2.76
270
2.74
255
2.72
240
2.70
225
2.68
210
2.66
195
2.64
180
2.62
165
2.60
150
ENABLE LOW CURRENT ( A)
V UVLO
V UVLOHYS
2.78
VUVLOHYS(mV)
2.80
56
54
52
50
48
46
44
42
40
-40 -20 0 20 40 60 80 100 120
JUNCTION TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100 120
JUNCTION TEMPERATURE (°C)
Figure 6-7. UVLO Threshold and Hysteresis vs
Temperature
Figure 6-8. Enable Low Current vs Temperature
160
156
0.68
MINIMUM ON-TIME (nS)
VOVP,VUVP(V)
0.66
VUVP
VOVP
0.64
0.62
0.60
0.58
0.57
0.54
Figure 6-9. OVP/UVP Threshold vs Temperature
140
136
132
128
-40 -20 0 20 40 60 80 100 120
JUNCTION TEMPERATURE (°C)
Figure 6-10. Minimum On-Time vs Temperature
12
LOW SIDE
HIGH SIDE
11
8
10
7
9
ICLR(A)
RDSON(m )
144
120
0.50
-40 -20 0 20 40 60 80 100 120
JUNCTION TEMPERATURE (°C)
9
148
124
0.52
10
152
6
8
5
7
4
6
3
5
2
4
-40 -20 0 20 40 60 80 100 120
JUNCTION TEMPERATURE (°C)
Figure 6-11. FET Resistance vs Temperature
RILIM = 41.2k
RILIM = 74.9k
3.0
3.5
4.0
4.5
VIN(V)
5.0
5.5
Figure 6-12. Peak Current Limit (ICLR) vs VIN
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22
21
23.0
RILIM = 24.9k
RILIM = 16.5k
22.5
22.0
CURRENT LIMIT (A)
ICLR(A)
20
19
18
17
16
VIN = 3.3V
VIN = 5.5V
21.5
21.0
20.5
20.0
15
19.5
14
19.0
3.0
3.5
4.0
4.5
VIN(V)
5.0
5.5
Figure 6-13. Peak Current Limit (ICLR) vs VIN
-40 -20 0 20 40 60 80 100 120
JUNCTION TEMPERATURE (°C)
RILIM = 10 KΩ
Figure 6-14. Peak Current Limit (ICLR) vs
Temperature
8.0
VIN = 3.3V
VIN = 5.5V
VOUT (500 mV/Div)
CURRENT LIMIT (A)
7.8
7.6
VPGOOD (5V/Div)
7.4
7.2
VENABLE (5V/Div)
7.0
6.8
6.6
-40 -20 0 20 40 60 80 100 120
JUNCTION TEMPERATURE (°C)
2 ms/DIV
Figure 6-16. Start-up With Prebiased Output
RILIM = 61.9 KΩ
Figure 6-15. Peak Current Limit (ICLR) vs
Temperature
VOUT (500 mV/Div)
VOUT (500 mV/Div)
VPGOOD (5V/Div)
VTRACK (500 mV/Div)
VPGOOD (5V/Div)
VENABLE (5V/Div)
IOUT (10A/Div)
IOUT (10A/Div)
100 µs/DIV
200 µs/DIV
Figure 6-18. Start-up With Applied Track Signal
200 µs/DIV
Figure 6-17. Start-up With SS/TRK Open Circuit
8
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VPGOOD (5V/Div)
VOUT (1V/Div)
IL (10A/Div)
100 µs/DIV
RILIM = 20 KΩ
Figure 6-19. Output Overcurrent Condition
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7 Detailed Description
7.1 Overview
The LM21215 switching regulator features all of the functions necessary to implement an efficient low voltage
buck regulator using a minimum number of external components. This easy-to-use regulator features two
integrated switches and is capable of supplying up to 15 A of continuous output current. The regulator utilizes
voltage mode control with trailing edge modulation to optimize stability and transient response over the entire
output voltage range. The precision internal voltage reference allows the output to be set as low as 0.6 V. Fault
protection features include: current limiting, thermal shutdown, overvoltage protection, and shutdown capability.
The device is available in the 20-pin HTSSOP package featuring an exposed pad to aid thermal dissipation. The
LM21215 can be used in numerous applications to efficiently step-down from a 5-V or 3.3-V bus.
7.2 Functional Block Diagram
CURRENT
LIMIT
ILIM
Ilimit high
VREF
AVIN
PVIN
Over
temp
+
-
PVIN
UVLO
2.7V
+
-
SD
OR
Driver
Precision
enable
AVIN
1.35V
+
-
EN
Control
Logic
PWM
comparator
AVIN
OSC
RAMP
+
-
Zero-cross
+
-
PWM
SW
INT
SS
PVIN
+
SS/TRK
0.6V
EA
Driver
FB
OVP
COMP
0.68V
0.54V
+
-
Ilimit low
OR
Powerbad
+
-
PGND
UVP
AGND
OR
PGOOD
7.3 Feature Description
7.3.1 Precision Enable
The enable (EN) pin allows the output of the device to be enabled or disabled with an external control signal.
This pin is a precision analog input that enables the device when the voltage exceeds 1.35 V (typical). The EN
pin has 110 mV of hysteresis and disables the output when the enable voltage falls below 1.24 V (typical). If
the EN pin is not used, it can be left open, and will be pulled high by an internal 2-µA current source. Since the
enable pin has a precise turn-on threshold, it can be used along with an external resistor divider network from
VIN to configure the device to turn on at a precise input voltage.
10
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7.3.2 UVLO
The LM21215 has a built-in undervoltage lockout protection circuit that keeps the device from switching until the
input voltage reaches 2.7 V (typical). The UVLO threshold has 200 mV of hysteresis that keeps the device from
responding to power-on glitches during start-up. If desired, the turn-on point of the supply can be changed by
using the precision enable pin and a resistor divider network connected to VIN as shown in Figure 8-3 in the
design guide.
7.3.3 Current Limit
The LM21215 has programmable current limit protection to avoid dangerous current levels through the power
FETs and inductor. A current limit condition is met when the current through the high side FET exceeds the
rising current limit level (ICLR). The control circuitry will respond to this event by turning off the high-side FET and
turning on the low-side FET. This forces a negative voltage on the inductor, thereby causing the inductor current
to decrease. The high-side FET will not conduct again until the lower current limit level (ICLF) is sensed on the
low-side FET. At this point, the device will resume normal switching.
A current limit condition will cause the internal soft-start voltage to ramp downward. After the internal soft-start
ramps below the feedback (FB) pin voltage (nominally 0.6 V), FB will begin to ramp downward, as well. This
voltage foldback will limit the power consumption in the device, thereby protecting the device from continuously
supplying power to the load under a condition that does not fall within the device SOA. After the current limit
condition is cleared, the internal soft-start voltage will ramp up again. Figure 7-1 shows current limit behavior
with VSS, VFB, VOUT, and VSW.
7.3.4 Short-Circuit Protection
In the unfortunate event that the output is shorted with a low impedance to ground, the LM21215 limits the
current into the short by resetting the device. A short-circuit condition is sensed by a current-limit condition
coinciding with a voltage on the FB pin that is lower than 100 mV. When this condition occurs, the device begins
its reset sequence, turning off both power FETs and discharging the soft-start capacitor after tRESETSS (nominally
110 µs). The device will then attempt to restart. If the short-circuit condition still exists, it will reset again, and
repeat until the short-circuit is cleared. The reset prevents excess current flowing through the FETs in a highly
inefficient manner, potentially causing thermal damage to the device or the bus supply.
Iclr
IL
Iclf
VSS
VFB
100 mV
VOUT
VSW
CURRENT LIMIT
SHORT-CIRCUIT
SHORT-CIRCUIT
REMOVED
Figure 7-1. Current Limit Conditions
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7.3.5 Thermal Protection
Internal thermal shutdown circuitry is provided to protect the integrated circuit in the event that the maximum
junction temperature is exceeded. When activated, typically at 165°C, the LM21215 tri-states the power FETs
and resets soft start. After the junction cools to approximately 155°C, the device starts up using the normal startup routine. This feature is provided to prevent catastrophic failures from accidental device overheating. Note that
thermal limit will not stop the die from operating above the specified maximum operating temperature,125°C.
The die should be kept under 125°C to ensure correct operation.
7.3.6 Light Load Operation
The LM21215 offers increased efficiency when operating at light loads. Whenever the load current is reduced to
a point where the peak to peak inductor ripple current is greater than two times the load current, the device will
enter the diode emulation mode, preventing significant negative inductor current. The point at which this occurs
is the critical conduction boundary and can be calculated with Equation 1:
IBOUNDARY =
(VIN ± VOUT) x D
2 x L x fSW
(1)
It can be seen that in diode emulation mode, whenever the inductor current reaches zero, the SW node
becomes high impedance. Ringing will occur on this pin as a result of the LC tank circuit formed by the inductor
and the parasitic capacitance at the node. If this ringing is of concern, an additional RC snubber circuit can be
added from the switch node to ground.
At very light loads, usually below 100 mA, several pulses can be skipped in between switching cycles, effectively
reducing the switching frequency and further improving light-load efficiency.
7.3.7 Power Good Flag
The PGOOD pin provides the user with a way to monitor the status of the LM21215. In order to use the PGOOD
pin, the application must provide a pullup resistor to a desired DC voltage (in other words, VIN). PGOOD will
respond to a fault condition by pulling the PGOOD pin low with the open-drain output. PGOOD pulls low on the
following conditions:
• VFB moves above or below the VOVP or VUVP, respectively.
• The enable pin (EN) is brought below the enable threshold.
• The device enters a prebiased output condition (VFB > VSS).
Figure 7-2 shows the conditions that will cause PGOOD to fall.
12
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t RESETSS
V ss
0.6V
Vovp
VOVPHYS
VFB
Vuvp
VUVPHYS
VEN
V PGOOD
V SW
OVP
UVP
DISABLE
tPGDGL
PRE-BIASED
STARTUP
t PGDGH
Figure 7-2. PGOOD Conditions
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7.4 Device Functional Modes
Switchnode Voltage
Several diagrams are shown in illustrating continuous conduction mode (CCM), discontinuous conduction mode
(DCM), and the boundary condition.
Continuous Conduction Mode (CCM)
VIN
Inductor Current
Time (s)
Continuous Conduction Mode (CCM)
IAVERAGE
Inductor Current
Time (s)
DCM - CCM Boundary
IAVERAGE
Switchnode Voltage
Time (s)
Discontinuous Conduction Mode (DCM)
VIN
Inductor Current
Time (s)
Discontinuous Conduction Mode (DCM)
IPeak
Time (s)
Figure 7-3. Modes Of Operation for LM21215
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The LM21212-2 switching regulator features all of the functions necessary to implement an efficient low voltage
buck regulator using a minimum number of external components. This easy-to-use regulator features two
integrated switches and is capable of supplying up to 12 A of continuous output current. The regulator utilizes
voltage mode control with trailing edge modulation to optimize stability and transient response over the entire
output voltage range.
8.2 Typical Application
8.2.1 Typical Application 1
HTSSOP-20
5,6,7
VIN
3
RF
PVIN
LO
SW
11-16
CC3
EN
RFB1
4
CIN1 CIN2 CIN3
VOUT
RC2
AVIN
CF
LM21215
FB
CSS
2 SS /
TRK
COMP
CO1 CO2 CO3
19
18
CC1 RC1
RFB2
CC2
VIN
1
ILIM
RILIM
17
PGOOD
PGND AGND
8,9,10
RPGOOD
20
Figure 8-1. Typical Application Schematic 1
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8.2.1.1 Design Requirements
Table 8-1. Bill Of Materials (VIN = 3.3 V–5.5 V, VOUT = 1.2 V, IOUT = 15 A)
ID
DESCRIPTION
VENDOR
PART NUMBER
QUANTITY
CF
CAP, CERM, 1 μF, 10 V, ±10%, X7R, 0603
MuRata
GRM188R71A105KA61D
1
CIN1, CIN2,
CIN3, CO1, CO2,
CO3
CAP, CERM, 100 μF, 6.3 V, ±20%, X5R, 1206
MuRata
GRM31CR60J107ME39L
6
CC1
CAP, CERM, 1800 pF, 50 V, ±5%, C0G/NP0, 0603
TDK
C1608C0G1H182J
1
CC2
CAP, CERM, 68 pF, 50 V, ±5%, C0G/NP0, 0603
TDK
C1608C0G1H680J
1
CC3
CAP, CERM, 820 pF, 50 V, ±5%, C0G/NP0, 0603
TDK
C1608C0G1H821J
1
CSS
CAP, CERM, 0.033 μF, 16 V, ±10%, X7R, 0603
MuRata
GRM188R71C333KA01D
1
LO
Inductor, Shielded Drum Core, Powdered Iron, 560 nH,
27.5 A, 0.0018 Ω, SMD
Vishay-Dale
IHLP4040DZERR56M01
1
RF
RES, 1.0 Ω, 5%, 0.1 W, 0603
Vishay-Dale
CRCW06031R00JNEA
1
RC1
RES, 9.31 kΩ, 1%, 0.1 W, 0603
Vishay-Dale
CRCW06039K31FKEA
1
RC2
RES, 165 Ω, 1%, 0.1 W, 0603
Vishay-Dale
CRCW0603165RFKEA
1
RFB1, RFB2,
RPGOOD
RES, 10 kΩ, 1%, 0.1 W, 0603
Vishay-Dale
CRCW060310K0FKEA
3
RILIM
RES, 7.15 kΩ, 1%, 0.1 W, 0603
Vishay-Dale
CRCW06037K15FKEA
1
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM21215 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.1.2.2 Output Voltage
The first step in designing the LM21215 application is setting the output voltage. This is done by using a voltage
divider between VOUT and AGND, with the middle node connected to VFB. When operating under steady-state
conditions, the LM21215 forces VOUT so that VFB is driven to 0.6 V.
VOUT
LM21215
RFB1
0.6V
FB
RFB2
Figure 8-2. Setting VOUT
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A good starting point for the lower feedback resistor, RFB2, is 10 kΩ. RFB1 can then be calculated with Equation
2:
VOUT =
RFB1 + RFB2
0.6V
RFB2
(2)
8.2.1.2.3 Precision Enable
The enable (EN) pin of the LM21215 allows the output to be toggled on and off. This pin is a precision analog
input. When the voltage exceeds 1.35 V, the controller will try to regulate the output voltage as long as the
input voltage has exceeded the UVLO voltage of 2.7 V. There is an internal current source connected to EN
so if enable is not used, the device will turn on automatically. If EN is not toggled directly, the device can be
pre-programmed to turn on at a certain input voltage higher than the UVLO voltage. This can be done with an
external resistor divider from AVIN to EN and EN to AGND as shown in Figure 8-3.
Input Power
Supply
RA
AVIN
LM21215
EN
VOUT
RB
Figure 8-3. Enable Start-Up Through VIN
The resistor values of RA and RB can be relatively sized to allow EN to reach the enable threshold voltage
depending on the input supply voltage. With the enable current source accounted for, the equation solving for RA
is the following:
RA =
RB VPVIN - 1.35V
1.35V - IENRB
(3)
where
•
•
•
•
RA is the resistor from VIN to enable.
RB is the resistor from enable to ground.
IEN is the internal enable pullup current (2 µA).
1.35 V is the fixed precision enable threshold voltage.
Typical values for RB range from 10 kΩ to 100 kΩ.
8.2.1.2.4 Soft Start
When EN has exceeded 1.35 V, and both PVIN and AVIN have exceeded the UVLO threshold, the LM21215
begins charging the output linearly to the voltage level dictated by the feedback resistor network. The LM21215
employs a user-adjustable soft-start circuit to lengthen the charging time of the output set by a capacitor from
the soft-start pin to ground. After enable exceeds 1.35 V, an internal 2-µA current source begins to charge
the soft-start capacitor. This allows the user to limit inrush currents due to a high output capacitance and not
cause an overcurrent condition. Adding a soft-start capacitor can also reduce the stress on the input rail. Larger
capacitor values will result in longer start-up times. Use Equation 4 to approximate the size of the soft-start
capacitor:
tSS x ISS
= CSS
0.6V
(4)
where
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•
•
ISS is nominally 2 µA.
tSS is the desired start-up time.
If VIN is higher than the UVLO level and enable is toggled high the soft start sequence begins. There is a small
delay between enable transitioning high and the beginning of the soft start sequence. This delay allows the
LM21215 to initialize its internal circuitry. Once the output has charged to 90% of the nominal output voltage the
power-good flag transitions high. This behavior is illustrated in Figure 8-4.
Voltage
90% VOUT
(VUVP)
VOUT
Enable
Delay
(tRESETSS)
0V
VEN
VPGOOD
Soft Start Time (tss)
Time
Figure 8-4. Soft-Start Timing
As shown above, the size of the capacitor is influenced by the nominal feedback voltage level 0.6 V, the
soft-start charging current, ISS (2 µA), and the desired soft-start time. If no soft-start capacitor is used, then
the LM21215 defaults to a minimum start-up time of 500 µs. The LM21215 does not start up faster than 500
µs. When enable is cycled or the device enters UVLO, the charge developed on the soft-start capacitor is
discharged to reset the start-up process. This also happens when the device enters short circuit mode from an
overcurrent event.
8.2.1.2.5 Inductor Selection
The inductor (L) used in the application influences the ripple current and the efficiency of the system. The first
selection criteria is to define a ripple current, ΔIL. In a buck converter, it is typically selected to run between
20% to 30% of the maximum output current. Figure 8-5 shows the ripple current in a standard buck converter
operating in continuous conduction mode. Larger ripple current results in a smaller inductance value, which will
lead to a lower series resistance in the inductor and improved efficiency. However, larger ripple current will also
cause the device to operate in discontinuous conduction mode at a higher average output current.
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VSW
VIN
Time
IL
IL AVG = IOUT
'IL
Time
Figure 8-5. Switch And Inductor Current Waveforms
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Once the ripple current has been determined, the appropriate inductor size can be calculated using Equation 5:
L=
(VIN ± VOUT) D
üIL fSW
(5)
8.2.1.2.6 Output Capacitor Selection
The output capacitor, COUT, filters the inductor ripple current and provides a source of charge for transient load
conditions. A wide range of output capacitors can be used with the LM21215 that provide various advantages.
The best performance is typically obtained using ceramic, SP, or OSCON type chemistries. Typical trade-offs
are that the ceramic capacitor provides extremely low ESR to reduce the output ripple voltage and noise spikes,
while the SP and OSCON capacitors provide a large bulk capacitance in a small volume for transient loading
conditions.
When selecting the value for the output capacitor, the two performance characteristics to consider are the output
voltage ripple and transient response. The output voltage ripple can be approximated by using Equation 6:
'VOUT
'IL x RESR +
1
8 x fSW x COUT
(6)
where
•
•
•
•
ΔVOUT (V) is the amount of peak-to-peak voltage ripple at the power supply output.
RESR (Ω) is the series resistance of the output capacitor.
fSW (Hz) is the switching frequency.
COUT (F) is the output capacitance used in the design.
The amount of output ripple that can be tolerated is application specific, however, a general recommendation
is to keep the output ripple less than 1% of the rated output voltage. Keep in mind ceramic capacitors are
sometimes preferred because they have very low ESR, however, depending on package and voltage rating
of the capacitor, the value of the capacitance can drop significantly with applied voltage. The output capacitor
selection will also affect the output voltage droop during a load transient. The peak droop on the output voltage
during a load transient is dependent on many factors, however, an approximation of the transient droop ignoring
loop bandwidth can be obtained using Equation 7:
VDROOP = 'IOUTSTEP x RESR +
L x 'IOUTSTEP2
COUT x (VIN - VOUT)
(7)
where
•
•
•
•
•
•
•
COUT (F) is the minimum required output capacitance.
L (H) is the value of the inductor.
VDROOP (V) is the output voltage drop ignoring loop bandwidth considerations.
ΔIOUTSTEP (A) is the load step change.
RESR (Ω) is the output capacitor ESR.
VIN (V) is the input voltage.
VOUT (V) is the set regulator output voltage.
Examine both the tolerance and voltage coefficient of the capacitor when designing for a specific output ripple or
transient droop target.
8.2.1.2.7 Input Capacitor Selection
Quality input capacitors are necessary to limit the ripple voltage at the VIN pin while supplying most of the switch
current during the on time. Additionally, they help minimize input voltage droop in an output current transient
condition. In general, it is recommended to use a ceramic capacitor for the input as it provides both a low
impedance and small footprint. Use of a high grade dielectric for the ceramic capacitor, such as X5R or X7R, will
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provide improved overtemperature performance and also minimize the DC voltage derating that occurs with Y5V
capacitors. The input capacitors CIN1 and CIN2 must be placed as close as possible to the PVIN and PGND pins.
Select non-ceramic input capacitors for RMS current rating and minimum ripple voltage. A good approximation
for the required ripple current rating is given by the relationship:
IIN-RMS = IOUT D(1 - D)
(8)
As indicated by the RMS ripple current equation, the highest requirement for RMS current rating occurs at
50% duty cycle. For this case, the RMS ripple current rating of the input capacitor should be greater than half
the output current. For best performance, low-ESR ceramic capacitors should be placed in parallel with higher
capacitance capacitors to provide the best input filtering for the device.
When operating at low input voltages (3.3 V or lower), additional capacitance can be necessary to protect from
triggering an undervoltage condition on an output current transient. This will depend on the impedance between
the input voltage supply and the LM21215, as well as the magnitude and slew rate of the output transient.
The AVIN pin requires a 1-µF ceramic capacitor to AGND and a 1-Ω resistor to PVIN. This RC network filters
inherent noise on PVIN from the sensitive analog circuitry connected to AVIN.
8.2.1.2.8 Programmable Current Limit
A resistor from the ILIM pin to GND sets the internal current limit on the LM21215. Program the current limit so
that the peak inductor current (IL) does not trigger the current limit in normal operation. This requires setting the
resistor from the ILIM pin to GND (RILIM) to the appropriate value to allow the maximum ripple current, ΔILMAX
plus the DC output current through the high-side FET during normal operation. The maximum ripple current can
be described as:
For D > 0.5
'ILMAX =
(VINMAX - VOUTMIN) VOUTMIN
LMIN fSWMIN VINMAX
For D < 0.5
'ILMAX =
(VINMIN - VOUTMAX) VOUTMAX
LMIN fSWMIN VINMIN
(9)
where
•
VINMAX, VINMIN, VOUTMAX, VOUTMIN, LMIN, and FSWMIN are the respective maximum and minimum conditions of
the system as defined by the component tolerance and device variation.
From this, the maximum allowable current through the high-side FET (IHSMAX) of device can be described as:
IHSMAX =
'ILMAX
+ IDCMAX
2
(10)
where
•
IOUTMAX is the maximum defined DC output current, up to 15 A.
Once the IHSMAX value has been determined, a nominal value of the RILIM resistor can be calculated as follows:
RILIM (k:) =
582.4
- 14.2
IHSMAX
(11)
where
•
RILIM value is the nominal resistance necessary for the given IHSMAX value.
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A conservative design should also take into account the device variation over VIN and temperature, as seen in
the Electrical Characteristics for the ICLR parameter and the typical performance characteristics. These variations
can cause the IHSMAX value to increase, depending on the range of the input voltage and junction temperature.
8.2.1.2.9 Control Loop Compensation
The LM21215 incorporates a high bandwidth amplifier between the FB and COMP pins to allow the user to
design a compensation network that matches the application. This section will walk through the various steps in
obtaining the open loop transfer function.
There are three main blocks of a voltage mode buck switcher that the power supply designer must consider
when designing the control system: the power train, modulator, and the compensated error amplifier. A closed
loop diagram is shown in Figure 8-6.
Power Train
PWM Modulator
VIN
RDCR LOUT
DRIVER
VOUT
SW
RESR
RO
COUT
PWM
+
Error Amplifier and Compensation
COMP
+
EA
-
CC1
RC1
0.6V
FB
RFB1
RC2 C
C3
RFB2
CC2
Figure 8-6. Loop Diagram
The power train consists of the output inductor (L) with DCR (DC resistance RDCR), output capacitor (C0) with
ESR (effective series resistance RESR), and load resistance (Ro). The error amplifier (EA) constantly forces FB
to 0.6 V. The passive compensation components around the error amplifier help maintain system stability. The
modulator creates the duty cycle by comparing the error amplifier signal with an internally generated ramp set at
the switching frequency.
There are three transfer functions that must be taken into consideration when obtaining the total open loop
transfer function: COMP to SW (modulator), SW to VOUT (power train), and VOUT to COMP (error amplifier). The
COMP to SW transfer function is simply the gain of the PWM modulator.
V
GPWM = üVinramp
(12)
where
•
ΔVRAMP is the oscillator peak-to-peak ramp voltage (nominally 0.8 V).
The SW to COMP transfer function includes the output inductor, output capacitor, and output load resistance.
The inductor and capacitor create two complex poles at a frequency described by:
fLC =
22
1
2S
RO + RDCR
LOUTCOUT(RO + RESR)
(13)
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In addition to two complex poles, a left half plane zero is created by the output capacitor ESR located at a
frequency described by:
fesr =
1
2SCoResr
(14)
A Bode plot showing the power train response can be seen in Figure 8-7.
60
0
-40
40
GAIN (dB)
-120
0
-160
-20
-200
PHASE (°)
-80
20
-240
-40
-280
-60
GAIN
PHASE
-80
100
1k
10k 100k
1M
FREQUENCY (HZ)
-320
-360
10M
Figure 8-7. Power Train Bode Plot
The complex poles created by the output inductor and capacitor cause a 180° phase shift at the resonant
frequency as seen in Figure 8-7. The phase is boosted back up to –90° due to the output capacitor ESR zero.
The 180° phase shift must be compensated out and phase boosted through the error amplifier to stabilize the
closed loop response. The compensation network shown around the error amplifier in Figure 8-6 creates two
poles, two zeros, and a pole at the origin. Placing these poles and zeros at the correct frequencies stabilizes the
closed loop response. The Compensated Error Amplifier transfer function is:
s
s
+1
+1
2SfZ1
2SfZ2
GEA = Km
s
s
s
+1
+1
2SfP1
2SfP2
(15)
The pole located at the origin gives high open loop gain at DC, translating into improved load regulation
accuracy. This pole occurs at a very low frequency due to the limited gain of the error amplifier, however, it can
be approximated at DC for the purposes of compensation. The other two poles and two zeros can be located
accordingly to stabilize the voltage mode loop depending on the power stage complex poles and Q. Figure 8-8 is
an illustration of what the Error Amplifier Compensation transfer function will look like.
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GAIN
PHASE
90
80
45
60
0
40
-45
20
-90
0
-135
-20
PHASE (°)
GAIN (dB)
100
-180
100
1k
10k 100k 1M
FREQUENCY (Hz)
10M
Figure 8-8. Type 3 Compensation Network Bode Plot
As seen in Figure 8-8, the two zeros (fLC/2, fLC) in the compensation network give a phase boost. This will cancel
out the effects of the phase loss from the output filter. The compensation network also adds two poles to the
system. One pole should be located at the zero caused by the output capacitor ESR (fESR), and the other pole
must be at half the switching frequency (fSW/2) to roll off the high frequency response. The dependency of the
pole and zero locations on the compensation components is described in Equation 16.
fLC
1
fZ1 = 2 = 2SR C
C1 C1
1
fZ2 = fLC = 2S(R + R )C
C1
FB1 C3
fP1 = fESR =
fP2 =
fsw
1
2SRC2CC3
CC1 + CC2
= 2SR C C
2
C1 C1 C2
(16)
An example of the step-by-step procedure to generate compensation component values using the typical
application setup, is given. The parameters needed for the compensation values are given in Table 8-2.
Table 8-2. Required Parameters for Compensation Values
PARAMETER
VALUE
VIN
5V
VOUT
1.2 V
IOUT
15 A
fCROSSOVER
100 kHz
L
0.56 µH
RDCR
1.8 mΩ
CO
150 µF
RESR
1.0 mΩ
ΔVRAMP
0.8 V
fSW
500 kHz
where ΔVRAMP is the oscillator peak-to-peak ramp voltage (nominally 0.8 V), and fCROSSOVER is the frequency
at which the open-loop gain is a magnitude of 1. It is recommended that the fCROSSOVER not exceed one-fifth
of the switching frequency. The output capacitance, CO, depends on capacitor chemistry and bias voltage. For
24
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multi-layer ceramic capacitors (MLCC), the total capacitance will degrade as the DC bias voltage is increased.
Measuring the actual capacitance value for the output capacitors at the output voltage is recommended to
accurately calculate the compensation network. The example given here is the total output capacitance using
the three MLCC output capacitors biased at 1.2 V, as seen in Figure 8-1. Note that it is more conservative, from
a stability standpoint, to err on the side of a smaller output capacitance value in the compensation calculations
rather than a larger, as this will result in a lower bandwidth but increased phase margin.
First, the value of RFB1 should be chosen. A typical value is 10 kΩ. From this, the value of RC1 can be calculated
to set the mid-band gain so that the desired crossover frequency is achieved:
RC1 =
fcrossover
'VRAMP
fLC
VIN
RFB1
100 kHz 0.8 V
10 k:
17.4 kHz 5.0 V
= 9.2 k:
=
(17)
Next, the value of CC1 can be calculated by placing a zero at half of the LC double pole frequency (fLC):
1
CC1 =
SfLCRC1
= 1.99 nF
(18)
Now the value of CC2 can be calculated to place a pole at half of the switching frequency (fSW):
CC2 =
CC1
SfSWRC1 CC1 -1
= 71 pF
(19)
RC2 can then be calculated to set the second zero at the LC double pole frequency:
RC2 =
RFB1 fLC
fESR - fLC
= 166:
(20)
Last, CC3 can be calculated to place a pole at the same frequency as the zero created by the output capacitor
ESR:
1
2SfESRRC2
= 898 pF
CC3 =
(21)
An illustration of the total loop response can be seen in Figure 8-9.
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200
160
GAIN
PHASE
140
150
GAIN (dB)
100
100
80
60
50
40
20
0
PHASE MARGIN (°)
120
0
-20
-50
-40
10
100
1k
10k 100k
FREQUENCY (Hz)
1M
Figure 8-9. Loop Response
It is important to verify the stability by either observing the load transient response or by using a network
analyzer. A phase margin between 45° and 70° is usually desired for voltage mode systems. Excessive phase
margin can cause slow system response to load transients and low phase margin can cause an oscillatory load
transient response. If the load step response peak deviation is larger than desired, increasing fCROSSOVER and
recalculating the compensation components can help, but usually at the expense of phase margin.
0.04
0.10
0.03
0.08
û OUTPUT VOLTAGE (%)
û OUTPUT VOLTAGE (%)
8.2.1.3 Application Curves
0.02
0.01
0.00
-0.01
-0.02
VIN = 3.3V
VIN = 5.0V
-0.03
2
4
6
8
10
OUTPUT CURRENT (A)
0.04
0.02
0.00
-0.02
-0.04
-0.06
-0.08
-0.04
0
0.06
12
-0.10
3.0
Figure 8-10. Load Regulation
26
IOUT = 0A
IOUT = 12A
3.5
4.0
4.5
5.0
INPUT VOLTAGE (V)
5.5
Figure 8-11. Line Regulation
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VOUT (50 mV/Div)
VOUT (10 mV/Div)
IOUT (10A/Div)
2 µs/DIV
100 µs/DIV
Figure 8-12. Load Transient Response
Figure 8-13. Output Voltage Ripple (IOUT = 15 A)
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8.2.2 Typical Application Schematic 2
HTSSOP-20
LO
5,6,7
VIN
PVIN
RF
CIN1
REN1
3
SW
11-16
VOUT
CC3
EN
RFB1
4
RC2
AVIN
CF
REN2
LM21215
FB
CSS
2 SS/
TRK
COMP
CO1 CO2
19
18
CC1 RC1
RFB2
CC2
VIN
1
ILIM
PGOOD
17
RPGOOD
PGND AGND
RILIM
8,9,10
20
Figure 8-14. Typical Application Schematic 2
8.2.2.1 Design Requirements
Table 8-3. Bill Of Materials (VIN = 4 V–5.5 V, VOUT = 0.9 V, IOUT = 8 A)
ID
DESCRIPTION
VENDOR
PART NUMBER
QUANTITY
CF
CAP, CERM, 1 μF, 10 V, ±10%, X7R, 0603
MuRata
GRM188R71A105KA61D
1
CIN1, CO1, CO2
CAP, CERM, 100 μF, 6.3 V, ±20%, X5R, 1206
MuRata
GRM31CR60J107ME39L
3
CC1
CAP, CERM, 1800 pF, 50 V, ±5%, C0G/NP0, 0603
MuRata
GRM1885C1H182JA01D
1
CC2
CAP, CERM, 82 pF, 50 V, ±5%, C0G/NP0, 0603
TDK
C1608C0G1H820J
1
CC3
CAP, CERM, 820 pF, 50 V, ±5%, C0G/NP0, 0603
TDK
C1608C0G1H821J
1
CSS
CAP, CERM, 0.033 μF, 16 V, ±10%, X7R, 0603
MuRata
GRM188R71C333KA01D
1
LO
Inductor, Shielded Drum Core, 680 nH, 22 A, 0.0014 Ω,
SMD
Coilcraft
XAL1060-681ME
1
RF
RES, 1.0 Ω, 5%, 0.1 W, 0603
Vishay-Dale
CRCW06031R00JNEA
1
RC1
RES, 8.25 kΩ, 1%, 0.1 W, 0603
Vishay-Dale
CRCW06038K25FKEA
1
RC2
RES, 124 Ω, 1%, 0.1 W, 0603
Vishay-Dale
CRCW0603124RFKEA
1
REN1, RFB1,
RPGOOD
RES, 10 kΩ, 1%, 0.1 W, 0603
Vishay-Dale
CRCW060310K0FKEA
3
REN2
RES, 19.6 kΩ, 1%, 0.1 W, 0603
Vishay-Dale
CRCW060319K6FKEA
1
RFB2
RES, 20.0 kΩ, 1%, 0.1 W, 0603
Vishay-Dale
CRCW060320K0FKEA
1
RILIM
RES, 39.2 kΩ, 1%, 0.1 W, 0603
Vishay-Dale
CRCW060339K2FKEA
1
8.2.2.2 Detailed Design Procedure
See Section 8.2.1.2
28
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9 Layout
9.1 Layout Considerations
PC board layout is an important part of DC/DC converter design. Poor board layout can disrupt the performance
of a DC/DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss
in the traces. These can send erroneous signals to the DC/DC converter resulting in poor regulation or instability.
Good layout can be implemented by following a few simple design rules.
•
•
•
•
•
•
Minimize area of switched current loops. In a buck regulator, there are two loops where currents are switched
at high slew rates. The first loop starts from the input capacitor, to the regulator PVIN pin, to the regulator
SW pin, to the inductor then out to the output capacitor and load. The second loop starts from the output
capacitor ground, to the regulator GND pins, to the inductor and then out to the load (see Figure 9-1). To
minimize both loop areas, place the input capacitor as close as possible to the VIN pin. Grounding for both
the input and output capacitor must be close. Ideally, a ground plane should be placed on the top layer that
connects the PGND pins, the exposed pad (EP) of the device, and the ground connections of the input and
output capacitors in a small area near pin 10 and 11 of the device. The inductor should be placed as close as
possible to the SW pin and output capacitor.
Minimize the copper area of the switch node. Route the six SW pins on a single top plane to the pad of the
inductor. Place the inductor should be placed to the switch pins of the device with a wide trace to minimize
conductive losses. The inductor can be placed on the bottom side of the PCB relative to the LM21215, but
care must be taken to not allow any coupling of the magnetic field of the inductor into the sensitive feedback
or compensation traces.
Have a solid ground plane between PGND, the EP, and the input and output capacitor ground connections.
The ground connections for the AGND, compensation, feedback, and soft-start components should be
physically isolated (located near pin 1 and 20) from the power ground plane but a separate ground
connection is not necessary. If not properly handled, poor grounding can result in degraded load regulation or
erratic switching behavior.
Carefully route the connection from the VOUT signal to the compensation network. This node is high
impedance and can be susceptible to noise coupling. The trace should be routed away from the SW pin
and inductor to avoid contaminating the feedback signal with switch noise.
Make input and output bus connections as wide as possible. This reduces any voltage drops on the input or
output of the converter and can improve efficiency. Voltage accuracy at the load is important so make sure
feedback voltage sense is made at the load. Doing so corrects for voltage drops at the load and provide the
best output accuracy.
Provide adequate device heat sinking. For most 15-A, designs a four layer board is recommended. Use as
many vias as is possible to connect the EP to the power plane heatsink. The vias located underneath the
EP wicks solder into them if they are not filled. Complete solder coverage of the EP to the board is required
to achieve the θJA values described in the previous section. Either an adequate amount of solder must be
applied to the EP pad to fill the vias, or the vias must be filled during manufacturing. See Section 9.2.1 to
ensure enough copper heatsinking area is used to keep the junction temperature below 125°C.
9.2 Layout Example
LM21215
L
VOUT
SW
PVIN
VIN
CIN
COUT
PGND
LOOP1
LOOP2
Figure 9-1. Schematic of LM21215 Highlighting Layout Sensitive Nodes
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9.2.1 Thermal Considerations
The thermal characteristics of the LM21215 are specified using the parameter θJA, which relates the junction
temperature to the ambient temperature. Although the value of θJA is dependent on many variables, it still can be
used to approximate the operating junction temperature of the device.
To obtain an estimate of the device junction temperature, one can use the following relationship:
TJ = PD TJA + TA
(22)
and
PD = PIN (1 - Efficiency) - IOUT2 RDCR
(23)
where
•
•
•
•
•
TJ is the junction temperature in °C.
PIN is the input power in Watts (PIN = VIN × IIN).
θJA is the junction to ambient thermal resistance for the LM21215.
TA is the ambient temperature in °C.
IOUT is the output load current in A.
It is important to always keep the operating junction temperature (TJ) below 125°C for reliable operation. If the
junction temperature exceeds 165°C, the device cycles in and out of thermal shutdown. If thermal shutdown
occurs, it is a sign of inadequate heat sinking or excessive power dissipation in the device.
Figure 9-2 provides a better approximation of the θJA for a given PCB copper area. The PCB used in this test
consisted of four layers: 1-oz. copper was used for the internal layers while the external layers were plated to
2-oz. copper weight. To provide an optimal thermal connection, a 3 × 5 array of 8-mil. vias under the thermal pad
were used, and an additional twelve 8-mil. vias under the rest of the device were used to connect the four layers.
THERMAL RESISTANCE ( JA)
30
28
26
24
22
20
18
16
14
12
10
2
3
4
5
6
7
8
2
BOARD AREA (in )
9
10
Figure 9-2. Thermal Resistance vs PCB Area (4-Layer Board)
30
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Figure 9-3 shows a plot of the maximum ambient temperature vs output current for the typical application circuit
shown in Figure 8-1, assuming a θJA value of 24°C/W.
MAX. AMBIENT TEMERATURE (°C)
125
120
115
110
105
100
95
90
85
80
0
3
6
9
12
OUTPUT CURRENT (A)
15
Figure 9-3. Maximum Ambient Temperature vs Output Current (0 LFM)
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10 Device and Documentation Support
10.1 Device Support
10.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
10.1.2 Development Support
10.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM21215 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
10.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.6 Glossary
TI Glossary
32
This glossary lists and explains terms, acronyms, and definitions.
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11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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6-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LM21215MH/NOPB
ACTIVE
HTSSOP
PWP
20
73
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LM21215
MH
LM21215MHE/NOPB
ACTIVE
HTSSOP
PWP
20
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LM21215
MH
LM21215MHX/NOPB
ACTIVE
HTSSOP
PWP
20
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LM21215
MH
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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